tx.c 30 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2005-2008 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/pci.h>
  11. #include <linux/tcp.h>
  12. #include <linux/ip.h>
  13. #include <linux/in.h>
  14. #include <linux/if_ether.h>
  15. #include <linux/highmem.h>
  16. #include "net_driver.h"
  17. #include "tx.h"
  18. #include "efx.h"
  19. #include "falcon.h"
  20. #include "workarounds.h"
  21. /*
  22. * TX descriptor ring full threshold
  23. *
  24. * The tx_queue descriptor ring fill-level must fall below this value
  25. * before we restart the netif queue
  26. */
  27. #define EFX_NETDEV_TX_THRESHOLD(_tx_queue) \
  28. (_tx_queue->efx->type->txd_ring_mask / 2u)
  29. /* We want to be able to nest calls to netif_stop_queue(), since each
  30. * channel can have an individual stop on the queue.
  31. */
  32. void efx_stop_queue(struct efx_nic *efx)
  33. {
  34. spin_lock_bh(&efx->netif_stop_lock);
  35. EFX_TRACE(efx, "stop TX queue\n");
  36. atomic_inc(&efx->netif_stop_count);
  37. netif_stop_queue(efx->net_dev);
  38. spin_unlock_bh(&efx->netif_stop_lock);
  39. }
  40. /* Wake netif's TX queue
  41. * We want to be able to nest calls to netif_stop_queue(), since each
  42. * channel can have an individual stop on the queue.
  43. */
  44. inline void efx_wake_queue(struct efx_nic *efx)
  45. {
  46. local_bh_disable();
  47. if (atomic_dec_and_lock(&efx->netif_stop_count,
  48. &efx->netif_stop_lock)) {
  49. EFX_TRACE(efx, "waking TX queue\n");
  50. netif_wake_queue(efx->net_dev);
  51. spin_unlock(&efx->netif_stop_lock);
  52. }
  53. local_bh_enable();
  54. }
  55. static inline void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
  56. struct efx_tx_buffer *buffer)
  57. {
  58. if (buffer->unmap_len) {
  59. struct pci_dev *pci_dev = tx_queue->efx->pci_dev;
  60. if (buffer->unmap_single)
  61. pci_unmap_single(pci_dev, buffer->unmap_addr,
  62. buffer->unmap_len, PCI_DMA_TODEVICE);
  63. else
  64. pci_unmap_page(pci_dev, buffer->unmap_addr,
  65. buffer->unmap_len, PCI_DMA_TODEVICE);
  66. buffer->unmap_len = 0;
  67. buffer->unmap_single = 0;
  68. }
  69. if (buffer->skb) {
  70. dev_kfree_skb_any((struct sk_buff *) buffer->skb);
  71. buffer->skb = NULL;
  72. EFX_TRACE(tx_queue->efx, "TX queue %d transmission id %x "
  73. "complete\n", tx_queue->queue, read_ptr);
  74. }
  75. }
  76. /**
  77. * struct efx_tso_header - a DMA mapped buffer for packet headers
  78. * @next: Linked list of free ones.
  79. * The list is protected by the TX queue lock.
  80. * @dma_unmap_len: Length to unmap for an oversize buffer, or 0.
  81. * @dma_addr: The DMA address of the header below.
  82. *
  83. * This controls the memory used for a TSO header. Use TSOH_DATA()
  84. * to find the packet header data. Use TSOH_SIZE() to calculate the
  85. * total size required for a given packet header length. TSO headers
  86. * in the free list are exactly %TSOH_STD_SIZE bytes in size.
  87. */
  88. struct efx_tso_header {
  89. union {
  90. struct efx_tso_header *next;
  91. size_t unmap_len;
  92. };
  93. dma_addr_t dma_addr;
  94. };
  95. static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
  96. const struct sk_buff *skb);
  97. static void efx_fini_tso(struct efx_tx_queue *tx_queue);
  98. static void efx_tsoh_heap_free(struct efx_tx_queue *tx_queue,
  99. struct efx_tso_header *tsoh);
  100. static inline void efx_tsoh_free(struct efx_tx_queue *tx_queue,
  101. struct efx_tx_buffer *buffer)
  102. {
  103. if (buffer->tsoh) {
  104. if (likely(!buffer->tsoh->unmap_len)) {
  105. buffer->tsoh->next = tx_queue->tso_headers_free;
  106. tx_queue->tso_headers_free = buffer->tsoh;
  107. } else {
  108. efx_tsoh_heap_free(tx_queue, buffer->tsoh);
  109. }
  110. buffer->tsoh = NULL;
  111. }
  112. }
  113. /*
  114. * Add a socket buffer to a TX queue
  115. *
  116. * This maps all fragments of a socket buffer for DMA and adds them to
  117. * the TX queue. The queue's insert pointer will be incremented by
  118. * the number of fragments in the socket buffer.
  119. *
  120. * If any DMA mapping fails, any mapped fragments will be unmapped,
  121. * the queue's insert pointer will be restored to its original value.
  122. *
  123. * Returns NETDEV_TX_OK or NETDEV_TX_BUSY
  124. * You must hold netif_tx_lock() to call this function.
  125. */
  126. static inline int efx_enqueue_skb(struct efx_tx_queue *tx_queue,
  127. const struct sk_buff *skb)
  128. {
  129. struct efx_nic *efx = tx_queue->efx;
  130. struct pci_dev *pci_dev = efx->pci_dev;
  131. struct efx_tx_buffer *buffer;
  132. skb_frag_t *fragment;
  133. struct page *page;
  134. int page_offset;
  135. unsigned int len, unmap_len = 0, fill_level, insert_ptr, misalign;
  136. dma_addr_t dma_addr, unmap_addr = 0;
  137. unsigned int dma_len;
  138. unsigned unmap_single;
  139. int q_space, i = 0;
  140. int rc = NETDEV_TX_OK;
  141. EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
  142. if (skb_shinfo((struct sk_buff *)skb)->gso_size)
  143. return efx_enqueue_skb_tso(tx_queue, skb);
  144. /* Get size of the initial fragment */
  145. len = skb_headlen(skb);
  146. fill_level = tx_queue->insert_count - tx_queue->old_read_count;
  147. q_space = efx->type->txd_ring_mask - 1 - fill_level;
  148. /* Map for DMA. Use pci_map_single rather than pci_map_page
  149. * since this is more efficient on machines with sparse
  150. * memory.
  151. */
  152. unmap_single = 1;
  153. dma_addr = pci_map_single(pci_dev, skb->data, len, PCI_DMA_TODEVICE);
  154. /* Process all fragments */
  155. while (1) {
  156. if (unlikely(pci_dma_mapping_error(dma_addr)))
  157. goto pci_err;
  158. /* Store fields for marking in the per-fragment final
  159. * descriptor */
  160. unmap_len = len;
  161. unmap_addr = dma_addr;
  162. /* Add to TX queue, splitting across DMA boundaries */
  163. do {
  164. if (unlikely(q_space-- <= 0)) {
  165. /* It might be that completions have
  166. * happened since the xmit path last
  167. * checked. Update the xmit path's
  168. * copy of read_count.
  169. */
  170. ++tx_queue->stopped;
  171. /* This memory barrier protects the
  172. * change of stopped from the access
  173. * of read_count. */
  174. smp_mb();
  175. tx_queue->old_read_count =
  176. *(volatile unsigned *)
  177. &tx_queue->read_count;
  178. fill_level = (tx_queue->insert_count
  179. - tx_queue->old_read_count);
  180. q_space = (efx->type->txd_ring_mask - 1 -
  181. fill_level);
  182. if (unlikely(q_space-- <= 0))
  183. goto stop;
  184. smp_mb();
  185. --tx_queue->stopped;
  186. }
  187. insert_ptr = (tx_queue->insert_count &
  188. efx->type->txd_ring_mask);
  189. buffer = &tx_queue->buffer[insert_ptr];
  190. efx_tsoh_free(tx_queue, buffer);
  191. EFX_BUG_ON_PARANOID(buffer->tsoh);
  192. EFX_BUG_ON_PARANOID(buffer->skb);
  193. EFX_BUG_ON_PARANOID(buffer->len);
  194. EFX_BUG_ON_PARANOID(buffer->continuation != 1);
  195. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  196. dma_len = (((~dma_addr) & efx->type->tx_dma_mask) + 1);
  197. if (likely(dma_len > len))
  198. dma_len = len;
  199. misalign = (unsigned)dma_addr & efx->type->bug5391_mask;
  200. if (misalign && dma_len + misalign > 512)
  201. dma_len = 512 - misalign;
  202. /* Fill out per descriptor fields */
  203. buffer->len = dma_len;
  204. buffer->dma_addr = dma_addr;
  205. len -= dma_len;
  206. dma_addr += dma_len;
  207. ++tx_queue->insert_count;
  208. } while (len);
  209. /* Transfer ownership of the unmapping to the final buffer */
  210. buffer->unmap_addr = unmap_addr;
  211. buffer->unmap_single = unmap_single;
  212. buffer->unmap_len = unmap_len;
  213. unmap_len = 0;
  214. /* Get address and size of next fragment */
  215. if (i >= skb_shinfo(skb)->nr_frags)
  216. break;
  217. fragment = &skb_shinfo(skb)->frags[i];
  218. len = fragment->size;
  219. page = fragment->page;
  220. page_offset = fragment->page_offset;
  221. i++;
  222. /* Map for DMA */
  223. unmap_single = 0;
  224. dma_addr = pci_map_page(pci_dev, page, page_offset, len,
  225. PCI_DMA_TODEVICE);
  226. }
  227. /* Transfer ownership of the skb to the final buffer */
  228. buffer->skb = skb;
  229. buffer->continuation = 0;
  230. /* Pass off to hardware */
  231. falcon_push_buffers(tx_queue);
  232. return NETDEV_TX_OK;
  233. pci_err:
  234. EFX_ERR_RL(efx, " TX queue %d could not map skb with %d bytes %d "
  235. "fragments for DMA\n", tx_queue->queue, skb->len,
  236. skb_shinfo(skb)->nr_frags + 1);
  237. /* Mark the packet as transmitted, and free the SKB ourselves */
  238. dev_kfree_skb_any((struct sk_buff *)skb);
  239. goto unwind;
  240. stop:
  241. rc = NETDEV_TX_BUSY;
  242. if (tx_queue->stopped == 1)
  243. efx_stop_queue(efx);
  244. unwind:
  245. /* Work backwards until we hit the original insert pointer value */
  246. while (tx_queue->insert_count != tx_queue->write_count) {
  247. --tx_queue->insert_count;
  248. insert_ptr = tx_queue->insert_count & efx->type->txd_ring_mask;
  249. buffer = &tx_queue->buffer[insert_ptr];
  250. efx_dequeue_buffer(tx_queue, buffer);
  251. buffer->len = 0;
  252. }
  253. /* Free the fragment we were mid-way through pushing */
  254. if (unmap_len)
  255. pci_unmap_page(pci_dev, unmap_addr, unmap_len,
  256. PCI_DMA_TODEVICE);
  257. return rc;
  258. }
  259. /* Remove packets from the TX queue
  260. *
  261. * This removes packets from the TX queue, up to and including the
  262. * specified index.
  263. */
  264. static inline void efx_dequeue_buffers(struct efx_tx_queue *tx_queue,
  265. unsigned int index)
  266. {
  267. struct efx_nic *efx = tx_queue->efx;
  268. unsigned int stop_index, read_ptr;
  269. unsigned int mask = tx_queue->efx->type->txd_ring_mask;
  270. stop_index = (index + 1) & mask;
  271. read_ptr = tx_queue->read_count & mask;
  272. while (read_ptr != stop_index) {
  273. struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
  274. if (unlikely(buffer->len == 0)) {
  275. EFX_ERR(tx_queue->efx, "TX queue %d spurious TX "
  276. "completion id %x\n", tx_queue->queue,
  277. read_ptr);
  278. efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
  279. return;
  280. }
  281. efx_dequeue_buffer(tx_queue, buffer);
  282. buffer->continuation = 1;
  283. buffer->len = 0;
  284. ++tx_queue->read_count;
  285. read_ptr = tx_queue->read_count & mask;
  286. }
  287. }
  288. /* Initiate a packet transmission on the specified TX queue.
  289. * Note that returning anything other than NETDEV_TX_OK will cause the
  290. * OS to free the skb.
  291. *
  292. * This function is split out from efx_hard_start_xmit to allow the
  293. * loopback test to direct packets via specific TX queues. It is
  294. * therefore a non-static inline, so as not to penalise performance
  295. * for non-loopback transmissions.
  296. *
  297. * Context: netif_tx_lock held
  298. */
  299. inline int efx_xmit(struct efx_nic *efx,
  300. struct efx_tx_queue *tx_queue, struct sk_buff *skb)
  301. {
  302. int rc;
  303. /* Map fragments for DMA and add to TX queue */
  304. rc = efx_enqueue_skb(tx_queue, skb);
  305. if (unlikely(rc != NETDEV_TX_OK))
  306. goto out;
  307. /* Update last TX timer */
  308. efx->net_dev->trans_start = jiffies;
  309. out:
  310. return rc;
  311. }
  312. /* Initiate a packet transmission. We use one channel per CPU
  313. * (sharing when we have more CPUs than channels). On Falcon, the TX
  314. * completion events will be directed back to the CPU that transmitted
  315. * the packet, which should be cache-efficient.
  316. *
  317. * Context: non-blocking.
  318. * Note that returning anything other than NETDEV_TX_OK will cause the
  319. * OS to free the skb.
  320. */
  321. int efx_hard_start_xmit(struct sk_buff *skb, struct net_device *net_dev)
  322. {
  323. struct efx_nic *efx = net_dev->priv;
  324. return efx_xmit(efx, &efx->tx_queue[0], skb);
  325. }
  326. void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
  327. {
  328. unsigned fill_level;
  329. struct efx_nic *efx = tx_queue->efx;
  330. EFX_BUG_ON_PARANOID(index > efx->type->txd_ring_mask);
  331. efx_dequeue_buffers(tx_queue, index);
  332. /* See if we need to restart the netif queue. This barrier
  333. * separates the update of read_count from the test of
  334. * stopped. */
  335. smp_mb();
  336. if (unlikely(tx_queue->stopped)) {
  337. fill_level = tx_queue->insert_count - tx_queue->read_count;
  338. if (fill_level < EFX_NETDEV_TX_THRESHOLD(tx_queue)) {
  339. EFX_BUG_ON_PARANOID(!efx_dev_registered(efx));
  340. /* Do this under netif_tx_lock(), to avoid racing
  341. * with efx_xmit(). */
  342. netif_tx_lock(efx->net_dev);
  343. if (tx_queue->stopped) {
  344. tx_queue->stopped = 0;
  345. efx_wake_queue(efx);
  346. }
  347. netif_tx_unlock(efx->net_dev);
  348. }
  349. }
  350. }
  351. int efx_probe_tx_queue(struct efx_tx_queue *tx_queue)
  352. {
  353. struct efx_nic *efx = tx_queue->efx;
  354. unsigned int txq_size;
  355. int i, rc;
  356. EFX_LOG(efx, "creating TX queue %d\n", tx_queue->queue);
  357. /* Allocate software ring */
  358. txq_size = (efx->type->txd_ring_mask + 1) * sizeof(*tx_queue->buffer);
  359. tx_queue->buffer = kzalloc(txq_size, GFP_KERNEL);
  360. if (!tx_queue->buffer) {
  361. rc = -ENOMEM;
  362. goto fail1;
  363. }
  364. for (i = 0; i <= efx->type->txd_ring_mask; ++i)
  365. tx_queue->buffer[i].continuation = 1;
  366. /* Allocate hardware ring */
  367. rc = falcon_probe_tx(tx_queue);
  368. if (rc)
  369. goto fail2;
  370. return 0;
  371. fail2:
  372. kfree(tx_queue->buffer);
  373. tx_queue->buffer = NULL;
  374. fail1:
  375. tx_queue->used = 0;
  376. return rc;
  377. }
  378. int efx_init_tx_queue(struct efx_tx_queue *tx_queue)
  379. {
  380. EFX_LOG(tx_queue->efx, "initialising TX queue %d\n", tx_queue->queue);
  381. tx_queue->insert_count = 0;
  382. tx_queue->write_count = 0;
  383. tx_queue->read_count = 0;
  384. tx_queue->old_read_count = 0;
  385. BUG_ON(tx_queue->stopped);
  386. /* Set up TX descriptor ring */
  387. return falcon_init_tx(tx_queue);
  388. }
  389. void efx_release_tx_buffers(struct efx_tx_queue *tx_queue)
  390. {
  391. struct efx_tx_buffer *buffer;
  392. if (!tx_queue->buffer)
  393. return;
  394. /* Free any buffers left in the ring */
  395. while (tx_queue->read_count != tx_queue->write_count) {
  396. buffer = &tx_queue->buffer[tx_queue->read_count &
  397. tx_queue->efx->type->txd_ring_mask];
  398. efx_dequeue_buffer(tx_queue, buffer);
  399. buffer->continuation = 1;
  400. buffer->len = 0;
  401. ++tx_queue->read_count;
  402. }
  403. }
  404. void efx_fini_tx_queue(struct efx_tx_queue *tx_queue)
  405. {
  406. EFX_LOG(tx_queue->efx, "shutting down TX queue %d\n", tx_queue->queue);
  407. /* Flush TX queue, remove descriptor ring */
  408. falcon_fini_tx(tx_queue);
  409. efx_release_tx_buffers(tx_queue);
  410. /* Free up TSO header cache */
  411. efx_fini_tso(tx_queue);
  412. /* Release queue's stop on port, if any */
  413. if (tx_queue->stopped) {
  414. tx_queue->stopped = 0;
  415. efx_wake_queue(tx_queue->efx);
  416. }
  417. }
  418. void efx_remove_tx_queue(struct efx_tx_queue *tx_queue)
  419. {
  420. EFX_LOG(tx_queue->efx, "destroying TX queue %d\n", tx_queue->queue);
  421. falcon_remove_tx(tx_queue);
  422. kfree(tx_queue->buffer);
  423. tx_queue->buffer = NULL;
  424. tx_queue->used = 0;
  425. }
  426. /* Efx TCP segmentation acceleration.
  427. *
  428. * Why? Because by doing it here in the driver we can go significantly
  429. * faster than the GSO.
  430. *
  431. * Requires TX checksum offload support.
  432. */
  433. /* Number of bytes inserted at the start of a TSO header buffer,
  434. * similar to NET_IP_ALIGN.
  435. */
  436. #if defined(__i386__) || defined(__x86_64__)
  437. #define TSOH_OFFSET 0
  438. #else
  439. #define TSOH_OFFSET NET_IP_ALIGN
  440. #endif
  441. #define TSOH_BUFFER(tsoh) ((u8 *)(tsoh + 1) + TSOH_OFFSET)
  442. /* Total size of struct efx_tso_header, buffer and padding */
  443. #define TSOH_SIZE(hdr_len) \
  444. (sizeof(struct efx_tso_header) + TSOH_OFFSET + hdr_len)
  445. /* Size of blocks on free list. Larger blocks must be allocated from
  446. * the heap.
  447. */
  448. #define TSOH_STD_SIZE 128
  449. #define PTR_DIFF(p1, p2) ((u8 *)(p1) - (u8 *)(p2))
  450. #define ETH_HDR_LEN(skb) (skb_network_header(skb) - (skb)->data)
  451. #define SKB_TCP_OFF(skb) PTR_DIFF(tcp_hdr(skb), (skb)->data)
  452. #define SKB_IPV4_OFF(skb) PTR_DIFF(ip_hdr(skb), (skb)->data)
  453. /**
  454. * struct tso_state - TSO state for an SKB
  455. * @remaining_len: Bytes of data we've yet to segment
  456. * @seqnum: Current sequence number
  457. * @packet_space: Remaining space in current packet
  458. * @ifc: Input fragment cursor.
  459. * Where we are in the current fragment of the incoming SKB. These
  460. * values get updated in place when we split a fragment over
  461. * multiple packets.
  462. * @p: Parameters.
  463. * These values are set once at the start of the TSO send and do
  464. * not get changed as the routine progresses.
  465. *
  466. * The state used during segmentation. It is put into this data structure
  467. * just to make it easy to pass into inline functions.
  468. */
  469. struct tso_state {
  470. unsigned remaining_len;
  471. unsigned seqnum;
  472. unsigned packet_space;
  473. struct {
  474. /* DMA address of current position */
  475. dma_addr_t dma_addr;
  476. /* Remaining length */
  477. unsigned int len;
  478. /* DMA address and length of the whole fragment */
  479. unsigned int unmap_len;
  480. dma_addr_t unmap_addr;
  481. struct page *page;
  482. unsigned page_off;
  483. } ifc;
  484. struct {
  485. /* The number of bytes of header */
  486. unsigned int header_length;
  487. /* The number of bytes to put in each outgoing segment. */
  488. int full_packet_size;
  489. /* Current IPv4 ID, host endian. */
  490. unsigned ipv4_id;
  491. } p;
  492. };
  493. /*
  494. * Verify that our various assumptions about sk_buffs and the conditions
  495. * under which TSO will be attempted hold true.
  496. */
  497. static inline void efx_tso_check_safe(const struct sk_buff *skb)
  498. {
  499. EFX_BUG_ON_PARANOID(skb->protocol != htons(ETH_P_IP));
  500. EFX_BUG_ON_PARANOID(((struct ethhdr *)skb->data)->h_proto !=
  501. skb->protocol);
  502. EFX_BUG_ON_PARANOID(ip_hdr(skb)->protocol != IPPROTO_TCP);
  503. EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb), skb->data)
  504. + (tcp_hdr(skb)->doff << 2u)) >
  505. skb_headlen(skb));
  506. }
  507. /*
  508. * Allocate a page worth of efx_tso_header structures, and string them
  509. * into the tx_queue->tso_headers_free linked list. Return 0 or -ENOMEM.
  510. */
  511. static int efx_tsoh_block_alloc(struct efx_tx_queue *tx_queue)
  512. {
  513. struct pci_dev *pci_dev = tx_queue->efx->pci_dev;
  514. struct efx_tso_header *tsoh;
  515. dma_addr_t dma_addr;
  516. u8 *base_kva, *kva;
  517. base_kva = pci_alloc_consistent(pci_dev, PAGE_SIZE, &dma_addr);
  518. if (base_kva == NULL) {
  519. EFX_ERR(tx_queue->efx, "Unable to allocate page for TSO"
  520. " headers\n");
  521. return -ENOMEM;
  522. }
  523. /* pci_alloc_consistent() allocates pages. */
  524. EFX_BUG_ON_PARANOID(dma_addr & (PAGE_SIZE - 1u));
  525. for (kva = base_kva; kva < base_kva + PAGE_SIZE; kva += TSOH_STD_SIZE) {
  526. tsoh = (struct efx_tso_header *)kva;
  527. tsoh->dma_addr = dma_addr + (TSOH_BUFFER(tsoh) - base_kva);
  528. tsoh->next = tx_queue->tso_headers_free;
  529. tx_queue->tso_headers_free = tsoh;
  530. }
  531. return 0;
  532. }
  533. /* Free up a TSO header, and all others in the same page. */
  534. static void efx_tsoh_block_free(struct efx_tx_queue *tx_queue,
  535. struct efx_tso_header *tsoh,
  536. struct pci_dev *pci_dev)
  537. {
  538. struct efx_tso_header **p;
  539. unsigned long base_kva;
  540. dma_addr_t base_dma;
  541. base_kva = (unsigned long)tsoh & PAGE_MASK;
  542. base_dma = tsoh->dma_addr & PAGE_MASK;
  543. p = &tx_queue->tso_headers_free;
  544. while (*p != NULL) {
  545. if (((unsigned long)*p & PAGE_MASK) == base_kva)
  546. *p = (*p)->next;
  547. else
  548. p = &(*p)->next;
  549. }
  550. pci_free_consistent(pci_dev, PAGE_SIZE, (void *)base_kva, base_dma);
  551. }
  552. static struct efx_tso_header *
  553. efx_tsoh_heap_alloc(struct efx_tx_queue *tx_queue, size_t header_len)
  554. {
  555. struct efx_tso_header *tsoh;
  556. tsoh = kmalloc(TSOH_SIZE(header_len), GFP_ATOMIC | GFP_DMA);
  557. if (unlikely(!tsoh))
  558. return NULL;
  559. tsoh->dma_addr = pci_map_single(tx_queue->efx->pci_dev,
  560. TSOH_BUFFER(tsoh), header_len,
  561. PCI_DMA_TODEVICE);
  562. if (unlikely(pci_dma_mapping_error(tsoh->dma_addr))) {
  563. kfree(tsoh);
  564. return NULL;
  565. }
  566. tsoh->unmap_len = header_len;
  567. return tsoh;
  568. }
  569. static void
  570. efx_tsoh_heap_free(struct efx_tx_queue *tx_queue, struct efx_tso_header *tsoh)
  571. {
  572. pci_unmap_single(tx_queue->efx->pci_dev,
  573. tsoh->dma_addr, tsoh->unmap_len,
  574. PCI_DMA_TODEVICE);
  575. kfree(tsoh);
  576. }
  577. /**
  578. * efx_tx_queue_insert - push descriptors onto the TX queue
  579. * @tx_queue: Efx TX queue
  580. * @dma_addr: DMA address of fragment
  581. * @len: Length of fragment
  582. * @skb: Only non-null for end of last segment
  583. * @end_of_packet: True if last fragment in a packet
  584. * @unmap_addr: DMA address of fragment for unmapping
  585. * @unmap_len: Only set this in last segment of a fragment
  586. *
  587. * Push descriptors onto the TX queue. Return 0 on success or 1 if
  588. * @tx_queue full.
  589. */
  590. static int efx_tx_queue_insert(struct efx_tx_queue *tx_queue,
  591. dma_addr_t dma_addr, unsigned len,
  592. const struct sk_buff *skb, int end_of_packet,
  593. dma_addr_t unmap_addr, unsigned unmap_len)
  594. {
  595. struct efx_tx_buffer *buffer;
  596. struct efx_nic *efx = tx_queue->efx;
  597. unsigned dma_len, fill_level, insert_ptr, misalign;
  598. int q_space;
  599. EFX_BUG_ON_PARANOID(len <= 0);
  600. fill_level = tx_queue->insert_count - tx_queue->old_read_count;
  601. /* -1 as there is no way to represent all descriptors used */
  602. q_space = efx->type->txd_ring_mask - 1 - fill_level;
  603. while (1) {
  604. if (unlikely(q_space-- <= 0)) {
  605. /* It might be that completions have happened
  606. * since the xmit path last checked. Update
  607. * the xmit path's copy of read_count.
  608. */
  609. ++tx_queue->stopped;
  610. /* This memory barrier protects the change of
  611. * stopped from the access of read_count. */
  612. smp_mb();
  613. tx_queue->old_read_count =
  614. *(volatile unsigned *)&tx_queue->read_count;
  615. fill_level = (tx_queue->insert_count
  616. - tx_queue->old_read_count);
  617. q_space = efx->type->txd_ring_mask - 1 - fill_level;
  618. if (unlikely(q_space-- <= 0))
  619. return 1;
  620. smp_mb();
  621. --tx_queue->stopped;
  622. }
  623. insert_ptr = tx_queue->insert_count & efx->type->txd_ring_mask;
  624. buffer = &tx_queue->buffer[insert_ptr];
  625. ++tx_queue->insert_count;
  626. EFX_BUG_ON_PARANOID(tx_queue->insert_count -
  627. tx_queue->read_count >
  628. efx->type->txd_ring_mask);
  629. efx_tsoh_free(tx_queue, buffer);
  630. EFX_BUG_ON_PARANOID(buffer->len);
  631. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  632. EFX_BUG_ON_PARANOID(buffer->skb);
  633. EFX_BUG_ON_PARANOID(buffer->continuation != 1);
  634. EFX_BUG_ON_PARANOID(buffer->tsoh);
  635. buffer->dma_addr = dma_addr;
  636. /* Ensure we do not cross a boundary unsupported by H/W */
  637. dma_len = (~dma_addr & efx->type->tx_dma_mask) + 1;
  638. misalign = (unsigned)dma_addr & efx->type->bug5391_mask;
  639. if (misalign && dma_len + misalign > 512)
  640. dma_len = 512 - misalign;
  641. /* If there is enough space to send then do so */
  642. if (dma_len >= len)
  643. break;
  644. buffer->len = dma_len; /* Don't set the other members */
  645. dma_addr += dma_len;
  646. len -= dma_len;
  647. }
  648. EFX_BUG_ON_PARANOID(!len);
  649. buffer->len = len;
  650. buffer->skb = skb;
  651. buffer->continuation = !end_of_packet;
  652. buffer->unmap_addr = unmap_addr;
  653. buffer->unmap_len = unmap_len;
  654. return 0;
  655. }
  656. /*
  657. * Put a TSO header into the TX queue.
  658. *
  659. * This is special-cased because we know that it is small enough to fit in
  660. * a single fragment, and we know it doesn't cross a page boundary. It
  661. * also allows us to not worry about end-of-packet etc.
  662. */
  663. static inline void efx_tso_put_header(struct efx_tx_queue *tx_queue,
  664. struct efx_tso_header *tsoh, unsigned len)
  665. {
  666. struct efx_tx_buffer *buffer;
  667. buffer = &tx_queue->buffer[tx_queue->insert_count &
  668. tx_queue->efx->type->txd_ring_mask];
  669. efx_tsoh_free(tx_queue, buffer);
  670. EFX_BUG_ON_PARANOID(buffer->len);
  671. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  672. EFX_BUG_ON_PARANOID(buffer->skb);
  673. EFX_BUG_ON_PARANOID(buffer->continuation != 1);
  674. EFX_BUG_ON_PARANOID(buffer->tsoh);
  675. buffer->len = len;
  676. buffer->dma_addr = tsoh->dma_addr;
  677. buffer->tsoh = tsoh;
  678. ++tx_queue->insert_count;
  679. }
  680. /* Remove descriptors put into a tx_queue. */
  681. static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue)
  682. {
  683. struct efx_tx_buffer *buffer;
  684. /* Work backwards until we hit the original insert pointer value */
  685. while (tx_queue->insert_count != tx_queue->write_count) {
  686. --tx_queue->insert_count;
  687. buffer = &tx_queue->buffer[tx_queue->insert_count &
  688. tx_queue->efx->type->txd_ring_mask];
  689. efx_tsoh_free(tx_queue, buffer);
  690. EFX_BUG_ON_PARANOID(buffer->skb);
  691. buffer->len = 0;
  692. buffer->continuation = 1;
  693. if (buffer->unmap_len) {
  694. pci_unmap_page(tx_queue->efx->pci_dev,
  695. buffer->unmap_addr,
  696. buffer->unmap_len, PCI_DMA_TODEVICE);
  697. buffer->unmap_len = 0;
  698. }
  699. }
  700. }
  701. /* Parse the SKB header and initialise state. */
  702. static inline void tso_start(struct tso_state *st, const struct sk_buff *skb)
  703. {
  704. /* All ethernet/IP/TCP headers combined size is TCP header size
  705. * plus offset of TCP header relative to start of packet.
  706. */
  707. st->p.header_length = ((tcp_hdr(skb)->doff << 2u)
  708. + PTR_DIFF(tcp_hdr(skb), skb->data));
  709. st->p.full_packet_size = (st->p.header_length
  710. + skb_shinfo(skb)->gso_size);
  711. st->p.ipv4_id = ntohs(ip_hdr(skb)->id);
  712. st->seqnum = ntohl(tcp_hdr(skb)->seq);
  713. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->urg);
  714. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->syn);
  715. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->rst);
  716. st->packet_space = st->p.full_packet_size;
  717. st->remaining_len = skb->len - st->p.header_length;
  718. }
  719. /**
  720. * tso_get_fragment - record fragment details and map for DMA
  721. * @st: TSO state
  722. * @efx: Efx NIC
  723. * @data: Pointer to fragment data
  724. * @len: Length of fragment
  725. *
  726. * Record fragment details and map for DMA. Return 0 on success, or
  727. * -%ENOMEM if DMA mapping fails.
  728. */
  729. static inline int tso_get_fragment(struct tso_state *st, struct efx_nic *efx,
  730. int len, struct page *page, int page_off)
  731. {
  732. st->ifc.unmap_addr = pci_map_page(efx->pci_dev, page, page_off,
  733. len, PCI_DMA_TODEVICE);
  734. if (likely(!pci_dma_mapping_error(st->ifc.unmap_addr))) {
  735. st->ifc.unmap_len = len;
  736. st->ifc.len = len;
  737. st->ifc.dma_addr = st->ifc.unmap_addr;
  738. st->ifc.page = page;
  739. st->ifc.page_off = page_off;
  740. return 0;
  741. }
  742. return -ENOMEM;
  743. }
  744. /**
  745. * tso_fill_packet_with_fragment - form descriptors for the current fragment
  746. * @tx_queue: Efx TX queue
  747. * @skb: Socket buffer
  748. * @st: TSO state
  749. *
  750. * Form descriptors for the current fragment, until we reach the end
  751. * of fragment or end-of-packet. Return 0 on success, 1 if not enough
  752. * space in @tx_queue.
  753. */
  754. static inline int tso_fill_packet_with_fragment(struct efx_tx_queue *tx_queue,
  755. const struct sk_buff *skb,
  756. struct tso_state *st)
  757. {
  758. int n, end_of_packet, rc;
  759. if (st->ifc.len == 0)
  760. return 0;
  761. if (st->packet_space == 0)
  762. return 0;
  763. EFX_BUG_ON_PARANOID(st->ifc.len <= 0);
  764. EFX_BUG_ON_PARANOID(st->packet_space <= 0);
  765. n = min(st->ifc.len, st->packet_space);
  766. st->packet_space -= n;
  767. st->remaining_len -= n;
  768. st->ifc.len -= n;
  769. st->ifc.page_off += n;
  770. end_of_packet = st->remaining_len == 0 || st->packet_space == 0;
  771. rc = efx_tx_queue_insert(tx_queue, st->ifc.dma_addr, n,
  772. st->remaining_len ? NULL : skb,
  773. end_of_packet, st->ifc.unmap_addr,
  774. st->ifc.len ? 0 : st->ifc.unmap_len);
  775. st->ifc.dma_addr += n;
  776. return rc;
  777. }
  778. /**
  779. * tso_start_new_packet - generate a new header and prepare for the new packet
  780. * @tx_queue: Efx TX queue
  781. * @skb: Socket buffer
  782. * @st: TSO state
  783. *
  784. * Generate a new header and prepare for the new packet. Return 0 on
  785. * success, or -1 if failed to alloc header.
  786. */
  787. static inline int tso_start_new_packet(struct efx_tx_queue *tx_queue,
  788. const struct sk_buff *skb,
  789. struct tso_state *st)
  790. {
  791. struct efx_tso_header *tsoh;
  792. struct iphdr *tsoh_iph;
  793. struct tcphdr *tsoh_th;
  794. unsigned ip_length;
  795. u8 *header;
  796. /* Allocate a DMA-mapped header buffer. */
  797. if (likely(TSOH_SIZE(st->p.header_length) <= TSOH_STD_SIZE)) {
  798. if (tx_queue->tso_headers_free == NULL) {
  799. if (efx_tsoh_block_alloc(tx_queue))
  800. return -1;
  801. }
  802. EFX_BUG_ON_PARANOID(!tx_queue->tso_headers_free);
  803. tsoh = tx_queue->tso_headers_free;
  804. tx_queue->tso_headers_free = tsoh->next;
  805. tsoh->unmap_len = 0;
  806. } else {
  807. tx_queue->tso_long_headers++;
  808. tsoh = efx_tsoh_heap_alloc(tx_queue, st->p.header_length);
  809. if (unlikely(!tsoh))
  810. return -1;
  811. }
  812. header = TSOH_BUFFER(tsoh);
  813. tsoh_th = (struct tcphdr *)(header + SKB_TCP_OFF(skb));
  814. tsoh_iph = (struct iphdr *)(header + SKB_IPV4_OFF(skb));
  815. /* Copy and update the headers. */
  816. memcpy(header, skb->data, st->p.header_length);
  817. tsoh_th->seq = htonl(st->seqnum);
  818. st->seqnum += skb_shinfo(skb)->gso_size;
  819. if (st->remaining_len > skb_shinfo(skb)->gso_size) {
  820. /* This packet will not finish the TSO burst. */
  821. ip_length = st->p.full_packet_size - ETH_HDR_LEN(skb);
  822. tsoh_th->fin = 0;
  823. tsoh_th->psh = 0;
  824. } else {
  825. /* This packet will be the last in the TSO burst. */
  826. ip_length = (st->p.header_length - ETH_HDR_LEN(skb)
  827. + st->remaining_len);
  828. tsoh_th->fin = tcp_hdr(skb)->fin;
  829. tsoh_th->psh = tcp_hdr(skb)->psh;
  830. }
  831. tsoh_iph->tot_len = htons(ip_length);
  832. /* Linux leaves suitable gaps in the IP ID space for us to fill. */
  833. tsoh_iph->id = htons(st->p.ipv4_id);
  834. st->p.ipv4_id++;
  835. st->packet_space = skb_shinfo(skb)->gso_size;
  836. ++tx_queue->tso_packets;
  837. /* Form a descriptor for this header. */
  838. efx_tso_put_header(tx_queue, tsoh, st->p.header_length);
  839. return 0;
  840. }
  841. /**
  842. * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer
  843. * @tx_queue: Efx TX queue
  844. * @skb: Socket buffer
  845. *
  846. * Context: You must hold netif_tx_lock() to call this function.
  847. *
  848. * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if
  849. * @skb was not enqueued. In all cases @skb is consumed. Return
  850. * %NETDEV_TX_OK or %NETDEV_TX_BUSY.
  851. */
  852. static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
  853. const struct sk_buff *skb)
  854. {
  855. int frag_i, rc, rc2 = NETDEV_TX_OK;
  856. struct tso_state state;
  857. skb_frag_t *f;
  858. /* Verify TSO is safe - these checks should never fail. */
  859. efx_tso_check_safe(skb);
  860. EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
  861. tso_start(&state, skb);
  862. /* Assume that skb header area contains exactly the headers, and
  863. * all payload is in the frag list.
  864. */
  865. if (skb_headlen(skb) == state.p.header_length) {
  866. /* Grab the first payload fragment. */
  867. EFX_BUG_ON_PARANOID(skb_shinfo(skb)->nr_frags < 1);
  868. frag_i = 0;
  869. f = &skb_shinfo(skb)->frags[frag_i];
  870. rc = tso_get_fragment(&state, tx_queue->efx,
  871. f->size, f->page, f->page_offset);
  872. if (rc)
  873. goto mem_err;
  874. } else {
  875. /* It may look like this code fragment assumes that the
  876. * skb->data portion does not cross a page boundary, but
  877. * that is not the case. It is guaranteed to be direct
  878. * mapped memory, and therefore is physically contiguous,
  879. * and so DMA will work fine. kmap_atomic() on this region
  880. * will just return the direct mapping, so that will work
  881. * too.
  882. */
  883. int page_off = (unsigned long)skb->data & (PAGE_SIZE - 1);
  884. int hl = state.p.header_length;
  885. rc = tso_get_fragment(&state, tx_queue->efx,
  886. skb_headlen(skb) - hl,
  887. virt_to_page(skb->data), page_off + hl);
  888. if (rc)
  889. goto mem_err;
  890. frag_i = -1;
  891. }
  892. if (tso_start_new_packet(tx_queue, skb, &state) < 0)
  893. goto mem_err;
  894. while (1) {
  895. rc = tso_fill_packet_with_fragment(tx_queue, skb, &state);
  896. if (unlikely(rc))
  897. goto stop;
  898. /* Move onto the next fragment? */
  899. if (state.ifc.len == 0) {
  900. if (++frag_i >= skb_shinfo(skb)->nr_frags)
  901. /* End of payload reached. */
  902. break;
  903. f = &skb_shinfo(skb)->frags[frag_i];
  904. rc = tso_get_fragment(&state, tx_queue->efx,
  905. f->size, f->page, f->page_offset);
  906. if (rc)
  907. goto mem_err;
  908. }
  909. /* Start at new packet? */
  910. if (state.packet_space == 0 &&
  911. tso_start_new_packet(tx_queue, skb, &state) < 0)
  912. goto mem_err;
  913. }
  914. /* Pass off to hardware */
  915. falcon_push_buffers(tx_queue);
  916. tx_queue->tso_bursts++;
  917. return NETDEV_TX_OK;
  918. mem_err:
  919. EFX_ERR(tx_queue->efx, "Out of memory for TSO headers, or PCI mapping"
  920. " error\n");
  921. dev_kfree_skb_any((struct sk_buff *)skb);
  922. goto unwind;
  923. stop:
  924. rc2 = NETDEV_TX_BUSY;
  925. /* Stop the queue if it wasn't stopped before. */
  926. if (tx_queue->stopped == 1)
  927. efx_stop_queue(tx_queue->efx);
  928. unwind:
  929. efx_enqueue_unwind(tx_queue);
  930. return rc2;
  931. }
  932. /*
  933. * Free up all TSO datastructures associated with tx_queue. This
  934. * routine should be called only once the tx_queue is both empty and
  935. * will no longer be used.
  936. */
  937. static void efx_fini_tso(struct efx_tx_queue *tx_queue)
  938. {
  939. unsigned i;
  940. if (tx_queue->buffer) {
  941. for (i = 0; i <= tx_queue->efx->type->txd_ring_mask; ++i)
  942. efx_tsoh_free(tx_queue, &tx_queue->buffer[i]);
  943. }
  944. while (tx_queue->tso_headers_free != NULL)
  945. efx_tsoh_block_free(tx_queue, tx_queue->tso_headers_free,
  946. tx_queue->efx->pci_dev);
  947. }