atl1.c 100 KB

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  1. /*
  2. * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
  3. * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
  4. * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
  5. *
  6. * Derived from Intel e1000 driver
  7. * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the Free
  11. * Software Foundation; either version 2 of the License, or (at your option)
  12. * any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful, but WITHOUT
  15. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  17. * more details.
  18. *
  19. * You should have received a copy of the GNU General Public License along with
  20. * this program; if not, write to the Free Software Foundation, Inc., 59
  21. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22. *
  23. * The full GNU General Public License is included in this distribution in the
  24. * file called COPYING.
  25. *
  26. * Contact Information:
  27. * Xiong Huang <xiong_huang@attansic.com>
  28. * Attansic Technology Corp. 3F 147, Xianzheng 9th Road, Zhubei,
  29. * Xinzhu 302, TAIWAN, REPUBLIC OF CHINA
  30. *
  31. * Chris Snook <csnook@redhat.com>
  32. * Jay Cliburn <jcliburn@gmail.com>
  33. *
  34. * This version is adapted from the Attansic reference driver for
  35. * inclusion in the Linux kernel. It is currently under heavy development.
  36. * A very incomplete list of things that need to be dealt with:
  37. *
  38. * TODO:
  39. * Add more ethtool functions.
  40. * Fix abstruse irq enable/disable condition described here:
  41. * http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2
  42. *
  43. * NEEDS TESTING:
  44. * VLAN
  45. * multicast
  46. * promiscuous mode
  47. * interrupt coalescing
  48. * SMP torture testing
  49. */
  50. #include <asm/atomic.h>
  51. #include <asm/byteorder.h>
  52. #include <linux/compiler.h>
  53. #include <linux/crc32.h>
  54. #include <linux/delay.h>
  55. #include <linux/dma-mapping.h>
  56. #include <linux/etherdevice.h>
  57. #include <linux/hardirq.h>
  58. #include <linux/if_ether.h>
  59. #include <linux/if_vlan.h>
  60. #include <linux/in.h>
  61. #include <linux/interrupt.h>
  62. #include <linux/ip.h>
  63. #include <linux/irqflags.h>
  64. #include <linux/irqreturn.h>
  65. #include <linux/jiffies.h>
  66. #include <linux/mii.h>
  67. #include <linux/module.h>
  68. #include <linux/moduleparam.h>
  69. #include <linux/net.h>
  70. #include <linux/netdevice.h>
  71. #include <linux/pci.h>
  72. #include <linux/pci_ids.h>
  73. #include <linux/pm.h>
  74. #include <linux/skbuff.h>
  75. #include <linux/slab.h>
  76. #include <linux/spinlock.h>
  77. #include <linux/string.h>
  78. #include <linux/tcp.h>
  79. #include <linux/timer.h>
  80. #include <linux/types.h>
  81. #include <linux/workqueue.h>
  82. #include <net/checksum.h>
  83. #include "atl1.h"
  84. /* Temporary hack for merging atl1 and atl2 */
  85. #include "atlx.c"
  86. /*
  87. * This is the only thing that needs to be changed to adjust the
  88. * maximum number of ports that the driver can manage.
  89. */
  90. #define ATL1_MAX_NIC 4
  91. #define OPTION_UNSET -1
  92. #define OPTION_DISABLED 0
  93. #define OPTION_ENABLED 1
  94. #define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET }
  95. /*
  96. * Interrupt Moderate Timer in units of 2 us
  97. *
  98. * Valid Range: 10-65535
  99. *
  100. * Default Value: 100 (200us)
  101. */
  102. static int __devinitdata int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
  103. static int num_int_mod_timer;
  104. module_param_array_named(int_mod_timer, int_mod_timer, int,
  105. &num_int_mod_timer, 0);
  106. MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer");
  107. #define DEFAULT_INT_MOD_CNT 100 /* 200us */
  108. #define MAX_INT_MOD_CNT 65000
  109. #define MIN_INT_MOD_CNT 50
  110. struct atl1_option {
  111. enum { enable_option, range_option, list_option } type;
  112. char *name;
  113. char *err;
  114. int def;
  115. union {
  116. struct { /* range_option info */
  117. int min;
  118. int max;
  119. } r;
  120. struct { /* list_option info */
  121. int nr;
  122. struct atl1_opt_list {
  123. int i;
  124. char *str;
  125. } *p;
  126. } l;
  127. } arg;
  128. };
  129. static int __devinit atl1_validate_option(int *value, struct atl1_option *opt,
  130. struct pci_dev *pdev)
  131. {
  132. if (*value == OPTION_UNSET) {
  133. *value = opt->def;
  134. return 0;
  135. }
  136. switch (opt->type) {
  137. case enable_option:
  138. switch (*value) {
  139. case OPTION_ENABLED:
  140. dev_info(&pdev->dev, "%s enabled\n", opt->name);
  141. return 0;
  142. case OPTION_DISABLED:
  143. dev_info(&pdev->dev, "%s disabled\n", opt->name);
  144. return 0;
  145. }
  146. break;
  147. case range_option:
  148. if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
  149. dev_info(&pdev->dev, "%s set to %i\n", opt->name,
  150. *value);
  151. return 0;
  152. }
  153. break;
  154. case list_option:{
  155. int i;
  156. struct atl1_opt_list *ent;
  157. for (i = 0; i < opt->arg.l.nr; i++) {
  158. ent = &opt->arg.l.p[i];
  159. if (*value == ent->i) {
  160. if (ent->str[0] != '\0')
  161. dev_info(&pdev->dev, "%s\n",
  162. ent->str);
  163. return 0;
  164. }
  165. }
  166. }
  167. break;
  168. default:
  169. break;
  170. }
  171. dev_info(&pdev->dev, "invalid %s specified (%i) %s\n",
  172. opt->name, *value, opt->err);
  173. *value = opt->def;
  174. return -1;
  175. }
  176. /*
  177. * atl1_check_options - Range Checking for Command Line Parameters
  178. * @adapter: board private structure
  179. *
  180. * This routine checks all command line parameters for valid user
  181. * input. If an invalid value is given, or if no user specified
  182. * value exists, a default value is used. The final value is stored
  183. * in a variable in the adapter structure.
  184. */
  185. void __devinit atl1_check_options(struct atl1_adapter *adapter)
  186. {
  187. struct pci_dev *pdev = adapter->pdev;
  188. int bd = adapter->bd_number;
  189. if (bd >= ATL1_MAX_NIC) {
  190. dev_notice(&pdev->dev, "no configuration for board#%i\n", bd);
  191. dev_notice(&pdev->dev, "using defaults for all values\n");
  192. }
  193. { /* Interrupt Moderate Timer */
  194. struct atl1_option opt = {
  195. .type = range_option,
  196. .name = "Interrupt Moderator Timer",
  197. .err = "using default of "
  198. __MODULE_STRING(DEFAULT_INT_MOD_CNT),
  199. .def = DEFAULT_INT_MOD_CNT,
  200. .arg = {.r = {.min = MIN_INT_MOD_CNT,
  201. .max = MAX_INT_MOD_CNT} }
  202. };
  203. int val;
  204. if (num_int_mod_timer > bd) {
  205. val = int_mod_timer[bd];
  206. atl1_validate_option(&val, &opt, pdev);
  207. adapter->imt = (u16) val;
  208. } else
  209. adapter->imt = (u16) (opt.def);
  210. }
  211. }
  212. /*
  213. * atl1_pci_tbl - PCI Device ID Table
  214. */
  215. static const struct pci_device_id atl1_pci_tbl[] = {
  216. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1)},
  217. /* required last entry */
  218. {0,}
  219. };
  220. MODULE_DEVICE_TABLE(pci, atl1_pci_tbl);
  221. static const u32 atl1_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
  222. NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
  223. static int debug = -1;
  224. module_param(debug, int, 0);
  225. MODULE_PARM_DESC(debug, "Message level (0=none,...,16=all)");
  226. /*
  227. * Reset the transmit and receive units; mask and clear all interrupts.
  228. * hw - Struct containing variables accessed by shared code
  229. * return : 0 or idle status (if error)
  230. */
  231. static s32 atl1_reset_hw(struct atl1_hw *hw)
  232. {
  233. struct pci_dev *pdev = hw->back->pdev;
  234. struct atl1_adapter *adapter = hw->back;
  235. u32 icr;
  236. int i;
  237. /*
  238. * Clear Interrupt mask to stop board from generating
  239. * interrupts & Clear any pending interrupt events
  240. */
  241. /*
  242. * iowrite32(0, hw->hw_addr + REG_IMR);
  243. * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
  244. */
  245. /*
  246. * Issue Soft Reset to the MAC. This will reset the chip's
  247. * transmit, receive, DMA. It will not effect
  248. * the current PCI configuration. The global reset bit is self-
  249. * clearing, and should clear within a microsecond.
  250. */
  251. iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
  252. ioread32(hw->hw_addr + REG_MASTER_CTRL);
  253. iowrite16(1, hw->hw_addr + REG_PHY_ENABLE);
  254. ioread16(hw->hw_addr + REG_PHY_ENABLE);
  255. /* delay about 1ms */
  256. msleep(1);
  257. /* Wait at least 10ms for All module to be Idle */
  258. for (i = 0; i < 10; i++) {
  259. icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
  260. if (!icr)
  261. break;
  262. /* delay 1 ms */
  263. msleep(1);
  264. /* FIXME: still the right way to do this? */
  265. cpu_relax();
  266. }
  267. if (icr) {
  268. if (netif_msg_hw(adapter))
  269. dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
  270. return icr;
  271. }
  272. return 0;
  273. }
  274. /* function about EEPROM
  275. *
  276. * check_eeprom_exist
  277. * return 0 if eeprom exist
  278. */
  279. static int atl1_check_eeprom_exist(struct atl1_hw *hw)
  280. {
  281. u32 value;
  282. value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
  283. if (value & SPI_FLASH_CTRL_EN_VPD) {
  284. value &= ~SPI_FLASH_CTRL_EN_VPD;
  285. iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
  286. }
  287. value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
  288. return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
  289. }
  290. static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
  291. {
  292. int i;
  293. u32 control;
  294. if (offset & 3)
  295. /* address do not align */
  296. return false;
  297. iowrite32(0, hw->hw_addr + REG_VPD_DATA);
  298. control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
  299. iowrite32(control, hw->hw_addr + REG_VPD_CAP);
  300. ioread32(hw->hw_addr + REG_VPD_CAP);
  301. for (i = 0; i < 10; i++) {
  302. msleep(2);
  303. control = ioread32(hw->hw_addr + REG_VPD_CAP);
  304. if (control & VPD_CAP_VPD_FLAG)
  305. break;
  306. }
  307. if (control & VPD_CAP_VPD_FLAG) {
  308. *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
  309. return true;
  310. }
  311. /* timeout */
  312. return false;
  313. }
  314. /*
  315. * Reads the value from a PHY register
  316. * hw - Struct containing variables accessed by shared code
  317. * reg_addr - address of the PHY register to read
  318. */
  319. s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
  320. {
  321. u32 val;
  322. int i;
  323. val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
  324. MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
  325. MDIO_CLK_SEL_SHIFT;
  326. iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
  327. ioread32(hw->hw_addr + REG_MDIO_CTRL);
  328. for (i = 0; i < MDIO_WAIT_TIMES; i++) {
  329. udelay(2);
  330. val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
  331. if (!(val & (MDIO_START | MDIO_BUSY)))
  332. break;
  333. }
  334. if (!(val & (MDIO_START | MDIO_BUSY))) {
  335. *phy_data = (u16) val;
  336. return 0;
  337. }
  338. return ATLX_ERR_PHY;
  339. }
  340. #define CUSTOM_SPI_CS_SETUP 2
  341. #define CUSTOM_SPI_CLK_HI 2
  342. #define CUSTOM_SPI_CLK_LO 2
  343. #define CUSTOM_SPI_CS_HOLD 2
  344. #define CUSTOM_SPI_CS_HI 3
  345. static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
  346. {
  347. int i;
  348. u32 value;
  349. iowrite32(0, hw->hw_addr + REG_SPI_DATA);
  350. iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
  351. value = SPI_FLASH_CTRL_WAIT_READY |
  352. (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
  353. SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
  354. SPI_FLASH_CTRL_CLK_HI_MASK) <<
  355. SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
  356. SPI_FLASH_CTRL_CLK_LO_MASK) <<
  357. SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
  358. SPI_FLASH_CTRL_CS_HOLD_MASK) <<
  359. SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
  360. SPI_FLASH_CTRL_CS_HI_MASK) <<
  361. SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
  362. SPI_FLASH_CTRL_INS_SHIFT;
  363. iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
  364. value |= SPI_FLASH_CTRL_START;
  365. iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
  366. ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
  367. for (i = 0; i < 10; i++) {
  368. msleep(1);
  369. value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
  370. if (!(value & SPI_FLASH_CTRL_START))
  371. break;
  372. }
  373. if (value & SPI_FLASH_CTRL_START)
  374. return false;
  375. *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
  376. return true;
  377. }
  378. /*
  379. * get_permanent_address
  380. * return 0 if get valid mac address,
  381. */
  382. static int atl1_get_permanent_address(struct atl1_hw *hw)
  383. {
  384. u32 addr[2];
  385. u32 i, control;
  386. u16 reg;
  387. u8 eth_addr[ETH_ALEN];
  388. bool key_valid;
  389. if (is_valid_ether_addr(hw->perm_mac_addr))
  390. return 0;
  391. /* init */
  392. addr[0] = addr[1] = 0;
  393. if (!atl1_check_eeprom_exist(hw)) {
  394. reg = 0;
  395. key_valid = false;
  396. /* Read out all EEPROM content */
  397. i = 0;
  398. while (1) {
  399. if (atl1_read_eeprom(hw, i + 0x100, &control)) {
  400. if (key_valid) {
  401. if (reg == REG_MAC_STA_ADDR)
  402. addr[0] = control;
  403. else if (reg == (REG_MAC_STA_ADDR + 4))
  404. addr[1] = control;
  405. key_valid = false;
  406. } else if ((control & 0xff) == 0x5A) {
  407. key_valid = true;
  408. reg = (u16) (control >> 16);
  409. } else
  410. break;
  411. } else
  412. /* read error */
  413. break;
  414. i += 4;
  415. }
  416. *(u32 *) &eth_addr[2] = swab32(addr[0]);
  417. *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
  418. if (is_valid_ether_addr(eth_addr)) {
  419. memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
  420. return 0;
  421. }
  422. }
  423. /* see if SPI FLAGS exist ? */
  424. addr[0] = addr[1] = 0;
  425. reg = 0;
  426. key_valid = false;
  427. i = 0;
  428. while (1) {
  429. if (atl1_spi_read(hw, i + 0x1f000, &control)) {
  430. if (key_valid) {
  431. if (reg == REG_MAC_STA_ADDR)
  432. addr[0] = control;
  433. else if (reg == (REG_MAC_STA_ADDR + 4))
  434. addr[1] = control;
  435. key_valid = false;
  436. } else if ((control & 0xff) == 0x5A) {
  437. key_valid = true;
  438. reg = (u16) (control >> 16);
  439. } else
  440. /* data end */
  441. break;
  442. } else
  443. /* read error */
  444. break;
  445. i += 4;
  446. }
  447. *(u32 *) &eth_addr[2] = swab32(addr[0]);
  448. *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
  449. if (is_valid_ether_addr(eth_addr)) {
  450. memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
  451. return 0;
  452. }
  453. /*
  454. * On some motherboards, the MAC address is written by the
  455. * BIOS directly to the MAC register during POST, and is
  456. * not stored in eeprom. If all else thus far has failed
  457. * to fetch the permanent MAC address, try reading it directly.
  458. */
  459. addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
  460. addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
  461. *(u32 *) &eth_addr[2] = swab32(addr[0]);
  462. *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
  463. if (is_valid_ether_addr(eth_addr)) {
  464. memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
  465. return 0;
  466. }
  467. return 1;
  468. }
  469. /*
  470. * Reads the adapter's MAC address from the EEPROM
  471. * hw - Struct containing variables accessed by shared code
  472. */
  473. s32 atl1_read_mac_addr(struct atl1_hw *hw)
  474. {
  475. u16 i;
  476. if (atl1_get_permanent_address(hw))
  477. random_ether_addr(hw->perm_mac_addr);
  478. for (i = 0; i < ETH_ALEN; i++)
  479. hw->mac_addr[i] = hw->perm_mac_addr[i];
  480. return 0;
  481. }
  482. /*
  483. * Hashes an address to determine its location in the multicast table
  484. * hw - Struct containing variables accessed by shared code
  485. * mc_addr - the multicast address to hash
  486. *
  487. * atl1_hash_mc_addr
  488. * purpose
  489. * set hash value for a multicast address
  490. * hash calcu processing :
  491. * 1. calcu 32bit CRC for multicast address
  492. * 2. reverse crc with MSB to LSB
  493. */
  494. u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
  495. {
  496. u32 crc32, value = 0;
  497. int i;
  498. crc32 = ether_crc_le(6, mc_addr);
  499. for (i = 0; i < 32; i++)
  500. value |= (((crc32 >> i) & 1) << (31 - i));
  501. return value;
  502. }
  503. /*
  504. * Sets the bit in the multicast table corresponding to the hash value.
  505. * hw - Struct containing variables accessed by shared code
  506. * hash_value - Multicast address hash value
  507. */
  508. void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
  509. {
  510. u32 hash_bit, hash_reg;
  511. u32 mta;
  512. /*
  513. * The HASH Table is a register array of 2 32-bit registers.
  514. * It is treated like an array of 64 bits. We want to set
  515. * bit BitArray[hash_value]. So we figure out what register
  516. * the bit is in, read it, OR in the new bit, then write
  517. * back the new value. The register is determined by the
  518. * upper 7 bits of the hash value and the bit within that
  519. * register are determined by the lower 5 bits of the value.
  520. */
  521. hash_reg = (hash_value >> 31) & 0x1;
  522. hash_bit = (hash_value >> 26) & 0x1F;
  523. mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
  524. mta |= (1 << hash_bit);
  525. iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
  526. }
  527. /*
  528. * Writes a value to a PHY register
  529. * hw - Struct containing variables accessed by shared code
  530. * reg_addr - address of the PHY register to write
  531. * data - data to write to the PHY
  532. */
  533. static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
  534. {
  535. int i;
  536. u32 val;
  537. val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
  538. (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
  539. MDIO_SUP_PREAMBLE |
  540. MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
  541. iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
  542. ioread32(hw->hw_addr + REG_MDIO_CTRL);
  543. for (i = 0; i < MDIO_WAIT_TIMES; i++) {
  544. udelay(2);
  545. val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
  546. if (!(val & (MDIO_START | MDIO_BUSY)))
  547. break;
  548. }
  549. if (!(val & (MDIO_START | MDIO_BUSY)))
  550. return 0;
  551. return ATLX_ERR_PHY;
  552. }
  553. /*
  554. * Make L001's PHY out of Power Saving State (bug)
  555. * hw - Struct containing variables accessed by shared code
  556. * when power on, L001's PHY always on Power saving State
  557. * (Gigabit Link forbidden)
  558. */
  559. static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
  560. {
  561. s32 ret;
  562. ret = atl1_write_phy_reg(hw, 29, 0x0029);
  563. if (ret)
  564. return ret;
  565. return atl1_write_phy_reg(hw, 30, 0);
  566. }
  567. /*
  568. * Resets the PHY and make all config validate
  569. * hw - Struct containing variables accessed by shared code
  570. *
  571. * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
  572. */
  573. static s32 atl1_phy_reset(struct atl1_hw *hw)
  574. {
  575. struct pci_dev *pdev = hw->back->pdev;
  576. struct atl1_adapter *adapter = hw->back;
  577. s32 ret_val;
  578. u16 phy_data;
  579. if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
  580. hw->media_type == MEDIA_TYPE_1000M_FULL)
  581. phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
  582. else {
  583. switch (hw->media_type) {
  584. case MEDIA_TYPE_100M_FULL:
  585. phy_data =
  586. MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
  587. MII_CR_RESET;
  588. break;
  589. case MEDIA_TYPE_100M_HALF:
  590. phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
  591. break;
  592. case MEDIA_TYPE_10M_FULL:
  593. phy_data =
  594. MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
  595. break;
  596. default:
  597. /* MEDIA_TYPE_10M_HALF: */
  598. phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
  599. break;
  600. }
  601. }
  602. ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
  603. if (ret_val) {
  604. u32 val;
  605. int i;
  606. /* pcie serdes link may be down! */
  607. if (netif_msg_hw(adapter))
  608. dev_dbg(&pdev->dev, "pcie phy link down\n");
  609. for (i = 0; i < 25; i++) {
  610. msleep(1);
  611. val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
  612. if (!(val & (MDIO_START | MDIO_BUSY)))
  613. break;
  614. }
  615. if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
  616. if (netif_msg_hw(adapter))
  617. dev_warn(&pdev->dev,
  618. "pcie link down at least 25ms\n");
  619. return ret_val;
  620. }
  621. }
  622. return 0;
  623. }
  624. /*
  625. * Configures PHY autoneg and flow control advertisement settings
  626. * hw - Struct containing variables accessed by shared code
  627. */
  628. static s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
  629. {
  630. s32 ret_val;
  631. s16 mii_autoneg_adv_reg;
  632. s16 mii_1000t_ctrl_reg;
  633. /* Read the MII Auto-Neg Advertisement Register (Address 4). */
  634. mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
  635. /* Read the MII 1000Base-T Control Register (Address 9). */
  636. mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK;
  637. /*
  638. * First we clear all the 10/100 mb speed bits in the Auto-Neg
  639. * Advertisement Register (Address 4) and the 1000 mb speed bits in
  640. * the 1000Base-T Control Register (Address 9).
  641. */
  642. mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
  643. mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK;
  644. /*
  645. * Need to parse media_type and set up
  646. * the appropriate PHY registers.
  647. */
  648. switch (hw->media_type) {
  649. case MEDIA_TYPE_AUTO_SENSOR:
  650. mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
  651. MII_AR_10T_FD_CAPS |
  652. MII_AR_100TX_HD_CAPS |
  653. MII_AR_100TX_FD_CAPS);
  654. mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
  655. break;
  656. case MEDIA_TYPE_1000M_FULL:
  657. mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
  658. break;
  659. case MEDIA_TYPE_100M_FULL:
  660. mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
  661. break;
  662. case MEDIA_TYPE_100M_HALF:
  663. mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
  664. break;
  665. case MEDIA_TYPE_10M_FULL:
  666. mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
  667. break;
  668. default:
  669. mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
  670. break;
  671. }
  672. /* flow control fixed to enable all */
  673. mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
  674. hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
  675. hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
  676. ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
  677. if (ret_val)
  678. return ret_val;
  679. ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg);
  680. if (ret_val)
  681. return ret_val;
  682. return 0;
  683. }
  684. /*
  685. * Configures link settings.
  686. * hw - Struct containing variables accessed by shared code
  687. * Assumes the hardware has previously been reset and the
  688. * transmitter and receiver are not enabled.
  689. */
  690. static s32 atl1_setup_link(struct atl1_hw *hw)
  691. {
  692. struct pci_dev *pdev = hw->back->pdev;
  693. struct atl1_adapter *adapter = hw->back;
  694. s32 ret_val;
  695. /*
  696. * Options:
  697. * PHY will advertise value(s) parsed from
  698. * autoneg_advertised and fc
  699. * no matter what autoneg is , We will not wait link result.
  700. */
  701. ret_val = atl1_phy_setup_autoneg_adv(hw);
  702. if (ret_val) {
  703. if (netif_msg_link(adapter))
  704. dev_dbg(&pdev->dev,
  705. "error setting up autonegotiation\n");
  706. return ret_val;
  707. }
  708. /* SW.Reset , En-Auto-Neg if needed */
  709. ret_val = atl1_phy_reset(hw);
  710. if (ret_val) {
  711. if (netif_msg_link(adapter))
  712. dev_dbg(&pdev->dev, "error resetting phy\n");
  713. return ret_val;
  714. }
  715. hw->phy_configured = true;
  716. return ret_val;
  717. }
  718. static void atl1_init_flash_opcode(struct atl1_hw *hw)
  719. {
  720. if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
  721. /* Atmel */
  722. hw->flash_vendor = 0;
  723. /* Init OP table */
  724. iowrite8(flash_table[hw->flash_vendor].cmd_program,
  725. hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
  726. iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
  727. hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
  728. iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
  729. hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
  730. iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
  731. hw->hw_addr + REG_SPI_FLASH_OP_RDID);
  732. iowrite8(flash_table[hw->flash_vendor].cmd_wren,
  733. hw->hw_addr + REG_SPI_FLASH_OP_WREN);
  734. iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
  735. hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
  736. iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
  737. hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
  738. iowrite8(flash_table[hw->flash_vendor].cmd_read,
  739. hw->hw_addr + REG_SPI_FLASH_OP_READ);
  740. }
  741. /*
  742. * Performs basic configuration of the adapter.
  743. * hw - Struct containing variables accessed by shared code
  744. * Assumes that the controller has previously been reset and is in a
  745. * post-reset uninitialized state. Initializes multicast table,
  746. * and Calls routines to setup link
  747. * Leaves the transmit and receive units disabled and uninitialized.
  748. */
  749. static s32 atl1_init_hw(struct atl1_hw *hw)
  750. {
  751. u32 ret_val = 0;
  752. /* Zero out the Multicast HASH table */
  753. iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
  754. /* clear the old settings from the multicast hash table */
  755. iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
  756. atl1_init_flash_opcode(hw);
  757. if (!hw->phy_configured) {
  758. /* enable GPHY LinkChange Interrrupt */
  759. ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
  760. if (ret_val)
  761. return ret_val;
  762. /* make PHY out of power-saving state */
  763. ret_val = atl1_phy_leave_power_saving(hw);
  764. if (ret_val)
  765. return ret_val;
  766. /* Call a subroutine to configure the link */
  767. ret_val = atl1_setup_link(hw);
  768. }
  769. return ret_val;
  770. }
  771. /*
  772. * Detects the current speed and duplex settings of the hardware.
  773. * hw - Struct containing variables accessed by shared code
  774. * speed - Speed of the connection
  775. * duplex - Duplex setting of the connection
  776. */
  777. static s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
  778. {
  779. struct pci_dev *pdev = hw->back->pdev;
  780. struct atl1_adapter *adapter = hw->back;
  781. s32 ret_val;
  782. u16 phy_data;
  783. /* ; --- Read PHY Specific Status Register (17) */
  784. ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
  785. if (ret_val)
  786. return ret_val;
  787. if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
  788. return ATLX_ERR_PHY_RES;
  789. switch (phy_data & MII_ATLX_PSSR_SPEED) {
  790. case MII_ATLX_PSSR_1000MBS:
  791. *speed = SPEED_1000;
  792. break;
  793. case MII_ATLX_PSSR_100MBS:
  794. *speed = SPEED_100;
  795. break;
  796. case MII_ATLX_PSSR_10MBS:
  797. *speed = SPEED_10;
  798. break;
  799. default:
  800. if (netif_msg_hw(adapter))
  801. dev_dbg(&pdev->dev, "error getting speed\n");
  802. return ATLX_ERR_PHY_SPEED;
  803. break;
  804. }
  805. if (phy_data & MII_ATLX_PSSR_DPLX)
  806. *duplex = FULL_DUPLEX;
  807. else
  808. *duplex = HALF_DUPLEX;
  809. return 0;
  810. }
  811. void atl1_set_mac_addr(struct atl1_hw *hw)
  812. {
  813. u32 value;
  814. /*
  815. * 00-0B-6A-F6-00-DC
  816. * 0: 6AF600DC 1: 000B
  817. * low dword
  818. */
  819. value = (((u32) hw->mac_addr[2]) << 24) |
  820. (((u32) hw->mac_addr[3]) << 16) |
  821. (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
  822. iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
  823. /* high dword */
  824. value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
  825. iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
  826. }
  827. /*
  828. * atl1_sw_init - Initialize general software structures (struct atl1_adapter)
  829. * @adapter: board private structure to initialize
  830. *
  831. * atl1_sw_init initializes the Adapter private data structure.
  832. * Fields are initialized based on PCI device information and
  833. * OS network device settings (MTU size).
  834. */
  835. static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
  836. {
  837. struct atl1_hw *hw = &adapter->hw;
  838. struct net_device *netdev = adapter->netdev;
  839. hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
  840. hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
  841. adapter->wol = 0;
  842. adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7;
  843. adapter->ict = 50000; /* 100ms */
  844. adapter->link_speed = SPEED_0; /* hardware init */
  845. adapter->link_duplex = FULL_DUPLEX;
  846. hw->phy_configured = false;
  847. hw->preamble_len = 7;
  848. hw->ipgt = 0x60;
  849. hw->min_ifg = 0x50;
  850. hw->ipgr1 = 0x40;
  851. hw->ipgr2 = 0x60;
  852. hw->max_retry = 0xf;
  853. hw->lcol = 0x37;
  854. hw->jam_ipg = 7;
  855. hw->rfd_burst = 8;
  856. hw->rrd_burst = 8;
  857. hw->rfd_fetch_gap = 1;
  858. hw->rx_jumbo_th = adapter->rx_buffer_len / 8;
  859. hw->rx_jumbo_lkah = 1;
  860. hw->rrd_ret_timer = 16;
  861. hw->tpd_burst = 4;
  862. hw->tpd_fetch_th = 16;
  863. hw->txf_burst = 0x100;
  864. hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3;
  865. hw->tpd_fetch_gap = 1;
  866. hw->rcb_value = atl1_rcb_64;
  867. hw->dma_ord = atl1_dma_ord_enh;
  868. hw->dmar_block = atl1_dma_req_256;
  869. hw->dmaw_block = atl1_dma_req_256;
  870. hw->cmb_rrd = 4;
  871. hw->cmb_tpd = 4;
  872. hw->cmb_rx_timer = 1; /* about 2us */
  873. hw->cmb_tx_timer = 1; /* about 2us */
  874. hw->smb_timer = 100000; /* about 200ms */
  875. spin_lock_init(&adapter->lock);
  876. spin_lock_init(&adapter->mb_lock);
  877. return 0;
  878. }
  879. static int mdio_read(struct net_device *netdev, int phy_id, int reg_num)
  880. {
  881. struct atl1_adapter *adapter = netdev_priv(netdev);
  882. u16 result;
  883. atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result);
  884. return result;
  885. }
  886. static void mdio_write(struct net_device *netdev, int phy_id, int reg_num,
  887. int val)
  888. {
  889. struct atl1_adapter *adapter = netdev_priv(netdev);
  890. atl1_write_phy_reg(&adapter->hw, reg_num, val);
  891. }
  892. /*
  893. * atl1_mii_ioctl -
  894. * @netdev:
  895. * @ifreq:
  896. * @cmd:
  897. */
  898. static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
  899. {
  900. struct atl1_adapter *adapter = netdev_priv(netdev);
  901. unsigned long flags;
  902. int retval;
  903. if (!netif_running(netdev))
  904. return -EINVAL;
  905. spin_lock_irqsave(&adapter->lock, flags);
  906. retval = generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
  907. spin_unlock_irqrestore(&adapter->lock, flags);
  908. return retval;
  909. }
  910. /*
  911. * atl1_setup_mem_resources - allocate Tx / RX descriptor resources
  912. * @adapter: board private structure
  913. *
  914. * Return 0 on success, negative on failure
  915. */
  916. static s32 atl1_setup_ring_resources(struct atl1_adapter *adapter)
  917. {
  918. struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
  919. struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
  920. struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
  921. struct atl1_ring_header *ring_header = &adapter->ring_header;
  922. struct pci_dev *pdev = adapter->pdev;
  923. int size;
  924. u8 offset = 0;
  925. size = sizeof(struct atl1_buffer) * (tpd_ring->count + rfd_ring->count);
  926. tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
  927. if (unlikely(!tpd_ring->buffer_info)) {
  928. if (netif_msg_drv(adapter))
  929. dev_err(&pdev->dev, "kzalloc failed , size = D%d\n",
  930. size);
  931. goto err_nomem;
  932. }
  933. rfd_ring->buffer_info =
  934. (struct atl1_buffer *)(tpd_ring->buffer_info + tpd_ring->count);
  935. /*
  936. * real ring DMA buffer
  937. * each ring/block may need up to 8 bytes for alignment, hence the
  938. * additional 40 bytes tacked onto the end.
  939. */
  940. ring_header->size = size =
  941. sizeof(struct tx_packet_desc) * tpd_ring->count
  942. + sizeof(struct rx_free_desc) * rfd_ring->count
  943. + sizeof(struct rx_return_desc) * rrd_ring->count
  944. + sizeof(struct coals_msg_block)
  945. + sizeof(struct stats_msg_block)
  946. + 40;
  947. ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
  948. &ring_header->dma);
  949. if (unlikely(!ring_header->desc)) {
  950. if (netif_msg_drv(adapter))
  951. dev_err(&pdev->dev, "pci_alloc_consistent failed\n");
  952. goto err_nomem;
  953. }
  954. memset(ring_header->desc, 0, ring_header->size);
  955. /* init TPD ring */
  956. tpd_ring->dma = ring_header->dma;
  957. offset = (tpd_ring->dma & 0x7) ? (8 - (ring_header->dma & 0x7)) : 0;
  958. tpd_ring->dma += offset;
  959. tpd_ring->desc = (u8 *) ring_header->desc + offset;
  960. tpd_ring->size = sizeof(struct tx_packet_desc) * tpd_ring->count;
  961. /* init RFD ring */
  962. rfd_ring->dma = tpd_ring->dma + tpd_ring->size;
  963. offset = (rfd_ring->dma & 0x7) ? (8 - (rfd_ring->dma & 0x7)) : 0;
  964. rfd_ring->dma += offset;
  965. rfd_ring->desc = (u8 *) tpd_ring->desc + (tpd_ring->size + offset);
  966. rfd_ring->size = sizeof(struct rx_free_desc) * rfd_ring->count;
  967. /* init RRD ring */
  968. rrd_ring->dma = rfd_ring->dma + rfd_ring->size;
  969. offset = (rrd_ring->dma & 0x7) ? (8 - (rrd_ring->dma & 0x7)) : 0;
  970. rrd_ring->dma += offset;
  971. rrd_ring->desc = (u8 *) rfd_ring->desc + (rfd_ring->size + offset);
  972. rrd_ring->size = sizeof(struct rx_return_desc) * rrd_ring->count;
  973. /* init CMB */
  974. adapter->cmb.dma = rrd_ring->dma + rrd_ring->size;
  975. offset = (adapter->cmb.dma & 0x7) ? (8 - (adapter->cmb.dma & 0x7)) : 0;
  976. adapter->cmb.dma += offset;
  977. adapter->cmb.cmb = (struct coals_msg_block *)
  978. ((u8 *) rrd_ring->desc + (rrd_ring->size + offset));
  979. /* init SMB */
  980. adapter->smb.dma = adapter->cmb.dma + sizeof(struct coals_msg_block);
  981. offset = (adapter->smb.dma & 0x7) ? (8 - (adapter->smb.dma & 0x7)) : 0;
  982. adapter->smb.dma += offset;
  983. adapter->smb.smb = (struct stats_msg_block *)
  984. ((u8 *) adapter->cmb.cmb +
  985. (sizeof(struct coals_msg_block) + offset));
  986. return 0;
  987. err_nomem:
  988. kfree(tpd_ring->buffer_info);
  989. return -ENOMEM;
  990. }
  991. static void atl1_init_ring_ptrs(struct atl1_adapter *adapter)
  992. {
  993. struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
  994. struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
  995. struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
  996. atomic_set(&tpd_ring->next_to_use, 0);
  997. atomic_set(&tpd_ring->next_to_clean, 0);
  998. rfd_ring->next_to_clean = 0;
  999. atomic_set(&rfd_ring->next_to_use, 0);
  1000. rrd_ring->next_to_use = 0;
  1001. atomic_set(&rrd_ring->next_to_clean, 0);
  1002. }
  1003. /*
  1004. * atl1_clean_rx_ring - Free RFD Buffers
  1005. * @adapter: board private structure
  1006. */
  1007. static void atl1_clean_rx_ring(struct atl1_adapter *adapter)
  1008. {
  1009. struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
  1010. struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
  1011. struct atl1_buffer *buffer_info;
  1012. struct pci_dev *pdev = adapter->pdev;
  1013. unsigned long size;
  1014. unsigned int i;
  1015. /* Free all the Rx ring sk_buffs */
  1016. for (i = 0; i < rfd_ring->count; i++) {
  1017. buffer_info = &rfd_ring->buffer_info[i];
  1018. if (buffer_info->dma) {
  1019. pci_unmap_page(pdev, buffer_info->dma,
  1020. buffer_info->length, PCI_DMA_FROMDEVICE);
  1021. buffer_info->dma = 0;
  1022. }
  1023. if (buffer_info->skb) {
  1024. dev_kfree_skb(buffer_info->skb);
  1025. buffer_info->skb = NULL;
  1026. }
  1027. }
  1028. size = sizeof(struct atl1_buffer) * rfd_ring->count;
  1029. memset(rfd_ring->buffer_info, 0, size);
  1030. /* Zero out the descriptor ring */
  1031. memset(rfd_ring->desc, 0, rfd_ring->size);
  1032. rfd_ring->next_to_clean = 0;
  1033. atomic_set(&rfd_ring->next_to_use, 0);
  1034. rrd_ring->next_to_use = 0;
  1035. atomic_set(&rrd_ring->next_to_clean, 0);
  1036. }
  1037. /*
  1038. * atl1_clean_tx_ring - Free Tx Buffers
  1039. * @adapter: board private structure
  1040. */
  1041. static void atl1_clean_tx_ring(struct atl1_adapter *adapter)
  1042. {
  1043. struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
  1044. struct atl1_buffer *buffer_info;
  1045. struct pci_dev *pdev = adapter->pdev;
  1046. unsigned long size;
  1047. unsigned int i;
  1048. /* Free all the Tx ring sk_buffs */
  1049. for (i = 0; i < tpd_ring->count; i++) {
  1050. buffer_info = &tpd_ring->buffer_info[i];
  1051. if (buffer_info->dma) {
  1052. pci_unmap_page(pdev, buffer_info->dma,
  1053. buffer_info->length, PCI_DMA_TODEVICE);
  1054. buffer_info->dma = 0;
  1055. }
  1056. }
  1057. for (i = 0; i < tpd_ring->count; i++) {
  1058. buffer_info = &tpd_ring->buffer_info[i];
  1059. if (buffer_info->skb) {
  1060. dev_kfree_skb_any(buffer_info->skb);
  1061. buffer_info->skb = NULL;
  1062. }
  1063. }
  1064. size = sizeof(struct atl1_buffer) * tpd_ring->count;
  1065. memset(tpd_ring->buffer_info, 0, size);
  1066. /* Zero out the descriptor ring */
  1067. memset(tpd_ring->desc, 0, tpd_ring->size);
  1068. atomic_set(&tpd_ring->next_to_use, 0);
  1069. atomic_set(&tpd_ring->next_to_clean, 0);
  1070. }
  1071. /*
  1072. * atl1_free_ring_resources - Free Tx / RX descriptor Resources
  1073. * @adapter: board private structure
  1074. *
  1075. * Free all transmit software resources
  1076. */
  1077. static void atl1_free_ring_resources(struct atl1_adapter *adapter)
  1078. {
  1079. struct pci_dev *pdev = adapter->pdev;
  1080. struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
  1081. struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
  1082. struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
  1083. struct atl1_ring_header *ring_header = &adapter->ring_header;
  1084. atl1_clean_tx_ring(adapter);
  1085. atl1_clean_rx_ring(adapter);
  1086. kfree(tpd_ring->buffer_info);
  1087. pci_free_consistent(pdev, ring_header->size, ring_header->desc,
  1088. ring_header->dma);
  1089. tpd_ring->buffer_info = NULL;
  1090. tpd_ring->desc = NULL;
  1091. tpd_ring->dma = 0;
  1092. rfd_ring->buffer_info = NULL;
  1093. rfd_ring->desc = NULL;
  1094. rfd_ring->dma = 0;
  1095. rrd_ring->desc = NULL;
  1096. rrd_ring->dma = 0;
  1097. }
  1098. static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
  1099. {
  1100. u32 value;
  1101. struct atl1_hw *hw = &adapter->hw;
  1102. struct net_device *netdev = adapter->netdev;
  1103. /* Config MAC CTRL Register */
  1104. value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
  1105. /* duplex */
  1106. if (FULL_DUPLEX == adapter->link_duplex)
  1107. value |= MAC_CTRL_DUPLX;
  1108. /* speed */
  1109. value |= ((u32) ((SPEED_1000 == adapter->link_speed) ?
  1110. MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
  1111. MAC_CTRL_SPEED_SHIFT);
  1112. /* flow control */
  1113. value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
  1114. /* PAD & CRC */
  1115. value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
  1116. /* preamble length */
  1117. value |= (((u32) adapter->hw.preamble_len
  1118. & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
  1119. /* vlan */
  1120. if (adapter->vlgrp)
  1121. value |= MAC_CTRL_RMV_VLAN;
  1122. /* rx checksum
  1123. if (adapter->rx_csum)
  1124. value |= MAC_CTRL_RX_CHKSUM_EN;
  1125. */
  1126. /* filter mode */
  1127. value |= MAC_CTRL_BC_EN;
  1128. if (netdev->flags & IFF_PROMISC)
  1129. value |= MAC_CTRL_PROMIS_EN;
  1130. else if (netdev->flags & IFF_ALLMULTI)
  1131. value |= MAC_CTRL_MC_ALL_EN;
  1132. /* value |= MAC_CTRL_LOOPBACK; */
  1133. iowrite32(value, hw->hw_addr + REG_MAC_CTRL);
  1134. }
  1135. static u32 atl1_check_link(struct atl1_adapter *adapter)
  1136. {
  1137. struct atl1_hw *hw = &adapter->hw;
  1138. struct net_device *netdev = adapter->netdev;
  1139. u32 ret_val;
  1140. u16 speed, duplex, phy_data;
  1141. int reconfig = 0;
  1142. /* MII_BMSR must read twice */
  1143. atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
  1144. atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
  1145. if (!(phy_data & BMSR_LSTATUS)) {
  1146. /* link down */
  1147. if (netif_carrier_ok(netdev)) {
  1148. /* old link state: Up */
  1149. if (netif_msg_link(adapter))
  1150. dev_info(&adapter->pdev->dev, "link is down\n");
  1151. adapter->link_speed = SPEED_0;
  1152. netif_carrier_off(netdev);
  1153. netif_stop_queue(netdev);
  1154. }
  1155. return 0;
  1156. }
  1157. /* Link Up */
  1158. ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
  1159. if (ret_val)
  1160. return ret_val;
  1161. switch (hw->media_type) {
  1162. case MEDIA_TYPE_1000M_FULL:
  1163. if (speed != SPEED_1000 || duplex != FULL_DUPLEX)
  1164. reconfig = 1;
  1165. break;
  1166. case MEDIA_TYPE_100M_FULL:
  1167. if (speed != SPEED_100 || duplex != FULL_DUPLEX)
  1168. reconfig = 1;
  1169. break;
  1170. case MEDIA_TYPE_100M_HALF:
  1171. if (speed != SPEED_100 || duplex != HALF_DUPLEX)
  1172. reconfig = 1;
  1173. break;
  1174. case MEDIA_TYPE_10M_FULL:
  1175. if (speed != SPEED_10 || duplex != FULL_DUPLEX)
  1176. reconfig = 1;
  1177. break;
  1178. case MEDIA_TYPE_10M_HALF:
  1179. if (speed != SPEED_10 || duplex != HALF_DUPLEX)
  1180. reconfig = 1;
  1181. break;
  1182. }
  1183. /* link result is our setting */
  1184. if (!reconfig) {
  1185. if (adapter->link_speed != speed
  1186. || adapter->link_duplex != duplex) {
  1187. adapter->link_speed = speed;
  1188. adapter->link_duplex = duplex;
  1189. atl1_setup_mac_ctrl(adapter);
  1190. if (netif_msg_link(adapter))
  1191. dev_info(&adapter->pdev->dev,
  1192. "%s link is up %d Mbps %s\n",
  1193. netdev->name, adapter->link_speed,
  1194. adapter->link_duplex == FULL_DUPLEX ?
  1195. "full duplex" : "half duplex");
  1196. }
  1197. if (!netif_carrier_ok(netdev)) {
  1198. /* Link down -> Up */
  1199. netif_carrier_on(netdev);
  1200. netif_wake_queue(netdev);
  1201. }
  1202. return 0;
  1203. }
  1204. /* change original link status */
  1205. if (netif_carrier_ok(netdev)) {
  1206. adapter->link_speed = SPEED_0;
  1207. netif_carrier_off(netdev);
  1208. netif_stop_queue(netdev);
  1209. }
  1210. if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR &&
  1211. hw->media_type != MEDIA_TYPE_1000M_FULL) {
  1212. switch (hw->media_type) {
  1213. case MEDIA_TYPE_100M_FULL:
  1214. phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
  1215. MII_CR_RESET;
  1216. break;
  1217. case MEDIA_TYPE_100M_HALF:
  1218. phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
  1219. break;
  1220. case MEDIA_TYPE_10M_FULL:
  1221. phy_data =
  1222. MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
  1223. break;
  1224. default:
  1225. /* MEDIA_TYPE_10M_HALF: */
  1226. phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
  1227. break;
  1228. }
  1229. atl1_write_phy_reg(hw, MII_BMCR, phy_data);
  1230. return 0;
  1231. }
  1232. /* auto-neg, insert timer to re-config phy */
  1233. if (!adapter->phy_timer_pending) {
  1234. adapter->phy_timer_pending = true;
  1235. mod_timer(&adapter->phy_config_timer, jiffies + 3 * HZ);
  1236. }
  1237. return 0;
  1238. }
  1239. static void set_flow_ctrl_old(struct atl1_adapter *adapter)
  1240. {
  1241. u32 hi, lo, value;
  1242. /* RFD Flow Control */
  1243. value = adapter->rfd_ring.count;
  1244. hi = value / 16;
  1245. if (hi < 2)
  1246. hi = 2;
  1247. lo = value * 7 / 8;
  1248. value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
  1249. ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
  1250. iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
  1251. /* RRD Flow Control */
  1252. value = adapter->rrd_ring.count;
  1253. lo = value / 16;
  1254. hi = value * 7 / 8;
  1255. if (lo < 2)
  1256. lo = 2;
  1257. value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
  1258. ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
  1259. iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
  1260. }
  1261. static void set_flow_ctrl_new(struct atl1_hw *hw)
  1262. {
  1263. u32 hi, lo, value;
  1264. /* RXF Flow Control */
  1265. value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN);
  1266. lo = value / 16;
  1267. if (lo < 192)
  1268. lo = 192;
  1269. hi = value * 7 / 8;
  1270. if (hi < lo)
  1271. hi = lo + 16;
  1272. value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
  1273. ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
  1274. iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
  1275. /* RRD Flow Control */
  1276. value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN);
  1277. lo = value / 8;
  1278. hi = value * 7 / 8;
  1279. if (lo < 2)
  1280. lo = 2;
  1281. if (hi < lo)
  1282. hi = lo + 3;
  1283. value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
  1284. ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
  1285. iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
  1286. }
  1287. /*
  1288. * atl1_configure - Configure Transmit&Receive Unit after Reset
  1289. * @adapter: board private structure
  1290. *
  1291. * Configure the Tx /Rx unit of the MAC after a reset.
  1292. */
  1293. static u32 atl1_configure(struct atl1_adapter *adapter)
  1294. {
  1295. struct atl1_hw *hw = &adapter->hw;
  1296. u32 value;
  1297. /* clear interrupt status */
  1298. iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR);
  1299. /* set MAC Address */
  1300. value = (((u32) hw->mac_addr[2]) << 24) |
  1301. (((u32) hw->mac_addr[3]) << 16) |
  1302. (((u32) hw->mac_addr[4]) << 8) |
  1303. (((u32) hw->mac_addr[5]));
  1304. iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
  1305. value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
  1306. iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4));
  1307. /* tx / rx ring */
  1308. /* HI base address */
  1309. iowrite32((u32) ((adapter->tpd_ring.dma & 0xffffffff00000000ULL) >> 32),
  1310. hw->hw_addr + REG_DESC_BASE_ADDR_HI);
  1311. /* LO base address */
  1312. iowrite32((u32) (adapter->rfd_ring.dma & 0x00000000ffffffffULL),
  1313. hw->hw_addr + REG_DESC_RFD_ADDR_LO);
  1314. iowrite32((u32) (adapter->rrd_ring.dma & 0x00000000ffffffffULL),
  1315. hw->hw_addr + REG_DESC_RRD_ADDR_LO);
  1316. iowrite32((u32) (adapter->tpd_ring.dma & 0x00000000ffffffffULL),
  1317. hw->hw_addr + REG_DESC_TPD_ADDR_LO);
  1318. iowrite32((u32) (adapter->cmb.dma & 0x00000000ffffffffULL),
  1319. hw->hw_addr + REG_DESC_CMB_ADDR_LO);
  1320. iowrite32((u32) (adapter->smb.dma & 0x00000000ffffffffULL),
  1321. hw->hw_addr + REG_DESC_SMB_ADDR_LO);
  1322. /* element count */
  1323. value = adapter->rrd_ring.count;
  1324. value <<= 16;
  1325. value += adapter->rfd_ring.count;
  1326. iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE);
  1327. iowrite32(adapter->tpd_ring.count, hw->hw_addr +
  1328. REG_DESC_TPD_RING_SIZE);
  1329. /* Load Ptr */
  1330. iowrite32(1, hw->hw_addr + REG_LOAD_PTR);
  1331. /* config Mailbox */
  1332. value = ((atomic_read(&adapter->tpd_ring.next_to_use)
  1333. & MB_TPD_PROD_INDX_MASK) << MB_TPD_PROD_INDX_SHIFT) |
  1334. ((atomic_read(&adapter->rrd_ring.next_to_clean)
  1335. & MB_RRD_CONS_INDX_MASK) << MB_RRD_CONS_INDX_SHIFT) |
  1336. ((atomic_read(&adapter->rfd_ring.next_to_use)
  1337. & MB_RFD_PROD_INDX_MASK) << MB_RFD_PROD_INDX_SHIFT);
  1338. iowrite32(value, hw->hw_addr + REG_MAILBOX);
  1339. /* config IPG/IFG */
  1340. value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK)
  1341. << MAC_IPG_IFG_IPGT_SHIFT) |
  1342. (((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK)
  1343. << MAC_IPG_IFG_MIFG_SHIFT) |
  1344. (((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK)
  1345. << MAC_IPG_IFG_IPGR1_SHIFT) |
  1346. (((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK)
  1347. << MAC_IPG_IFG_IPGR2_SHIFT);
  1348. iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG);
  1349. /* config Half-Duplex Control */
  1350. value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
  1351. (((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK)
  1352. << MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
  1353. MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
  1354. (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
  1355. (((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK)
  1356. << MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
  1357. iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL);
  1358. /* set Interrupt Moderator Timer */
  1359. iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT);
  1360. iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL);
  1361. /* set Interrupt Clear Timer */
  1362. iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER);
  1363. /* set max frame size hw will accept */
  1364. iowrite32(hw->max_frame_size, hw->hw_addr + REG_MTU);
  1365. /* jumbo size & rrd retirement timer */
  1366. value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK)
  1367. << RXQ_JMBOSZ_TH_SHIFT) |
  1368. (((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK)
  1369. << RXQ_JMBO_LKAH_SHIFT) |
  1370. (((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK)
  1371. << RXQ_RRD_TIMER_SHIFT);
  1372. iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM);
  1373. /* Flow Control */
  1374. switch (hw->dev_rev) {
  1375. case 0x8001:
  1376. case 0x9001:
  1377. case 0x9002:
  1378. case 0x9003:
  1379. set_flow_ctrl_old(adapter);
  1380. break;
  1381. default:
  1382. set_flow_ctrl_new(hw);
  1383. break;
  1384. }
  1385. /* config TXQ */
  1386. value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK)
  1387. << TXQ_CTRL_TPD_BURST_NUM_SHIFT) |
  1388. (((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK)
  1389. << TXQ_CTRL_TXF_BURST_NUM_SHIFT) |
  1390. (((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK)
  1391. << TXQ_CTRL_TPD_FETCH_TH_SHIFT) | TXQ_CTRL_ENH_MODE |
  1392. TXQ_CTRL_EN;
  1393. iowrite32(value, hw->hw_addr + REG_TXQ_CTRL);
  1394. /* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */
  1395. value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK)
  1396. << TX_JUMBO_TASK_TH_SHIFT) |
  1397. (((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK)
  1398. << TX_TPD_MIN_IPG_SHIFT);
  1399. iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG);
  1400. /* config RXQ */
  1401. value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK)
  1402. << RXQ_CTRL_RFD_BURST_NUM_SHIFT) |
  1403. (((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK)
  1404. << RXQ_CTRL_RRD_BURST_THRESH_SHIFT) |
  1405. (((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK)
  1406. << RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT) | RXQ_CTRL_CUT_THRU_EN |
  1407. RXQ_CTRL_EN;
  1408. iowrite32(value, hw->hw_addr + REG_RXQ_CTRL);
  1409. /* config DMA Engine */
  1410. value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
  1411. << DMA_CTRL_DMAR_BURST_LEN_SHIFT) |
  1412. ((((u32) hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
  1413. << DMA_CTRL_DMAW_BURST_LEN_SHIFT) | DMA_CTRL_DMAR_EN |
  1414. DMA_CTRL_DMAW_EN;
  1415. value |= (u32) hw->dma_ord;
  1416. if (atl1_rcb_128 == hw->rcb_value)
  1417. value |= DMA_CTRL_RCB_VALUE;
  1418. iowrite32(value, hw->hw_addr + REG_DMA_CTRL);
  1419. /* config CMB / SMB */
  1420. value = (hw->cmb_tpd > adapter->tpd_ring.count) ?
  1421. hw->cmb_tpd : adapter->tpd_ring.count;
  1422. value <<= 16;
  1423. value |= hw->cmb_rrd;
  1424. iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH);
  1425. value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16);
  1426. iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER);
  1427. iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER);
  1428. /* --- enable CMB / SMB */
  1429. value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN;
  1430. iowrite32(value, hw->hw_addr + REG_CSMB_CTRL);
  1431. value = ioread32(adapter->hw.hw_addr + REG_ISR);
  1432. if (unlikely((value & ISR_PHY_LINKDOWN) != 0))
  1433. value = 1; /* config failed */
  1434. else
  1435. value = 0;
  1436. /* clear all interrupt status */
  1437. iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR);
  1438. iowrite32(0, adapter->hw.hw_addr + REG_ISR);
  1439. return value;
  1440. }
  1441. /*
  1442. * atl1_pcie_patch - Patch for PCIE module
  1443. */
  1444. static void atl1_pcie_patch(struct atl1_adapter *adapter)
  1445. {
  1446. u32 value;
  1447. /* much vendor magic here */
  1448. value = 0x6500;
  1449. iowrite32(value, adapter->hw.hw_addr + 0x12FC);
  1450. /* pcie flow control mode change */
  1451. value = ioread32(adapter->hw.hw_addr + 0x1008);
  1452. value |= 0x8000;
  1453. iowrite32(value, adapter->hw.hw_addr + 0x1008);
  1454. }
  1455. /*
  1456. * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400
  1457. * on PCI Command register is disable.
  1458. * The function enable this bit.
  1459. * Brackett, 2006/03/15
  1460. */
  1461. static void atl1_via_workaround(struct atl1_adapter *adapter)
  1462. {
  1463. unsigned long value;
  1464. value = ioread16(adapter->hw.hw_addr + PCI_COMMAND);
  1465. if (value & PCI_COMMAND_INTX_DISABLE)
  1466. value &= ~PCI_COMMAND_INTX_DISABLE;
  1467. iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
  1468. }
  1469. static void atl1_inc_smb(struct atl1_adapter *adapter)
  1470. {
  1471. struct stats_msg_block *smb = adapter->smb.smb;
  1472. /* Fill out the OS statistics structure */
  1473. adapter->soft_stats.rx_packets += smb->rx_ok;
  1474. adapter->soft_stats.tx_packets += smb->tx_ok;
  1475. adapter->soft_stats.rx_bytes += smb->rx_byte_cnt;
  1476. adapter->soft_stats.tx_bytes += smb->tx_byte_cnt;
  1477. adapter->soft_stats.multicast += smb->rx_mcast;
  1478. adapter->soft_stats.collisions += (smb->tx_1_col + smb->tx_2_col * 2 +
  1479. smb->tx_late_col + smb->tx_abort_col * adapter->hw.max_retry);
  1480. /* Rx Errors */
  1481. adapter->soft_stats.rx_errors += (smb->rx_frag + smb->rx_fcs_err +
  1482. smb->rx_len_err + smb->rx_sz_ov + smb->rx_rxf_ov +
  1483. smb->rx_rrd_ov + smb->rx_align_err);
  1484. adapter->soft_stats.rx_fifo_errors += smb->rx_rxf_ov;
  1485. adapter->soft_stats.rx_length_errors += smb->rx_len_err;
  1486. adapter->soft_stats.rx_crc_errors += smb->rx_fcs_err;
  1487. adapter->soft_stats.rx_frame_errors += smb->rx_align_err;
  1488. adapter->soft_stats.rx_missed_errors += (smb->rx_rrd_ov +
  1489. smb->rx_rxf_ov);
  1490. adapter->soft_stats.rx_pause += smb->rx_pause;
  1491. adapter->soft_stats.rx_rrd_ov += smb->rx_rrd_ov;
  1492. adapter->soft_stats.rx_trunc += smb->rx_sz_ov;
  1493. /* Tx Errors */
  1494. adapter->soft_stats.tx_errors += (smb->tx_late_col +
  1495. smb->tx_abort_col + smb->tx_underrun + smb->tx_trunc);
  1496. adapter->soft_stats.tx_fifo_errors += smb->tx_underrun;
  1497. adapter->soft_stats.tx_aborted_errors += smb->tx_abort_col;
  1498. adapter->soft_stats.tx_window_errors += smb->tx_late_col;
  1499. adapter->soft_stats.excecol += smb->tx_abort_col;
  1500. adapter->soft_stats.deffer += smb->tx_defer;
  1501. adapter->soft_stats.scc += smb->tx_1_col;
  1502. adapter->soft_stats.mcc += smb->tx_2_col;
  1503. adapter->soft_stats.latecol += smb->tx_late_col;
  1504. adapter->soft_stats.tx_underun += smb->tx_underrun;
  1505. adapter->soft_stats.tx_trunc += smb->tx_trunc;
  1506. adapter->soft_stats.tx_pause += smb->tx_pause;
  1507. adapter->net_stats.rx_packets = adapter->soft_stats.rx_packets;
  1508. adapter->net_stats.tx_packets = adapter->soft_stats.tx_packets;
  1509. adapter->net_stats.rx_bytes = adapter->soft_stats.rx_bytes;
  1510. adapter->net_stats.tx_bytes = adapter->soft_stats.tx_bytes;
  1511. adapter->net_stats.multicast = adapter->soft_stats.multicast;
  1512. adapter->net_stats.collisions = adapter->soft_stats.collisions;
  1513. adapter->net_stats.rx_errors = adapter->soft_stats.rx_errors;
  1514. adapter->net_stats.rx_over_errors =
  1515. adapter->soft_stats.rx_missed_errors;
  1516. adapter->net_stats.rx_length_errors =
  1517. adapter->soft_stats.rx_length_errors;
  1518. adapter->net_stats.rx_crc_errors = adapter->soft_stats.rx_crc_errors;
  1519. adapter->net_stats.rx_frame_errors =
  1520. adapter->soft_stats.rx_frame_errors;
  1521. adapter->net_stats.rx_fifo_errors = adapter->soft_stats.rx_fifo_errors;
  1522. adapter->net_stats.rx_missed_errors =
  1523. adapter->soft_stats.rx_missed_errors;
  1524. adapter->net_stats.tx_errors = adapter->soft_stats.tx_errors;
  1525. adapter->net_stats.tx_fifo_errors = adapter->soft_stats.tx_fifo_errors;
  1526. adapter->net_stats.tx_aborted_errors =
  1527. adapter->soft_stats.tx_aborted_errors;
  1528. adapter->net_stats.tx_window_errors =
  1529. adapter->soft_stats.tx_window_errors;
  1530. adapter->net_stats.tx_carrier_errors =
  1531. adapter->soft_stats.tx_carrier_errors;
  1532. }
  1533. static void atl1_update_mailbox(struct atl1_adapter *adapter)
  1534. {
  1535. unsigned long flags;
  1536. u32 tpd_next_to_use;
  1537. u32 rfd_next_to_use;
  1538. u32 rrd_next_to_clean;
  1539. u32 value;
  1540. spin_lock_irqsave(&adapter->mb_lock, flags);
  1541. tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
  1542. rfd_next_to_use = atomic_read(&adapter->rfd_ring.next_to_use);
  1543. rrd_next_to_clean = atomic_read(&adapter->rrd_ring.next_to_clean);
  1544. value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
  1545. MB_RFD_PROD_INDX_SHIFT) |
  1546. ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
  1547. MB_RRD_CONS_INDX_SHIFT) |
  1548. ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
  1549. MB_TPD_PROD_INDX_SHIFT);
  1550. iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
  1551. spin_unlock_irqrestore(&adapter->mb_lock, flags);
  1552. }
  1553. static void atl1_clean_alloc_flag(struct atl1_adapter *adapter,
  1554. struct rx_return_desc *rrd, u16 offset)
  1555. {
  1556. struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
  1557. while (rfd_ring->next_to_clean != (rrd->buf_indx + offset)) {
  1558. rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced = 0;
  1559. if (++rfd_ring->next_to_clean == rfd_ring->count) {
  1560. rfd_ring->next_to_clean = 0;
  1561. }
  1562. }
  1563. }
  1564. static void atl1_update_rfd_index(struct atl1_adapter *adapter,
  1565. struct rx_return_desc *rrd)
  1566. {
  1567. u16 num_buf;
  1568. num_buf = (rrd->xsz.xsum_sz.pkt_size + adapter->rx_buffer_len - 1) /
  1569. adapter->rx_buffer_len;
  1570. if (rrd->num_buf == num_buf)
  1571. /* clean alloc flag for bad rrd */
  1572. atl1_clean_alloc_flag(adapter, rrd, num_buf);
  1573. }
  1574. static void atl1_rx_checksum(struct atl1_adapter *adapter,
  1575. struct rx_return_desc *rrd, struct sk_buff *skb)
  1576. {
  1577. struct pci_dev *pdev = adapter->pdev;
  1578. skb->ip_summed = CHECKSUM_NONE;
  1579. if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
  1580. if (rrd->err_flg & (ERR_FLAG_CRC | ERR_FLAG_TRUNC |
  1581. ERR_FLAG_CODE | ERR_FLAG_OV)) {
  1582. adapter->hw_csum_err++;
  1583. if (netif_msg_rx_err(adapter))
  1584. dev_printk(KERN_DEBUG, &pdev->dev,
  1585. "rx checksum error\n");
  1586. return;
  1587. }
  1588. }
  1589. /* not IPv4 */
  1590. if (!(rrd->pkt_flg & PACKET_FLAG_IPV4))
  1591. /* checksum is invalid, but it's not an IPv4 pkt, so ok */
  1592. return;
  1593. /* IPv4 packet */
  1594. if (likely(!(rrd->err_flg &
  1595. (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM)))) {
  1596. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1597. adapter->hw_csum_good++;
  1598. return;
  1599. }
  1600. /* IPv4, but hardware thinks its checksum is wrong */
  1601. if (netif_msg_rx_err(adapter))
  1602. dev_printk(KERN_DEBUG, &pdev->dev,
  1603. "hw csum wrong, pkt_flag:%x, err_flag:%x\n",
  1604. rrd->pkt_flg, rrd->err_flg);
  1605. skb->ip_summed = CHECKSUM_COMPLETE;
  1606. skb->csum = htons(rrd->xsz.xsum_sz.rx_chksum);
  1607. adapter->hw_csum_err++;
  1608. return;
  1609. }
  1610. /*
  1611. * atl1_alloc_rx_buffers - Replace used receive buffers
  1612. * @adapter: address of board private structure
  1613. */
  1614. static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter)
  1615. {
  1616. struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
  1617. struct pci_dev *pdev = adapter->pdev;
  1618. struct page *page;
  1619. unsigned long offset;
  1620. struct atl1_buffer *buffer_info, *next_info;
  1621. struct sk_buff *skb;
  1622. u16 num_alloc = 0;
  1623. u16 rfd_next_to_use, next_next;
  1624. struct rx_free_desc *rfd_desc;
  1625. next_next = rfd_next_to_use = atomic_read(&rfd_ring->next_to_use);
  1626. if (++next_next == rfd_ring->count)
  1627. next_next = 0;
  1628. buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
  1629. next_info = &rfd_ring->buffer_info[next_next];
  1630. while (!buffer_info->alloced && !next_info->alloced) {
  1631. if (buffer_info->skb) {
  1632. buffer_info->alloced = 1;
  1633. goto next;
  1634. }
  1635. rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use);
  1636. skb = dev_alloc_skb(adapter->rx_buffer_len + NET_IP_ALIGN);
  1637. if (unlikely(!skb)) {
  1638. /* Better luck next round */
  1639. adapter->net_stats.rx_dropped++;
  1640. break;
  1641. }
  1642. /*
  1643. * Make buffer alignment 2 beyond a 16 byte boundary
  1644. * this will result in a 16 byte aligned IP header after
  1645. * the 14 byte MAC header is removed
  1646. */
  1647. skb_reserve(skb, NET_IP_ALIGN);
  1648. buffer_info->alloced = 1;
  1649. buffer_info->skb = skb;
  1650. buffer_info->length = (u16) adapter->rx_buffer_len;
  1651. page = virt_to_page(skb->data);
  1652. offset = (unsigned long)skb->data & ~PAGE_MASK;
  1653. buffer_info->dma = pci_map_page(pdev, page, offset,
  1654. adapter->rx_buffer_len,
  1655. PCI_DMA_FROMDEVICE);
  1656. rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
  1657. rfd_desc->buf_len = cpu_to_le16(adapter->rx_buffer_len);
  1658. rfd_desc->coalese = 0;
  1659. next:
  1660. rfd_next_to_use = next_next;
  1661. if (unlikely(++next_next == rfd_ring->count))
  1662. next_next = 0;
  1663. buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
  1664. next_info = &rfd_ring->buffer_info[next_next];
  1665. num_alloc++;
  1666. }
  1667. if (num_alloc) {
  1668. /*
  1669. * Force memory writes to complete before letting h/w
  1670. * know there are new descriptors to fetch. (Only
  1671. * applicable for weak-ordered memory model archs,
  1672. * such as IA-64).
  1673. */
  1674. wmb();
  1675. atomic_set(&rfd_ring->next_to_use, (int)rfd_next_to_use);
  1676. }
  1677. return num_alloc;
  1678. }
  1679. static void atl1_intr_rx(struct atl1_adapter *adapter)
  1680. {
  1681. int i, count;
  1682. u16 length;
  1683. u16 rrd_next_to_clean;
  1684. u32 value;
  1685. struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
  1686. struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
  1687. struct atl1_buffer *buffer_info;
  1688. struct rx_return_desc *rrd;
  1689. struct sk_buff *skb;
  1690. count = 0;
  1691. rrd_next_to_clean = atomic_read(&rrd_ring->next_to_clean);
  1692. while (1) {
  1693. rrd = ATL1_RRD_DESC(rrd_ring, rrd_next_to_clean);
  1694. i = 1;
  1695. if (likely(rrd->xsz.valid)) { /* packet valid */
  1696. chk_rrd:
  1697. /* check rrd status */
  1698. if (likely(rrd->num_buf == 1))
  1699. goto rrd_ok;
  1700. else if (netif_msg_rx_err(adapter)) {
  1701. dev_printk(KERN_DEBUG, &adapter->pdev->dev,
  1702. "unexpected RRD buffer count\n");
  1703. dev_printk(KERN_DEBUG, &adapter->pdev->dev,
  1704. "rx_buf_len = %d\n",
  1705. adapter->rx_buffer_len);
  1706. dev_printk(KERN_DEBUG, &adapter->pdev->dev,
  1707. "RRD num_buf = %d\n",
  1708. rrd->num_buf);
  1709. dev_printk(KERN_DEBUG, &adapter->pdev->dev,
  1710. "RRD pkt_len = %d\n",
  1711. rrd->xsz.xsum_sz.pkt_size);
  1712. dev_printk(KERN_DEBUG, &adapter->pdev->dev,
  1713. "RRD pkt_flg = 0x%08X\n",
  1714. rrd->pkt_flg);
  1715. dev_printk(KERN_DEBUG, &adapter->pdev->dev,
  1716. "RRD err_flg = 0x%08X\n",
  1717. rrd->err_flg);
  1718. dev_printk(KERN_DEBUG, &adapter->pdev->dev,
  1719. "RRD vlan_tag = 0x%08X\n",
  1720. rrd->vlan_tag);
  1721. }
  1722. /* rrd seems to be bad */
  1723. if (unlikely(i-- > 0)) {
  1724. /* rrd may not be DMAed completely */
  1725. udelay(1);
  1726. goto chk_rrd;
  1727. }
  1728. /* bad rrd */
  1729. if (netif_msg_rx_err(adapter))
  1730. dev_printk(KERN_DEBUG, &adapter->pdev->dev,
  1731. "bad RRD\n");
  1732. /* see if update RFD index */
  1733. if (rrd->num_buf > 1)
  1734. atl1_update_rfd_index(adapter, rrd);
  1735. /* update rrd */
  1736. rrd->xsz.valid = 0;
  1737. if (++rrd_next_to_clean == rrd_ring->count)
  1738. rrd_next_to_clean = 0;
  1739. count++;
  1740. continue;
  1741. } else { /* current rrd still not be updated */
  1742. break;
  1743. }
  1744. rrd_ok:
  1745. /* clean alloc flag for bad rrd */
  1746. atl1_clean_alloc_flag(adapter, rrd, 0);
  1747. buffer_info = &rfd_ring->buffer_info[rrd->buf_indx];
  1748. if (++rfd_ring->next_to_clean == rfd_ring->count)
  1749. rfd_ring->next_to_clean = 0;
  1750. /* update rrd next to clean */
  1751. if (++rrd_next_to_clean == rrd_ring->count)
  1752. rrd_next_to_clean = 0;
  1753. count++;
  1754. if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
  1755. if (!(rrd->err_flg &
  1756. (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM
  1757. | ERR_FLAG_LEN))) {
  1758. /* packet error, don't need upstream */
  1759. buffer_info->alloced = 0;
  1760. rrd->xsz.valid = 0;
  1761. continue;
  1762. }
  1763. }
  1764. /* Good Receive */
  1765. pci_unmap_page(adapter->pdev, buffer_info->dma,
  1766. buffer_info->length, PCI_DMA_FROMDEVICE);
  1767. buffer_info->dma = 0;
  1768. skb = buffer_info->skb;
  1769. length = le16_to_cpu(rrd->xsz.xsum_sz.pkt_size);
  1770. skb_put(skb, length - ETH_FCS_LEN);
  1771. /* Receive Checksum Offload */
  1772. atl1_rx_checksum(adapter, rrd, skb);
  1773. skb->protocol = eth_type_trans(skb, adapter->netdev);
  1774. if (adapter->vlgrp && (rrd->pkt_flg & PACKET_FLAG_VLAN_INS)) {
  1775. u16 vlan_tag = (rrd->vlan_tag >> 4) |
  1776. ((rrd->vlan_tag & 7) << 13) |
  1777. ((rrd->vlan_tag & 8) << 9);
  1778. vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
  1779. } else
  1780. netif_rx(skb);
  1781. /* let protocol layer free skb */
  1782. buffer_info->skb = NULL;
  1783. buffer_info->alloced = 0;
  1784. rrd->xsz.valid = 0;
  1785. adapter->netdev->last_rx = jiffies;
  1786. }
  1787. atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean);
  1788. atl1_alloc_rx_buffers(adapter);
  1789. /* update mailbox ? */
  1790. if (count) {
  1791. u32 tpd_next_to_use;
  1792. u32 rfd_next_to_use;
  1793. spin_lock(&adapter->mb_lock);
  1794. tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
  1795. rfd_next_to_use =
  1796. atomic_read(&adapter->rfd_ring.next_to_use);
  1797. rrd_next_to_clean =
  1798. atomic_read(&adapter->rrd_ring.next_to_clean);
  1799. value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
  1800. MB_RFD_PROD_INDX_SHIFT) |
  1801. ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
  1802. MB_RRD_CONS_INDX_SHIFT) |
  1803. ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
  1804. MB_TPD_PROD_INDX_SHIFT);
  1805. iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
  1806. spin_unlock(&adapter->mb_lock);
  1807. }
  1808. }
  1809. static void atl1_intr_tx(struct atl1_adapter *adapter)
  1810. {
  1811. struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
  1812. struct atl1_buffer *buffer_info;
  1813. u16 sw_tpd_next_to_clean;
  1814. u16 cmb_tpd_next_to_clean;
  1815. sw_tpd_next_to_clean = atomic_read(&tpd_ring->next_to_clean);
  1816. cmb_tpd_next_to_clean = le16_to_cpu(adapter->cmb.cmb->tpd_cons_idx);
  1817. while (cmb_tpd_next_to_clean != sw_tpd_next_to_clean) {
  1818. struct tx_packet_desc *tpd;
  1819. tpd = ATL1_TPD_DESC(tpd_ring, sw_tpd_next_to_clean);
  1820. buffer_info = &tpd_ring->buffer_info[sw_tpd_next_to_clean];
  1821. if (buffer_info->dma) {
  1822. pci_unmap_page(adapter->pdev, buffer_info->dma,
  1823. buffer_info->length, PCI_DMA_TODEVICE);
  1824. buffer_info->dma = 0;
  1825. }
  1826. if (buffer_info->skb) {
  1827. dev_kfree_skb_irq(buffer_info->skb);
  1828. buffer_info->skb = NULL;
  1829. }
  1830. if (++sw_tpd_next_to_clean == tpd_ring->count)
  1831. sw_tpd_next_to_clean = 0;
  1832. }
  1833. atomic_set(&tpd_ring->next_to_clean, sw_tpd_next_to_clean);
  1834. if (netif_queue_stopped(adapter->netdev)
  1835. && netif_carrier_ok(adapter->netdev))
  1836. netif_wake_queue(adapter->netdev);
  1837. }
  1838. static u16 atl1_tpd_avail(struct atl1_tpd_ring *tpd_ring)
  1839. {
  1840. u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
  1841. u16 next_to_use = atomic_read(&tpd_ring->next_to_use);
  1842. return ((next_to_clean > next_to_use) ?
  1843. next_to_clean - next_to_use - 1 :
  1844. tpd_ring->count + next_to_clean - next_to_use - 1);
  1845. }
  1846. static int atl1_tso(struct atl1_adapter *adapter, struct sk_buff *skb,
  1847. struct tx_packet_desc *ptpd)
  1848. {
  1849. /* spinlock held */
  1850. u8 hdr_len, ip_off;
  1851. u32 real_len;
  1852. int err;
  1853. if (skb_shinfo(skb)->gso_size) {
  1854. if (skb_header_cloned(skb)) {
  1855. err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
  1856. if (unlikely(err))
  1857. return -1;
  1858. }
  1859. if (skb->protocol == htons(ETH_P_IP)) {
  1860. struct iphdr *iph = ip_hdr(skb);
  1861. real_len = (((unsigned char *)iph - skb->data) +
  1862. ntohs(iph->tot_len));
  1863. if (real_len < skb->len)
  1864. pskb_trim(skb, real_len);
  1865. hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
  1866. if (skb->len == hdr_len) {
  1867. iph->check = 0;
  1868. tcp_hdr(skb)->check =
  1869. ~csum_tcpudp_magic(iph->saddr,
  1870. iph->daddr, tcp_hdrlen(skb),
  1871. IPPROTO_TCP, 0);
  1872. ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
  1873. TPD_IPHL_SHIFT;
  1874. ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
  1875. TPD_TCPHDRLEN_MASK) <<
  1876. TPD_TCPHDRLEN_SHIFT;
  1877. ptpd->word3 |= 1 << TPD_IP_CSUM_SHIFT;
  1878. ptpd->word3 |= 1 << TPD_TCP_CSUM_SHIFT;
  1879. return 1;
  1880. }
  1881. iph->check = 0;
  1882. tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
  1883. iph->daddr, 0, IPPROTO_TCP, 0);
  1884. ip_off = (unsigned char *)iph -
  1885. (unsigned char *) skb_network_header(skb);
  1886. if (ip_off == 8) /* 802.3-SNAP frame */
  1887. ptpd->word3 |= 1 << TPD_ETHTYPE_SHIFT;
  1888. else if (ip_off != 0)
  1889. return -2;
  1890. ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
  1891. TPD_IPHL_SHIFT;
  1892. ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
  1893. TPD_TCPHDRLEN_MASK) << TPD_TCPHDRLEN_SHIFT;
  1894. ptpd->word3 |= (skb_shinfo(skb)->gso_size &
  1895. TPD_MSS_MASK) << TPD_MSS_SHIFT;
  1896. ptpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
  1897. return 3;
  1898. }
  1899. }
  1900. return false;
  1901. }
  1902. static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb,
  1903. struct tx_packet_desc *ptpd)
  1904. {
  1905. u8 css, cso;
  1906. if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
  1907. css = (u8) (skb->csum_start - skb_headroom(skb));
  1908. cso = css + (u8) skb->csum_offset;
  1909. if (unlikely(css & 0x1)) {
  1910. /* L1 hardware requires an even number here */
  1911. if (netif_msg_tx_err(adapter))
  1912. dev_printk(KERN_DEBUG, &adapter->pdev->dev,
  1913. "payload offset not an even number\n");
  1914. return -1;
  1915. }
  1916. ptpd->word3 |= (css & TPD_PLOADOFFSET_MASK) <<
  1917. TPD_PLOADOFFSET_SHIFT;
  1918. ptpd->word3 |= (cso & TPD_CCSUMOFFSET_MASK) <<
  1919. TPD_CCSUMOFFSET_SHIFT;
  1920. ptpd->word3 |= 1 << TPD_CUST_CSUM_EN_SHIFT;
  1921. return true;
  1922. }
  1923. return 0;
  1924. }
  1925. static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb,
  1926. struct tx_packet_desc *ptpd)
  1927. {
  1928. /* spinlock held */
  1929. struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
  1930. struct atl1_buffer *buffer_info;
  1931. u16 buf_len = skb->len;
  1932. struct page *page;
  1933. unsigned long offset;
  1934. unsigned int nr_frags;
  1935. unsigned int f;
  1936. int retval;
  1937. u16 next_to_use;
  1938. u16 data_len;
  1939. u8 hdr_len;
  1940. buf_len -= skb->data_len;
  1941. nr_frags = skb_shinfo(skb)->nr_frags;
  1942. next_to_use = atomic_read(&tpd_ring->next_to_use);
  1943. buffer_info = &tpd_ring->buffer_info[next_to_use];
  1944. if (unlikely(buffer_info->skb))
  1945. BUG();
  1946. /* put skb in last TPD */
  1947. buffer_info->skb = NULL;
  1948. retval = (ptpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK;
  1949. if (retval) {
  1950. /* TSO */
  1951. hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  1952. buffer_info->length = hdr_len;
  1953. page = virt_to_page(skb->data);
  1954. offset = (unsigned long)skb->data & ~PAGE_MASK;
  1955. buffer_info->dma = pci_map_page(adapter->pdev, page,
  1956. offset, hdr_len,
  1957. PCI_DMA_TODEVICE);
  1958. if (++next_to_use == tpd_ring->count)
  1959. next_to_use = 0;
  1960. if (buf_len > hdr_len) {
  1961. int i, nseg;
  1962. data_len = buf_len - hdr_len;
  1963. nseg = (data_len + ATL1_MAX_TX_BUF_LEN - 1) /
  1964. ATL1_MAX_TX_BUF_LEN;
  1965. for (i = 0; i < nseg; i++) {
  1966. buffer_info =
  1967. &tpd_ring->buffer_info[next_to_use];
  1968. buffer_info->skb = NULL;
  1969. buffer_info->length =
  1970. (ATL1_MAX_TX_BUF_LEN >=
  1971. data_len) ? ATL1_MAX_TX_BUF_LEN : data_len;
  1972. data_len -= buffer_info->length;
  1973. page = virt_to_page(skb->data +
  1974. (hdr_len + i * ATL1_MAX_TX_BUF_LEN));
  1975. offset = (unsigned long)(skb->data +
  1976. (hdr_len + i * ATL1_MAX_TX_BUF_LEN)) &
  1977. ~PAGE_MASK;
  1978. buffer_info->dma = pci_map_page(adapter->pdev,
  1979. page, offset, buffer_info->length,
  1980. PCI_DMA_TODEVICE);
  1981. if (++next_to_use == tpd_ring->count)
  1982. next_to_use = 0;
  1983. }
  1984. }
  1985. } else {
  1986. /* not TSO */
  1987. buffer_info->length = buf_len;
  1988. page = virt_to_page(skb->data);
  1989. offset = (unsigned long)skb->data & ~PAGE_MASK;
  1990. buffer_info->dma = pci_map_page(adapter->pdev, page,
  1991. offset, buf_len, PCI_DMA_TODEVICE);
  1992. if (++next_to_use == tpd_ring->count)
  1993. next_to_use = 0;
  1994. }
  1995. for (f = 0; f < nr_frags; f++) {
  1996. struct skb_frag_struct *frag;
  1997. u16 i, nseg;
  1998. frag = &skb_shinfo(skb)->frags[f];
  1999. buf_len = frag->size;
  2000. nseg = (buf_len + ATL1_MAX_TX_BUF_LEN - 1) /
  2001. ATL1_MAX_TX_BUF_LEN;
  2002. for (i = 0; i < nseg; i++) {
  2003. buffer_info = &tpd_ring->buffer_info[next_to_use];
  2004. if (unlikely(buffer_info->skb))
  2005. BUG();
  2006. buffer_info->skb = NULL;
  2007. buffer_info->length = (buf_len > ATL1_MAX_TX_BUF_LEN) ?
  2008. ATL1_MAX_TX_BUF_LEN : buf_len;
  2009. buf_len -= buffer_info->length;
  2010. buffer_info->dma = pci_map_page(adapter->pdev,
  2011. frag->page,
  2012. frag->page_offset + (i * ATL1_MAX_TX_BUF_LEN),
  2013. buffer_info->length, PCI_DMA_TODEVICE);
  2014. if (++next_to_use == tpd_ring->count)
  2015. next_to_use = 0;
  2016. }
  2017. }
  2018. /* last tpd's buffer-info */
  2019. buffer_info->skb = skb;
  2020. }
  2021. static void atl1_tx_queue(struct atl1_adapter *adapter, u16 count,
  2022. struct tx_packet_desc *ptpd)
  2023. {
  2024. /* spinlock held */
  2025. struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
  2026. struct atl1_buffer *buffer_info;
  2027. struct tx_packet_desc *tpd;
  2028. u16 j;
  2029. u32 val;
  2030. u16 next_to_use = (u16) atomic_read(&tpd_ring->next_to_use);
  2031. for (j = 0; j < count; j++) {
  2032. buffer_info = &tpd_ring->buffer_info[next_to_use];
  2033. tpd = ATL1_TPD_DESC(&adapter->tpd_ring, next_to_use);
  2034. if (tpd != ptpd)
  2035. memcpy(tpd, ptpd, sizeof(struct tx_packet_desc));
  2036. tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  2037. tpd->word2 = (cpu_to_le16(buffer_info->length) &
  2038. TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT;
  2039. /*
  2040. * if this is the first packet in a TSO chain, set
  2041. * TPD_HDRFLAG, otherwise, clear it.
  2042. */
  2043. val = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) &
  2044. TPD_SEGMENT_EN_MASK;
  2045. if (val) {
  2046. if (!j)
  2047. tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT;
  2048. else
  2049. tpd->word3 &= ~(1 << TPD_HDRFLAG_SHIFT);
  2050. }
  2051. if (j == (count - 1))
  2052. tpd->word3 |= 1 << TPD_EOP_SHIFT;
  2053. if (++next_to_use == tpd_ring->count)
  2054. next_to_use = 0;
  2055. }
  2056. /*
  2057. * Force memory writes to complete before letting h/w
  2058. * know there are new descriptors to fetch. (Only
  2059. * applicable for weak-ordered memory model archs,
  2060. * such as IA-64).
  2061. */
  2062. wmb();
  2063. atomic_set(&tpd_ring->next_to_use, next_to_use);
  2064. }
  2065. static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
  2066. {
  2067. struct atl1_adapter *adapter = netdev_priv(netdev);
  2068. struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
  2069. int len = skb->len;
  2070. int tso;
  2071. int count = 1;
  2072. int ret_val;
  2073. struct tx_packet_desc *ptpd;
  2074. u16 frag_size;
  2075. u16 vlan_tag;
  2076. unsigned long flags;
  2077. unsigned int nr_frags = 0;
  2078. unsigned int mss = 0;
  2079. unsigned int f;
  2080. unsigned int proto_hdr_len;
  2081. len -= skb->data_len;
  2082. if (unlikely(skb->len <= 0)) {
  2083. dev_kfree_skb_any(skb);
  2084. return NETDEV_TX_OK;
  2085. }
  2086. nr_frags = skb_shinfo(skb)->nr_frags;
  2087. for (f = 0; f < nr_frags; f++) {
  2088. frag_size = skb_shinfo(skb)->frags[f].size;
  2089. if (frag_size)
  2090. count += (frag_size + ATL1_MAX_TX_BUF_LEN - 1) /
  2091. ATL1_MAX_TX_BUF_LEN;
  2092. }
  2093. mss = skb_shinfo(skb)->gso_size;
  2094. if (mss) {
  2095. if (skb->protocol == ntohs(ETH_P_IP)) {
  2096. proto_hdr_len = (skb_transport_offset(skb) +
  2097. tcp_hdrlen(skb));
  2098. if (unlikely(proto_hdr_len > len)) {
  2099. dev_kfree_skb_any(skb);
  2100. return NETDEV_TX_OK;
  2101. }
  2102. /* need additional TPD ? */
  2103. if (proto_hdr_len != len)
  2104. count += (len - proto_hdr_len +
  2105. ATL1_MAX_TX_BUF_LEN - 1) /
  2106. ATL1_MAX_TX_BUF_LEN;
  2107. }
  2108. }
  2109. if (!spin_trylock_irqsave(&adapter->lock, flags)) {
  2110. /* Can't get lock - tell upper layer to requeue */
  2111. if (netif_msg_tx_queued(adapter))
  2112. dev_printk(KERN_DEBUG, &adapter->pdev->dev,
  2113. "tx locked\n");
  2114. return NETDEV_TX_LOCKED;
  2115. }
  2116. if (atl1_tpd_avail(&adapter->tpd_ring) < count) {
  2117. /* not enough descriptors */
  2118. netif_stop_queue(netdev);
  2119. spin_unlock_irqrestore(&adapter->lock, flags);
  2120. if (netif_msg_tx_queued(adapter))
  2121. dev_printk(KERN_DEBUG, &adapter->pdev->dev,
  2122. "tx busy\n");
  2123. return NETDEV_TX_BUSY;
  2124. }
  2125. ptpd = ATL1_TPD_DESC(tpd_ring,
  2126. (u16) atomic_read(&tpd_ring->next_to_use));
  2127. memset(ptpd, 0, sizeof(struct tx_packet_desc));
  2128. if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
  2129. vlan_tag = vlan_tx_tag_get(skb);
  2130. vlan_tag = (vlan_tag << 4) | (vlan_tag >> 13) |
  2131. ((vlan_tag >> 9) & 0x8);
  2132. ptpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT;
  2133. ptpd->word3 |= (vlan_tag & TPD_VL_TAGGED_MASK) <<
  2134. TPD_VL_TAGGED_SHIFT;
  2135. }
  2136. tso = atl1_tso(adapter, skb, ptpd);
  2137. if (tso < 0) {
  2138. spin_unlock_irqrestore(&adapter->lock, flags);
  2139. dev_kfree_skb_any(skb);
  2140. return NETDEV_TX_OK;
  2141. }
  2142. if (!tso) {
  2143. ret_val = atl1_tx_csum(adapter, skb, ptpd);
  2144. if (ret_val < 0) {
  2145. spin_unlock_irqrestore(&adapter->lock, flags);
  2146. dev_kfree_skb_any(skb);
  2147. return NETDEV_TX_OK;
  2148. }
  2149. }
  2150. atl1_tx_map(adapter, skb, ptpd);
  2151. atl1_tx_queue(adapter, count, ptpd);
  2152. atl1_update_mailbox(adapter);
  2153. spin_unlock_irqrestore(&adapter->lock, flags);
  2154. netdev->trans_start = jiffies;
  2155. return NETDEV_TX_OK;
  2156. }
  2157. /*
  2158. * atl1_intr - Interrupt Handler
  2159. * @irq: interrupt number
  2160. * @data: pointer to a network interface device structure
  2161. * @pt_regs: CPU registers structure
  2162. */
  2163. static irqreturn_t atl1_intr(int irq, void *data)
  2164. {
  2165. struct atl1_adapter *adapter = netdev_priv(data);
  2166. u32 status;
  2167. int max_ints = 10;
  2168. status = adapter->cmb.cmb->int_stats;
  2169. if (!status)
  2170. return IRQ_NONE;
  2171. do {
  2172. /* clear CMB interrupt status at once */
  2173. adapter->cmb.cmb->int_stats = 0;
  2174. if (status & ISR_GPHY) /* clear phy status */
  2175. atlx_clear_phy_int(adapter);
  2176. /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
  2177. iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR);
  2178. /* check if SMB intr */
  2179. if (status & ISR_SMB)
  2180. atl1_inc_smb(adapter);
  2181. /* check if PCIE PHY Link down */
  2182. if (status & ISR_PHY_LINKDOWN) {
  2183. if (netif_msg_intr(adapter))
  2184. dev_printk(KERN_DEBUG, &adapter->pdev->dev,
  2185. "pcie phy link down %x\n", status);
  2186. if (netif_running(adapter->netdev)) { /* reset MAC */
  2187. iowrite32(0, adapter->hw.hw_addr + REG_IMR);
  2188. schedule_work(&adapter->pcie_dma_to_rst_task);
  2189. return IRQ_HANDLED;
  2190. }
  2191. }
  2192. /* check if DMA read/write error ? */
  2193. if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
  2194. if (netif_msg_intr(adapter))
  2195. dev_printk(KERN_DEBUG, &adapter->pdev->dev,
  2196. "pcie DMA r/w error (status = 0x%x)\n",
  2197. status);
  2198. iowrite32(0, adapter->hw.hw_addr + REG_IMR);
  2199. schedule_work(&adapter->pcie_dma_to_rst_task);
  2200. return IRQ_HANDLED;
  2201. }
  2202. /* link event */
  2203. if (status & ISR_GPHY) {
  2204. adapter->soft_stats.tx_carrier_errors++;
  2205. atl1_check_for_link(adapter);
  2206. }
  2207. /* transmit event */
  2208. if (status & ISR_CMB_TX)
  2209. atl1_intr_tx(adapter);
  2210. /* rx exception */
  2211. if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN |
  2212. ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
  2213. ISR_HOST_RRD_OV | ISR_CMB_RX))) {
  2214. if (status & (ISR_RXF_OV | ISR_RFD_UNRUN |
  2215. ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
  2216. ISR_HOST_RRD_OV))
  2217. if (netif_msg_intr(adapter))
  2218. dev_printk(KERN_DEBUG,
  2219. &adapter->pdev->dev,
  2220. "rx exception, ISR = 0x%x\n",
  2221. status);
  2222. atl1_intr_rx(adapter);
  2223. }
  2224. if (--max_ints < 0)
  2225. break;
  2226. } while ((status = adapter->cmb.cmb->int_stats));
  2227. /* re-enable Interrupt */
  2228. iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR);
  2229. return IRQ_HANDLED;
  2230. }
  2231. /*
  2232. * atl1_watchdog - Timer Call-back
  2233. * @data: pointer to netdev cast into an unsigned long
  2234. */
  2235. static void atl1_watchdog(unsigned long data)
  2236. {
  2237. struct atl1_adapter *adapter = (struct atl1_adapter *)data;
  2238. /* Reset the timer */
  2239. mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
  2240. }
  2241. /*
  2242. * atl1_phy_config - Timer Call-back
  2243. * @data: pointer to netdev cast into an unsigned long
  2244. */
  2245. static void atl1_phy_config(unsigned long data)
  2246. {
  2247. struct atl1_adapter *adapter = (struct atl1_adapter *)data;
  2248. struct atl1_hw *hw = &adapter->hw;
  2249. unsigned long flags;
  2250. spin_lock_irqsave(&adapter->lock, flags);
  2251. adapter->phy_timer_pending = false;
  2252. atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
  2253. atl1_write_phy_reg(hw, MII_ATLX_CR, hw->mii_1000t_ctrl_reg);
  2254. atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN);
  2255. spin_unlock_irqrestore(&adapter->lock, flags);
  2256. }
  2257. /*
  2258. * Orphaned vendor comment left intact here:
  2259. * <vendor comment>
  2260. * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT
  2261. * will assert. We do soft reset <0x1400=1> according
  2262. * with the SPEC. BUT, it seemes that PCIE or DMA
  2263. * state-machine will not be reset. DMAR_TO_INT will
  2264. * assert again and again.
  2265. * </vendor comment>
  2266. */
  2267. static int atl1_reset(struct atl1_adapter *adapter)
  2268. {
  2269. int ret;
  2270. ret = atl1_reset_hw(&adapter->hw);
  2271. if (ret)
  2272. return ret;
  2273. return atl1_init_hw(&adapter->hw);
  2274. }
  2275. static s32 atl1_up(struct atl1_adapter *adapter)
  2276. {
  2277. struct net_device *netdev = adapter->netdev;
  2278. int err;
  2279. int irq_flags = IRQF_SAMPLE_RANDOM;
  2280. /* hardware has been reset, we need to reload some things */
  2281. atlx_set_multi(netdev);
  2282. atl1_init_ring_ptrs(adapter);
  2283. atlx_restore_vlan(adapter);
  2284. err = atl1_alloc_rx_buffers(adapter);
  2285. if (unlikely(!err))
  2286. /* no RX BUFFER allocated */
  2287. return -ENOMEM;
  2288. if (unlikely(atl1_configure(adapter))) {
  2289. err = -EIO;
  2290. goto err_up;
  2291. }
  2292. err = pci_enable_msi(adapter->pdev);
  2293. if (err) {
  2294. if (netif_msg_ifup(adapter))
  2295. dev_info(&adapter->pdev->dev,
  2296. "Unable to enable MSI: %d\n", err);
  2297. irq_flags |= IRQF_SHARED;
  2298. }
  2299. err = request_irq(adapter->pdev->irq, &atl1_intr, irq_flags,
  2300. netdev->name, netdev);
  2301. if (unlikely(err))
  2302. goto err_up;
  2303. mod_timer(&adapter->watchdog_timer, jiffies);
  2304. atlx_irq_enable(adapter);
  2305. atl1_check_link(adapter);
  2306. return 0;
  2307. err_up:
  2308. pci_disable_msi(adapter->pdev);
  2309. /* free rx_buffers */
  2310. atl1_clean_rx_ring(adapter);
  2311. return err;
  2312. }
  2313. static void atl1_down(struct atl1_adapter *adapter)
  2314. {
  2315. struct net_device *netdev = adapter->netdev;
  2316. del_timer_sync(&adapter->watchdog_timer);
  2317. del_timer_sync(&adapter->phy_config_timer);
  2318. adapter->phy_timer_pending = false;
  2319. atlx_irq_disable(adapter);
  2320. free_irq(adapter->pdev->irq, netdev);
  2321. pci_disable_msi(adapter->pdev);
  2322. atl1_reset_hw(&adapter->hw);
  2323. adapter->cmb.cmb->int_stats = 0;
  2324. adapter->link_speed = SPEED_0;
  2325. adapter->link_duplex = -1;
  2326. netif_carrier_off(netdev);
  2327. netif_stop_queue(netdev);
  2328. atl1_clean_tx_ring(adapter);
  2329. atl1_clean_rx_ring(adapter);
  2330. }
  2331. static void atl1_tx_timeout_task(struct work_struct *work)
  2332. {
  2333. struct atl1_adapter *adapter =
  2334. container_of(work, struct atl1_adapter, tx_timeout_task);
  2335. struct net_device *netdev = adapter->netdev;
  2336. netif_device_detach(netdev);
  2337. atl1_down(adapter);
  2338. atl1_up(adapter);
  2339. netif_device_attach(netdev);
  2340. }
  2341. /*
  2342. * atl1_change_mtu - Change the Maximum Transfer Unit
  2343. * @netdev: network interface device structure
  2344. * @new_mtu: new value for maximum frame size
  2345. *
  2346. * Returns 0 on success, negative on failure
  2347. */
  2348. static int atl1_change_mtu(struct net_device *netdev, int new_mtu)
  2349. {
  2350. struct atl1_adapter *adapter = netdev_priv(netdev);
  2351. int old_mtu = netdev->mtu;
  2352. int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
  2353. if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
  2354. (max_frame > MAX_JUMBO_FRAME_SIZE)) {
  2355. if (netif_msg_link(adapter))
  2356. dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
  2357. return -EINVAL;
  2358. }
  2359. adapter->hw.max_frame_size = max_frame;
  2360. adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3;
  2361. adapter->rx_buffer_len = (max_frame + 7) & ~7;
  2362. adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8;
  2363. netdev->mtu = new_mtu;
  2364. if ((old_mtu != new_mtu) && netif_running(netdev)) {
  2365. atl1_down(adapter);
  2366. atl1_up(adapter);
  2367. }
  2368. return 0;
  2369. }
  2370. /*
  2371. * atl1_open - Called when a network interface is made active
  2372. * @netdev: network interface device structure
  2373. *
  2374. * Returns 0 on success, negative value on failure
  2375. *
  2376. * The open entry point is called when a network interface is made
  2377. * active by the system (IFF_UP). At this point all resources needed
  2378. * for transmit and receive operations are allocated, the interrupt
  2379. * handler is registered with the OS, the watchdog timer is started,
  2380. * and the stack is notified that the interface is ready.
  2381. */
  2382. static int atl1_open(struct net_device *netdev)
  2383. {
  2384. struct atl1_adapter *adapter = netdev_priv(netdev);
  2385. int err;
  2386. /* allocate transmit descriptors */
  2387. err = atl1_setup_ring_resources(adapter);
  2388. if (err)
  2389. return err;
  2390. err = atl1_up(adapter);
  2391. if (err)
  2392. goto err_up;
  2393. return 0;
  2394. err_up:
  2395. atl1_reset(adapter);
  2396. return err;
  2397. }
  2398. /*
  2399. * atl1_close - Disables a network interface
  2400. * @netdev: network interface device structure
  2401. *
  2402. * Returns 0, this is not allowed to fail
  2403. *
  2404. * The close entry point is called when an interface is de-activated
  2405. * by the OS. The hardware is still under the drivers control, but
  2406. * needs to be disabled. A global MAC reset is issued to stop the
  2407. * hardware, and all transmit and receive resources are freed.
  2408. */
  2409. static int atl1_close(struct net_device *netdev)
  2410. {
  2411. struct atl1_adapter *adapter = netdev_priv(netdev);
  2412. atl1_down(adapter);
  2413. atl1_free_ring_resources(adapter);
  2414. return 0;
  2415. }
  2416. #ifdef CONFIG_PM
  2417. static int atl1_suspend(struct pci_dev *pdev, pm_message_t state)
  2418. {
  2419. struct net_device *netdev = pci_get_drvdata(pdev);
  2420. struct atl1_adapter *adapter = netdev_priv(netdev);
  2421. struct atl1_hw *hw = &adapter->hw;
  2422. u32 ctrl = 0;
  2423. u32 wufc = adapter->wol;
  2424. u32 val;
  2425. int retval;
  2426. u16 speed;
  2427. u16 duplex;
  2428. netif_device_detach(netdev);
  2429. if (netif_running(netdev))
  2430. atl1_down(adapter);
  2431. retval = pci_save_state(pdev);
  2432. if (retval)
  2433. return retval;
  2434. atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
  2435. atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
  2436. val = ctrl & BMSR_LSTATUS;
  2437. if (val)
  2438. wufc &= ~ATLX_WUFC_LNKC;
  2439. if (val && wufc) {
  2440. val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
  2441. if (val) {
  2442. if (netif_msg_ifdown(adapter))
  2443. dev_printk(KERN_DEBUG, &pdev->dev,
  2444. "error getting speed/duplex\n");
  2445. goto disable_wol;
  2446. }
  2447. ctrl = 0;
  2448. /* enable magic packet WOL */
  2449. if (wufc & ATLX_WUFC_MAG)
  2450. ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
  2451. iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
  2452. ioread32(hw->hw_addr + REG_WOL_CTRL);
  2453. /* configure the mac */
  2454. ctrl = MAC_CTRL_RX_EN;
  2455. ctrl |= ((u32)((speed == SPEED_1000) ? MAC_CTRL_SPEED_1000 :
  2456. MAC_CTRL_SPEED_10_100) << MAC_CTRL_SPEED_SHIFT);
  2457. if (duplex == FULL_DUPLEX)
  2458. ctrl |= MAC_CTRL_DUPLX;
  2459. ctrl |= (((u32)adapter->hw.preamble_len &
  2460. MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
  2461. if (adapter->vlgrp)
  2462. ctrl |= MAC_CTRL_RMV_VLAN;
  2463. if (wufc & ATLX_WUFC_MAG)
  2464. ctrl |= MAC_CTRL_BC_EN;
  2465. iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL);
  2466. ioread32(hw->hw_addr + REG_MAC_CTRL);
  2467. /* poke the PHY */
  2468. ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
  2469. ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
  2470. iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
  2471. ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
  2472. pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
  2473. goto exit;
  2474. }
  2475. if (!val && wufc) {
  2476. ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
  2477. iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
  2478. ioread32(hw->hw_addr + REG_WOL_CTRL);
  2479. iowrite32(0, hw->hw_addr + REG_MAC_CTRL);
  2480. ioread32(hw->hw_addr + REG_MAC_CTRL);
  2481. hw->phy_configured = false;
  2482. pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
  2483. goto exit;
  2484. }
  2485. disable_wol:
  2486. iowrite32(0, hw->hw_addr + REG_WOL_CTRL);
  2487. ioread32(hw->hw_addr + REG_WOL_CTRL);
  2488. ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
  2489. ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
  2490. iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
  2491. ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
  2492. hw->phy_configured = false;
  2493. pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
  2494. exit:
  2495. if (netif_running(netdev))
  2496. pci_disable_msi(adapter->pdev);
  2497. pci_disable_device(pdev);
  2498. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  2499. return 0;
  2500. }
  2501. static int atl1_resume(struct pci_dev *pdev)
  2502. {
  2503. struct net_device *netdev = pci_get_drvdata(pdev);
  2504. struct atl1_adapter *adapter = netdev_priv(netdev);
  2505. u32 err;
  2506. pci_set_power_state(pdev, PCI_D0);
  2507. pci_restore_state(pdev);
  2508. err = pci_enable_device(pdev);
  2509. if (err) {
  2510. if (netif_msg_ifup(adapter))
  2511. dev_printk(KERN_DEBUG, &pdev->dev,
  2512. "error enabling pci device\n");
  2513. return err;
  2514. }
  2515. pci_set_master(pdev);
  2516. iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL);
  2517. pci_enable_wake(pdev, PCI_D3hot, 0);
  2518. pci_enable_wake(pdev, PCI_D3cold, 0);
  2519. atl1_reset_hw(&adapter->hw);
  2520. adapter->cmb.cmb->int_stats = 0;
  2521. if (netif_running(netdev))
  2522. atl1_up(adapter);
  2523. netif_device_attach(netdev);
  2524. return 0;
  2525. }
  2526. #else
  2527. #define atl1_suspend NULL
  2528. #define atl1_resume NULL
  2529. #endif
  2530. static void atl1_shutdown(struct pci_dev *pdev)
  2531. {
  2532. #ifdef CONFIG_PM
  2533. atl1_suspend(pdev, PMSG_SUSPEND);
  2534. #endif
  2535. }
  2536. #ifdef CONFIG_NET_POLL_CONTROLLER
  2537. static void atl1_poll_controller(struct net_device *netdev)
  2538. {
  2539. disable_irq(netdev->irq);
  2540. atl1_intr(netdev->irq, netdev);
  2541. enable_irq(netdev->irq);
  2542. }
  2543. #endif
  2544. /*
  2545. * atl1_probe - Device Initialization Routine
  2546. * @pdev: PCI device information struct
  2547. * @ent: entry in atl1_pci_tbl
  2548. *
  2549. * Returns 0 on success, negative on failure
  2550. *
  2551. * atl1_probe initializes an adapter identified by a pci_dev structure.
  2552. * The OS initialization, configuring of the adapter private structure,
  2553. * and a hardware reset occur.
  2554. */
  2555. static int __devinit atl1_probe(struct pci_dev *pdev,
  2556. const struct pci_device_id *ent)
  2557. {
  2558. struct net_device *netdev;
  2559. struct atl1_adapter *adapter;
  2560. static int cards_found = 0;
  2561. int err;
  2562. err = pci_enable_device(pdev);
  2563. if (err)
  2564. return err;
  2565. /*
  2566. * The atl1 chip can DMA to 64-bit addresses, but it uses a single
  2567. * shared register for the high 32 bits, so only a single, aligned,
  2568. * 4 GB physical address range can be used at a time.
  2569. *
  2570. * Supporting 64-bit DMA on this hardware is more trouble than it's
  2571. * worth. It is far easier to limit to 32-bit DMA than update
  2572. * various kernel subsystems to support the mechanics required by a
  2573. * fixed-high-32-bit system.
  2574. */
  2575. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  2576. if (err) {
  2577. dev_err(&pdev->dev, "no usable DMA configuration\n");
  2578. goto err_dma;
  2579. }
  2580. /*
  2581. * Mark all PCI regions associated with PCI device
  2582. * pdev as being reserved by owner atl1_driver_name
  2583. */
  2584. err = pci_request_regions(pdev, ATLX_DRIVER_NAME);
  2585. if (err)
  2586. goto err_request_regions;
  2587. /*
  2588. * Enables bus-mastering on the device and calls
  2589. * pcibios_set_master to do the needed arch specific settings
  2590. */
  2591. pci_set_master(pdev);
  2592. netdev = alloc_etherdev(sizeof(struct atl1_adapter));
  2593. if (!netdev) {
  2594. err = -ENOMEM;
  2595. goto err_alloc_etherdev;
  2596. }
  2597. SET_NETDEV_DEV(netdev, &pdev->dev);
  2598. pci_set_drvdata(pdev, netdev);
  2599. adapter = netdev_priv(netdev);
  2600. adapter->netdev = netdev;
  2601. adapter->pdev = pdev;
  2602. adapter->hw.back = adapter;
  2603. adapter->msg_enable = netif_msg_init(debug, atl1_default_msg);
  2604. adapter->hw.hw_addr = pci_iomap(pdev, 0, 0);
  2605. if (!adapter->hw.hw_addr) {
  2606. err = -EIO;
  2607. goto err_pci_iomap;
  2608. }
  2609. /* get device revision number */
  2610. adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr +
  2611. (REG_MASTER_CTRL + 2));
  2612. if (netif_msg_probe(adapter))
  2613. dev_info(&pdev->dev, "version %s\n", ATLX_DRIVER_VERSION);
  2614. /* set default ring resource counts */
  2615. adapter->rfd_ring.count = adapter->rrd_ring.count = ATL1_DEFAULT_RFD;
  2616. adapter->tpd_ring.count = ATL1_DEFAULT_TPD;
  2617. adapter->mii.dev = netdev;
  2618. adapter->mii.mdio_read = mdio_read;
  2619. adapter->mii.mdio_write = mdio_write;
  2620. adapter->mii.phy_id_mask = 0x1f;
  2621. adapter->mii.reg_num_mask = 0x1f;
  2622. netdev->open = &atl1_open;
  2623. netdev->stop = &atl1_close;
  2624. netdev->hard_start_xmit = &atl1_xmit_frame;
  2625. netdev->get_stats = &atlx_get_stats;
  2626. netdev->set_multicast_list = &atlx_set_multi;
  2627. netdev->set_mac_address = &atl1_set_mac;
  2628. netdev->change_mtu = &atl1_change_mtu;
  2629. netdev->do_ioctl = &atlx_ioctl;
  2630. netdev->tx_timeout = &atlx_tx_timeout;
  2631. netdev->watchdog_timeo = 5 * HZ;
  2632. #ifdef CONFIG_NET_POLL_CONTROLLER
  2633. netdev->poll_controller = atl1_poll_controller;
  2634. #endif
  2635. netdev->vlan_rx_register = atlx_vlan_rx_register;
  2636. netdev->ethtool_ops = &atl1_ethtool_ops;
  2637. adapter->bd_number = cards_found;
  2638. /* setup the private structure */
  2639. err = atl1_sw_init(adapter);
  2640. if (err)
  2641. goto err_common;
  2642. netdev->features = NETIF_F_HW_CSUM;
  2643. netdev->features |= NETIF_F_SG;
  2644. netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
  2645. netdev->features |= NETIF_F_TSO;
  2646. netdev->features |= NETIF_F_LLTX;
  2647. /*
  2648. * patch for some L1 of old version,
  2649. * the final version of L1 may not need these
  2650. * patches
  2651. */
  2652. /* atl1_pcie_patch(adapter); */
  2653. /* really reset GPHY core */
  2654. iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
  2655. /*
  2656. * reset the controller to
  2657. * put the device in a known good starting state
  2658. */
  2659. if (atl1_reset_hw(&adapter->hw)) {
  2660. err = -EIO;
  2661. goto err_common;
  2662. }
  2663. /* copy the MAC address out of the EEPROM */
  2664. atl1_read_mac_addr(&adapter->hw);
  2665. memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
  2666. if (!is_valid_ether_addr(netdev->dev_addr)) {
  2667. err = -EIO;
  2668. goto err_common;
  2669. }
  2670. atl1_check_options(adapter);
  2671. /* pre-init the MAC, and setup link */
  2672. err = atl1_init_hw(&adapter->hw);
  2673. if (err) {
  2674. err = -EIO;
  2675. goto err_common;
  2676. }
  2677. atl1_pcie_patch(adapter);
  2678. /* assume we have no link for now */
  2679. netif_carrier_off(netdev);
  2680. netif_stop_queue(netdev);
  2681. init_timer(&adapter->watchdog_timer);
  2682. adapter->watchdog_timer.function = &atl1_watchdog;
  2683. adapter->watchdog_timer.data = (unsigned long)adapter;
  2684. init_timer(&adapter->phy_config_timer);
  2685. adapter->phy_config_timer.function = &atl1_phy_config;
  2686. adapter->phy_config_timer.data = (unsigned long)adapter;
  2687. adapter->phy_timer_pending = false;
  2688. INIT_WORK(&adapter->tx_timeout_task, atl1_tx_timeout_task);
  2689. INIT_WORK(&adapter->link_chg_task, atlx_link_chg_task);
  2690. INIT_WORK(&adapter->pcie_dma_to_rst_task, atl1_tx_timeout_task);
  2691. err = register_netdev(netdev);
  2692. if (err)
  2693. goto err_common;
  2694. cards_found++;
  2695. atl1_via_workaround(adapter);
  2696. return 0;
  2697. err_common:
  2698. pci_iounmap(pdev, adapter->hw.hw_addr);
  2699. err_pci_iomap:
  2700. free_netdev(netdev);
  2701. err_alloc_etherdev:
  2702. pci_release_regions(pdev);
  2703. err_dma:
  2704. err_request_regions:
  2705. pci_disable_device(pdev);
  2706. return err;
  2707. }
  2708. /*
  2709. * atl1_remove - Device Removal Routine
  2710. * @pdev: PCI device information struct
  2711. *
  2712. * atl1_remove is called by the PCI subsystem to alert the driver
  2713. * that it should release a PCI device. The could be caused by a
  2714. * Hot-Plug event, or because the driver is going to be removed from
  2715. * memory.
  2716. */
  2717. static void __devexit atl1_remove(struct pci_dev *pdev)
  2718. {
  2719. struct net_device *netdev = pci_get_drvdata(pdev);
  2720. struct atl1_adapter *adapter;
  2721. /* Device not available. Return. */
  2722. if (!netdev)
  2723. return;
  2724. adapter = netdev_priv(netdev);
  2725. /*
  2726. * Some atl1 boards lack persistent storage for their MAC, and get it
  2727. * from the BIOS during POST. If we've been messing with the MAC
  2728. * address, we need to save the permanent one.
  2729. */
  2730. if (memcmp(adapter->hw.mac_addr, adapter->hw.perm_mac_addr, ETH_ALEN)) {
  2731. memcpy(adapter->hw.mac_addr, adapter->hw.perm_mac_addr,
  2732. ETH_ALEN);
  2733. atl1_set_mac_addr(&adapter->hw);
  2734. }
  2735. iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
  2736. unregister_netdev(netdev);
  2737. pci_iounmap(pdev, adapter->hw.hw_addr);
  2738. pci_release_regions(pdev);
  2739. free_netdev(netdev);
  2740. pci_disable_device(pdev);
  2741. }
  2742. static struct pci_driver atl1_driver = {
  2743. .name = ATLX_DRIVER_NAME,
  2744. .id_table = atl1_pci_tbl,
  2745. .probe = atl1_probe,
  2746. .remove = __devexit_p(atl1_remove),
  2747. .suspend = atl1_suspend,
  2748. .resume = atl1_resume,
  2749. .shutdown = atl1_shutdown
  2750. };
  2751. /*
  2752. * atl1_exit_module - Driver Exit Cleanup Routine
  2753. *
  2754. * atl1_exit_module is called just before the driver is removed
  2755. * from memory.
  2756. */
  2757. static void __exit atl1_exit_module(void)
  2758. {
  2759. pci_unregister_driver(&atl1_driver);
  2760. }
  2761. /*
  2762. * atl1_init_module - Driver Registration Routine
  2763. *
  2764. * atl1_init_module is the first routine called when the driver is
  2765. * loaded. All it does is register with the PCI subsystem.
  2766. */
  2767. static int __init atl1_init_module(void)
  2768. {
  2769. return pci_register_driver(&atl1_driver);
  2770. }
  2771. module_init(atl1_init_module);
  2772. module_exit(atl1_exit_module);
  2773. struct atl1_stats {
  2774. char stat_string[ETH_GSTRING_LEN];
  2775. int sizeof_stat;
  2776. int stat_offset;
  2777. };
  2778. #define ATL1_STAT(m) \
  2779. sizeof(((struct atl1_adapter *)0)->m), offsetof(struct atl1_adapter, m)
  2780. static struct atl1_stats atl1_gstrings_stats[] = {
  2781. {"rx_packets", ATL1_STAT(soft_stats.rx_packets)},
  2782. {"tx_packets", ATL1_STAT(soft_stats.tx_packets)},
  2783. {"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)},
  2784. {"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)},
  2785. {"rx_errors", ATL1_STAT(soft_stats.rx_errors)},
  2786. {"tx_errors", ATL1_STAT(soft_stats.tx_errors)},
  2787. {"rx_dropped", ATL1_STAT(net_stats.rx_dropped)},
  2788. {"tx_dropped", ATL1_STAT(net_stats.tx_dropped)},
  2789. {"multicast", ATL1_STAT(soft_stats.multicast)},
  2790. {"collisions", ATL1_STAT(soft_stats.collisions)},
  2791. {"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)},
  2792. {"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
  2793. {"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)},
  2794. {"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)},
  2795. {"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)},
  2796. {"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
  2797. {"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)},
  2798. {"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)},
  2799. {"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)},
  2800. {"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)},
  2801. {"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)},
  2802. {"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)},
  2803. {"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)},
  2804. {"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)},
  2805. {"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)},
  2806. {"tx_underun", ATL1_STAT(soft_stats.tx_underun)},
  2807. {"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)},
  2808. {"tx_pause", ATL1_STAT(soft_stats.tx_pause)},
  2809. {"rx_pause", ATL1_STAT(soft_stats.rx_pause)},
  2810. {"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)},
  2811. {"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)}
  2812. };
  2813. static void atl1_get_ethtool_stats(struct net_device *netdev,
  2814. struct ethtool_stats *stats, u64 *data)
  2815. {
  2816. struct atl1_adapter *adapter = netdev_priv(netdev);
  2817. int i;
  2818. char *p;
  2819. for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
  2820. p = (char *)adapter+atl1_gstrings_stats[i].stat_offset;
  2821. data[i] = (atl1_gstrings_stats[i].sizeof_stat ==
  2822. sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
  2823. }
  2824. }
  2825. static int atl1_get_sset_count(struct net_device *netdev, int sset)
  2826. {
  2827. switch (sset) {
  2828. case ETH_SS_STATS:
  2829. return ARRAY_SIZE(atl1_gstrings_stats);
  2830. default:
  2831. return -EOPNOTSUPP;
  2832. }
  2833. }
  2834. static int atl1_get_settings(struct net_device *netdev,
  2835. struct ethtool_cmd *ecmd)
  2836. {
  2837. struct atl1_adapter *adapter = netdev_priv(netdev);
  2838. struct atl1_hw *hw = &adapter->hw;
  2839. ecmd->supported = (SUPPORTED_10baseT_Half |
  2840. SUPPORTED_10baseT_Full |
  2841. SUPPORTED_100baseT_Half |
  2842. SUPPORTED_100baseT_Full |
  2843. SUPPORTED_1000baseT_Full |
  2844. SUPPORTED_Autoneg | SUPPORTED_TP);
  2845. ecmd->advertising = ADVERTISED_TP;
  2846. if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
  2847. hw->media_type == MEDIA_TYPE_1000M_FULL) {
  2848. ecmd->advertising |= ADVERTISED_Autoneg;
  2849. if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) {
  2850. ecmd->advertising |= ADVERTISED_Autoneg;
  2851. ecmd->advertising |=
  2852. (ADVERTISED_10baseT_Half |
  2853. ADVERTISED_10baseT_Full |
  2854. ADVERTISED_100baseT_Half |
  2855. ADVERTISED_100baseT_Full |
  2856. ADVERTISED_1000baseT_Full);
  2857. } else
  2858. ecmd->advertising |= (ADVERTISED_1000baseT_Full);
  2859. }
  2860. ecmd->port = PORT_TP;
  2861. ecmd->phy_address = 0;
  2862. ecmd->transceiver = XCVR_INTERNAL;
  2863. if (netif_carrier_ok(adapter->netdev)) {
  2864. u16 link_speed, link_duplex;
  2865. atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex);
  2866. ecmd->speed = link_speed;
  2867. if (link_duplex == FULL_DUPLEX)
  2868. ecmd->duplex = DUPLEX_FULL;
  2869. else
  2870. ecmd->duplex = DUPLEX_HALF;
  2871. } else {
  2872. ecmd->speed = -1;
  2873. ecmd->duplex = -1;
  2874. }
  2875. if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
  2876. hw->media_type == MEDIA_TYPE_1000M_FULL)
  2877. ecmd->autoneg = AUTONEG_ENABLE;
  2878. else
  2879. ecmd->autoneg = AUTONEG_DISABLE;
  2880. return 0;
  2881. }
  2882. static int atl1_set_settings(struct net_device *netdev,
  2883. struct ethtool_cmd *ecmd)
  2884. {
  2885. struct atl1_adapter *adapter = netdev_priv(netdev);
  2886. struct atl1_hw *hw = &adapter->hw;
  2887. u16 phy_data;
  2888. int ret_val = 0;
  2889. u16 old_media_type = hw->media_type;
  2890. if (netif_running(adapter->netdev)) {
  2891. if (netif_msg_link(adapter))
  2892. dev_dbg(&adapter->pdev->dev,
  2893. "ethtool shutting down adapter\n");
  2894. atl1_down(adapter);
  2895. }
  2896. if (ecmd->autoneg == AUTONEG_ENABLE)
  2897. hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
  2898. else {
  2899. if (ecmd->speed == SPEED_1000) {
  2900. if (ecmd->duplex != DUPLEX_FULL) {
  2901. if (netif_msg_link(adapter))
  2902. dev_warn(&adapter->pdev->dev,
  2903. "1000M half is invalid\n");
  2904. ret_val = -EINVAL;
  2905. goto exit_sset;
  2906. }
  2907. hw->media_type = MEDIA_TYPE_1000M_FULL;
  2908. } else if (ecmd->speed == SPEED_100) {
  2909. if (ecmd->duplex == DUPLEX_FULL)
  2910. hw->media_type = MEDIA_TYPE_100M_FULL;
  2911. else
  2912. hw->media_type = MEDIA_TYPE_100M_HALF;
  2913. } else {
  2914. if (ecmd->duplex == DUPLEX_FULL)
  2915. hw->media_type = MEDIA_TYPE_10M_FULL;
  2916. else
  2917. hw->media_type = MEDIA_TYPE_10M_HALF;
  2918. }
  2919. }
  2920. switch (hw->media_type) {
  2921. case MEDIA_TYPE_AUTO_SENSOR:
  2922. ecmd->advertising =
  2923. ADVERTISED_10baseT_Half |
  2924. ADVERTISED_10baseT_Full |
  2925. ADVERTISED_100baseT_Half |
  2926. ADVERTISED_100baseT_Full |
  2927. ADVERTISED_1000baseT_Full |
  2928. ADVERTISED_Autoneg | ADVERTISED_TP;
  2929. break;
  2930. case MEDIA_TYPE_1000M_FULL:
  2931. ecmd->advertising =
  2932. ADVERTISED_1000baseT_Full |
  2933. ADVERTISED_Autoneg | ADVERTISED_TP;
  2934. break;
  2935. default:
  2936. ecmd->advertising = 0;
  2937. break;
  2938. }
  2939. if (atl1_phy_setup_autoneg_adv(hw)) {
  2940. ret_val = -EINVAL;
  2941. if (netif_msg_link(adapter))
  2942. dev_warn(&adapter->pdev->dev,
  2943. "invalid ethtool speed/duplex setting\n");
  2944. goto exit_sset;
  2945. }
  2946. if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
  2947. hw->media_type == MEDIA_TYPE_1000M_FULL)
  2948. phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
  2949. else {
  2950. switch (hw->media_type) {
  2951. case MEDIA_TYPE_100M_FULL:
  2952. phy_data =
  2953. MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
  2954. MII_CR_RESET;
  2955. break;
  2956. case MEDIA_TYPE_100M_HALF:
  2957. phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
  2958. break;
  2959. case MEDIA_TYPE_10M_FULL:
  2960. phy_data =
  2961. MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
  2962. break;
  2963. default:
  2964. /* MEDIA_TYPE_10M_HALF: */
  2965. phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
  2966. break;
  2967. }
  2968. }
  2969. atl1_write_phy_reg(hw, MII_BMCR, phy_data);
  2970. exit_sset:
  2971. if (ret_val)
  2972. hw->media_type = old_media_type;
  2973. if (netif_running(adapter->netdev)) {
  2974. if (netif_msg_link(adapter))
  2975. dev_dbg(&adapter->pdev->dev,
  2976. "ethtool starting adapter\n");
  2977. atl1_up(adapter);
  2978. } else if (!ret_val) {
  2979. if (netif_msg_link(adapter))
  2980. dev_dbg(&adapter->pdev->dev,
  2981. "ethtool resetting adapter\n");
  2982. atl1_reset(adapter);
  2983. }
  2984. return ret_val;
  2985. }
  2986. static void atl1_get_drvinfo(struct net_device *netdev,
  2987. struct ethtool_drvinfo *drvinfo)
  2988. {
  2989. struct atl1_adapter *adapter = netdev_priv(netdev);
  2990. strncpy(drvinfo->driver, ATLX_DRIVER_NAME, sizeof(drvinfo->driver));
  2991. strncpy(drvinfo->version, ATLX_DRIVER_VERSION,
  2992. sizeof(drvinfo->version));
  2993. strncpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
  2994. strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
  2995. sizeof(drvinfo->bus_info));
  2996. drvinfo->eedump_len = ATL1_EEDUMP_LEN;
  2997. }
  2998. static void atl1_get_wol(struct net_device *netdev,
  2999. struct ethtool_wolinfo *wol)
  3000. {
  3001. struct atl1_adapter *adapter = netdev_priv(netdev);
  3002. wol->supported = WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | WAKE_MAGIC;
  3003. wol->wolopts = 0;
  3004. if (adapter->wol & ATLX_WUFC_EX)
  3005. wol->wolopts |= WAKE_UCAST;
  3006. if (adapter->wol & ATLX_WUFC_MC)
  3007. wol->wolopts |= WAKE_MCAST;
  3008. if (adapter->wol & ATLX_WUFC_BC)
  3009. wol->wolopts |= WAKE_BCAST;
  3010. if (adapter->wol & ATLX_WUFC_MAG)
  3011. wol->wolopts |= WAKE_MAGIC;
  3012. return;
  3013. }
  3014. static int atl1_set_wol(struct net_device *netdev,
  3015. struct ethtool_wolinfo *wol)
  3016. {
  3017. struct atl1_adapter *adapter = netdev_priv(netdev);
  3018. if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
  3019. return -EOPNOTSUPP;
  3020. adapter->wol = 0;
  3021. if (wol->wolopts & WAKE_UCAST)
  3022. adapter->wol |= ATLX_WUFC_EX;
  3023. if (wol->wolopts & WAKE_MCAST)
  3024. adapter->wol |= ATLX_WUFC_MC;
  3025. if (wol->wolopts & WAKE_BCAST)
  3026. adapter->wol |= ATLX_WUFC_BC;
  3027. if (wol->wolopts & WAKE_MAGIC)
  3028. adapter->wol |= ATLX_WUFC_MAG;
  3029. return 0;
  3030. }
  3031. static u32 atl1_get_msglevel(struct net_device *netdev)
  3032. {
  3033. struct atl1_adapter *adapter = netdev_priv(netdev);
  3034. return adapter->msg_enable;
  3035. }
  3036. static void atl1_set_msglevel(struct net_device *netdev, u32 value)
  3037. {
  3038. struct atl1_adapter *adapter = netdev_priv(netdev);
  3039. adapter->msg_enable = value;
  3040. }
  3041. static int atl1_get_regs_len(struct net_device *netdev)
  3042. {
  3043. return ATL1_REG_COUNT * sizeof(u32);
  3044. }
  3045. static void atl1_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
  3046. void *p)
  3047. {
  3048. struct atl1_adapter *adapter = netdev_priv(netdev);
  3049. struct atl1_hw *hw = &adapter->hw;
  3050. unsigned int i;
  3051. u32 *regbuf = p;
  3052. for (i = 0; i < ATL1_REG_COUNT; i++) {
  3053. /*
  3054. * This switch statement avoids reserved regions
  3055. * of register space.
  3056. */
  3057. switch (i) {
  3058. case 6 ... 9:
  3059. case 14:
  3060. case 29 ... 31:
  3061. case 34 ... 63:
  3062. case 75 ... 127:
  3063. case 136 ... 1023:
  3064. case 1027 ... 1087:
  3065. case 1091 ... 1151:
  3066. case 1194 ... 1195:
  3067. case 1200 ... 1201:
  3068. case 1206 ... 1213:
  3069. case 1216 ... 1279:
  3070. case 1290 ... 1311:
  3071. case 1323 ... 1343:
  3072. case 1358 ... 1359:
  3073. case 1368 ... 1375:
  3074. case 1378 ... 1383:
  3075. case 1388 ... 1391:
  3076. case 1393 ... 1395:
  3077. case 1402 ... 1403:
  3078. case 1410 ... 1471:
  3079. case 1522 ... 1535:
  3080. /* reserved region; don't read it */
  3081. regbuf[i] = 0;
  3082. break;
  3083. default:
  3084. /* unreserved region */
  3085. regbuf[i] = ioread32(hw->hw_addr + (i * sizeof(u32)));
  3086. }
  3087. }
  3088. }
  3089. static void atl1_get_ringparam(struct net_device *netdev,
  3090. struct ethtool_ringparam *ring)
  3091. {
  3092. struct atl1_adapter *adapter = netdev_priv(netdev);
  3093. struct atl1_tpd_ring *txdr = &adapter->tpd_ring;
  3094. struct atl1_rfd_ring *rxdr = &adapter->rfd_ring;
  3095. ring->rx_max_pending = ATL1_MAX_RFD;
  3096. ring->tx_max_pending = ATL1_MAX_TPD;
  3097. ring->rx_mini_max_pending = 0;
  3098. ring->rx_jumbo_max_pending = 0;
  3099. ring->rx_pending = rxdr->count;
  3100. ring->tx_pending = txdr->count;
  3101. ring->rx_mini_pending = 0;
  3102. ring->rx_jumbo_pending = 0;
  3103. }
  3104. static int atl1_set_ringparam(struct net_device *netdev,
  3105. struct ethtool_ringparam *ring)
  3106. {
  3107. struct atl1_adapter *adapter = netdev_priv(netdev);
  3108. struct atl1_tpd_ring *tpdr = &adapter->tpd_ring;
  3109. struct atl1_rrd_ring *rrdr = &adapter->rrd_ring;
  3110. struct atl1_rfd_ring *rfdr = &adapter->rfd_ring;
  3111. struct atl1_tpd_ring tpd_old, tpd_new;
  3112. struct atl1_rfd_ring rfd_old, rfd_new;
  3113. struct atl1_rrd_ring rrd_old, rrd_new;
  3114. struct atl1_ring_header rhdr_old, rhdr_new;
  3115. int err;
  3116. tpd_old = adapter->tpd_ring;
  3117. rfd_old = adapter->rfd_ring;
  3118. rrd_old = adapter->rrd_ring;
  3119. rhdr_old = adapter->ring_header;
  3120. if (netif_running(adapter->netdev))
  3121. atl1_down(adapter);
  3122. rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD);
  3123. rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD :
  3124. rfdr->count;
  3125. rfdr->count = (rfdr->count + 3) & ~3;
  3126. rrdr->count = rfdr->count;
  3127. tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD);
  3128. tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD :
  3129. tpdr->count;
  3130. tpdr->count = (tpdr->count + 3) & ~3;
  3131. if (netif_running(adapter->netdev)) {
  3132. /* try to get new resources before deleting old */
  3133. err = atl1_setup_ring_resources(adapter);
  3134. if (err)
  3135. goto err_setup_ring;
  3136. /*
  3137. * save the new, restore the old in order to free it,
  3138. * then restore the new back again
  3139. */
  3140. rfd_new = adapter->rfd_ring;
  3141. rrd_new = adapter->rrd_ring;
  3142. tpd_new = adapter->tpd_ring;
  3143. rhdr_new = adapter->ring_header;
  3144. adapter->rfd_ring = rfd_old;
  3145. adapter->rrd_ring = rrd_old;
  3146. adapter->tpd_ring = tpd_old;
  3147. adapter->ring_header = rhdr_old;
  3148. atl1_free_ring_resources(adapter);
  3149. adapter->rfd_ring = rfd_new;
  3150. adapter->rrd_ring = rrd_new;
  3151. adapter->tpd_ring = tpd_new;
  3152. adapter->ring_header = rhdr_new;
  3153. err = atl1_up(adapter);
  3154. if (err)
  3155. return err;
  3156. }
  3157. return 0;
  3158. err_setup_ring:
  3159. adapter->rfd_ring = rfd_old;
  3160. adapter->rrd_ring = rrd_old;
  3161. adapter->tpd_ring = tpd_old;
  3162. adapter->ring_header = rhdr_old;
  3163. atl1_up(adapter);
  3164. return err;
  3165. }
  3166. static void atl1_get_pauseparam(struct net_device *netdev,
  3167. struct ethtool_pauseparam *epause)
  3168. {
  3169. struct atl1_adapter *adapter = netdev_priv(netdev);
  3170. struct atl1_hw *hw = &adapter->hw;
  3171. if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
  3172. hw->media_type == MEDIA_TYPE_1000M_FULL) {
  3173. epause->autoneg = AUTONEG_ENABLE;
  3174. } else {
  3175. epause->autoneg = AUTONEG_DISABLE;
  3176. }
  3177. epause->rx_pause = 1;
  3178. epause->tx_pause = 1;
  3179. }
  3180. static int atl1_set_pauseparam(struct net_device *netdev,
  3181. struct ethtool_pauseparam *epause)
  3182. {
  3183. struct atl1_adapter *adapter = netdev_priv(netdev);
  3184. struct atl1_hw *hw = &adapter->hw;
  3185. if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
  3186. hw->media_type == MEDIA_TYPE_1000M_FULL) {
  3187. epause->autoneg = AUTONEG_ENABLE;
  3188. } else {
  3189. epause->autoneg = AUTONEG_DISABLE;
  3190. }
  3191. epause->rx_pause = 1;
  3192. epause->tx_pause = 1;
  3193. return 0;
  3194. }
  3195. /* FIXME: is this right? -- CHS */
  3196. static u32 atl1_get_rx_csum(struct net_device *netdev)
  3197. {
  3198. return 1;
  3199. }
  3200. static void atl1_get_strings(struct net_device *netdev, u32 stringset,
  3201. u8 *data)
  3202. {
  3203. u8 *p = data;
  3204. int i;
  3205. switch (stringset) {
  3206. case ETH_SS_STATS:
  3207. for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
  3208. memcpy(p, atl1_gstrings_stats[i].stat_string,
  3209. ETH_GSTRING_LEN);
  3210. p += ETH_GSTRING_LEN;
  3211. }
  3212. break;
  3213. }
  3214. }
  3215. static int atl1_nway_reset(struct net_device *netdev)
  3216. {
  3217. struct atl1_adapter *adapter = netdev_priv(netdev);
  3218. struct atl1_hw *hw = &adapter->hw;
  3219. if (netif_running(netdev)) {
  3220. u16 phy_data;
  3221. atl1_down(adapter);
  3222. if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
  3223. hw->media_type == MEDIA_TYPE_1000M_FULL) {
  3224. phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
  3225. } else {
  3226. switch (hw->media_type) {
  3227. case MEDIA_TYPE_100M_FULL:
  3228. phy_data = MII_CR_FULL_DUPLEX |
  3229. MII_CR_SPEED_100 | MII_CR_RESET;
  3230. break;
  3231. case MEDIA_TYPE_100M_HALF:
  3232. phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
  3233. break;
  3234. case MEDIA_TYPE_10M_FULL:
  3235. phy_data = MII_CR_FULL_DUPLEX |
  3236. MII_CR_SPEED_10 | MII_CR_RESET;
  3237. break;
  3238. default:
  3239. /* MEDIA_TYPE_10M_HALF */
  3240. phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
  3241. }
  3242. }
  3243. atl1_write_phy_reg(hw, MII_BMCR, phy_data);
  3244. atl1_up(adapter);
  3245. }
  3246. return 0;
  3247. }
  3248. const struct ethtool_ops atl1_ethtool_ops = {
  3249. .get_settings = atl1_get_settings,
  3250. .set_settings = atl1_set_settings,
  3251. .get_drvinfo = atl1_get_drvinfo,
  3252. .get_wol = atl1_get_wol,
  3253. .set_wol = atl1_set_wol,
  3254. .get_msglevel = atl1_get_msglevel,
  3255. .set_msglevel = atl1_set_msglevel,
  3256. .get_regs_len = atl1_get_regs_len,
  3257. .get_regs = atl1_get_regs,
  3258. .get_ringparam = atl1_get_ringparam,
  3259. .set_ringparam = atl1_set_ringparam,
  3260. .get_pauseparam = atl1_get_pauseparam,
  3261. .set_pauseparam = atl1_set_pauseparam,
  3262. .get_rx_csum = atl1_get_rx_csum,
  3263. .set_tx_csum = ethtool_op_set_tx_hw_csum,
  3264. .get_link = ethtool_op_get_link,
  3265. .set_sg = ethtool_op_set_sg,
  3266. .get_strings = atl1_get_strings,
  3267. .nway_reset = atl1_nway_reset,
  3268. .get_ethtool_stats = atl1_get_ethtool_stats,
  3269. .get_sset_count = atl1_get_sset_count,
  3270. .set_tso = ethtool_op_set_tso,
  3271. };