ucb1400_ts.c 15 KB

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  1. /*
  2. * Philips UCB1400 touchscreen driver
  3. *
  4. * Author: Nicolas Pitre
  5. * Created: September 25, 2006
  6. * Copyright: MontaVista Software, Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * This code is heavily based on ucb1x00-*.c copyrighted by Russell King
  13. * covering the UCB1100, UCB1200 and UCB1300.. Support for the UCB1400 has
  14. * been made separate from ucb1x00-core/ucb1x00-ts on Russell's request.
  15. */
  16. #include <linux/module.h>
  17. #include <linux/init.h>
  18. #include <linux/completion.h>
  19. #include <linux/delay.h>
  20. #include <linux/input.h>
  21. #include <linux/device.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/suspend.h>
  24. #include <linux/slab.h>
  25. #include <linux/kthread.h>
  26. #include <linux/freezer.h>
  27. #include <sound/core.h>
  28. #include <sound/ac97_codec.h>
  29. /*
  30. * Interesting UCB1400 AC-link registers
  31. */
  32. #define UCB_IE_RIS 0x5e
  33. #define UCB_IE_FAL 0x60
  34. #define UCB_IE_STATUS 0x62
  35. #define UCB_IE_CLEAR 0x62
  36. #define UCB_IE_ADC (1 << 11)
  37. #define UCB_IE_TSPX (1 << 12)
  38. #define UCB_TS_CR 0x64
  39. #define UCB_TS_CR_TSMX_POW (1 << 0)
  40. #define UCB_TS_CR_TSPX_POW (1 << 1)
  41. #define UCB_TS_CR_TSMY_POW (1 << 2)
  42. #define UCB_TS_CR_TSPY_POW (1 << 3)
  43. #define UCB_TS_CR_TSMX_GND (1 << 4)
  44. #define UCB_TS_CR_TSPX_GND (1 << 5)
  45. #define UCB_TS_CR_TSMY_GND (1 << 6)
  46. #define UCB_TS_CR_TSPY_GND (1 << 7)
  47. #define UCB_TS_CR_MODE_INT (0 << 8)
  48. #define UCB_TS_CR_MODE_PRES (1 << 8)
  49. #define UCB_TS_CR_MODE_POS (2 << 8)
  50. #define UCB_TS_CR_BIAS_ENA (1 << 11)
  51. #define UCB_TS_CR_TSPX_LOW (1 << 12)
  52. #define UCB_TS_CR_TSMX_LOW (1 << 13)
  53. #define UCB_ADC_CR 0x66
  54. #define UCB_ADC_SYNC_ENA (1 << 0)
  55. #define UCB_ADC_VREFBYP_CON (1 << 1)
  56. #define UCB_ADC_INP_TSPX (0 << 2)
  57. #define UCB_ADC_INP_TSMX (1 << 2)
  58. #define UCB_ADC_INP_TSPY (2 << 2)
  59. #define UCB_ADC_INP_TSMY (3 << 2)
  60. #define UCB_ADC_INP_AD0 (4 << 2)
  61. #define UCB_ADC_INP_AD1 (5 << 2)
  62. #define UCB_ADC_INP_AD2 (6 << 2)
  63. #define UCB_ADC_INP_AD3 (7 << 2)
  64. #define UCB_ADC_EXT_REF (1 << 5)
  65. #define UCB_ADC_START (1 << 7)
  66. #define UCB_ADC_ENA (1 << 15)
  67. #define UCB_ADC_DATA 0x68
  68. #define UCB_ADC_DAT_VALID (1 << 15)
  69. #define UCB_ADC_DAT_VALUE(x) ((x) & 0x3ff)
  70. #define UCB_ID 0x7e
  71. #define UCB_ID_1400 0x4304
  72. struct ucb1400 {
  73. struct snd_ac97 *ac97;
  74. struct input_dev *ts_idev;
  75. int irq;
  76. wait_queue_head_t ts_wait;
  77. struct task_struct *ts_task;
  78. unsigned int irq_pending; /* not bit field shared */
  79. unsigned int ts_restart:1;
  80. unsigned int adcsync:1;
  81. };
  82. static int adcsync;
  83. static int ts_delay = 55; /* us */
  84. static int ts_delay_pressure; /* us */
  85. static inline u16 ucb1400_reg_read(struct ucb1400 *ucb, u16 reg)
  86. {
  87. return ucb->ac97->bus->ops->read(ucb->ac97, reg);
  88. }
  89. static inline void ucb1400_reg_write(struct ucb1400 *ucb, u16 reg, u16 val)
  90. {
  91. ucb->ac97->bus->ops->write(ucb->ac97, reg, val);
  92. }
  93. static inline void ucb1400_adc_enable(struct ucb1400 *ucb)
  94. {
  95. ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA);
  96. }
  97. static unsigned int ucb1400_adc_read(struct ucb1400 *ucb, u16 adc_channel)
  98. {
  99. unsigned int val;
  100. if (ucb->adcsync)
  101. adc_channel |= UCB_ADC_SYNC_ENA;
  102. ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | adc_channel);
  103. ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | adc_channel | UCB_ADC_START);
  104. for (;;) {
  105. val = ucb1400_reg_read(ucb, UCB_ADC_DATA);
  106. if (val & UCB_ADC_DAT_VALID)
  107. break;
  108. /* yield to other processes */
  109. schedule_timeout_uninterruptible(1);
  110. }
  111. return UCB_ADC_DAT_VALUE(val);
  112. }
  113. static inline void ucb1400_adc_disable(struct ucb1400 *ucb)
  114. {
  115. ucb1400_reg_write(ucb, UCB_ADC_CR, 0);
  116. }
  117. /* Switch to interrupt mode. */
  118. static inline void ucb1400_ts_mode_int(struct ucb1400 *ucb)
  119. {
  120. ucb1400_reg_write(ucb, UCB_TS_CR,
  121. UCB_TS_CR_TSMX_POW | UCB_TS_CR_TSPX_POW |
  122. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_GND |
  123. UCB_TS_CR_MODE_INT);
  124. }
  125. /*
  126. * Switch to pressure mode, and read pressure. We don't need to wait
  127. * here, since both plates are being driven.
  128. */
  129. static inline unsigned int ucb1400_ts_read_pressure(struct ucb1400 *ucb)
  130. {
  131. ucb1400_reg_write(ucb, UCB_TS_CR,
  132. UCB_TS_CR_TSMX_POW | UCB_TS_CR_TSPX_POW |
  133. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_GND |
  134. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  135. udelay(ts_delay_pressure);
  136. return ucb1400_adc_read(ucb, UCB_ADC_INP_TSPY);
  137. }
  138. /*
  139. * Switch to X position mode and measure Y plate. We switch the plate
  140. * configuration in pressure mode, then switch to position mode. This
  141. * gives a faster response time. Even so, we need to wait about 55us
  142. * for things to stabilise.
  143. */
  144. static inline unsigned int ucb1400_ts_read_xpos(struct ucb1400 *ucb)
  145. {
  146. ucb1400_reg_write(ucb, UCB_TS_CR,
  147. UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
  148. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  149. ucb1400_reg_write(ucb, UCB_TS_CR,
  150. UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
  151. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  152. ucb1400_reg_write(ucb, UCB_TS_CR,
  153. UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
  154. UCB_TS_CR_MODE_POS | UCB_TS_CR_BIAS_ENA);
  155. udelay(ts_delay);
  156. return ucb1400_adc_read(ucb, UCB_ADC_INP_TSPY);
  157. }
  158. /*
  159. * Switch to Y position mode and measure X plate. We switch the plate
  160. * configuration in pressure mode, then switch to position mode. This
  161. * gives a faster response time. Even so, we need to wait about 55us
  162. * for things to stabilise.
  163. */
  164. static inline unsigned int ucb1400_ts_read_ypos(struct ucb1400 *ucb)
  165. {
  166. ucb1400_reg_write(ucb, UCB_TS_CR,
  167. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
  168. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  169. ucb1400_reg_write(ucb, UCB_TS_CR,
  170. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
  171. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  172. ucb1400_reg_write(ucb, UCB_TS_CR,
  173. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
  174. UCB_TS_CR_MODE_POS | UCB_TS_CR_BIAS_ENA);
  175. udelay(ts_delay);
  176. return ucb1400_adc_read(ucb, UCB_ADC_INP_TSPX);
  177. }
  178. /*
  179. * Switch to X plate resistance mode. Set MX to ground, PX to
  180. * supply. Measure current.
  181. */
  182. static inline unsigned int ucb1400_ts_read_xres(struct ucb1400 *ucb)
  183. {
  184. ucb1400_reg_write(ucb, UCB_TS_CR,
  185. UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
  186. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  187. return ucb1400_adc_read(ucb, 0);
  188. }
  189. /*
  190. * Switch to Y plate resistance mode. Set MY to ground, PY to
  191. * supply. Measure current.
  192. */
  193. static inline unsigned int ucb1400_ts_read_yres(struct ucb1400 *ucb)
  194. {
  195. ucb1400_reg_write(ucb, UCB_TS_CR,
  196. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
  197. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  198. return ucb1400_adc_read(ucb, 0);
  199. }
  200. static inline int ucb1400_ts_pen_down(struct ucb1400 *ucb)
  201. {
  202. unsigned short val = ucb1400_reg_read(ucb, UCB_TS_CR);
  203. return (val & (UCB_TS_CR_TSPX_LOW | UCB_TS_CR_TSMX_LOW));
  204. }
  205. static inline void ucb1400_ts_irq_enable(struct ucb1400 *ucb)
  206. {
  207. ucb1400_reg_write(ucb, UCB_IE_CLEAR, UCB_IE_TSPX);
  208. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0);
  209. ucb1400_reg_write(ucb, UCB_IE_FAL, UCB_IE_TSPX);
  210. }
  211. static inline void ucb1400_ts_irq_disable(struct ucb1400 *ucb)
  212. {
  213. ucb1400_reg_write(ucb, UCB_IE_FAL, 0);
  214. }
  215. static void ucb1400_ts_evt_add(struct input_dev *idev, u16 pressure, u16 x, u16 y)
  216. {
  217. input_report_abs(idev, ABS_X, x);
  218. input_report_abs(idev, ABS_Y, y);
  219. input_report_abs(idev, ABS_PRESSURE, pressure);
  220. input_sync(idev);
  221. }
  222. static void ucb1400_ts_event_release(struct input_dev *idev)
  223. {
  224. input_report_abs(idev, ABS_PRESSURE, 0);
  225. input_sync(idev);
  226. }
  227. static void ucb1400_handle_pending_irq(struct ucb1400 *ucb)
  228. {
  229. unsigned int isr;
  230. isr = ucb1400_reg_read(ucb, UCB_IE_STATUS);
  231. ucb1400_reg_write(ucb, UCB_IE_CLEAR, isr);
  232. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0);
  233. if (isr & UCB_IE_TSPX)
  234. ucb1400_ts_irq_disable(ucb);
  235. else
  236. printk(KERN_ERR "ucb1400: unexpected IE_STATUS = %#x\n", isr);
  237. enable_irq(ucb->irq);
  238. }
  239. static int ucb1400_ts_thread(void *_ucb)
  240. {
  241. struct ucb1400 *ucb = _ucb;
  242. struct task_struct *tsk = current;
  243. int valid = 0;
  244. struct sched_param param = { .sched_priority = 1 };
  245. sched_setscheduler(tsk, SCHED_FIFO, &param);
  246. set_freezable();
  247. while (!kthread_should_stop()) {
  248. unsigned int x, y, p;
  249. long timeout;
  250. ucb->ts_restart = 0;
  251. if (ucb->irq_pending) {
  252. ucb->irq_pending = 0;
  253. ucb1400_handle_pending_irq(ucb);
  254. }
  255. ucb1400_adc_enable(ucb);
  256. x = ucb1400_ts_read_xpos(ucb);
  257. y = ucb1400_ts_read_ypos(ucb);
  258. p = ucb1400_ts_read_pressure(ucb);
  259. ucb1400_adc_disable(ucb);
  260. /* Switch back to interrupt mode. */
  261. ucb1400_ts_mode_int(ucb);
  262. msleep(10);
  263. if (ucb1400_ts_pen_down(ucb)) {
  264. ucb1400_ts_irq_enable(ucb);
  265. /*
  266. * If we spat out a valid sample set last time,
  267. * spit out a "pen off" sample here.
  268. */
  269. if (valid) {
  270. ucb1400_ts_event_release(ucb->ts_idev);
  271. valid = 0;
  272. }
  273. timeout = MAX_SCHEDULE_TIMEOUT;
  274. } else {
  275. valid = 1;
  276. ucb1400_ts_evt_add(ucb->ts_idev, p, x, y);
  277. timeout = msecs_to_jiffies(10);
  278. }
  279. wait_event_freezable_timeout(ucb->ts_wait,
  280. ucb->irq_pending || ucb->ts_restart || kthread_should_stop(),
  281. timeout);
  282. }
  283. /* Send the "pen off" if we are stopping with the pen still active */
  284. if (valid)
  285. ucb1400_ts_event_release(ucb->ts_idev);
  286. ucb->ts_task = NULL;
  287. return 0;
  288. }
  289. /*
  290. * A restriction with interrupts exists when using the ucb1400, as
  291. * the codec read/write routines may sleep while waiting for codec
  292. * access completion and uses semaphores for access control to the
  293. * AC97 bus. A complete codec read cycle could take anywhere from
  294. * 60 to 100uSec so we *definitely* don't want to spin inside the
  295. * interrupt handler waiting for codec access. So, we handle the
  296. * interrupt by scheduling a RT kernel thread to run in process
  297. * context instead of interrupt context.
  298. */
  299. static irqreturn_t ucb1400_hard_irq(int irqnr, void *devid)
  300. {
  301. struct ucb1400 *ucb = devid;
  302. if (irqnr == ucb->irq) {
  303. disable_irq(ucb->irq);
  304. ucb->irq_pending = 1;
  305. wake_up(&ucb->ts_wait);
  306. return IRQ_HANDLED;
  307. }
  308. return IRQ_NONE;
  309. }
  310. static int ucb1400_ts_open(struct input_dev *idev)
  311. {
  312. struct ucb1400 *ucb = input_get_drvdata(idev);
  313. int ret = 0;
  314. BUG_ON(ucb->ts_task);
  315. ucb->ts_task = kthread_run(ucb1400_ts_thread, ucb, "UCB1400_ts");
  316. if (IS_ERR(ucb->ts_task)) {
  317. ret = PTR_ERR(ucb->ts_task);
  318. ucb->ts_task = NULL;
  319. }
  320. return ret;
  321. }
  322. static void ucb1400_ts_close(struct input_dev *idev)
  323. {
  324. struct ucb1400 *ucb = input_get_drvdata(idev);
  325. if (ucb->ts_task)
  326. kthread_stop(ucb->ts_task);
  327. ucb1400_ts_irq_disable(ucb);
  328. ucb1400_reg_write(ucb, UCB_TS_CR, 0);
  329. }
  330. #ifdef CONFIG_PM
  331. static int ucb1400_ts_resume(struct device *dev)
  332. {
  333. struct ucb1400 *ucb = dev_get_drvdata(dev);
  334. if (ucb->ts_task) {
  335. /*
  336. * Restart the TS thread to ensure the
  337. * TS interrupt mode is set up again
  338. * after sleep.
  339. */
  340. ucb->ts_restart = 1;
  341. wake_up(&ucb->ts_wait);
  342. }
  343. return 0;
  344. }
  345. #else
  346. #define ucb1400_ts_resume NULL
  347. #endif
  348. #ifndef NO_IRQ
  349. #define NO_IRQ 0
  350. #endif
  351. /*
  352. * Try to probe our interrupt, rather than relying on lots of
  353. * hard-coded machine dependencies.
  354. */
  355. static int ucb1400_detect_irq(struct ucb1400 *ucb)
  356. {
  357. unsigned long mask, timeout;
  358. mask = probe_irq_on();
  359. /* Enable the ADC interrupt. */
  360. ucb1400_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC);
  361. ucb1400_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC);
  362. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
  363. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0);
  364. /* Cause an ADC interrupt. */
  365. ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA);
  366. ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START);
  367. /* Wait for the conversion to complete. */
  368. timeout = jiffies + HZ/2;
  369. while (!(ucb1400_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VALID)) {
  370. cpu_relax();
  371. if (time_after(jiffies, timeout)) {
  372. printk(KERN_ERR "ucb1400: timed out in IRQ probe\n");
  373. probe_irq_off(mask);
  374. return -ENODEV;
  375. }
  376. }
  377. ucb1400_reg_write(ucb, UCB_ADC_CR, 0);
  378. /* Disable and clear interrupt. */
  379. ucb1400_reg_write(ucb, UCB_IE_RIS, 0);
  380. ucb1400_reg_write(ucb, UCB_IE_FAL, 0);
  381. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
  382. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0);
  383. /* Read triggered interrupt. */
  384. ucb->irq = probe_irq_off(mask);
  385. if (ucb->irq < 0 || ucb->irq == NO_IRQ)
  386. return -ENODEV;
  387. return 0;
  388. }
  389. static int ucb1400_ts_probe(struct device *dev)
  390. {
  391. struct ucb1400 *ucb;
  392. struct input_dev *idev;
  393. int error, id, x_res, y_res;
  394. ucb = kzalloc(sizeof(struct ucb1400), GFP_KERNEL);
  395. idev = input_allocate_device();
  396. if (!ucb || !idev) {
  397. error = -ENOMEM;
  398. goto err_free_devs;
  399. }
  400. ucb->ts_idev = idev;
  401. ucb->adcsync = adcsync;
  402. ucb->ac97 = to_ac97_t(dev);
  403. init_waitqueue_head(&ucb->ts_wait);
  404. id = ucb1400_reg_read(ucb, UCB_ID);
  405. if (id != UCB_ID_1400) {
  406. error = -ENODEV;
  407. goto err_free_devs;
  408. }
  409. error = ucb1400_detect_irq(ucb);
  410. if (error) {
  411. printk(KERN_ERR "UCB1400: IRQ probe failed\n");
  412. goto err_free_devs;
  413. }
  414. error = request_irq(ucb->irq, ucb1400_hard_irq, IRQF_TRIGGER_RISING,
  415. "UCB1400", ucb);
  416. if (error) {
  417. printk(KERN_ERR "ucb1400: unable to grab irq%d: %d\n",
  418. ucb->irq, error);
  419. goto err_free_devs;
  420. }
  421. printk(KERN_DEBUG "UCB1400: found IRQ %d\n", ucb->irq);
  422. input_set_drvdata(idev, ucb);
  423. idev->dev.parent = dev;
  424. idev->name = "UCB1400 touchscreen interface";
  425. idev->id.vendor = ucb1400_reg_read(ucb, AC97_VENDOR_ID1);
  426. idev->id.product = id;
  427. idev->open = ucb1400_ts_open;
  428. idev->close = ucb1400_ts_close;
  429. idev->evbit[0] = BIT_MASK(EV_ABS);
  430. ucb1400_adc_enable(ucb);
  431. x_res = ucb1400_ts_read_xres(ucb);
  432. y_res = ucb1400_ts_read_yres(ucb);
  433. ucb1400_adc_disable(ucb);
  434. printk(KERN_DEBUG "UCB1400: x/y = %d/%d\n", x_res, y_res);
  435. input_set_abs_params(idev, ABS_X, 0, x_res, 0, 0);
  436. input_set_abs_params(idev, ABS_Y, 0, y_res, 0, 0);
  437. input_set_abs_params(idev, ABS_PRESSURE, 0, 0, 0, 0);
  438. error = input_register_device(idev);
  439. if (error)
  440. goto err_free_irq;
  441. dev_set_drvdata(dev, ucb);
  442. return 0;
  443. err_free_irq:
  444. free_irq(ucb->irq, ucb);
  445. err_free_devs:
  446. input_free_device(idev);
  447. kfree(ucb);
  448. return error;
  449. }
  450. static int ucb1400_ts_remove(struct device *dev)
  451. {
  452. struct ucb1400 *ucb = dev_get_drvdata(dev);
  453. free_irq(ucb->irq, ucb);
  454. input_unregister_device(ucb->ts_idev);
  455. dev_set_drvdata(dev, NULL);
  456. kfree(ucb);
  457. return 0;
  458. }
  459. static struct device_driver ucb1400_ts_driver = {
  460. .name = "ucb1400_ts",
  461. .owner = THIS_MODULE,
  462. .bus = &ac97_bus_type,
  463. .probe = ucb1400_ts_probe,
  464. .remove = ucb1400_ts_remove,
  465. .resume = ucb1400_ts_resume,
  466. };
  467. static int __init ucb1400_ts_init(void)
  468. {
  469. return driver_register(&ucb1400_ts_driver);
  470. }
  471. static void __exit ucb1400_ts_exit(void)
  472. {
  473. driver_unregister(&ucb1400_ts_driver);
  474. }
  475. module_param(adcsync, bool, 0444);
  476. MODULE_PARM_DESC(adcsync, "Synchronize touch readings with ADCSYNC pin.");
  477. module_param(ts_delay, int, 0444);
  478. MODULE_PARM_DESC(ts_delay, "Delay between panel setup and position read. Default = 55us.");
  479. module_param(ts_delay_pressure, int, 0444);
  480. MODULE_PARM_DESC(ts_delay_pressure,
  481. "delay between panel setup and pressure read. Default = 0us.");
  482. module_init(ucb1400_ts_init);
  483. module_exit(ucb1400_ts_exit);
  484. MODULE_DESCRIPTION("Philips UCB1400 touchscreen driver");
  485. MODULE_LICENSE("GPL");