mthca_main.c 37 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. *
  34. * $Id: mthca_main.c 1396 2004-12-28 04:10:27Z roland $
  35. */
  36. #include <linux/module.h>
  37. #include <linux/init.h>
  38. #include <linux/errno.h>
  39. #include <linux/pci.h>
  40. #include <linux/interrupt.h>
  41. #include "mthca_dev.h"
  42. #include "mthca_config_reg.h"
  43. #include "mthca_cmd.h"
  44. #include "mthca_profile.h"
  45. #include "mthca_memfree.h"
  46. #include "mthca_wqe.h"
  47. MODULE_AUTHOR("Roland Dreier");
  48. MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
  49. MODULE_LICENSE("Dual BSD/GPL");
  50. MODULE_VERSION(DRV_VERSION);
  51. #ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
  52. int mthca_debug_level = 0;
  53. module_param_named(debug_level, mthca_debug_level, int, 0644);
  54. MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  55. #endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
  56. #ifdef CONFIG_PCI_MSI
  57. static int msi_x = 1;
  58. module_param(msi_x, int, 0444);
  59. MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  60. #else /* CONFIG_PCI_MSI */
  61. #define msi_x (0)
  62. #endif /* CONFIG_PCI_MSI */
  63. static int tune_pci = 0;
  64. module_param(tune_pci, int, 0444);
  65. MODULE_PARM_DESC(tune_pci, "increase PCI burst from the default set by BIOS if nonzero");
  66. DEFINE_MUTEX(mthca_device_mutex);
  67. #define MTHCA_DEFAULT_NUM_QP (1 << 16)
  68. #define MTHCA_DEFAULT_RDB_PER_QP (1 << 2)
  69. #define MTHCA_DEFAULT_NUM_CQ (1 << 16)
  70. #define MTHCA_DEFAULT_NUM_MCG (1 << 13)
  71. #define MTHCA_DEFAULT_NUM_MPT (1 << 17)
  72. #define MTHCA_DEFAULT_NUM_MTT (1 << 20)
  73. #define MTHCA_DEFAULT_NUM_UDAV (1 << 15)
  74. #define MTHCA_DEFAULT_NUM_RESERVED_MTTS (1 << 18)
  75. #define MTHCA_DEFAULT_NUM_UARC_SIZE (1 << 18)
  76. static struct mthca_profile hca_profile = {
  77. .num_qp = MTHCA_DEFAULT_NUM_QP,
  78. .rdb_per_qp = MTHCA_DEFAULT_RDB_PER_QP,
  79. .num_cq = MTHCA_DEFAULT_NUM_CQ,
  80. .num_mcg = MTHCA_DEFAULT_NUM_MCG,
  81. .num_mpt = MTHCA_DEFAULT_NUM_MPT,
  82. .num_mtt = MTHCA_DEFAULT_NUM_MTT,
  83. .num_udav = MTHCA_DEFAULT_NUM_UDAV, /* Tavor only */
  84. .fmr_reserved_mtts = MTHCA_DEFAULT_NUM_RESERVED_MTTS, /* Tavor only */
  85. .uarc_size = MTHCA_DEFAULT_NUM_UARC_SIZE, /* Arbel only */
  86. };
  87. module_param_named(num_qp, hca_profile.num_qp, int, 0444);
  88. MODULE_PARM_DESC(num_qp, "maximum number of QPs per HCA");
  89. module_param_named(rdb_per_qp, hca_profile.rdb_per_qp, int, 0444);
  90. MODULE_PARM_DESC(rdb_per_qp, "number of RDB buffers per QP");
  91. module_param_named(num_cq, hca_profile.num_cq, int, 0444);
  92. MODULE_PARM_DESC(num_cq, "maximum number of CQs per HCA");
  93. module_param_named(num_mcg, hca_profile.num_mcg, int, 0444);
  94. MODULE_PARM_DESC(num_mcg, "maximum number of multicast groups per HCA");
  95. module_param_named(num_mpt, hca_profile.num_mpt, int, 0444);
  96. MODULE_PARM_DESC(num_mpt,
  97. "maximum number of memory protection table entries per HCA");
  98. module_param_named(num_mtt, hca_profile.num_mtt, int, 0444);
  99. MODULE_PARM_DESC(num_mtt,
  100. "maximum number of memory translation table segments per HCA");
  101. module_param_named(num_udav, hca_profile.num_udav, int, 0444);
  102. MODULE_PARM_DESC(num_udav, "maximum number of UD address vectors per HCA");
  103. module_param_named(fmr_reserved_mtts, hca_profile.fmr_reserved_mtts, int, 0444);
  104. MODULE_PARM_DESC(fmr_reserved_mtts,
  105. "number of memory translation table segments reserved for FMR");
  106. static char mthca_version[] __devinitdata =
  107. DRV_NAME ": Mellanox InfiniBand HCA driver v"
  108. DRV_VERSION " (" DRV_RELDATE ")\n";
  109. static int mthca_tune_pci(struct mthca_dev *mdev)
  110. {
  111. if (!tune_pci)
  112. return 0;
  113. /* First try to max out Read Byte Count */
  114. if (pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX)) {
  115. if (pcix_set_mmrbc(mdev->pdev, pcix_get_max_mmrbc(mdev->pdev))) {
  116. mthca_err(mdev, "Couldn't set PCI-X max read count, "
  117. "aborting.\n");
  118. return -ENODEV;
  119. }
  120. } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
  121. mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
  122. if (pci_find_capability(mdev->pdev, PCI_CAP_ID_EXP)) {
  123. if (pcie_set_readrq(mdev->pdev, 4096)) {
  124. mthca_err(mdev, "Couldn't write PCI Express read request, "
  125. "aborting.\n");
  126. return -ENODEV;
  127. }
  128. } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
  129. mthca_info(mdev, "No PCI Express capability, "
  130. "not setting Max Read Request Size.\n");
  131. return 0;
  132. }
  133. static int mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
  134. {
  135. int err;
  136. u8 status;
  137. err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status);
  138. if (err) {
  139. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  140. return err;
  141. }
  142. if (status) {
  143. mthca_err(mdev, "QUERY_DEV_LIM returned status 0x%02x, "
  144. "aborting.\n", status);
  145. return -EINVAL;
  146. }
  147. if (dev_lim->min_page_sz > PAGE_SIZE) {
  148. mthca_err(mdev, "HCA minimum page size of %d bigger than "
  149. "kernel PAGE_SIZE of %ld, aborting.\n",
  150. dev_lim->min_page_sz, PAGE_SIZE);
  151. return -ENODEV;
  152. }
  153. if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
  154. mthca_err(mdev, "HCA has %d ports, but we only support %d, "
  155. "aborting.\n",
  156. dev_lim->num_ports, MTHCA_MAX_PORTS);
  157. return -ENODEV;
  158. }
  159. if (dev_lim->uar_size > pci_resource_len(mdev->pdev, 2)) {
  160. mthca_err(mdev, "HCA reported UAR size of 0x%x bigger than "
  161. "PCI resource 2 size of 0x%llx, aborting.\n",
  162. dev_lim->uar_size,
  163. (unsigned long long)pci_resource_len(mdev->pdev, 2));
  164. return -ENODEV;
  165. }
  166. mdev->limits.num_ports = dev_lim->num_ports;
  167. mdev->limits.vl_cap = dev_lim->max_vl;
  168. mdev->limits.mtu_cap = dev_lim->max_mtu;
  169. mdev->limits.gid_table_len = dev_lim->max_gids;
  170. mdev->limits.pkey_table_len = dev_lim->max_pkeys;
  171. mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
  172. /*
  173. * Need to allow for worst case send WQE overhead and check
  174. * whether max_desc_sz imposes a lower limit than max_sg; UD
  175. * send has the biggest overhead.
  176. */
  177. mdev->limits.max_sg = min_t(int, dev_lim->max_sg,
  178. (dev_lim->max_desc_sz -
  179. sizeof (struct mthca_next_seg) -
  180. (mthca_is_memfree(mdev) ?
  181. sizeof (struct mthca_arbel_ud_seg) :
  182. sizeof (struct mthca_tavor_ud_seg))) /
  183. sizeof (struct mthca_data_seg));
  184. mdev->limits.max_wqes = dev_lim->max_qp_sz;
  185. mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp;
  186. mdev->limits.reserved_qps = dev_lim->reserved_qps;
  187. mdev->limits.max_srq_wqes = dev_lim->max_srq_sz;
  188. mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
  189. mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
  190. mdev->limits.max_desc_sz = dev_lim->max_desc_sz;
  191. mdev->limits.max_srq_sge = mthca_max_srq_sge(mdev);
  192. /*
  193. * Subtract 1 from the limit because we need to allocate a
  194. * spare CQE so the HCA HW can tell the difference between an
  195. * empty CQ and a full CQ.
  196. */
  197. mdev->limits.max_cqes = dev_lim->max_cq_sz - 1;
  198. mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
  199. mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
  200. mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
  201. mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
  202. mdev->limits.reserved_uars = dev_lim->reserved_uars;
  203. mdev->limits.reserved_pds = dev_lim->reserved_pds;
  204. mdev->limits.port_width_cap = dev_lim->max_port_width;
  205. mdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1);
  206. mdev->limits.flags = dev_lim->flags;
  207. /*
  208. * For old FW that doesn't return static rate support, use a
  209. * value of 0x3 (only static rate values of 0 or 1 are handled),
  210. * except on Sinai, where even old FW can handle static rate
  211. * values of 2 and 3.
  212. */
  213. if (dev_lim->stat_rate_support)
  214. mdev->limits.stat_rate_support = dev_lim->stat_rate_support;
  215. else if (mdev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
  216. mdev->limits.stat_rate_support = 0xf;
  217. else
  218. mdev->limits.stat_rate_support = 0x3;
  219. /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
  220. May be doable since hardware supports it for SRQ.
  221. IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
  222. IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
  223. supported by driver. */
  224. mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  225. IB_DEVICE_PORT_ACTIVE_EVENT |
  226. IB_DEVICE_SYS_IMAGE_GUID |
  227. IB_DEVICE_RC_RNR_NAK_GEN;
  228. if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
  229. mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  230. if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
  231. mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  232. if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
  233. mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
  234. if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
  235. mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  236. if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
  237. mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  238. if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
  239. mdev->mthca_flags |= MTHCA_FLAG_SRQ;
  240. if (mthca_is_memfree(mdev))
  241. if (dev_lim->flags & DEV_LIM_FLAG_IPOIB_CSUM)
  242. mdev->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
  243. return 0;
  244. }
  245. static int mthca_init_tavor(struct mthca_dev *mdev)
  246. {
  247. s64 size;
  248. u8 status;
  249. int err;
  250. struct mthca_dev_lim dev_lim;
  251. struct mthca_profile profile;
  252. struct mthca_init_hca_param init_hca;
  253. err = mthca_SYS_EN(mdev, &status);
  254. if (err) {
  255. mthca_err(mdev, "SYS_EN command failed, aborting.\n");
  256. return err;
  257. }
  258. if (status) {
  259. mthca_err(mdev, "SYS_EN returned status 0x%02x, "
  260. "aborting.\n", status);
  261. return -EINVAL;
  262. }
  263. err = mthca_QUERY_FW(mdev, &status);
  264. if (err) {
  265. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  266. goto err_disable;
  267. }
  268. if (status) {
  269. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  270. "aborting.\n", status);
  271. err = -EINVAL;
  272. goto err_disable;
  273. }
  274. err = mthca_QUERY_DDR(mdev, &status);
  275. if (err) {
  276. mthca_err(mdev, "QUERY_DDR command failed, aborting.\n");
  277. goto err_disable;
  278. }
  279. if (status) {
  280. mthca_err(mdev, "QUERY_DDR returned status 0x%02x, "
  281. "aborting.\n", status);
  282. err = -EINVAL;
  283. goto err_disable;
  284. }
  285. err = mthca_dev_lim(mdev, &dev_lim);
  286. if (err) {
  287. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  288. goto err_disable;
  289. }
  290. profile = hca_profile;
  291. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  292. profile.uarc_size = 0;
  293. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  294. profile.num_srq = dev_lim.max_srqs;
  295. size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  296. if (size < 0) {
  297. err = size;
  298. goto err_disable;
  299. }
  300. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  301. if (err) {
  302. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  303. goto err_disable;
  304. }
  305. if (status) {
  306. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  307. "aborting.\n", status);
  308. err = -EINVAL;
  309. goto err_disable;
  310. }
  311. return 0;
  312. err_disable:
  313. mthca_SYS_DIS(mdev, &status);
  314. return err;
  315. }
  316. static int mthca_load_fw(struct mthca_dev *mdev)
  317. {
  318. u8 status;
  319. int err;
  320. /* FIXME: use HCA-attached memory for FW if present */
  321. mdev->fw.arbel.fw_icm =
  322. mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
  323. GFP_HIGHUSER | __GFP_NOWARN, 0);
  324. if (!mdev->fw.arbel.fw_icm) {
  325. mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
  326. return -ENOMEM;
  327. }
  328. err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm, &status);
  329. if (err) {
  330. mthca_err(mdev, "MAP_FA command failed, aborting.\n");
  331. goto err_free;
  332. }
  333. if (status) {
  334. mthca_err(mdev, "MAP_FA returned status 0x%02x, aborting.\n", status);
  335. err = -EINVAL;
  336. goto err_free;
  337. }
  338. err = mthca_RUN_FW(mdev, &status);
  339. if (err) {
  340. mthca_err(mdev, "RUN_FW command failed, aborting.\n");
  341. goto err_unmap_fa;
  342. }
  343. if (status) {
  344. mthca_err(mdev, "RUN_FW returned status 0x%02x, aborting.\n", status);
  345. err = -EINVAL;
  346. goto err_unmap_fa;
  347. }
  348. return 0;
  349. err_unmap_fa:
  350. mthca_UNMAP_FA(mdev, &status);
  351. err_free:
  352. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  353. return err;
  354. }
  355. static int mthca_init_icm(struct mthca_dev *mdev,
  356. struct mthca_dev_lim *dev_lim,
  357. struct mthca_init_hca_param *init_hca,
  358. u64 icm_size)
  359. {
  360. u64 aux_pages;
  361. u8 status;
  362. int err;
  363. err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages, &status);
  364. if (err) {
  365. mthca_err(mdev, "SET_ICM_SIZE command failed, aborting.\n");
  366. return err;
  367. }
  368. if (status) {
  369. mthca_err(mdev, "SET_ICM_SIZE returned status 0x%02x, "
  370. "aborting.\n", status);
  371. return -EINVAL;
  372. }
  373. mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
  374. (unsigned long long) icm_size >> 10,
  375. (unsigned long long) aux_pages << 2);
  376. mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
  377. GFP_HIGHUSER | __GFP_NOWARN, 0);
  378. if (!mdev->fw.arbel.aux_icm) {
  379. mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
  380. return -ENOMEM;
  381. }
  382. err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm, &status);
  383. if (err) {
  384. mthca_err(mdev, "MAP_ICM_AUX command failed, aborting.\n");
  385. goto err_free_aux;
  386. }
  387. if (status) {
  388. mthca_err(mdev, "MAP_ICM_AUX returned status 0x%02x, aborting.\n", status);
  389. err = -EINVAL;
  390. goto err_free_aux;
  391. }
  392. err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
  393. if (err) {
  394. mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
  395. goto err_unmap_aux;
  396. }
  397. /* CPU writes to non-reserved MTTs, while HCA might DMA to reserved mtts */
  398. mdev->limits.reserved_mtts = ALIGN(mdev->limits.reserved_mtts * MTHCA_MTT_SEG_SIZE,
  399. dma_get_cache_alignment()) / MTHCA_MTT_SEG_SIZE;
  400. mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
  401. MTHCA_MTT_SEG_SIZE,
  402. mdev->limits.num_mtt_segs,
  403. mdev->limits.reserved_mtts,
  404. 1, 0);
  405. if (!mdev->mr_table.mtt_table) {
  406. mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
  407. err = -ENOMEM;
  408. goto err_unmap_eq;
  409. }
  410. mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
  411. dev_lim->mpt_entry_sz,
  412. mdev->limits.num_mpts,
  413. mdev->limits.reserved_mrws,
  414. 1, 1);
  415. if (!mdev->mr_table.mpt_table) {
  416. mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
  417. err = -ENOMEM;
  418. goto err_unmap_mtt;
  419. }
  420. mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
  421. dev_lim->qpc_entry_sz,
  422. mdev->limits.num_qps,
  423. mdev->limits.reserved_qps,
  424. 0, 0);
  425. if (!mdev->qp_table.qp_table) {
  426. mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
  427. err = -ENOMEM;
  428. goto err_unmap_mpt;
  429. }
  430. mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
  431. dev_lim->eqpc_entry_sz,
  432. mdev->limits.num_qps,
  433. mdev->limits.reserved_qps,
  434. 0, 0);
  435. if (!mdev->qp_table.eqp_table) {
  436. mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
  437. err = -ENOMEM;
  438. goto err_unmap_qp;
  439. }
  440. mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
  441. MTHCA_RDB_ENTRY_SIZE,
  442. mdev->limits.num_qps <<
  443. mdev->qp_table.rdb_shift, 0,
  444. 0, 0);
  445. if (!mdev->qp_table.rdb_table) {
  446. mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
  447. err = -ENOMEM;
  448. goto err_unmap_eqp;
  449. }
  450. mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
  451. dev_lim->cqc_entry_sz,
  452. mdev->limits.num_cqs,
  453. mdev->limits.reserved_cqs,
  454. 0, 0);
  455. if (!mdev->cq_table.table) {
  456. mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
  457. err = -ENOMEM;
  458. goto err_unmap_rdb;
  459. }
  460. if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
  461. mdev->srq_table.table =
  462. mthca_alloc_icm_table(mdev, init_hca->srqc_base,
  463. dev_lim->srq_entry_sz,
  464. mdev->limits.num_srqs,
  465. mdev->limits.reserved_srqs,
  466. 0, 0);
  467. if (!mdev->srq_table.table) {
  468. mthca_err(mdev, "Failed to map SRQ context memory, "
  469. "aborting.\n");
  470. err = -ENOMEM;
  471. goto err_unmap_cq;
  472. }
  473. }
  474. /*
  475. * It's not strictly required, but for simplicity just map the
  476. * whole multicast group table now. The table isn't very big
  477. * and it's a lot easier than trying to track ref counts.
  478. */
  479. mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
  480. MTHCA_MGM_ENTRY_SIZE,
  481. mdev->limits.num_mgms +
  482. mdev->limits.num_amgms,
  483. mdev->limits.num_mgms +
  484. mdev->limits.num_amgms,
  485. 0, 0);
  486. if (!mdev->mcg_table.table) {
  487. mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
  488. err = -ENOMEM;
  489. goto err_unmap_srq;
  490. }
  491. return 0;
  492. err_unmap_srq:
  493. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  494. mthca_free_icm_table(mdev, mdev->srq_table.table);
  495. err_unmap_cq:
  496. mthca_free_icm_table(mdev, mdev->cq_table.table);
  497. err_unmap_rdb:
  498. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  499. err_unmap_eqp:
  500. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  501. err_unmap_qp:
  502. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  503. err_unmap_mpt:
  504. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  505. err_unmap_mtt:
  506. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  507. err_unmap_eq:
  508. mthca_unmap_eq_icm(mdev);
  509. err_unmap_aux:
  510. mthca_UNMAP_ICM_AUX(mdev, &status);
  511. err_free_aux:
  512. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
  513. return err;
  514. }
  515. static void mthca_free_icms(struct mthca_dev *mdev)
  516. {
  517. u8 status;
  518. mthca_free_icm_table(mdev, mdev->mcg_table.table);
  519. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  520. mthca_free_icm_table(mdev, mdev->srq_table.table);
  521. mthca_free_icm_table(mdev, mdev->cq_table.table);
  522. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  523. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  524. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  525. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  526. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  527. mthca_unmap_eq_icm(mdev);
  528. mthca_UNMAP_ICM_AUX(mdev, &status);
  529. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
  530. }
  531. static int mthca_init_arbel(struct mthca_dev *mdev)
  532. {
  533. struct mthca_dev_lim dev_lim;
  534. struct mthca_profile profile;
  535. struct mthca_init_hca_param init_hca;
  536. s64 icm_size;
  537. u8 status;
  538. int err;
  539. err = mthca_QUERY_FW(mdev, &status);
  540. if (err) {
  541. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  542. return err;
  543. }
  544. if (status) {
  545. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  546. "aborting.\n", status);
  547. return -EINVAL;
  548. }
  549. err = mthca_ENABLE_LAM(mdev, &status);
  550. if (err) {
  551. mthca_err(mdev, "ENABLE_LAM command failed, aborting.\n");
  552. return err;
  553. }
  554. if (status == MTHCA_CMD_STAT_LAM_NOT_PRE) {
  555. mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
  556. mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
  557. } else if (status) {
  558. mthca_err(mdev, "ENABLE_LAM returned status 0x%02x, "
  559. "aborting.\n", status);
  560. return -EINVAL;
  561. }
  562. err = mthca_load_fw(mdev);
  563. if (err) {
  564. mthca_err(mdev, "Failed to start FW, aborting.\n");
  565. goto err_disable;
  566. }
  567. err = mthca_dev_lim(mdev, &dev_lim);
  568. if (err) {
  569. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  570. goto err_stop_fw;
  571. }
  572. profile = hca_profile;
  573. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  574. profile.num_udav = 0;
  575. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  576. profile.num_srq = dev_lim.max_srqs;
  577. icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  578. if (icm_size < 0) {
  579. err = icm_size;
  580. goto err_stop_fw;
  581. }
  582. err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
  583. if (err)
  584. goto err_stop_fw;
  585. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  586. if (err) {
  587. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  588. goto err_free_icm;
  589. }
  590. if (status) {
  591. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  592. "aborting.\n", status);
  593. err = -EINVAL;
  594. goto err_free_icm;
  595. }
  596. return 0;
  597. err_free_icm:
  598. mthca_free_icms(mdev);
  599. err_stop_fw:
  600. mthca_UNMAP_FA(mdev, &status);
  601. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  602. err_disable:
  603. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  604. mthca_DISABLE_LAM(mdev, &status);
  605. return err;
  606. }
  607. static void mthca_close_hca(struct mthca_dev *mdev)
  608. {
  609. u8 status;
  610. mthca_CLOSE_HCA(mdev, 0, &status);
  611. if (mthca_is_memfree(mdev)) {
  612. mthca_free_icms(mdev);
  613. mthca_UNMAP_FA(mdev, &status);
  614. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  615. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  616. mthca_DISABLE_LAM(mdev, &status);
  617. } else
  618. mthca_SYS_DIS(mdev, &status);
  619. }
  620. static int mthca_init_hca(struct mthca_dev *mdev)
  621. {
  622. u8 status;
  623. int err;
  624. struct mthca_adapter adapter;
  625. if (mthca_is_memfree(mdev))
  626. err = mthca_init_arbel(mdev);
  627. else
  628. err = mthca_init_tavor(mdev);
  629. if (err)
  630. return err;
  631. err = mthca_QUERY_ADAPTER(mdev, &adapter, &status);
  632. if (err) {
  633. mthca_err(mdev, "QUERY_ADAPTER command failed, aborting.\n");
  634. goto err_close;
  635. }
  636. if (status) {
  637. mthca_err(mdev, "QUERY_ADAPTER returned status 0x%02x, "
  638. "aborting.\n", status);
  639. err = -EINVAL;
  640. goto err_close;
  641. }
  642. mdev->eq_table.inta_pin = adapter.inta_pin;
  643. if (!mthca_is_memfree(mdev))
  644. mdev->rev_id = adapter.revision_id;
  645. memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
  646. return 0;
  647. err_close:
  648. mthca_close_hca(mdev);
  649. return err;
  650. }
  651. static int mthca_setup_hca(struct mthca_dev *dev)
  652. {
  653. int err;
  654. u8 status;
  655. MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
  656. err = mthca_init_uar_table(dev);
  657. if (err) {
  658. mthca_err(dev, "Failed to initialize "
  659. "user access region table, aborting.\n");
  660. return err;
  661. }
  662. err = mthca_uar_alloc(dev, &dev->driver_uar);
  663. if (err) {
  664. mthca_err(dev, "Failed to allocate driver access region, "
  665. "aborting.\n");
  666. goto err_uar_table_free;
  667. }
  668. dev->kar = ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  669. if (!dev->kar) {
  670. mthca_err(dev, "Couldn't map kernel access region, "
  671. "aborting.\n");
  672. err = -ENOMEM;
  673. goto err_uar_free;
  674. }
  675. err = mthca_init_pd_table(dev);
  676. if (err) {
  677. mthca_err(dev, "Failed to initialize "
  678. "protection domain table, aborting.\n");
  679. goto err_kar_unmap;
  680. }
  681. err = mthca_init_mr_table(dev);
  682. if (err) {
  683. mthca_err(dev, "Failed to initialize "
  684. "memory region table, aborting.\n");
  685. goto err_pd_table_free;
  686. }
  687. err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
  688. if (err) {
  689. mthca_err(dev, "Failed to create driver PD, "
  690. "aborting.\n");
  691. goto err_mr_table_free;
  692. }
  693. err = mthca_init_eq_table(dev);
  694. if (err) {
  695. mthca_err(dev, "Failed to initialize "
  696. "event queue table, aborting.\n");
  697. goto err_pd_free;
  698. }
  699. err = mthca_cmd_use_events(dev);
  700. if (err) {
  701. mthca_err(dev, "Failed to switch to event-driven "
  702. "firmware commands, aborting.\n");
  703. goto err_eq_table_free;
  704. }
  705. err = mthca_NOP(dev, &status);
  706. if (err || status) {
  707. if (dev->mthca_flags & MTHCA_FLAG_MSI_X) {
  708. mthca_warn(dev, "NOP command failed to generate interrupt "
  709. "(IRQ %d).\n",
  710. dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector);
  711. mthca_warn(dev, "Trying again with MSI-X disabled.\n");
  712. } else {
  713. mthca_err(dev, "NOP command failed to generate interrupt "
  714. "(IRQ %d), aborting.\n",
  715. dev->pdev->irq);
  716. mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
  717. }
  718. goto err_cmd_poll;
  719. }
  720. mthca_dbg(dev, "NOP command IRQ test passed\n");
  721. err = mthca_init_cq_table(dev);
  722. if (err) {
  723. mthca_err(dev, "Failed to initialize "
  724. "completion queue table, aborting.\n");
  725. goto err_cmd_poll;
  726. }
  727. err = mthca_init_srq_table(dev);
  728. if (err) {
  729. mthca_err(dev, "Failed to initialize "
  730. "shared receive queue table, aborting.\n");
  731. goto err_cq_table_free;
  732. }
  733. err = mthca_init_qp_table(dev);
  734. if (err) {
  735. mthca_err(dev, "Failed to initialize "
  736. "queue pair table, aborting.\n");
  737. goto err_srq_table_free;
  738. }
  739. err = mthca_init_av_table(dev);
  740. if (err) {
  741. mthca_err(dev, "Failed to initialize "
  742. "address vector table, aborting.\n");
  743. goto err_qp_table_free;
  744. }
  745. err = mthca_init_mcg_table(dev);
  746. if (err) {
  747. mthca_err(dev, "Failed to initialize "
  748. "multicast group table, aborting.\n");
  749. goto err_av_table_free;
  750. }
  751. return 0;
  752. err_av_table_free:
  753. mthca_cleanup_av_table(dev);
  754. err_qp_table_free:
  755. mthca_cleanup_qp_table(dev);
  756. err_srq_table_free:
  757. mthca_cleanup_srq_table(dev);
  758. err_cq_table_free:
  759. mthca_cleanup_cq_table(dev);
  760. err_cmd_poll:
  761. mthca_cmd_use_polling(dev);
  762. err_eq_table_free:
  763. mthca_cleanup_eq_table(dev);
  764. err_pd_free:
  765. mthca_pd_free(dev, &dev->driver_pd);
  766. err_mr_table_free:
  767. mthca_cleanup_mr_table(dev);
  768. err_pd_table_free:
  769. mthca_cleanup_pd_table(dev);
  770. err_kar_unmap:
  771. iounmap(dev->kar);
  772. err_uar_free:
  773. mthca_uar_free(dev, &dev->driver_uar);
  774. err_uar_table_free:
  775. mthca_cleanup_uar_table(dev);
  776. return err;
  777. }
  778. static int mthca_request_regions(struct pci_dev *pdev, int ddr_hidden)
  779. {
  780. int err;
  781. /*
  782. * We can't just use pci_request_regions() because the MSI-X
  783. * table is right in the middle of the first BAR. If we did
  784. * pci_request_region and grab all of the first BAR, then
  785. * setting up MSI-X would fail, since the PCI core wants to do
  786. * request_mem_region on the MSI-X vector table.
  787. *
  788. * So just request what we need right now, and request any
  789. * other regions we need when setting up EQs.
  790. */
  791. if (!request_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  792. MTHCA_HCR_SIZE, DRV_NAME))
  793. return -EBUSY;
  794. err = pci_request_region(pdev, 2, DRV_NAME);
  795. if (err)
  796. goto err_bar2_failed;
  797. if (!ddr_hidden) {
  798. err = pci_request_region(pdev, 4, DRV_NAME);
  799. if (err)
  800. goto err_bar4_failed;
  801. }
  802. return 0;
  803. err_bar4_failed:
  804. pci_release_region(pdev, 2);
  805. err_bar2_failed:
  806. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  807. MTHCA_HCR_SIZE);
  808. return err;
  809. }
  810. static void mthca_release_regions(struct pci_dev *pdev,
  811. int ddr_hidden)
  812. {
  813. if (!ddr_hidden)
  814. pci_release_region(pdev, 4);
  815. pci_release_region(pdev, 2);
  816. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  817. MTHCA_HCR_SIZE);
  818. }
  819. static int mthca_enable_msi_x(struct mthca_dev *mdev)
  820. {
  821. struct msix_entry entries[3];
  822. int err;
  823. entries[0].entry = 0;
  824. entries[1].entry = 1;
  825. entries[2].entry = 2;
  826. err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries));
  827. if (err) {
  828. if (err > 0)
  829. mthca_info(mdev, "Only %d MSI-X vectors available, "
  830. "not using MSI-X\n", err);
  831. return err;
  832. }
  833. mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
  834. mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
  835. mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector;
  836. return 0;
  837. }
  838. /* Types of supported HCA */
  839. enum {
  840. TAVOR, /* MT23108 */
  841. ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
  842. ARBEL_NATIVE, /* MT25208 with extended features */
  843. SINAI /* MT25204 */
  844. };
  845. #define MTHCA_FW_VER(major, minor, subminor) \
  846. (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
  847. static struct {
  848. u64 latest_fw;
  849. u32 flags;
  850. } mthca_hca_table[] = {
  851. [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 5, 0),
  852. .flags = 0 },
  853. [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 8, 200),
  854. .flags = MTHCA_FLAG_PCIE },
  855. [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 3, 0),
  856. .flags = MTHCA_FLAG_MEMFREE |
  857. MTHCA_FLAG_PCIE },
  858. [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 2, 0),
  859. .flags = MTHCA_FLAG_MEMFREE |
  860. MTHCA_FLAG_PCIE |
  861. MTHCA_FLAG_SINAI_OPT }
  862. };
  863. static int __mthca_init_one(struct pci_dev *pdev, int hca_type)
  864. {
  865. int ddr_hidden = 0;
  866. int err;
  867. struct mthca_dev *mdev;
  868. printk(KERN_INFO PFX "Initializing %s\n",
  869. pci_name(pdev));
  870. err = pci_enable_device(pdev);
  871. if (err) {
  872. dev_err(&pdev->dev, "Cannot enable PCI device, "
  873. "aborting.\n");
  874. return err;
  875. }
  876. /*
  877. * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
  878. * be present)
  879. */
  880. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  881. pci_resource_len(pdev, 0) != 1 << 20) {
  882. dev_err(&pdev->dev, "Missing DCS, aborting.\n");
  883. err = -ENODEV;
  884. goto err_disable_pdev;
  885. }
  886. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
  887. dev_err(&pdev->dev, "Missing UAR, aborting.\n");
  888. err = -ENODEV;
  889. goto err_disable_pdev;
  890. }
  891. if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
  892. ddr_hidden = 1;
  893. err = mthca_request_regions(pdev, ddr_hidden);
  894. if (err) {
  895. dev_err(&pdev->dev, "Cannot obtain PCI resources, "
  896. "aborting.\n");
  897. goto err_disable_pdev;
  898. }
  899. pci_set_master(pdev);
  900. err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  901. if (err) {
  902. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
  903. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  904. if (err) {
  905. dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
  906. goto err_free_res;
  907. }
  908. }
  909. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  910. if (err) {
  911. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
  912. "consistent PCI DMA mask.\n");
  913. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  914. if (err) {
  915. dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
  916. "aborting.\n");
  917. goto err_free_res;
  918. }
  919. }
  920. mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
  921. if (!mdev) {
  922. dev_err(&pdev->dev, "Device struct alloc failed, "
  923. "aborting.\n");
  924. err = -ENOMEM;
  925. goto err_free_res;
  926. }
  927. mdev->pdev = pdev;
  928. mdev->mthca_flags = mthca_hca_table[hca_type].flags;
  929. if (ddr_hidden)
  930. mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
  931. /*
  932. * Now reset the HCA before we touch the PCI capabilities or
  933. * attempt a firmware command, since a boot ROM may have left
  934. * the HCA in an undefined state.
  935. */
  936. err = mthca_reset(mdev);
  937. if (err) {
  938. mthca_err(mdev, "Failed to reset HCA, aborting.\n");
  939. goto err_free_dev;
  940. }
  941. if (mthca_cmd_init(mdev)) {
  942. mthca_err(mdev, "Failed to init command interface, aborting.\n");
  943. goto err_free_dev;
  944. }
  945. err = mthca_tune_pci(mdev);
  946. if (err)
  947. goto err_cmd;
  948. err = mthca_init_hca(mdev);
  949. if (err)
  950. goto err_cmd;
  951. if (mdev->fw_ver < mthca_hca_table[hca_type].latest_fw) {
  952. mthca_warn(mdev, "HCA FW version %d.%d.%03d is old (%d.%d.%03d is current).\n",
  953. (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
  954. (int) (mdev->fw_ver & 0xffff),
  955. (int) (mthca_hca_table[hca_type].latest_fw >> 32),
  956. (int) (mthca_hca_table[hca_type].latest_fw >> 16) & 0xffff,
  957. (int) (mthca_hca_table[hca_type].latest_fw & 0xffff));
  958. mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
  959. }
  960. if (msi_x && !mthca_enable_msi_x(mdev))
  961. mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
  962. err = mthca_setup_hca(mdev);
  963. if (err == -EBUSY && (mdev->mthca_flags & MTHCA_FLAG_MSI_X)) {
  964. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  965. pci_disable_msix(pdev);
  966. mdev->mthca_flags &= ~MTHCA_FLAG_MSI_X;
  967. err = mthca_setup_hca(mdev);
  968. }
  969. if (err)
  970. goto err_close;
  971. err = mthca_register_device(mdev);
  972. if (err)
  973. goto err_cleanup;
  974. err = mthca_create_agents(mdev);
  975. if (err)
  976. goto err_unregister;
  977. pci_set_drvdata(pdev, mdev);
  978. mdev->hca_type = hca_type;
  979. return 0;
  980. err_unregister:
  981. mthca_unregister_device(mdev);
  982. err_cleanup:
  983. mthca_cleanup_mcg_table(mdev);
  984. mthca_cleanup_av_table(mdev);
  985. mthca_cleanup_qp_table(mdev);
  986. mthca_cleanup_srq_table(mdev);
  987. mthca_cleanup_cq_table(mdev);
  988. mthca_cmd_use_polling(mdev);
  989. mthca_cleanup_eq_table(mdev);
  990. mthca_pd_free(mdev, &mdev->driver_pd);
  991. mthca_cleanup_mr_table(mdev);
  992. mthca_cleanup_pd_table(mdev);
  993. mthca_cleanup_uar_table(mdev);
  994. err_close:
  995. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  996. pci_disable_msix(pdev);
  997. mthca_close_hca(mdev);
  998. err_cmd:
  999. mthca_cmd_cleanup(mdev);
  1000. err_free_dev:
  1001. ib_dealloc_device(&mdev->ib_dev);
  1002. err_free_res:
  1003. mthca_release_regions(pdev, ddr_hidden);
  1004. err_disable_pdev:
  1005. pci_disable_device(pdev);
  1006. pci_set_drvdata(pdev, NULL);
  1007. return err;
  1008. }
  1009. static void __mthca_remove_one(struct pci_dev *pdev)
  1010. {
  1011. struct mthca_dev *mdev = pci_get_drvdata(pdev);
  1012. u8 status;
  1013. int p;
  1014. if (mdev) {
  1015. mthca_free_agents(mdev);
  1016. mthca_unregister_device(mdev);
  1017. for (p = 1; p <= mdev->limits.num_ports; ++p)
  1018. mthca_CLOSE_IB(mdev, p, &status);
  1019. mthca_cleanup_mcg_table(mdev);
  1020. mthca_cleanup_av_table(mdev);
  1021. mthca_cleanup_qp_table(mdev);
  1022. mthca_cleanup_srq_table(mdev);
  1023. mthca_cleanup_cq_table(mdev);
  1024. mthca_cmd_use_polling(mdev);
  1025. mthca_cleanup_eq_table(mdev);
  1026. mthca_pd_free(mdev, &mdev->driver_pd);
  1027. mthca_cleanup_mr_table(mdev);
  1028. mthca_cleanup_pd_table(mdev);
  1029. iounmap(mdev->kar);
  1030. mthca_uar_free(mdev, &mdev->driver_uar);
  1031. mthca_cleanup_uar_table(mdev);
  1032. mthca_close_hca(mdev);
  1033. mthca_cmd_cleanup(mdev);
  1034. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  1035. pci_disable_msix(pdev);
  1036. ib_dealloc_device(&mdev->ib_dev);
  1037. mthca_release_regions(pdev, mdev->mthca_flags &
  1038. MTHCA_FLAG_DDR_HIDDEN);
  1039. pci_disable_device(pdev);
  1040. pci_set_drvdata(pdev, NULL);
  1041. }
  1042. }
  1043. int __mthca_restart_one(struct pci_dev *pdev)
  1044. {
  1045. struct mthca_dev *mdev;
  1046. int hca_type;
  1047. mdev = pci_get_drvdata(pdev);
  1048. if (!mdev)
  1049. return -ENODEV;
  1050. hca_type = mdev->hca_type;
  1051. __mthca_remove_one(pdev);
  1052. return __mthca_init_one(pdev, hca_type);
  1053. }
  1054. static int __devinit mthca_init_one(struct pci_dev *pdev,
  1055. const struct pci_device_id *id)
  1056. {
  1057. static int mthca_version_printed = 0;
  1058. int ret;
  1059. mutex_lock(&mthca_device_mutex);
  1060. if (!mthca_version_printed) {
  1061. printk(KERN_INFO "%s", mthca_version);
  1062. ++mthca_version_printed;
  1063. }
  1064. if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
  1065. printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
  1066. pci_name(pdev), id->driver_data);
  1067. mutex_unlock(&mthca_device_mutex);
  1068. return -ENODEV;
  1069. }
  1070. ret = __mthca_init_one(pdev, id->driver_data);
  1071. mutex_unlock(&mthca_device_mutex);
  1072. return ret;
  1073. }
  1074. static void __devexit mthca_remove_one(struct pci_dev *pdev)
  1075. {
  1076. mutex_lock(&mthca_device_mutex);
  1077. __mthca_remove_one(pdev);
  1078. mutex_unlock(&mthca_device_mutex);
  1079. }
  1080. static struct pci_device_id mthca_pci_table[] = {
  1081. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1082. .driver_data = TAVOR },
  1083. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1084. .driver_data = TAVOR },
  1085. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1086. .driver_data = ARBEL_COMPAT },
  1087. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1088. .driver_data = ARBEL_COMPAT },
  1089. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1090. .driver_data = ARBEL_NATIVE },
  1091. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1092. .driver_data = ARBEL_NATIVE },
  1093. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
  1094. .driver_data = SINAI },
  1095. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
  1096. .driver_data = SINAI },
  1097. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1098. .driver_data = SINAI },
  1099. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1100. .driver_data = SINAI },
  1101. { 0, }
  1102. };
  1103. MODULE_DEVICE_TABLE(pci, mthca_pci_table);
  1104. static struct pci_driver mthca_driver = {
  1105. .name = DRV_NAME,
  1106. .id_table = mthca_pci_table,
  1107. .probe = mthca_init_one,
  1108. .remove = __devexit_p(mthca_remove_one)
  1109. };
  1110. static void __init __mthca_check_profile_val(const char *name, int *pval,
  1111. int pval_default)
  1112. {
  1113. /* value must be positive and power of 2 */
  1114. int old_pval = *pval;
  1115. if (old_pval <= 0)
  1116. *pval = pval_default;
  1117. else
  1118. *pval = roundup_pow_of_two(old_pval);
  1119. if (old_pval != *pval) {
  1120. printk(KERN_WARNING PFX "Invalid value %d for %s in module parameter.\n",
  1121. old_pval, name);
  1122. printk(KERN_WARNING PFX "Corrected %s to %d.\n", name, *pval);
  1123. }
  1124. }
  1125. #define mthca_check_profile_val(name, default) \
  1126. __mthca_check_profile_val(#name, &hca_profile.name, default)
  1127. static void __init mthca_validate_profile(void)
  1128. {
  1129. mthca_check_profile_val(num_qp, MTHCA_DEFAULT_NUM_QP);
  1130. mthca_check_profile_val(rdb_per_qp, MTHCA_DEFAULT_RDB_PER_QP);
  1131. mthca_check_profile_val(num_cq, MTHCA_DEFAULT_NUM_CQ);
  1132. mthca_check_profile_val(num_mcg, MTHCA_DEFAULT_NUM_MCG);
  1133. mthca_check_profile_val(num_mpt, MTHCA_DEFAULT_NUM_MPT);
  1134. mthca_check_profile_val(num_mtt, MTHCA_DEFAULT_NUM_MTT);
  1135. mthca_check_profile_val(num_udav, MTHCA_DEFAULT_NUM_UDAV);
  1136. mthca_check_profile_val(fmr_reserved_mtts, MTHCA_DEFAULT_NUM_RESERVED_MTTS);
  1137. if (hca_profile.fmr_reserved_mtts >= hca_profile.num_mtt) {
  1138. printk(KERN_WARNING PFX "Invalid fmr_reserved_mtts module parameter %d.\n",
  1139. hca_profile.fmr_reserved_mtts);
  1140. printk(KERN_WARNING PFX "(Must be smaller than num_mtt %d)\n",
  1141. hca_profile.num_mtt);
  1142. hca_profile.fmr_reserved_mtts = hca_profile.num_mtt / 2;
  1143. printk(KERN_WARNING PFX "Corrected fmr_reserved_mtts to %d.\n",
  1144. hca_profile.fmr_reserved_mtts);
  1145. }
  1146. }
  1147. static int __init mthca_init(void)
  1148. {
  1149. int ret;
  1150. mthca_validate_profile();
  1151. ret = mthca_catas_init();
  1152. if (ret)
  1153. return ret;
  1154. ret = pci_register_driver(&mthca_driver);
  1155. if (ret < 0) {
  1156. mthca_catas_cleanup();
  1157. return ret;
  1158. }
  1159. return 0;
  1160. }
  1161. static void __exit mthca_cleanup(void)
  1162. {
  1163. pci_unregister_driver(&mthca_driver);
  1164. mthca_catas_cleanup();
  1165. }
  1166. module_init(mthca_init);
  1167. module_exit(mthca_cleanup);