cq.c 19 KB

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  1. /*
  2. * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/mlx4/cq.h>
  33. #include <linux/mlx4/qp.h>
  34. #include "mlx4_ib.h"
  35. #include "user.h"
  36. static void mlx4_ib_cq_comp(struct mlx4_cq *cq)
  37. {
  38. struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
  39. ibcq->comp_handler(ibcq, ibcq->cq_context);
  40. }
  41. static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type)
  42. {
  43. struct ib_event event;
  44. struct ib_cq *ibcq;
  45. if (type != MLX4_EVENT_TYPE_CQ_ERROR) {
  46. printk(KERN_WARNING "mlx4_ib: Unexpected event type %d "
  47. "on CQ %06x\n", type, cq->cqn);
  48. return;
  49. }
  50. ibcq = &to_mibcq(cq)->ibcq;
  51. if (ibcq->event_handler) {
  52. event.device = ibcq->device;
  53. event.event = IB_EVENT_CQ_ERR;
  54. event.element.cq = ibcq;
  55. ibcq->event_handler(&event, ibcq->cq_context);
  56. }
  57. }
  58. static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n)
  59. {
  60. return mlx4_buf_offset(&buf->buf, n * sizeof (struct mlx4_cqe));
  61. }
  62. static void *get_cqe(struct mlx4_ib_cq *cq, int n)
  63. {
  64. return get_cqe_from_buf(&cq->buf, n);
  65. }
  66. static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n)
  67. {
  68. struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe);
  69. return (!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
  70. !!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe;
  71. }
  72. static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq)
  73. {
  74. return get_sw_cqe(cq, cq->mcq.cons_index);
  75. }
  76. int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
  77. {
  78. struct mlx4_ib_cq *mcq = to_mcq(cq);
  79. struct mlx4_ib_dev *dev = to_mdev(cq->device);
  80. return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period);
  81. }
  82. static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int nent)
  83. {
  84. int err;
  85. err = mlx4_buf_alloc(dev->dev, nent * sizeof(struct mlx4_cqe),
  86. PAGE_SIZE * 2, &buf->buf);
  87. if (err)
  88. goto out;
  89. err = mlx4_mtt_init(dev->dev, buf->buf.npages, buf->buf.page_shift,
  90. &buf->mtt);
  91. if (err)
  92. goto err_buf;
  93. err = mlx4_buf_write_mtt(dev->dev, &buf->mtt, &buf->buf);
  94. if (err)
  95. goto err_mtt;
  96. return 0;
  97. err_mtt:
  98. mlx4_mtt_cleanup(dev->dev, &buf->mtt);
  99. err_buf:
  100. mlx4_buf_free(dev->dev, nent * sizeof(struct mlx4_cqe),
  101. &buf->buf);
  102. out:
  103. return err;
  104. }
  105. static void mlx4_ib_free_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int cqe)
  106. {
  107. mlx4_buf_free(dev->dev, (cqe + 1) * sizeof(struct mlx4_cqe), &buf->buf);
  108. }
  109. static int mlx4_ib_get_cq_umem(struct mlx4_ib_dev *dev, struct ib_ucontext *context,
  110. struct mlx4_ib_cq_buf *buf, struct ib_umem **umem,
  111. u64 buf_addr, int cqe)
  112. {
  113. int err;
  114. *umem = ib_umem_get(context, buf_addr, cqe * sizeof (struct mlx4_cqe),
  115. IB_ACCESS_LOCAL_WRITE, 1);
  116. if (IS_ERR(*umem))
  117. return PTR_ERR(*umem);
  118. err = mlx4_mtt_init(dev->dev, ib_umem_page_count(*umem),
  119. ilog2((*umem)->page_size), &buf->mtt);
  120. if (err)
  121. goto err_buf;
  122. err = mlx4_ib_umem_write_mtt(dev, &buf->mtt, *umem);
  123. if (err)
  124. goto err_mtt;
  125. return 0;
  126. err_mtt:
  127. mlx4_mtt_cleanup(dev->dev, &buf->mtt);
  128. err_buf:
  129. ib_umem_release(*umem);
  130. return err;
  131. }
  132. struct ib_cq *mlx4_ib_create_cq(struct ib_device *ibdev, int entries, int vector,
  133. struct ib_ucontext *context,
  134. struct ib_udata *udata)
  135. {
  136. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  137. struct mlx4_ib_cq *cq;
  138. struct mlx4_uar *uar;
  139. int err;
  140. if (entries < 1 || entries > dev->dev->caps.max_cqes)
  141. return ERR_PTR(-EINVAL);
  142. cq = kmalloc(sizeof *cq, GFP_KERNEL);
  143. if (!cq)
  144. return ERR_PTR(-ENOMEM);
  145. entries = roundup_pow_of_two(entries + 1);
  146. cq->ibcq.cqe = entries - 1;
  147. mutex_init(&cq->resize_mutex);
  148. spin_lock_init(&cq->lock);
  149. cq->resize_buf = NULL;
  150. cq->resize_umem = NULL;
  151. if (context) {
  152. struct mlx4_ib_create_cq ucmd;
  153. if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
  154. err = -EFAULT;
  155. goto err_cq;
  156. }
  157. err = mlx4_ib_get_cq_umem(dev, context, &cq->buf, &cq->umem,
  158. ucmd.buf_addr, entries);
  159. if (err)
  160. goto err_cq;
  161. err = mlx4_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
  162. &cq->db);
  163. if (err)
  164. goto err_mtt;
  165. uar = &to_mucontext(context)->uar;
  166. } else {
  167. err = mlx4_db_alloc(dev->dev, &cq->db, 1);
  168. if (err)
  169. goto err_cq;
  170. cq->mcq.set_ci_db = cq->db.db;
  171. cq->mcq.arm_db = cq->db.db + 1;
  172. *cq->mcq.set_ci_db = 0;
  173. *cq->mcq.arm_db = 0;
  174. err = mlx4_ib_alloc_cq_buf(dev, &cq->buf, entries);
  175. if (err)
  176. goto err_db;
  177. uar = &dev->priv_uar;
  178. }
  179. err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar,
  180. cq->db.dma, &cq->mcq, 0);
  181. if (err)
  182. goto err_dbmap;
  183. cq->mcq.comp = mlx4_ib_cq_comp;
  184. cq->mcq.event = mlx4_ib_cq_event;
  185. if (context)
  186. if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) {
  187. err = -EFAULT;
  188. goto err_dbmap;
  189. }
  190. return &cq->ibcq;
  191. err_dbmap:
  192. if (context)
  193. mlx4_ib_db_unmap_user(to_mucontext(context), &cq->db);
  194. err_mtt:
  195. mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt);
  196. if (context)
  197. ib_umem_release(cq->umem);
  198. else
  199. mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
  200. err_db:
  201. if (!context)
  202. mlx4_db_free(dev->dev, &cq->db);
  203. err_cq:
  204. kfree(cq);
  205. return ERR_PTR(err);
  206. }
  207. static int mlx4_alloc_resize_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
  208. int entries)
  209. {
  210. int err;
  211. if (cq->resize_buf)
  212. return -EBUSY;
  213. cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC);
  214. if (!cq->resize_buf)
  215. return -ENOMEM;
  216. err = mlx4_ib_alloc_cq_buf(dev, &cq->resize_buf->buf, entries);
  217. if (err) {
  218. kfree(cq->resize_buf);
  219. cq->resize_buf = NULL;
  220. return err;
  221. }
  222. cq->resize_buf->cqe = entries - 1;
  223. return 0;
  224. }
  225. static int mlx4_alloc_resize_umem(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
  226. int entries, struct ib_udata *udata)
  227. {
  228. struct mlx4_ib_resize_cq ucmd;
  229. int err;
  230. if (cq->resize_umem)
  231. return -EBUSY;
  232. if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd))
  233. return -EFAULT;
  234. cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC);
  235. if (!cq->resize_buf)
  236. return -ENOMEM;
  237. err = mlx4_ib_get_cq_umem(dev, cq->umem->context, &cq->resize_buf->buf,
  238. &cq->resize_umem, ucmd.buf_addr, entries);
  239. if (err) {
  240. kfree(cq->resize_buf);
  241. cq->resize_buf = NULL;
  242. return err;
  243. }
  244. cq->resize_buf->cqe = entries - 1;
  245. return 0;
  246. }
  247. static int mlx4_ib_get_outstanding_cqes(struct mlx4_ib_cq *cq)
  248. {
  249. u32 i;
  250. i = cq->mcq.cons_index;
  251. while (get_sw_cqe(cq, i & cq->ibcq.cqe))
  252. ++i;
  253. return i - cq->mcq.cons_index;
  254. }
  255. static void mlx4_ib_cq_resize_copy_cqes(struct mlx4_ib_cq *cq)
  256. {
  257. struct mlx4_cqe *cqe;
  258. int i;
  259. i = cq->mcq.cons_index;
  260. cqe = get_cqe(cq, i & cq->ibcq.cqe);
  261. while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) {
  262. memcpy(get_cqe_from_buf(&cq->resize_buf->buf,
  263. (i + 1) & cq->resize_buf->cqe),
  264. get_cqe(cq, i & cq->ibcq.cqe), sizeof(struct mlx4_cqe));
  265. cqe = get_cqe(cq, ++i & cq->ibcq.cqe);
  266. }
  267. ++cq->mcq.cons_index;
  268. }
  269. int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
  270. {
  271. struct mlx4_ib_dev *dev = to_mdev(ibcq->device);
  272. struct mlx4_ib_cq *cq = to_mcq(ibcq);
  273. int outst_cqe;
  274. int err;
  275. mutex_lock(&cq->resize_mutex);
  276. if (entries < 1 || entries > dev->dev->caps.max_cqes) {
  277. err = -EINVAL;
  278. goto out;
  279. }
  280. entries = roundup_pow_of_two(entries + 1);
  281. if (entries == ibcq->cqe + 1) {
  282. err = 0;
  283. goto out;
  284. }
  285. if (ibcq->uobject) {
  286. err = mlx4_alloc_resize_umem(dev, cq, entries, udata);
  287. if (err)
  288. goto out;
  289. } else {
  290. /* Can't be smaller then the number of outstanding CQEs */
  291. outst_cqe = mlx4_ib_get_outstanding_cqes(cq);
  292. if (entries < outst_cqe + 1) {
  293. err = 0;
  294. goto out;
  295. }
  296. err = mlx4_alloc_resize_buf(dev, cq, entries);
  297. if (err)
  298. goto out;
  299. }
  300. err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt);
  301. if (err)
  302. goto err_buf;
  303. if (ibcq->uobject) {
  304. cq->buf = cq->resize_buf->buf;
  305. cq->ibcq.cqe = cq->resize_buf->cqe;
  306. ib_umem_release(cq->umem);
  307. cq->umem = cq->resize_umem;
  308. kfree(cq->resize_buf);
  309. cq->resize_buf = NULL;
  310. cq->resize_umem = NULL;
  311. } else {
  312. spin_lock_irq(&cq->lock);
  313. if (cq->resize_buf) {
  314. mlx4_ib_cq_resize_copy_cqes(cq);
  315. mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
  316. cq->buf = cq->resize_buf->buf;
  317. cq->ibcq.cqe = cq->resize_buf->cqe;
  318. kfree(cq->resize_buf);
  319. cq->resize_buf = NULL;
  320. }
  321. spin_unlock_irq(&cq->lock);
  322. }
  323. goto out;
  324. err_buf:
  325. if (!ibcq->uobject)
  326. mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf,
  327. cq->resize_buf->cqe);
  328. kfree(cq->resize_buf);
  329. cq->resize_buf = NULL;
  330. if (cq->resize_umem) {
  331. ib_umem_release(cq->resize_umem);
  332. cq->resize_umem = NULL;
  333. }
  334. out:
  335. mutex_unlock(&cq->resize_mutex);
  336. return err;
  337. }
  338. int mlx4_ib_destroy_cq(struct ib_cq *cq)
  339. {
  340. struct mlx4_ib_dev *dev = to_mdev(cq->device);
  341. struct mlx4_ib_cq *mcq = to_mcq(cq);
  342. mlx4_cq_free(dev->dev, &mcq->mcq);
  343. mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt);
  344. if (cq->uobject) {
  345. mlx4_ib_db_unmap_user(to_mucontext(cq->uobject->context), &mcq->db);
  346. ib_umem_release(mcq->umem);
  347. } else {
  348. mlx4_ib_free_cq_buf(dev, &mcq->buf, cq->cqe);
  349. mlx4_db_free(dev->dev, &mcq->db);
  350. }
  351. kfree(mcq);
  352. return 0;
  353. }
  354. static void dump_cqe(void *cqe)
  355. {
  356. __be32 *buf = cqe;
  357. printk(KERN_DEBUG "CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
  358. be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]),
  359. be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]),
  360. be32_to_cpu(buf[6]), be32_to_cpu(buf[7]));
  361. }
  362. static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe,
  363. struct ib_wc *wc)
  364. {
  365. if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) {
  366. printk(KERN_DEBUG "local QP operation err "
  367. "(QPN %06x, WQE index %x, vendor syndrome %02x, "
  368. "opcode = %02x)\n",
  369. be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index),
  370. cqe->vendor_err_syndrome,
  371. cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
  372. dump_cqe(cqe);
  373. }
  374. switch (cqe->syndrome) {
  375. case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR:
  376. wc->status = IB_WC_LOC_LEN_ERR;
  377. break;
  378. case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR:
  379. wc->status = IB_WC_LOC_QP_OP_ERR;
  380. break;
  381. case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR:
  382. wc->status = IB_WC_LOC_PROT_ERR;
  383. break;
  384. case MLX4_CQE_SYNDROME_WR_FLUSH_ERR:
  385. wc->status = IB_WC_WR_FLUSH_ERR;
  386. break;
  387. case MLX4_CQE_SYNDROME_MW_BIND_ERR:
  388. wc->status = IB_WC_MW_BIND_ERR;
  389. break;
  390. case MLX4_CQE_SYNDROME_BAD_RESP_ERR:
  391. wc->status = IB_WC_BAD_RESP_ERR;
  392. break;
  393. case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR:
  394. wc->status = IB_WC_LOC_ACCESS_ERR;
  395. break;
  396. case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
  397. wc->status = IB_WC_REM_INV_REQ_ERR;
  398. break;
  399. case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR:
  400. wc->status = IB_WC_REM_ACCESS_ERR;
  401. break;
  402. case MLX4_CQE_SYNDROME_REMOTE_OP_ERR:
  403. wc->status = IB_WC_REM_OP_ERR;
  404. break;
  405. case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
  406. wc->status = IB_WC_RETRY_EXC_ERR;
  407. break;
  408. case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
  409. wc->status = IB_WC_RNR_RETRY_EXC_ERR;
  410. break;
  411. case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR:
  412. wc->status = IB_WC_REM_ABORT_ERR;
  413. break;
  414. default:
  415. wc->status = IB_WC_GENERAL_ERR;
  416. break;
  417. }
  418. wc->vendor_err = cqe->vendor_err_syndrome;
  419. }
  420. static int mlx4_ib_ipoib_csum_ok(__be32 status, __be16 checksum)
  421. {
  422. return ((status & cpu_to_be32(MLX4_CQE_IPOIB_STATUS_IPV4 |
  423. MLX4_CQE_IPOIB_STATUS_IPV4F |
  424. MLX4_CQE_IPOIB_STATUS_IPV4OPT |
  425. MLX4_CQE_IPOIB_STATUS_IPV6 |
  426. MLX4_CQE_IPOIB_STATUS_IPOK)) ==
  427. cpu_to_be32(MLX4_CQE_IPOIB_STATUS_IPV4 |
  428. MLX4_CQE_IPOIB_STATUS_IPOK)) &&
  429. (status & cpu_to_be32(MLX4_CQE_IPOIB_STATUS_UDP |
  430. MLX4_CQE_IPOIB_STATUS_TCP)) &&
  431. checksum == cpu_to_be16(0xffff);
  432. }
  433. static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq,
  434. struct mlx4_ib_qp **cur_qp,
  435. struct ib_wc *wc)
  436. {
  437. struct mlx4_cqe *cqe;
  438. struct mlx4_qp *mqp;
  439. struct mlx4_ib_wq *wq;
  440. struct mlx4_ib_srq *srq;
  441. int is_send;
  442. int is_error;
  443. u32 g_mlpath_rqpn;
  444. u16 wqe_ctr;
  445. repoll:
  446. cqe = next_cqe_sw(cq);
  447. if (!cqe)
  448. return -EAGAIN;
  449. ++cq->mcq.cons_index;
  450. /*
  451. * Make sure we read CQ entry contents after we've checked the
  452. * ownership bit.
  453. */
  454. rmb();
  455. is_send = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK;
  456. is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
  457. MLX4_CQE_OPCODE_ERROR;
  458. if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_OPCODE_NOP &&
  459. is_send)) {
  460. printk(KERN_WARNING "Completion for NOP opcode detected!\n");
  461. return -EINVAL;
  462. }
  463. /* Resize CQ in progress */
  464. if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_RESIZE)) {
  465. if (cq->resize_buf) {
  466. struct mlx4_ib_dev *dev = to_mdev(cq->ibcq.device);
  467. mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
  468. cq->buf = cq->resize_buf->buf;
  469. cq->ibcq.cqe = cq->resize_buf->cqe;
  470. kfree(cq->resize_buf);
  471. cq->resize_buf = NULL;
  472. }
  473. goto repoll;
  474. }
  475. if (!*cur_qp ||
  476. (be32_to_cpu(cqe->my_qpn) & 0xffffff) != (*cur_qp)->mqp.qpn) {
  477. /*
  478. * We do not have to take the QP table lock here,
  479. * because CQs will be locked while QPs are removed
  480. * from the table.
  481. */
  482. mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev,
  483. be32_to_cpu(cqe->my_qpn));
  484. if (unlikely(!mqp)) {
  485. printk(KERN_WARNING "CQ %06x with entry for unknown QPN %06x\n",
  486. cq->mcq.cqn, be32_to_cpu(cqe->my_qpn) & 0xffffff);
  487. return -EINVAL;
  488. }
  489. *cur_qp = to_mibqp(mqp);
  490. }
  491. wc->qp = &(*cur_qp)->ibqp;
  492. if (is_send) {
  493. wq = &(*cur_qp)->sq;
  494. if (!(*cur_qp)->sq_signal_bits) {
  495. wqe_ctr = be16_to_cpu(cqe->wqe_index);
  496. wq->tail += (u16) (wqe_ctr - (u16) wq->tail);
  497. }
  498. wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
  499. ++wq->tail;
  500. } else if ((*cur_qp)->ibqp.srq) {
  501. srq = to_msrq((*cur_qp)->ibqp.srq);
  502. wqe_ctr = be16_to_cpu(cqe->wqe_index);
  503. wc->wr_id = srq->wrid[wqe_ctr];
  504. mlx4_ib_free_srq_wqe(srq, wqe_ctr);
  505. } else {
  506. wq = &(*cur_qp)->rq;
  507. wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
  508. ++wq->tail;
  509. }
  510. if (unlikely(is_error)) {
  511. mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc);
  512. return 0;
  513. }
  514. wc->status = IB_WC_SUCCESS;
  515. if (is_send) {
  516. wc->wc_flags = 0;
  517. switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
  518. case MLX4_OPCODE_RDMA_WRITE_IMM:
  519. wc->wc_flags |= IB_WC_WITH_IMM;
  520. case MLX4_OPCODE_RDMA_WRITE:
  521. wc->opcode = IB_WC_RDMA_WRITE;
  522. break;
  523. case MLX4_OPCODE_SEND_IMM:
  524. wc->wc_flags |= IB_WC_WITH_IMM;
  525. case MLX4_OPCODE_SEND:
  526. wc->opcode = IB_WC_SEND;
  527. break;
  528. case MLX4_OPCODE_RDMA_READ:
  529. wc->opcode = IB_WC_RDMA_READ;
  530. wc->byte_len = be32_to_cpu(cqe->byte_cnt);
  531. break;
  532. case MLX4_OPCODE_ATOMIC_CS:
  533. wc->opcode = IB_WC_COMP_SWAP;
  534. wc->byte_len = 8;
  535. break;
  536. case MLX4_OPCODE_ATOMIC_FA:
  537. wc->opcode = IB_WC_FETCH_ADD;
  538. wc->byte_len = 8;
  539. break;
  540. case MLX4_OPCODE_BIND_MW:
  541. wc->opcode = IB_WC_BIND_MW;
  542. break;
  543. case MLX4_OPCODE_LSO:
  544. wc->opcode = IB_WC_LSO;
  545. break;
  546. }
  547. } else {
  548. wc->byte_len = be32_to_cpu(cqe->byte_cnt);
  549. switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
  550. case MLX4_RECV_OPCODE_RDMA_WRITE_IMM:
  551. wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
  552. wc->wc_flags = IB_WC_WITH_IMM;
  553. wc->imm_data = cqe->immed_rss_invalid;
  554. break;
  555. case MLX4_RECV_OPCODE_SEND:
  556. wc->opcode = IB_WC_RECV;
  557. wc->wc_flags = 0;
  558. break;
  559. case MLX4_RECV_OPCODE_SEND_IMM:
  560. wc->opcode = IB_WC_RECV;
  561. wc->wc_flags = IB_WC_WITH_IMM;
  562. wc->imm_data = cqe->immed_rss_invalid;
  563. break;
  564. }
  565. wc->slid = be16_to_cpu(cqe->rlid);
  566. wc->sl = cqe->sl >> 4;
  567. g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn);
  568. wc->src_qp = g_mlpath_rqpn & 0xffffff;
  569. wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f;
  570. wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0;
  571. wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f;
  572. wc->csum_ok = mlx4_ib_ipoib_csum_ok(cqe->ipoib_status,
  573. cqe->checksum);
  574. }
  575. return 0;
  576. }
  577. int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
  578. {
  579. struct mlx4_ib_cq *cq = to_mcq(ibcq);
  580. struct mlx4_ib_qp *cur_qp = NULL;
  581. unsigned long flags;
  582. int npolled;
  583. int err = 0;
  584. spin_lock_irqsave(&cq->lock, flags);
  585. for (npolled = 0; npolled < num_entries; ++npolled) {
  586. err = mlx4_ib_poll_one(cq, &cur_qp, wc + npolled);
  587. if (err)
  588. break;
  589. }
  590. if (npolled)
  591. mlx4_cq_set_ci(&cq->mcq);
  592. spin_unlock_irqrestore(&cq->lock, flags);
  593. if (err == 0 || err == -EAGAIN)
  594. return npolled;
  595. else
  596. return err;
  597. }
  598. int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
  599. {
  600. mlx4_cq_arm(&to_mcq(ibcq)->mcq,
  601. (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
  602. MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT,
  603. to_mdev(ibcq->device)->uar_map,
  604. MLX4_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->uar_lock));
  605. return 0;
  606. }
  607. void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
  608. {
  609. u32 prod_index;
  610. int nfreed = 0;
  611. struct mlx4_cqe *cqe, *dest;
  612. u8 owner_bit;
  613. /*
  614. * First we need to find the current producer index, so we
  615. * know where to start cleaning from. It doesn't matter if HW
  616. * adds new entries after this loop -- the QP we're worried
  617. * about is already in RESET, so the new entries won't come
  618. * from our QP and therefore don't need to be checked.
  619. */
  620. for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index)
  621. if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
  622. break;
  623. /*
  624. * Now sweep backwards through the CQ, removing CQ entries
  625. * that match our QP by copying older entries on top of them.
  626. */
  627. while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
  628. cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
  629. if ((be32_to_cpu(cqe->my_qpn) & 0xffffff) == qpn) {
  630. if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK))
  631. mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index));
  632. ++nfreed;
  633. } else if (nfreed) {
  634. dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
  635. owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK;
  636. memcpy(dest, cqe, sizeof *cqe);
  637. dest->owner_sr_opcode = owner_bit |
  638. (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
  639. }
  640. }
  641. if (nfreed) {
  642. cq->mcq.cons_index += nfreed;
  643. /*
  644. * Make sure update of buffer contents is done before
  645. * updating consumer index.
  646. */
  647. wmb();
  648. mlx4_cq_set_ci(&cq->mcq);
  649. }
  650. }
  651. void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
  652. {
  653. spin_lock_irq(&cq->lock);
  654. __mlx4_ib_cq_clean(cq, qpn, srq);
  655. spin_unlock_irq(&cq->lock);
  656. }