i2c-bfin-twi.c 18 KB

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  1. /*
  2. * Blackfin On-Chip Two Wire Interface Driver
  3. *
  4. * Copyright 2005-2007 Analog Devices Inc.
  5. *
  6. * Enter bugs at http://blackfin.uclinux.org/
  7. *
  8. * Licensed under the GPL-2 or later.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/init.h>
  13. #include <linux/i2c.h>
  14. #include <linux/mm.h>
  15. #include <linux/timer.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/completion.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/platform_device.h>
  20. #include <asm/blackfin.h>
  21. #include <asm/portmux.h>
  22. #include <asm/irq.h>
  23. #define POLL_TIMEOUT (2 * HZ)
  24. /* SMBus mode*/
  25. #define TWI_I2C_MODE_STANDARD 1
  26. #define TWI_I2C_MODE_STANDARDSUB 2
  27. #define TWI_I2C_MODE_COMBINED 3
  28. #define TWI_I2C_MODE_REPEAT 4
  29. struct bfin_twi_iface {
  30. int irq;
  31. spinlock_t lock;
  32. char read_write;
  33. u8 command;
  34. u8 *transPtr;
  35. int readNum;
  36. int writeNum;
  37. int cur_mode;
  38. int manual_stop;
  39. int result;
  40. int timeout_count;
  41. struct timer_list timeout_timer;
  42. struct i2c_adapter adap;
  43. struct completion complete;
  44. struct i2c_msg *pmsg;
  45. int msg_num;
  46. int cur_msg;
  47. void __iomem *regs_base;
  48. };
  49. #define DEFINE_TWI_REG(reg, off) \
  50. static inline u16 read_##reg(struct bfin_twi_iface *iface) \
  51. { return bfin_read16(iface->regs_base + (off)); } \
  52. static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
  53. { bfin_write16(iface->regs_base + (off), v); }
  54. DEFINE_TWI_REG(CLKDIV, 0x00)
  55. DEFINE_TWI_REG(CONTROL, 0x04)
  56. DEFINE_TWI_REG(SLAVE_CTL, 0x08)
  57. DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
  58. DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
  59. DEFINE_TWI_REG(MASTER_CTL, 0x14)
  60. DEFINE_TWI_REG(MASTER_STAT, 0x18)
  61. DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
  62. DEFINE_TWI_REG(INT_STAT, 0x20)
  63. DEFINE_TWI_REG(INT_MASK, 0x24)
  64. DEFINE_TWI_REG(FIFO_CTL, 0x28)
  65. DEFINE_TWI_REG(FIFO_STAT, 0x2C)
  66. DEFINE_TWI_REG(XMT_DATA8, 0x80)
  67. DEFINE_TWI_REG(XMT_DATA16, 0x84)
  68. DEFINE_TWI_REG(RCV_DATA8, 0x88)
  69. DEFINE_TWI_REG(RCV_DATA16, 0x8C)
  70. static const u16 pin_req[2][3] = {
  71. {P_TWI0_SCL, P_TWI0_SDA, 0},
  72. {P_TWI1_SCL, P_TWI1_SDA, 0},
  73. };
  74. static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
  75. {
  76. unsigned short twi_int_status = read_INT_STAT(iface);
  77. unsigned short mast_stat = read_MASTER_STAT(iface);
  78. if (twi_int_status & XMTSERV) {
  79. /* Transmit next data */
  80. if (iface->writeNum > 0) {
  81. write_XMT_DATA8(iface, *(iface->transPtr++));
  82. iface->writeNum--;
  83. }
  84. /* start receive immediately after complete sending in
  85. * combine mode.
  86. */
  87. else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
  88. write_MASTER_CTL(iface,
  89. read_MASTER_CTL(iface) | MDIR | RSTART);
  90. else if (iface->manual_stop)
  91. write_MASTER_CTL(iface,
  92. read_MASTER_CTL(iface) | STOP);
  93. else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
  94. iface->cur_msg+1 < iface->msg_num)
  95. write_MASTER_CTL(iface,
  96. read_MASTER_CTL(iface) | RSTART);
  97. SSYNC();
  98. /* Clear status */
  99. write_INT_STAT(iface, XMTSERV);
  100. SSYNC();
  101. }
  102. if (twi_int_status & RCVSERV) {
  103. if (iface->readNum > 0) {
  104. /* Receive next data */
  105. *(iface->transPtr) = read_RCV_DATA8(iface);
  106. if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
  107. /* Change combine mode into sub mode after
  108. * read first data.
  109. */
  110. iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
  111. /* Get read number from first byte in block
  112. * combine mode.
  113. */
  114. if (iface->readNum == 1 && iface->manual_stop)
  115. iface->readNum = *iface->transPtr + 1;
  116. }
  117. iface->transPtr++;
  118. iface->readNum--;
  119. } else if (iface->manual_stop) {
  120. write_MASTER_CTL(iface,
  121. read_MASTER_CTL(iface) | STOP);
  122. SSYNC();
  123. } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
  124. iface->cur_msg+1 < iface->msg_num) {
  125. write_MASTER_CTL(iface,
  126. read_MASTER_CTL(iface) | RSTART);
  127. SSYNC();
  128. }
  129. /* Clear interrupt source */
  130. write_INT_STAT(iface, RCVSERV);
  131. SSYNC();
  132. }
  133. if (twi_int_status & MERR) {
  134. write_INT_STAT(iface, MERR);
  135. write_INT_MASK(iface, 0);
  136. write_MASTER_STAT(iface, 0x3e);
  137. write_MASTER_CTL(iface, 0);
  138. SSYNC();
  139. iface->result = -EIO;
  140. /* if both err and complete int stats are set, return proper
  141. * results.
  142. */
  143. if (twi_int_status & MCOMP) {
  144. write_INT_STAT(iface, MCOMP);
  145. write_INT_MASK(iface, 0);
  146. write_MASTER_CTL(iface, 0);
  147. SSYNC();
  148. /* If it is a quick transfer, only address bug no data,
  149. * not an err, return 1.
  150. */
  151. if (iface->writeNum == 0 && (mast_stat & BUFRDERR))
  152. iface->result = 1;
  153. /* If address not acknowledged return -1,
  154. * else return 0.
  155. */
  156. else if (!(mast_stat & ANAK))
  157. iface->result = 0;
  158. }
  159. complete(&iface->complete);
  160. return;
  161. }
  162. if (twi_int_status & MCOMP) {
  163. write_INT_STAT(iface, MCOMP);
  164. SSYNC();
  165. if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
  166. if (iface->readNum == 0) {
  167. /* set the read number to 1 and ask for manual
  168. * stop in block combine mode
  169. */
  170. iface->readNum = 1;
  171. iface->manual_stop = 1;
  172. write_MASTER_CTL(iface,
  173. read_MASTER_CTL(iface) | (0xff << 6));
  174. } else {
  175. /* set the readd number in other
  176. * combine mode.
  177. */
  178. write_MASTER_CTL(iface,
  179. (read_MASTER_CTL(iface) &
  180. (~(0xff << 6))) |
  181. (iface->readNum << 6));
  182. }
  183. /* remove restart bit and enable master receive */
  184. write_MASTER_CTL(iface,
  185. read_MASTER_CTL(iface) & ~RSTART);
  186. write_MASTER_CTL(iface,
  187. read_MASTER_CTL(iface) | MEN | MDIR);
  188. SSYNC();
  189. } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
  190. iface->cur_msg+1 < iface->msg_num) {
  191. iface->cur_msg++;
  192. iface->transPtr = iface->pmsg[iface->cur_msg].buf;
  193. iface->writeNum = iface->readNum =
  194. iface->pmsg[iface->cur_msg].len;
  195. /* Set Transmit device address */
  196. write_MASTER_ADDR(iface,
  197. iface->pmsg[iface->cur_msg].addr);
  198. if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
  199. iface->read_write = I2C_SMBUS_READ;
  200. else {
  201. iface->read_write = I2C_SMBUS_WRITE;
  202. /* Transmit first data */
  203. if (iface->writeNum > 0) {
  204. write_XMT_DATA8(iface,
  205. *(iface->transPtr++));
  206. iface->writeNum--;
  207. SSYNC();
  208. }
  209. }
  210. if (iface->pmsg[iface->cur_msg].len <= 255)
  211. write_MASTER_CTL(iface,
  212. iface->pmsg[iface->cur_msg].len << 6);
  213. else {
  214. write_MASTER_CTL(iface, 0xff << 6);
  215. iface->manual_stop = 1;
  216. }
  217. /* remove restart bit and enable master receive */
  218. write_MASTER_CTL(iface,
  219. read_MASTER_CTL(iface) & ~RSTART);
  220. write_MASTER_CTL(iface, read_MASTER_CTL(iface) |
  221. MEN | ((iface->read_write == I2C_SMBUS_READ) ?
  222. MDIR : 0));
  223. SSYNC();
  224. } else {
  225. iface->result = 1;
  226. write_INT_MASK(iface, 0);
  227. write_MASTER_CTL(iface, 0);
  228. SSYNC();
  229. complete(&iface->complete);
  230. }
  231. }
  232. }
  233. /* Interrupt handler */
  234. static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
  235. {
  236. struct bfin_twi_iface *iface = dev_id;
  237. unsigned long flags;
  238. spin_lock_irqsave(&iface->lock, flags);
  239. del_timer(&iface->timeout_timer);
  240. bfin_twi_handle_interrupt(iface);
  241. spin_unlock_irqrestore(&iface->lock, flags);
  242. return IRQ_HANDLED;
  243. }
  244. static void bfin_twi_timeout(unsigned long data)
  245. {
  246. struct bfin_twi_iface *iface = (struct bfin_twi_iface *)data;
  247. unsigned long flags;
  248. spin_lock_irqsave(&iface->lock, flags);
  249. bfin_twi_handle_interrupt(iface);
  250. if (iface->result == 0) {
  251. iface->timeout_count--;
  252. if (iface->timeout_count > 0) {
  253. iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
  254. add_timer(&iface->timeout_timer);
  255. } else {
  256. iface->result = -1;
  257. complete(&iface->complete);
  258. }
  259. }
  260. spin_unlock_irqrestore(&iface->lock, flags);
  261. }
  262. /*
  263. * Generic i2c master transfer entrypoint
  264. */
  265. static int bfin_twi_master_xfer(struct i2c_adapter *adap,
  266. struct i2c_msg *msgs, int num)
  267. {
  268. struct bfin_twi_iface *iface = adap->algo_data;
  269. struct i2c_msg *pmsg;
  270. int rc = 0;
  271. if (!(read_CONTROL(iface) & TWI_ENA))
  272. return -ENXIO;
  273. while (read_MASTER_STAT(iface) & BUSBUSY)
  274. yield();
  275. iface->pmsg = msgs;
  276. iface->msg_num = num;
  277. iface->cur_msg = 0;
  278. pmsg = &msgs[0];
  279. if (pmsg->flags & I2C_M_TEN) {
  280. dev_err(&adap->dev, "10 bits addr not supported!\n");
  281. return -EINVAL;
  282. }
  283. iface->cur_mode = TWI_I2C_MODE_REPEAT;
  284. iface->manual_stop = 0;
  285. iface->transPtr = pmsg->buf;
  286. iface->writeNum = iface->readNum = pmsg->len;
  287. iface->result = 0;
  288. iface->timeout_count = 10;
  289. init_completion(&(iface->complete));
  290. /* Set Transmit device address */
  291. write_MASTER_ADDR(iface, pmsg->addr);
  292. /* FIFO Initiation. Data in FIFO should be
  293. * discarded before start a new operation.
  294. */
  295. write_FIFO_CTL(iface, 0x3);
  296. SSYNC();
  297. write_FIFO_CTL(iface, 0);
  298. SSYNC();
  299. if (pmsg->flags & I2C_M_RD)
  300. iface->read_write = I2C_SMBUS_READ;
  301. else {
  302. iface->read_write = I2C_SMBUS_WRITE;
  303. /* Transmit first data */
  304. if (iface->writeNum > 0) {
  305. write_XMT_DATA8(iface, *(iface->transPtr++));
  306. iface->writeNum--;
  307. SSYNC();
  308. }
  309. }
  310. /* clear int stat */
  311. write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
  312. /* Interrupt mask . Enable XMT, RCV interrupt */
  313. write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
  314. SSYNC();
  315. if (pmsg->len <= 255)
  316. write_MASTER_CTL(iface, pmsg->len << 6);
  317. else {
  318. write_MASTER_CTL(iface, 0xff << 6);
  319. iface->manual_stop = 1;
  320. }
  321. iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
  322. add_timer(&iface->timeout_timer);
  323. /* Master enable */
  324. write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
  325. ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
  326. ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
  327. SSYNC();
  328. wait_for_completion(&iface->complete);
  329. rc = iface->result;
  330. if (rc == 1)
  331. return num;
  332. else
  333. return rc;
  334. }
  335. /*
  336. * SMBus type transfer entrypoint
  337. */
  338. int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
  339. unsigned short flags, char read_write,
  340. u8 command, int size, union i2c_smbus_data *data)
  341. {
  342. struct bfin_twi_iface *iface = adap->algo_data;
  343. int rc = 0;
  344. if (!(read_CONTROL(iface) & TWI_ENA))
  345. return -ENXIO;
  346. while (read_MASTER_STAT(iface) & BUSBUSY)
  347. yield();
  348. iface->writeNum = 0;
  349. iface->readNum = 0;
  350. /* Prepare datas & select mode */
  351. switch (size) {
  352. case I2C_SMBUS_QUICK:
  353. iface->transPtr = NULL;
  354. iface->cur_mode = TWI_I2C_MODE_STANDARD;
  355. break;
  356. case I2C_SMBUS_BYTE:
  357. if (data == NULL)
  358. iface->transPtr = NULL;
  359. else {
  360. if (read_write == I2C_SMBUS_READ)
  361. iface->readNum = 1;
  362. else
  363. iface->writeNum = 1;
  364. iface->transPtr = &data->byte;
  365. }
  366. iface->cur_mode = TWI_I2C_MODE_STANDARD;
  367. break;
  368. case I2C_SMBUS_BYTE_DATA:
  369. if (read_write == I2C_SMBUS_READ) {
  370. iface->readNum = 1;
  371. iface->cur_mode = TWI_I2C_MODE_COMBINED;
  372. } else {
  373. iface->writeNum = 1;
  374. iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
  375. }
  376. iface->transPtr = &data->byte;
  377. break;
  378. case I2C_SMBUS_WORD_DATA:
  379. if (read_write == I2C_SMBUS_READ) {
  380. iface->readNum = 2;
  381. iface->cur_mode = TWI_I2C_MODE_COMBINED;
  382. } else {
  383. iface->writeNum = 2;
  384. iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
  385. }
  386. iface->transPtr = (u8 *)&data->word;
  387. break;
  388. case I2C_SMBUS_PROC_CALL:
  389. iface->writeNum = 2;
  390. iface->readNum = 2;
  391. iface->cur_mode = TWI_I2C_MODE_COMBINED;
  392. iface->transPtr = (u8 *)&data->word;
  393. break;
  394. case I2C_SMBUS_BLOCK_DATA:
  395. if (read_write == I2C_SMBUS_READ) {
  396. iface->readNum = 0;
  397. iface->cur_mode = TWI_I2C_MODE_COMBINED;
  398. } else {
  399. iface->writeNum = data->block[0] + 1;
  400. iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
  401. }
  402. iface->transPtr = data->block;
  403. break;
  404. default:
  405. return -1;
  406. }
  407. iface->result = 0;
  408. iface->manual_stop = 0;
  409. iface->read_write = read_write;
  410. iface->command = command;
  411. iface->timeout_count = 10;
  412. init_completion(&(iface->complete));
  413. /* FIFO Initiation. Data in FIFO should be discarded before
  414. * start a new operation.
  415. */
  416. write_FIFO_CTL(iface, 0x3);
  417. SSYNC();
  418. write_FIFO_CTL(iface, 0);
  419. /* clear int stat */
  420. write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
  421. /* Set Transmit device address */
  422. write_MASTER_ADDR(iface, addr);
  423. SSYNC();
  424. iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
  425. add_timer(&iface->timeout_timer);
  426. switch (iface->cur_mode) {
  427. case TWI_I2C_MODE_STANDARDSUB:
  428. write_XMT_DATA8(iface, iface->command);
  429. write_INT_MASK(iface, MCOMP | MERR |
  430. ((iface->read_write == I2C_SMBUS_READ) ?
  431. RCVSERV : XMTSERV));
  432. SSYNC();
  433. if (iface->writeNum + 1 <= 255)
  434. write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
  435. else {
  436. write_MASTER_CTL(iface, 0xff << 6);
  437. iface->manual_stop = 1;
  438. }
  439. /* Master enable */
  440. write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
  441. ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
  442. break;
  443. case TWI_I2C_MODE_COMBINED:
  444. write_XMT_DATA8(iface, iface->command);
  445. write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
  446. SSYNC();
  447. if (iface->writeNum > 0)
  448. write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
  449. else
  450. write_MASTER_CTL(iface, 0x1 << 6);
  451. /* Master enable */
  452. write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
  453. ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
  454. break;
  455. default:
  456. write_MASTER_CTL(iface, 0);
  457. if (size != I2C_SMBUS_QUICK) {
  458. /* Don't access xmit data register when this is a
  459. * read operation.
  460. */
  461. if (iface->read_write != I2C_SMBUS_READ) {
  462. if (iface->writeNum > 0) {
  463. write_XMT_DATA8(iface,
  464. *(iface->transPtr++));
  465. if (iface->writeNum <= 255)
  466. write_MASTER_CTL(iface,
  467. iface->writeNum << 6);
  468. else {
  469. write_MASTER_CTL(iface,
  470. 0xff << 6);
  471. iface->manual_stop = 1;
  472. }
  473. iface->writeNum--;
  474. } else {
  475. write_XMT_DATA8(iface, iface->command);
  476. write_MASTER_CTL(iface, 1 << 6);
  477. }
  478. } else {
  479. if (iface->readNum > 0 && iface->readNum <= 255)
  480. write_MASTER_CTL(iface,
  481. iface->readNum << 6);
  482. else if (iface->readNum > 255) {
  483. write_MASTER_CTL(iface, 0xff << 6);
  484. iface->manual_stop = 1;
  485. } else {
  486. del_timer(&iface->timeout_timer);
  487. break;
  488. }
  489. }
  490. }
  491. write_INT_MASK(iface, MCOMP | MERR |
  492. ((iface->read_write == I2C_SMBUS_READ) ?
  493. RCVSERV : XMTSERV));
  494. SSYNC();
  495. /* Master enable */
  496. write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
  497. ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
  498. ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
  499. break;
  500. }
  501. SSYNC();
  502. wait_for_completion(&iface->complete);
  503. rc = (iface->result >= 0) ? 0 : -1;
  504. return rc;
  505. }
  506. /*
  507. * Return what the adapter supports
  508. */
  509. static u32 bfin_twi_functionality(struct i2c_adapter *adap)
  510. {
  511. return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
  512. I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
  513. I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
  514. I2C_FUNC_I2C;
  515. }
  516. static struct i2c_algorithm bfin_twi_algorithm = {
  517. .master_xfer = bfin_twi_master_xfer,
  518. .smbus_xfer = bfin_twi_smbus_xfer,
  519. .functionality = bfin_twi_functionality,
  520. };
  521. static int i2c_bfin_twi_suspend(struct platform_device *dev, pm_message_t state)
  522. {
  523. struct bfin_twi_iface *iface = platform_get_drvdata(dev);
  524. /* Disable TWI */
  525. write_CONTROL(iface, read_CONTROL(iface) & ~TWI_ENA);
  526. SSYNC();
  527. return 0;
  528. }
  529. static int i2c_bfin_twi_resume(struct platform_device *dev)
  530. {
  531. struct bfin_twi_iface *iface = platform_get_drvdata(dev);
  532. /* Enable TWI */
  533. write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
  534. SSYNC();
  535. return 0;
  536. }
  537. static int i2c_bfin_twi_probe(struct platform_device *pdev)
  538. {
  539. struct bfin_twi_iface *iface;
  540. struct i2c_adapter *p_adap;
  541. struct resource *res;
  542. int rc;
  543. iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
  544. if (!iface) {
  545. dev_err(&pdev->dev, "Cannot allocate memory\n");
  546. rc = -ENOMEM;
  547. goto out_error_nomem;
  548. }
  549. spin_lock_init(&(iface->lock));
  550. /* Find and map our resources */
  551. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  552. if (res == NULL) {
  553. dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
  554. rc = -ENOENT;
  555. goto out_error_get_res;
  556. }
  557. iface->regs_base = ioremap(res->start, res->end - res->start + 1);
  558. if (iface->regs_base == NULL) {
  559. dev_err(&pdev->dev, "Cannot map IO\n");
  560. rc = -ENXIO;
  561. goto out_error_ioremap;
  562. }
  563. iface->irq = platform_get_irq(pdev, 0);
  564. if (iface->irq < 0) {
  565. dev_err(&pdev->dev, "No IRQ specified\n");
  566. rc = -ENOENT;
  567. goto out_error_no_irq;
  568. }
  569. init_timer(&(iface->timeout_timer));
  570. iface->timeout_timer.function = bfin_twi_timeout;
  571. iface->timeout_timer.data = (unsigned long)iface;
  572. p_adap = &iface->adap;
  573. p_adap->id = I2C_HW_BLACKFIN;
  574. p_adap->nr = pdev->id;
  575. strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
  576. p_adap->algo = &bfin_twi_algorithm;
  577. p_adap->algo_data = iface;
  578. p_adap->class = I2C_CLASS_ALL;
  579. p_adap->dev.parent = &pdev->dev;
  580. rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
  581. if (rc) {
  582. dev_err(&pdev->dev, "Can't setup pin mux!\n");
  583. goto out_error_pin_mux;
  584. }
  585. rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
  586. IRQF_DISABLED, pdev->name, iface);
  587. if (rc) {
  588. dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
  589. rc = -ENODEV;
  590. goto out_error_req_irq;
  591. }
  592. /* Set TWI internal clock as 10MHz */
  593. write_CONTROL(iface, ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
  594. /* Set Twi interface clock as specified */
  595. write_CLKDIV(iface, ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ)
  596. << 8) | ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ)
  597. & 0xFF));
  598. /* Enable TWI */
  599. write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
  600. SSYNC();
  601. rc = i2c_add_numbered_adapter(p_adap);
  602. if (rc < 0) {
  603. dev_err(&pdev->dev, "Can't add i2c adapter!\n");
  604. goto out_error_add_adapter;
  605. }
  606. platform_set_drvdata(pdev, iface);
  607. dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
  608. "regs_base@%p\n", iface->regs_base);
  609. return 0;
  610. out_error_add_adapter:
  611. free_irq(iface->irq, iface);
  612. out_error_req_irq:
  613. out_error_no_irq:
  614. peripheral_free_list(pin_req[pdev->id]);
  615. out_error_pin_mux:
  616. iounmap(iface->regs_base);
  617. out_error_ioremap:
  618. out_error_get_res:
  619. kfree(iface);
  620. out_error_nomem:
  621. return rc;
  622. }
  623. static int i2c_bfin_twi_remove(struct platform_device *pdev)
  624. {
  625. struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
  626. platform_set_drvdata(pdev, NULL);
  627. i2c_del_adapter(&(iface->adap));
  628. free_irq(iface->irq, iface);
  629. peripheral_free_list(pin_req[pdev->id]);
  630. iounmap(iface->regs_base);
  631. kfree(iface);
  632. return 0;
  633. }
  634. static struct platform_driver i2c_bfin_twi_driver = {
  635. .probe = i2c_bfin_twi_probe,
  636. .remove = i2c_bfin_twi_remove,
  637. .suspend = i2c_bfin_twi_suspend,
  638. .resume = i2c_bfin_twi_resume,
  639. .driver = {
  640. .name = "i2c-bfin-twi",
  641. .owner = THIS_MODULE,
  642. },
  643. };
  644. static int __init i2c_bfin_twi_init(void)
  645. {
  646. return platform_driver_register(&i2c_bfin_twi_driver);
  647. }
  648. static void __exit i2c_bfin_twi_exit(void)
  649. {
  650. platform_driver_unregister(&i2c_bfin_twi_driver);
  651. }
  652. module_init(i2c_bfin_twi_init);
  653. module_exit(i2c_bfin_twi_exit);
  654. MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
  655. MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
  656. MODULE_LICENSE("GPL");
  657. MODULE_ALIAS("platform:i2c-bfin-twi");