early-quirks.c 4.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172
  1. /* Various workarounds for chipset bugs.
  2. This code runs very early and can't use the regular PCI subsystem
  3. The entries are keyed to PCI bridges which usually identify chipsets
  4. uniquely.
  5. This is only for whole classes of chipsets with specific problems which
  6. need early invasive action (e.g. before the timers are initialized).
  7. Most PCI device specific workarounds can be done later and should be
  8. in standard PCI quirks
  9. Mainboard specific bugs should be handled by DMI entries.
  10. CPU specific bugs in setup.c */
  11. #include <linux/pci.h>
  12. #include <linux/acpi.h>
  13. #include <linux/pci_ids.h>
  14. #include <asm/pci-direct.h>
  15. #include <asm/dma.h>
  16. #include <asm/io_apic.h>
  17. #include <asm/apic.h>
  18. #ifdef CONFIG_GART_IOMMU
  19. #include <asm/gart.h>
  20. #endif
  21. static void __init fix_hypertransport_config(int num, int slot, int func)
  22. {
  23. u32 htcfg;
  24. /*
  25. * we found a hypertransport bus
  26. * make sure that we are broadcasting
  27. * interrupts to all cpus on the ht bus
  28. * if we're using extended apic ids
  29. */
  30. htcfg = read_pci_config(num, slot, func, 0x68);
  31. if (htcfg & (1 << 18)) {
  32. printk(KERN_INFO "Detected use of extended apic ids "
  33. "on hypertransport bus\n");
  34. if ((htcfg & (1 << 17)) == 0) {
  35. printk(KERN_INFO "Enabling hypertransport extended "
  36. "apic interrupt broadcast\n");
  37. printk(KERN_INFO "Note this is a bios bug, "
  38. "please contact your hw vendor\n");
  39. htcfg |= (1 << 17);
  40. write_pci_config(num, slot, func, 0x68, htcfg);
  41. }
  42. }
  43. }
  44. static void __init via_bugs(int num, int slot, int func)
  45. {
  46. #ifdef CONFIG_GART_IOMMU
  47. if ((max_pfn > MAX_DMA32_PFN || force_iommu) &&
  48. !gart_iommu_aperture_allowed) {
  49. printk(KERN_INFO
  50. "Looks like a VIA chipset. Disabling IOMMU."
  51. " Override with iommu=allowed\n");
  52. gart_iommu_aperture_disabled = 1;
  53. }
  54. #endif
  55. }
  56. #ifdef CONFIG_ACPI
  57. #ifdef CONFIG_X86_IO_APIC
  58. static int __init nvidia_hpet_check(struct acpi_table_header *header)
  59. {
  60. return 0;
  61. }
  62. #endif /* CONFIG_X86_IO_APIC */
  63. #endif /* CONFIG_ACPI */
  64. static void __init nvidia_bugs(int num, int slot, int func)
  65. {
  66. #ifdef CONFIG_ACPI
  67. #ifdef CONFIG_X86_IO_APIC
  68. /*
  69. * All timer overrides on Nvidia are
  70. * wrong unless HPET is enabled.
  71. * Unfortunately that's not true on many Asus boards.
  72. * We don't know yet how to detect this automatically, but
  73. * at least allow a command line override.
  74. */
  75. if (acpi_use_timer_override)
  76. return;
  77. if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
  78. acpi_skip_timer_override = 1;
  79. printk(KERN_INFO "Nvidia board "
  80. "detected. Ignoring ACPI "
  81. "timer override.\n");
  82. printk(KERN_INFO "If you got timer trouble "
  83. "try acpi_use_timer_override\n");
  84. }
  85. #endif
  86. #endif
  87. /* RED-PEN skip them on mptables too? */
  88. }
  89. #define QFLAG_APPLY_ONCE 0x1
  90. #define QFLAG_APPLIED 0x2
  91. #define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
  92. struct chipset {
  93. u32 vendor;
  94. u32 device;
  95. u32 class;
  96. u32 class_mask;
  97. u32 flags;
  98. void (*f)(int num, int slot, int func);
  99. };
  100. static struct chipset early_qrk[] __initdata = {
  101. { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
  102. PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
  103. { PCI_VENDOR_ID_VIA, PCI_ANY_ID,
  104. PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
  105. { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
  106. PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
  107. {}
  108. };
  109. static void __init check_dev_quirk(int num, int slot, int func)
  110. {
  111. u16 class;
  112. u16 vendor;
  113. u16 device;
  114. u8 type;
  115. int i;
  116. class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
  117. if (class == 0xffff)
  118. return;
  119. vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
  120. device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
  121. for (i = 0; early_qrk[i].f != NULL; i++) {
  122. if (((early_qrk[i].vendor == PCI_ANY_ID) ||
  123. (early_qrk[i].vendor == vendor)) &&
  124. ((early_qrk[i].device == PCI_ANY_ID) ||
  125. (early_qrk[i].device == device)) &&
  126. (!((early_qrk[i].class ^ class) &
  127. early_qrk[i].class_mask))) {
  128. if ((early_qrk[i].flags &
  129. QFLAG_DONE) != QFLAG_DONE)
  130. early_qrk[i].f(num, slot, func);
  131. early_qrk[i].flags |= QFLAG_APPLIED;
  132. }
  133. }
  134. type = read_pci_config_byte(num, slot, func,
  135. PCI_HEADER_TYPE);
  136. if (!(type & 0x80))
  137. return;
  138. }
  139. void __init early_quirks(void)
  140. {
  141. int num, slot, func;
  142. if (!early_pci_allowed())
  143. return;
  144. /* Poor man's PCI discovery */
  145. for (num = 0; num < 32; num++)
  146. for (slot = 0; slot < 32; slot++)
  147. for (func = 0; func < 8; func++)
  148. check_dev_quirk(num, slot, func);
  149. }