walnut.dts 5.2 KB

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  1. /*
  2. * Device Tree Source for IBM Walnut
  3. *
  4. * Copyright 2007 IBM Corp.
  5. * Josh Boyer <jwboyer@linux.vnet.ibm.com>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without
  9. * any warranty of any kind, whether express or implied.
  10. */
  11. / {
  12. #address-cells = <1>;
  13. #size-cells = <1>;
  14. model = "ibm,walnut";
  15. compatible = "ibm,walnut";
  16. dcr-parent = <&/cpus/cpu@0>;
  17. aliases {
  18. ethernet0 = &EMAC;
  19. serial0 = &UART0;
  20. serial1 = &UART1;
  21. };
  22. cpus {
  23. #address-cells = <1>;
  24. #size-cells = <0>;
  25. cpu@0 {
  26. device_type = "cpu";
  27. model = "PowerPC,405GP";
  28. reg = <0>;
  29. clock-frequency = <bebc200>; /* Filled in by zImage */
  30. timebase-frequency = <0>; /* Filled in by zImage */
  31. i-cache-line-size = <20>;
  32. d-cache-line-size = <20>;
  33. i-cache-size = <4000>;
  34. d-cache-size = <4000>;
  35. dcr-controller;
  36. dcr-access-method = "native";
  37. };
  38. };
  39. memory {
  40. device_type = "memory";
  41. reg = <0 0>; /* Filled in by zImage */
  42. };
  43. UIC0: interrupt-controller {
  44. compatible = "ibm,uic";
  45. interrupt-controller;
  46. cell-index = <0>;
  47. dcr-reg = <0c0 9>;
  48. #address-cells = <0>;
  49. #size-cells = <0>;
  50. #interrupt-cells = <2>;
  51. };
  52. plb {
  53. compatible = "ibm,plb3";
  54. #address-cells = <1>;
  55. #size-cells = <1>;
  56. ranges;
  57. clock-frequency = <0>; /* Filled in by zImage */
  58. SDRAM0: memory-controller {
  59. compatible = "ibm,sdram-405gp";
  60. dcr-reg = <010 2>;
  61. };
  62. MAL: mcmal {
  63. compatible = "ibm,mcmal-405gp", "ibm,mcmal";
  64. dcr-reg = <180 62>;
  65. num-tx-chans = <1>;
  66. num-rx-chans = <1>;
  67. interrupt-parent = <&UIC0>;
  68. interrupts = <
  69. b 4 /* TXEOB */
  70. c 4 /* RXEOB */
  71. a 4 /* SERR */
  72. d 4 /* TXDE */
  73. e 4 /* RXDE */>;
  74. };
  75. POB0: opb {
  76. compatible = "ibm,opb-405gp", "ibm,opb";
  77. #address-cells = <1>;
  78. #size-cells = <1>;
  79. ranges = <ef600000 ef600000 a00000>;
  80. dcr-reg = <0a0 5>;
  81. clock-frequency = <0>; /* Filled in by zImage */
  82. UART0: serial@ef600300 {
  83. device_type = "serial";
  84. compatible = "ns16550";
  85. reg = <ef600300 8>;
  86. virtual-reg = <ef600300>;
  87. clock-frequency = <0>; /* Filled in by zImage */
  88. current-speed = <2580>;
  89. interrupt-parent = <&UIC0>;
  90. interrupts = <0 4>;
  91. };
  92. UART1: serial@ef600400 {
  93. device_type = "serial";
  94. compatible = "ns16550";
  95. reg = <ef600400 8>;
  96. virtual-reg = <ef600400>;
  97. clock-frequency = <0>; /* Filled in by zImage */
  98. current-speed = <2580>;
  99. interrupt-parent = <&UIC0>;
  100. interrupts = <1 4>;
  101. };
  102. IIC: i2c@ef600500 {
  103. compatible = "ibm,iic-405gp", "ibm,iic";
  104. reg = <ef600500 11>;
  105. interrupt-parent = <&UIC0>;
  106. interrupts = <2 4>;
  107. };
  108. GPIO: gpio@ef600700 {
  109. compatible = "ibm,gpio-405gp";
  110. reg = <ef600700 20>;
  111. };
  112. EMAC: ethernet@ef600800 {
  113. device_type = "network";
  114. compatible = "ibm,emac-405gp", "ibm,emac";
  115. interrupt-parent = <&UIC0>;
  116. interrupts = <
  117. f 4 /* Ethernet */
  118. 9 4 /* Ethernet Wake Up */>;
  119. local-mac-address = [000000000000]; /* Filled in by zImage */
  120. reg = <ef600800 70>;
  121. mal-device = <&MAL>;
  122. mal-tx-channel = <0>;
  123. mal-rx-channel = <0>;
  124. cell-index = <0>;
  125. max-frame-size = <5dc>;
  126. rx-fifo-size = <1000>;
  127. tx-fifo-size = <800>;
  128. phy-mode = "rmii";
  129. phy-map = <00000001>;
  130. };
  131. };
  132. EBC0: ebc {
  133. compatible = "ibm,ebc-405gp", "ibm,ebc";
  134. dcr-reg = <012 2>;
  135. #address-cells = <2>;
  136. #size-cells = <1>;
  137. /* The ranges property is supplied by the bootwrapper
  138. * and is based on the firmware's configuration of the
  139. * EBC bridge
  140. */
  141. clock-frequency = <0>; /* Filled in by zImage */
  142. sram@0,0 {
  143. reg = <0 0 80000>;
  144. };
  145. flash@0,80000 {
  146. compatible = "jedec-flash";
  147. bank-width = <1>;
  148. reg = <0 80000 80000>;
  149. #address-cells = <1>;
  150. #size-cells = <1>;
  151. partition@0 {
  152. label = "OpenBIOS";
  153. reg = <0 80000>;
  154. read-only;
  155. };
  156. };
  157. nvram@1,0 {
  158. /* NVRAM and RTC */
  159. compatible = "ds1743-nvram";
  160. #bytes = <2000>;
  161. reg = <1 0 2000>;
  162. };
  163. keyboard@2,0 {
  164. compatible = "intel,82C42PC";
  165. reg = <2 0 2>;
  166. };
  167. ir@3,0 {
  168. compatible = "ti,TIR2000PAG";
  169. reg = <3 0 10>;
  170. };
  171. fpga@7,0 {
  172. compatible = "Walnut-FPGA";
  173. reg = <7 0 10>;
  174. virtual-reg = <f0300005>;
  175. };
  176. };
  177. PCI0: pci@ec000000 {
  178. device_type = "pci";
  179. #interrupt-cells = <1>;
  180. #size-cells = <2>;
  181. #address-cells = <3>;
  182. compatible = "ibm,plb405gp-pci", "ibm,plb-pci";
  183. primary;
  184. reg = <eec00000 8 /* Config space access */
  185. eed80000 4 /* IACK */
  186. eed80000 4 /* Special cycle */
  187. ef480000 40>; /* Internal registers */
  188. /* Outbound ranges, one memory and one IO,
  189. * later cannot be changed. Chip supports a second
  190. * IO range but we don't use it for now
  191. */
  192. ranges = <02000000 0 80000000 80000000 0 20000000
  193. 01000000 0 00000000 e8000000 0 00010000>;
  194. /* Inbound 2GB range starting at 0 */
  195. dma-ranges = <42000000 0 0 0 0 80000000>;
  196. /* Walnut has all 4 IRQ pins tied together per slot */
  197. interrupt-map-mask = <f800 0 0 0>;
  198. interrupt-map = <
  199. /* IDSEL 1 */
  200. 0800 0 0 0 &UIC0 1c 8
  201. /* IDSEL 2 */
  202. 1000 0 0 0 &UIC0 1d 8
  203. /* IDSEL 3 */
  204. 1800 0 0 0 &UIC0 1e 8
  205. /* IDSEL 4 */
  206. 2000 0 0 0 &UIC0 1f 8
  207. >;
  208. };
  209. };
  210. chosen {
  211. linux,stdout-path = "/plb/opb/serial@ef600300";
  212. };
  213. };