tqm5200.dts 5.2 KB

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  1. /*
  2. * TQM5200 board Device Tree Source
  3. *
  4. * Copyright (C) 2007 Semihalf
  5. * Marian Balakowicz <m8@semihalf.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. */
  12. /dts-v1/;
  13. / {
  14. model = "tqc,tqm5200";
  15. compatible = "tqc,tqm5200";
  16. #address-cells = <1>;
  17. #size-cells = <1>;
  18. cpus {
  19. #address-cells = <1>;
  20. #size-cells = <0>;
  21. PowerPC,5200@0 {
  22. device_type = "cpu";
  23. reg = <0>;
  24. d-cache-line-size = <32>;
  25. i-cache-line-size = <32>;
  26. d-cache-size = <0x4000>; // L1, 16K
  27. i-cache-size = <0x4000>; // L1, 16K
  28. timebase-frequency = <0>; // from bootloader
  29. bus-frequency = <0>; // from bootloader
  30. clock-frequency = <0>; // from bootloader
  31. };
  32. };
  33. memory {
  34. device_type = "memory";
  35. reg = <0x00000000 0x04000000>; // 64MB
  36. };
  37. soc5200@f0000000 {
  38. #address-cells = <1>;
  39. #size-cells = <1>;
  40. compatible = "fsl,mpc5200-immr";
  41. ranges = <0 0xf0000000 0x0000c000>;
  42. reg = <0xf0000000 0x00000100>;
  43. bus-frequency = <0>; // from bootloader
  44. system-frequency = <0>; // from bootloader
  45. cdm@200 {
  46. compatible = "fsl,mpc5200-cdm";
  47. reg = <0x200 0x38>;
  48. };
  49. mpc5200_pic: interrupt-controller@500 {
  50. // 5200 interrupts are encoded into two levels;
  51. interrupt-controller;
  52. #interrupt-cells = <3>;
  53. compatible = "fsl,mpc5200-pic";
  54. reg = <0x500 0x80>;
  55. };
  56. timer@600 { // General Purpose Timer
  57. compatible = "fsl,mpc5200-gpt";
  58. reg = <0x600 0x10>;
  59. interrupts = <1 9 0>;
  60. interrupt-parent = <&mpc5200_pic>;
  61. fsl,has-wdt;
  62. };
  63. gpio@b00 {
  64. compatible = "fsl,mpc5200-gpio";
  65. reg = <0xb00 0x40>;
  66. interrupts = <1 7 0>;
  67. interrupt-parent = <&mpc5200_pic>;
  68. };
  69. usb@1000 {
  70. compatible = "fsl,mpc5200-ohci","ohci-be";
  71. reg = <0x1000 0xff>;
  72. interrupts = <2 6 0>;
  73. interrupt-parent = <&mpc5200_pic>;
  74. };
  75. dma-controller@1200 {
  76. compatible = "fsl,mpc5200-bestcomm";
  77. reg = <0x1200 0x80>;
  78. interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
  79. 3 4 0 3 5 0 3 6 0 3 7 0
  80. 3 8 0 3 9 0 3 10 0 3 11 0
  81. 3 12 0 3 13 0 3 14 0 3 15 0>;
  82. interrupt-parent = <&mpc5200_pic>;
  83. };
  84. xlb@1f00 {
  85. compatible = "fsl,mpc5200-xlb";
  86. reg = <0x1f00 0x100>;
  87. };
  88. serial@2000 { // PSC1
  89. device_type = "serial";
  90. compatible = "fsl,mpc5200-psc-uart";
  91. port-number = <0>; // Logical port assignment
  92. reg = <0x2000 0x100>;
  93. interrupts = <2 1 0>;
  94. interrupt-parent = <&mpc5200_pic>;
  95. };
  96. serial@2200 { // PSC2
  97. device_type = "serial";
  98. compatible = "fsl,mpc5200-psc-uart";
  99. port-number = <1>; // Logical port assignment
  100. reg = <0x2200 0x100>;
  101. interrupts = <2 2 0>;
  102. interrupt-parent = <&mpc5200_pic>;
  103. };
  104. serial@2400 { // PSC3
  105. device_type = "serial";
  106. compatible = "fsl,mpc5200-psc-uart";
  107. port-number = <2>; // Logical port assignment
  108. reg = <0x2400 0x100>;
  109. interrupts = <2 3 0>;
  110. interrupt-parent = <&mpc5200_pic>;
  111. };
  112. ethernet@3000 {
  113. device_type = "network";
  114. compatible = "fsl,mpc5200-fec";
  115. reg = <0x3000 0x400>;
  116. local-mac-address = [ 00 00 00 00 00 00 ];
  117. interrupts = <2 5 0>;
  118. interrupt-parent = <&mpc5200_pic>;
  119. phy-handle = <&phy0>;
  120. };
  121. mdio@3000 {
  122. #address-cells = <1>;
  123. #size-cells = <0>;
  124. compatible = "fsl,mpc5200-mdio";
  125. reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
  126. interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
  127. interrupt-parent = <&mpc5200_pic>;
  128. phy0: ethernet-phy@0 {
  129. device_type = "ethernet-phy";
  130. reg = <0>;
  131. };
  132. };
  133. ata@3a00 {
  134. compatible = "fsl,mpc5200-ata";
  135. reg = <0x3a00 0x100>;
  136. interrupts = <2 7 0>;
  137. interrupt-parent = <&mpc5200_pic>;
  138. };
  139. i2c@3d40 {
  140. #address-cells = <1>;
  141. #size-cells = <0>;
  142. compatible = "fsl,mpc5200-i2c","fsl-i2c";
  143. reg = <0x3d40 0x40>;
  144. interrupts = <2 16 0>;
  145. interrupt-parent = <&mpc5200_pic>;
  146. fsl5200-clocking;
  147. rtc@68 {
  148. device_type = "rtc";
  149. compatible = "dallas,ds1307";
  150. reg = <0x68>;
  151. };
  152. };
  153. sram@8000 {
  154. compatible = "fsl,mpc5200-sram";
  155. reg = <0x8000 0x4000>;
  156. };
  157. };
  158. lpb {
  159. model = "fsl,lpb";
  160. compatible = "fsl,lpb";
  161. #address-cells = <2>;
  162. #size-cells = <1>;
  163. ranges = <0 0 0xfc000000 0x02000000>;
  164. flash@0,0 {
  165. compatible = "cfi-flash";
  166. reg = <0 0 0x02000000>;
  167. bank-width = <4>;
  168. device-width = <2>;
  169. #size-cells = <1>;
  170. #address-cells = <1>;
  171. };
  172. };
  173. pci@f0000d00 {
  174. #interrupt-cells = <1>;
  175. #size-cells = <2>;
  176. #address-cells = <3>;
  177. device_type = "pci";
  178. compatible = "fsl,mpc5200-pci";
  179. reg = <0xf0000d00 0x100>;
  180. interrupt-map-mask = <0xf800 0 0 7>;
  181. interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
  182. 0xc000 0 0 2 &mpc5200_pic 0 0 3
  183. 0xc000 0 0 3 &mpc5200_pic 0 0 3
  184. 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
  185. clock-frequency = <0>; // From boot loader
  186. interrupts = <2 8 0 2 9 0 2 10 0>;
  187. interrupt-parent = <&mpc5200_pic>;
  188. bus-range = <0 0>;
  189. ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
  190. 0x02000000 0 0x90000000 0x90000000 0 0x10000000
  191. 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
  192. };
  193. };