mpc834x_mds.dts 8.3 KB

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  1. /*
  2. * MPC8349E MDS Device Tree Source
  3. *
  4. * Copyright 2005, 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "MPC8349EMDS";
  14. compatible = "MPC8349EMDS", "MPC834xMDS", "MPC83xxMDS";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. serial1 = &serial1;
  22. pci0 = &pci0;
  23. pci1 = &pci1;
  24. };
  25. cpus {
  26. #address-cells = <1>;
  27. #size-cells = <0>;
  28. PowerPC,8349@0 {
  29. device_type = "cpu";
  30. reg = <0x0>;
  31. d-cache-line-size = <32>;
  32. i-cache-line-size = <32>;
  33. d-cache-size = <32768>;
  34. i-cache-size = <32768>;
  35. timebase-frequency = <0>; // from bootloader
  36. bus-frequency = <0>; // from bootloader
  37. clock-frequency = <0>; // from bootloader
  38. };
  39. };
  40. memory {
  41. device_type = "memory";
  42. reg = <0x00000000 0x10000000>; // 256MB at 0
  43. };
  44. bcsr@e2400000 {
  45. device_type = "board-control";
  46. reg = <0xe2400000 0x8000>;
  47. };
  48. soc8349@e0000000 {
  49. #address-cells = <1>;
  50. #size-cells = <1>;
  51. device_type = "soc";
  52. ranges = <0x0 0xe0000000 0x00100000>;
  53. reg = <0xe0000000 0x00000200>;
  54. bus-frequency = <0>;
  55. wdt@200 {
  56. device_type = "watchdog";
  57. compatible = "mpc83xx_wdt";
  58. reg = <0x200 0x100>;
  59. };
  60. i2c@3000 {
  61. #address-cells = <1>;
  62. #size-cells = <0>;
  63. cell-index = <0>;
  64. compatible = "fsl-i2c";
  65. reg = <0x3000 0x100>;
  66. interrupts = <14 0x8>;
  67. interrupt-parent = <&ipic>;
  68. dfsrr;
  69. rtc@68 {
  70. compatible = "dallas,ds1374";
  71. reg = <0x68>;
  72. };
  73. };
  74. i2c@3100 {
  75. #address-cells = <1>;
  76. #size-cells = <0>;
  77. cell-index = <1>;
  78. compatible = "fsl-i2c";
  79. reg = <0x3100 0x100>;
  80. interrupts = <15 0x8>;
  81. interrupt-parent = <&ipic>;
  82. dfsrr;
  83. };
  84. spi@7000 {
  85. cell-index = <0>;
  86. compatible = "fsl,spi";
  87. reg = <0x7000 0x1000>;
  88. interrupts = <16 0x8>;
  89. interrupt-parent = <&ipic>;
  90. mode = "cpu";
  91. };
  92. /* phy type (ULPI or SERIAL) are only types supported for MPH */
  93. /* port = 0 or 1 */
  94. usb@22000 {
  95. compatible = "fsl-usb2-mph";
  96. reg = <0x22000 0x1000>;
  97. #address-cells = <1>;
  98. #size-cells = <0>;
  99. interrupt-parent = <&ipic>;
  100. interrupts = <39 0x8>;
  101. phy_type = "ulpi";
  102. port1;
  103. };
  104. /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
  105. usb@23000 {
  106. compatible = "fsl-usb2-dr";
  107. reg = <0x23000 0x1000>;
  108. #address-cells = <1>;
  109. #size-cells = <0>;
  110. interrupt-parent = <&ipic>;
  111. interrupts = <38 0x8>;
  112. dr_mode = "otg";
  113. phy_type = "ulpi";
  114. };
  115. mdio@24520 {
  116. #address-cells = <1>;
  117. #size-cells = <0>;
  118. compatible = "fsl,gianfar-mdio";
  119. reg = <0x24520 0x20>;
  120. phy0: ethernet-phy@0 {
  121. interrupt-parent = <&ipic>;
  122. interrupts = <17 0x8>;
  123. reg = <0x0>;
  124. device_type = "ethernet-phy";
  125. };
  126. phy1: ethernet-phy@1 {
  127. interrupt-parent = <&ipic>;
  128. interrupts = <18 0x8>;
  129. reg = <0x1>;
  130. device_type = "ethernet-phy";
  131. };
  132. };
  133. enet0: ethernet@24000 {
  134. cell-index = <0>;
  135. device_type = "network";
  136. model = "TSEC";
  137. compatible = "gianfar";
  138. reg = <0x24000 0x1000>;
  139. local-mac-address = [ 00 00 00 00 00 00 ];
  140. interrupts = <32 0x8 33 0x8 34 0x8>;
  141. interrupt-parent = <&ipic>;
  142. phy-handle = <&phy0>;
  143. linux,network-index = <0>;
  144. };
  145. enet1: ethernet@25000 {
  146. cell-index = <1>;
  147. device_type = "network";
  148. model = "TSEC";
  149. compatible = "gianfar";
  150. reg = <0x25000 0x1000>;
  151. local-mac-address = [ 00 00 00 00 00 00 ];
  152. interrupts = <35 0x8 36 0x8 37 0x8>;
  153. interrupt-parent = <&ipic>;
  154. phy-handle = <&phy1>;
  155. linux,network-index = <1>;
  156. };
  157. serial0: serial@4500 {
  158. cell-index = <0>;
  159. device_type = "serial";
  160. compatible = "ns16550";
  161. reg = <0x4500 0x100>;
  162. clock-frequency = <0>;
  163. interrupts = <9 0x8>;
  164. interrupt-parent = <&ipic>;
  165. };
  166. serial1: serial@4600 {
  167. cell-index = <1>;
  168. device_type = "serial";
  169. compatible = "ns16550";
  170. reg = <0x4600 0x100>;
  171. clock-frequency = <0>;
  172. interrupts = <10 0x8>;
  173. interrupt-parent = <&ipic>;
  174. };
  175. /* May need to remove if on a part without crypto engine */
  176. crypto@30000 {
  177. device_type = "crypto";
  178. model = "SEC2";
  179. compatible = "talitos";
  180. reg = <0x30000 0x10000>;
  181. interrupts = <11 0x8>;
  182. interrupt-parent = <&ipic>;
  183. num-channels = <4>;
  184. channel-fifo-len = <24>;
  185. exec-units-mask = <0x0000007e>;
  186. /* desc mask is for rev2.0,
  187. * we need runtime fixup for >2.0 */
  188. descriptor-types-mask = <0x01010ebf>;
  189. };
  190. /* IPIC
  191. * interrupts cell = <intr #, sense>
  192. * sense values match linux IORESOURCE_IRQ_* defines:
  193. * sense == 8: Level, low assertion
  194. * sense == 2: Edge, high-to-low change
  195. */
  196. ipic: pic@700 {
  197. interrupt-controller;
  198. #address-cells = <0>;
  199. #interrupt-cells = <2>;
  200. reg = <0x700 0x100>;
  201. device_type = "ipic";
  202. };
  203. };
  204. pci0: pci@e0008500 {
  205. cell-index = <1>;
  206. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  207. interrupt-map = <
  208. /* IDSEL 0x11 */
  209. 0x8800 0x0 0x0 0x1 &ipic 20 0x8
  210. 0x8800 0x0 0x0 0x2 &ipic 21 0x8
  211. 0x8800 0x0 0x0 0x3 &ipic 22 0x8
  212. 0x8800 0x0 0x0 0x4 &ipic 23 0x8
  213. /* IDSEL 0x12 */
  214. 0x9000 0x0 0x0 0x1 &ipic 22 0x8
  215. 0x9000 0x0 0x0 0x2 &ipic 23 0x8
  216. 0x9000 0x0 0x0 0x3 &ipic 20 0x8
  217. 0x9000 0x0 0x0 0x4 &ipic 21 0x8
  218. /* IDSEL 0x13 */
  219. 0x9800 0x0 0x0 0x1 &ipic 23 0x8
  220. 0x9800 0x0 0x0 0x2 &ipic 20 0x8
  221. 0x9800 0x0 0x0 0x3 &ipic 21 0x8
  222. 0x9800 0x0 0x0 0x4 &ipic 22 0x8
  223. /* IDSEL 0x15 */
  224. 0xa800 0x0 0x0 0x1 &ipic 20 0x8
  225. 0xa800 0x0 0x0 0x2 &ipic 21 0x8
  226. 0xa800 0x0 0x0 0x3 &ipic 22 0x8
  227. 0xa800 0x0 0x0 0x4 &ipic 23 0x8
  228. /* IDSEL 0x16 */
  229. 0xb000 0x0 0x0 0x1 &ipic 23 0x8
  230. 0xb000 0x0 0x0 0x2 &ipic 20 0x8
  231. 0xb000 0x0 0x0 0x3 &ipic 21 0x8
  232. 0xb000 0x0 0x0 0x4 &ipic 22 0x8
  233. /* IDSEL 0x17 */
  234. 0xb800 0x0 0x0 0x1 &ipic 22 0x8
  235. 0xb800 0x0 0x0 0x2 &ipic 23 0x8
  236. 0xb800 0x0 0x0 0x3 &ipic 20 0x8
  237. 0xb800 0x0 0x0 0x4 &ipic 21 0x8
  238. /* IDSEL 0x18 */
  239. 0xc000 0x0 0x0 0x1 &ipic 21 0x8
  240. 0xc000 0x0 0x0 0x2 &ipic 22 0x8
  241. 0xc000 0x0 0x0 0x3 &ipic 23 0x8
  242. 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
  243. interrupt-parent = <&ipic>;
  244. interrupts = <66 0x8>;
  245. bus-range = <0 0>;
  246. ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
  247. 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
  248. 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
  249. clock-frequency = <66666666>;
  250. #interrupt-cells = <1>;
  251. #size-cells = <2>;
  252. #address-cells = <3>;
  253. reg = <0xe0008500 0x100>;
  254. compatible = "fsl,mpc8349-pci";
  255. device_type = "pci";
  256. };
  257. pci1: pci@e0008600 {
  258. cell-index = <2>;
  259. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  260. interrupt-map = <
  261. /* IDSEL 0x11 */
  262. 0x8800 0x0 0x0 0x1 &ipic 20 0x8
  263. 0x8800 0x0 0x0 0x2 &ipic 21 0x8
  264. 0x8800 0x0 0x0 0x3 &ipic 22 0x8
  265. 0x8800 0x0 0x0 0x4 &ipic 23 0x8
  266. /* IDSEL 0x12 */
  267. 0x9000 0x0 0x0 0x1 &ipic 22 0x8
  268. 0x9000 0x0 0x0 0x2 &ipic 23 0x8
  269. 0x9000 0x0 0x0 0x3 &ipic 20 0x8
  270. 0x9000 0x0 0x0 0x4 &ipic 21 0x8
  271. /* IDSEL 0x13 */
  272. 0x9800 0x0 0x0 0x1 &ipic 23 0x8
  273. 0x9800 0x0 0x0 0x2 &ipic 20 0x8
  274. 0x9800 0x0 0x0 0x3 &ipic 21 0x8
  275. 0x9800 0x0 0x0 0x4 &ipic 22 0x8
  276. /* IDSEL 0x15 */
  277. 0xa800 0x0 0x0 0x1 &ipic 20 0x8
  278. 0xa800 0x0 0x0 0x2 &ipic 21 0x8
  279. 0xa800 0x0 0x0 0x3 &ipic 22 0x8
  280. 0xa800 0x0 0x0 0x4 &ipic 23 0x8
  281. /* IDSEL 0x16 */
  282. 0xb000 0x0 0x0 0x1 &ipic 23 0x8
  283. 0xb000 0x0 0x0 0x2 &ipic 20 0x8
  284. 0xb000 0x0 0x0 0x3 &ipic 21 0x8
  285. 0xb000 0x0 0x0 0x4 &ipic 22 0x8
  286. /* IDSEL 0x17 */
  287. 0xb800 0x0 0x0 0x1 &ipic 22 0x8
  288. 0xb800 0x0 0x0 0x2 &ipic 23 0x8
  289. 0xb800 0x0 0x0 0x3 &ipic 20 0x8
  290. 0xb800 0x0 0x0 0x4 &ipic 21 0x8
  291. /* IDSEL 0x18 */
  292. 0xc000 0x0 0x0 0x1 &ipic 21 0x8
  293. 0xc000 0x0 0x0 0x2 &ipic 22 0x8
  294. 0xc000 0x0 0x0 0x3 &ipic 23 0x8
  295. 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
  296. interrupt-parent = <&ipic>;
  297. interrupts = <67 0x8>;
  298. bus-range = <0 0>;
  299. ranges = <0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
  300. 0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
  301. 0x01000000 0x0 0x00000000 0xe2100000 0x0 0x00100000>;
  302. clock-frequency = <66666666>;
  303. #interrupt-cells = <1>;
  304. #size-cells = <2>;
  305. #address-cells = <3>;
  306. reg = <0xe0008600 0x100>;
  307. compatible = "fsl,mpc8349-pci";
  308. device_type = "pci";
  309. };
  310. };