mpc8315erdb.dts 6.4 KB

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  1. /*
  2. * MPC8315E RDB Device Tree Source
  3. *
  4. * Copyright 2007 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. compatible = "fsl,mpc8315erdb";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. aliases {
  17. ethernet0 = &enet0;
  18. ethernet1 = &enet1;
  19. serial0 = &serial0;
  20. serial1 = &serial1;
  21. pci0 = &pci0;
  22. };
  23. cpus {
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. PowerPC,8315@0 {
  27. device_type = "cpu";
  28. reg = <0x0>;
  29. d-cache-line-size = <32>;
  30. i-cache-line-size = <32>;
  31. d-cache-size = <16384>;
  32. i-cache-size = <16384>;
  33. timebase-frequency = <0>; // from bootloader
  34. bus-frequency = <0>; // from bootloader
  35. clock-frequency = <0>; // from bootloader
  36. };
  37. };
  38. memory {
  39. device_type = "memory";
  40. reg = <0x00000000 0x08000000>; // 128MB at 0
  41. };
  42. localbus@e0005000 {
  43. #address-cells = <2>;
  44. #size-cells = <1>;
  45. compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
  46. reg = <0xe0005000 0x1000>;
  47. interrupts = <77 0x8>;
  48. interrupt-parent = <&ipic>;
  49. // CS0 and CS1 are swapped when
  50. // booting from nand, but the
  51. // addresses are the same.
  52. ranges = <0x0 0x0 0xfe000000 0x00800000
  53. 0x1 0x0 0xe0600000 0x00002000
  54. 0x2 0x0 0xf0000000 0x00020000
  55. 0x3 0x0 0xfa000000 0x00008000>;
  56. flash@0,0 {
  57. #address-cells = <1>;
  58. #size-cells = <1>;
  59. compatible = "cfi-flash";
  60. reg = <0x0 0x0 0x800000>;
  61. bank-width = <2>;
  62. device-width = <1>;
  63. };
  64. nand@1,0 {
  65. #address-cells = <1>;
  66. #size-cells = <1>;
  67. compatible = "fsl,mpc8315-fcm-nand",
  68. "fsl,elbc-fcm-nand";
  69. reg = <0x1 0x0 0x2000>;
  70. u-boot@0 {
  71. reg = <0x0 0x100000>;
  72. read-only;
  73. };
  74. kernel@100000 {
  75. reg = <0x100000 0x300000>;
  76. };
  77. fs@400000 {
  78. reg = <0x400000 0x1c00000>;
  79. };
  80. };
  81. };
  82. immr@e0000000 {
  83. #address-cells = <1>;
  84. #size-cells = <1>;
  85. device_type = "soc";
  86. compatible = "fsl,mpc8315-immr", "simple-bus";
  87. ranges = <0 0xe0000000 0x00100000>;
  88. reg = <0xe0000000 0x00000200>;
  89. bus-frequency = <0>;
  90. wdt@200 {
  91. device_type = "watchdog";
  92. compatible = "mpc83xx_wdt";
  93. reg = <0x200 0x100>;
  94. };
  95. i2c@3000 {
  96. #address-cells = <1>;
  97. #size-cells = <0>;
  98. cell-index = <0>;
  99. compatible = "fsl-i2c";
  100. reg = <0x3000 0x100>;
  101. interrupts = <14 0x8>;
  102. interrupt-parent = <&ipic>;
  103. dfsrr;
  104. rtc@68 {
  105. device_type = "rtc";
  106. compatible = "dallas,ds1339";
  107. reg = <0x68>;
  108. };
  109. };
  110. spi@7000 {
  111. cell-index = <0>;
  112. compatible = "fsl,spi";
  113. reg = <0x7000 0x1000>;
  114. interrupts = <16 0x8>;
  115. interrupt-parent = <&ipic>;
  116. mode = "cpu";
  117. };
  118. usb@23000 {
  119. compatible = "fsl-usb2-dr";
  120. reg = <0x23000 0x1000>;
  121. #address-cells = <1>;
  122. #size-cells = <0>;
  123. interrupt-parent = <&ipic>;
  124. interrupts = <38 0x8>;
  125. phy_type = "utmi";
  126. };
  127. mdio@24520 {
  128. #address-cells = <1>;
  129. #size-cells = <0>;
  130. compatible = "fsl,gianfar-mdio";
  131. reg = <0x24520 0x20>;
  132. phy0: ethernet-phy@0 {
  133. interrupt-parent = <&ipic>;
  134. interrupts = <20 0x8>;
  135. reg = <0x0>;
  136. device_type = "ethernet-phy";
  137. };
  138. phy1: ethernet-phy@1 {
  139. interrupt-parent = <&ipic>;
  140. interrupts = <19 0x8>;
  141. reg = <0x1>;
  142. device_type = "ethernet-phy";
  143. };
  144. };
  145. enet0: ethernet@24000 {
  146. cell-index = <0>;
  147. device_type = "network";
  148. model = "eTSEC";
  149. compatible = "gianfar";
  150. reg = <0x24000 0x1000>;
  151. local-mac-address = [ 00 00 00 00 00 00 ];
  152. interrupts = <32 0x8 33 0x8 34 0x8>;
  153. interrupt-parent = <&ipic>;
  154. phy-handle = < &phy0 >;
  155. };
  156. enet1: ethernet@25000 {
  157. cell-index = <1>;
  158. device_type = "network";
  159. model = "eTSEC";
  160. compatible = "gianfar";
  161. reg = <0x25000 0x1000>;
  162. local-mac-address = [ 00 00 00 00 00 00 ];
  163. interrupts = <35 0x8 36 0x8 37 0x8>;
  164. interrupt-parent = <&ipic>;
  165. phy-handle = < &phy1 >;
  166. };
  167. serial0: serial@4500 {
  168. cell-index = <0>;
  169. device_type = "serial";
  170. compatible = "ns16550";
  171. reg = <0x4500 0x100>;
  172. clock-frequency = <0>;
  173. interrupts = <9 0x8>;
  174. interrupt-parent = <&ipic>;
  175. };
  176. serial1: serial@4600 {
  177. cell-index = <1>;
  178. device_type = "serial";
  179. compatible = "ns16550";
  180. reg = <0x4600 0x100>;
  181. clock-frequency = <0>;
  182. interrupts = <10 0x8>;
  183. interrupt-parent = <&ipic>;
  184. };
  185. crypto@30000 {
  186. model = "SEC3";
  187. device_type = "crypto";
  188. compatible = "talitos";
  189. reg = <0x30000 0x10000>;
  190. interrupts = <11 0x8>;
  191. interrupt-parent = <&ipic>;
  192. /* Rev. 3.0 geometry */
  193. num-channels = <4>;
  194. channel-fifo-len = <24>;
  195. exec-units-mask = <0x000001fe>;
  196. descriptor-types-mask = <0x03ab0ebf>;
  197. };
  198. sata@18000 {
  199. compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
  200. reg = <0x18000 0x1000>;
  201. cell-index = <1>;
  202. interrupts = <44 0x8>;
  203. interrupt-parent = <&ipic>;
  204. };
  205. sata@19000 {
  206. compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
  207. reg = <0x19000 0x1000>;
  208. cell-index = <2>;
  209. interrupts = <45 0x8>;
  210. interrupt-parent = <&ipic>;
  211. };
  212. /* IPIC
  213. * interrupts cell = <intr #, sense>
  214. * sense values match linux IORESOURCE_IRQ_* defines:
  215. * sense == 8: Level, low assertion
  216. * sense == 2: Edge, high-to-low change
  217. */
  218. ipic: interrupt-controller@700 {
  219. interrupt-controller;
  220. #address-cells = <0>;
  221. #interrupt-cells = <2>;
  222. reg = <0x700 0x100>;
  223. device_type = "ipic";
  224. };
  225. };
  226. pci0: pci@e0008500 {
  227. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  228. interrupt-map = <
  229. /* IDSEL 0x0E -mini PCI */
  230. 0x7000 0x0 0x0 0x1 &ipic 18 0x8
  231. 0x7000 0x0 0x0 0x2 &ipic 18 0x8
  232. 0x7000 0x0 0x0 0x3 &ipic 18 0x8
  233. 0x7000 0x0 0x0 0x4 &ipic 18 0x8
  234. /* IDSEL 0x0F -mini PCI */
  235. 0x7800 0x0 0x0 0x1 &ipic 17 0x8
  236. 0x7800 0x0 0x0 0x2 &ipic 17 0x8
  237. 0x7800 0x0 0x0 0x3 &ipic 17 0x8
  238. 0x7800 0x0 0x0 0x4 &ipic 17 0x8
  239. /* IDSEL 0x10 - PCI slot */
  240. 0x8000 0x0 0x0 0x1 &ipic 48 0x8
  241. 0x8000 0x0 0x0 0x2 &ipic 17 0x8
  242. 0x8000 0x0 0x0 0x3 &ipic 48 0x8
  243. 0x8000 0x0 0x0 0x4 &ipic 17 0x8>;
  244. interrupt-parent = <&ipic>;
  245. interrupts = <66 0x8>;
  246. bus-range = <0x0 0x0>;
  247. ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
  248. 0x42000000 0 0x80000000 0x80000000 0 0x10000000
  249. 0x01000000 0 0x00000000 0xe0300000 0 0x00100000>;
  250. clock-frequency = <66666666>;
  251. #interrupt-cells = <1>;
  252. #size-cells = <2>;
  253. #address-cells = <3>;
  254. reg = <0xe0008500 0x100>;
  255. compatible = "fsl,mpc8349-pci";
  256. device_type = "pci";
  257. };
  258. };