kilauea.dts 8.9 KB

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  1. /*
  2. * Device Tree Source for AMCC Kilauea (405EX)
  3. *
  4. * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
  5. *
  6. * This file is licensed under the terms of the GNU General Public
  7. * License version 2. This program is licensed "as is" without
  8. * any warranty of any kind, whether express or implied.
  9. */
  10. / {
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. model = "amcc,kilauea";
  14. compatible = "amcc,kilauea";
  15. dcr-parent = <&/cpus/cpu@0>;
  16. aliases {
  17. ethernet0 = &EMAC0;
  18. ethernet1 = &EMAC1;
  19. serial0 = &UART0;
  20. serial1 = &UART1;
  21. };
  22. cpus {
  23. #address-cells = <1>;
  24. #size-cells = <0>;
  25. cpu@0 {
  26. device_type = "cpu";
  27. model = "PowerPC,405EX";
  28. reg = <0>;
  29. clock-frequency = <0>; /* Filled in by U-Boot */
  30. timebase-frequency = <0>; /* Filled in by U-Boot */
  31. i-cache-line-size = <20>;
  32. d-cache-line-size = <20>;
  33. i-cache-size = <4000>; /* 16 kB */
  34. d-cache-size = <4000>; /* 16 kB */
  35. dcr-controller;
  36. dcr-access-method = "native";
  37. };
  38. };
  39. memory {
  40. device_type = "memory";
  41. reg = <0 0>; /* Filled in by U-Boot */
  42. };
  43. UIC0: interrupt-controller {
  44. compatible = "ibm,uic-405ex", "ibm,uic";
  45. interrupt-controller;
  46. cell-index = <0>;
  47. dcr-reg = <0c0 009>;
  48. #address-cells = <0>;
  49. #size-cells = <0>;
  50. #interrupt-cells = <2>;
  51. };
  52. UIC1: interrupt-controller1 {
  53. compatible = "ibm,uic-405ex","ibm,uic";
  54. interrupt-controller;
  55. cell-index = <1>;
  56. dcr-reg = <0d0 009>;
  57. #address-cells = <0>;
  58. #size-cells = <0>;
  59. #interrupt-cells = <2>;
  60. interrupts = <1e 4 1f 4>; /* cascade */
  61. interrupt-parent = <&UIC0>;
  62. };
  63. UIC2: interrupt-controller2 {
  64. compatible = "ibm,uic-405ex","ibm,uic";
  65. interrupt-controller;
  66. cell-index = <2>;
  67. dcr-reg = <0e0 009>;
  68. #address-cells = <0>;
  69. #size-cells = <0>;
  70. #interrupt-cells = <2>;
  71. interrupts = <1c 4 1d 4>; /* cascade */
  72. interrupt-parent = <&UIC0>;
  73. };
  74. plb {
  75. compatible = "ibm,plb-405ex", "ibm,plb4";
  76. #address-cells = <1>;
  77. #size-cells = <1>;
  78. ranges;
  79. clock-frequency = <0>; /* Filled in by U-Boot */
  80. SDRAM0: memory-controller {
  81. compatible = "ibm,sdram-405ex";
  82. dcr-reg = <010 2>;
  83. };
  84. MAL0: mcmal {
  85. compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
  86. dcr-reg = <180 62>;
  87. num-tx-chans = <2>;
  88. num-rx-chans = <2>;
  89. interrupt-parent = <&MAL0>;
  90. interrupts = <0 1 2 3 4>;
  91. #interrupt-cells = <1>;
  92. #address-cells = <0>;
  93. #size-cells = <0>;
  94. interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
  95. /*RXEOB*/ 1 &UIC0 b 4
  96. /*SERR*/ 2 &UIC1 0 4
  97. /*TXDE*/ 3 &UIC1 1 4
  98. /*RXDE*/ 4 &UIC1 2 4>;
  99. interrupt-map-mask = <ffffffff>;
  100. };
  101. POB0: opb {
  102. compatible = "ibm,opb-405ex", "ibm,opb";
  103. #address-cells = <1>;
  104. #size-cells = <1>;
  105. ranges = <80000000 80000000 10000000
  106. ef600000 ef600000 a00000
  107. f0000000 f0000000 10000000>;
  108. dcr-reg = <0a0 5>;
  109. clock-frequency = <0>; /* Filled in by U-Boot */
  110. EBC0: ebc {
  111. compatible = "ibm,ebc-405ex", "ibm,ebc";
  112. dcr-reg = <012 2>;
  113. #address-cells = <2>;
  114. #size-cells = <1>;
  115. clock-frequency = <0>; /* Filled in by U-Boot */
  116. /* ranges property is supplied by U-Boot */
  117. interrupts = <5 1>;
  118. interrupt-parent = <&UIC1>;
  119. nor_flash@0,0 {
  120. compatible = "amd,s29gl512n", "cfi-flash";
  121. bank-width = <2>;
  122. reg = <0 000000 4000000>;
  123. #address-cells = <1>;
  124. #size-cells = <1>;
  125. partition@0 {
  126. label = "kernel";
  127. reg = <0 200000>;
  128. };
  129. partition@200000 {
  130. label = "root";
  131. reg = <200000 200000>;
  132. };
  133. partition@400000 {
  134. label = "user";
  135. reg = <400000 3b60000>;
  136. };
  137. partition@3f60000 {
  138. label = "env";
  139. reg = <3f60000 40000>;
  140. };
  141. partition@3fa0000 {
  142. label = "u-boot";
  143. reg = <3fa0000 60000>;
  144. };
  145. };
  146. };
  147. UART0: serial@ef600200 {
  148. device_type = "serial";
  149. compatible = "ns16550";
  150. reg = <ef600200 8>;
  151. virtual-reg = <ef600200>;
  152. clock-frequency = <0>; /* Filled in by U-Boot */
  153. current-speed = <0>;
  154. interrupt-parent = <&UIC0>;
  155. interrupts = <1a 4>;
  156. };
  157. UART1: serial@ef600300 {
  158. device_type = "serial";
  159. compatible = "ns16550";
  160. reg = <ef600300 8>;
  161. virtual-reg = <ef600300>;
  162. clock-frequency = <0>; /* Filled in by U-Boot */
  163. current-speed = <0>;
  164. interrupt-parent = <&UIC0>;
  165. interrupts = <1 4>;
  166. };
  167. IIC0: i2c@ef600400 {
  168. compatible = "ibm,iic-405ex", "ibm,iic";
  169. reg = <ef600400 14>;
  170. interrupt-parent = <&UIC0>;
  171. interrupts = <2 4>;
  172. };
  173. IIC1: i2c@ef600500 {
  174. compatible = "ibm,iic-405ex", "ibm,iic";
  175. reg = <ef600500 14>;
  176. interrupt-parent = <&UIC0>;
  177. interrupts = <7 4>;
  178. };
  179. RGMII0: emac-rgmii@ef600b00 {
  180. compatible = "ibm,rgmii-405ex", "ibm,rgmii";
  181. reg = <ef600b00 104>;
  182. has-mdio;
  183. };
  184. EMAC0: ethernet@ef600900 {
  185. linux,network-index = <0>;
  186. device_type = "network";
  187. compatible = "ibm,emac-405ex", "ibm,emac4";
  188. interrupt-parent = <&EMAC0>;
  189. interrupts = <0 1>;
  190. #interrupt-cells = <1>;
  191. #address-cells = <0>;
  192. #size-cells = <0>;
  193. interrupt-map = </*Status*/ 0 &UIC0 18 4
  194. /*Wake*/ 1 &UIC1 1d 4>;
  195. reg = <ef600900 70>;
  196. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  197. mal-device = <&MAL0>;
  198. mal-tx-channel = <0>;
  199. mal-rx-channel = <0>;
  200. cell-index = <0>;
  201. max-frame-size = <2328>;
  202. rx-fifo-size = <1000>;
  203. tx-fifo-size = <800>;
  204. phy-mode = "rgmii";
  205. phy-map = <00000000>;
  206. rgmii-device = <&RGMII0>;
  207. rgmii-channel = <0>;
  208. has-inverted-stacr-oc;
  209. has-new-stacr-staopc;
  210. };
  211. EMAC1: ethernet@ef600a00 {
  212. linux,network-index = <1>;
  213. device_type = "network";
  214. compatible = "ibm,emac-405ex", "ibm,emac4";
  215. interrupt-parent = <&EMAC1>;
  216. interrupts = <0 1>;
  217. #interrupt-cells = <1>;
  218. #address-cells = <0>;
  219. #size-cells = <0>;
  220. interrupt-map = </*Status*/ 0 &UIC0 19 4
  221. /*Wake*/ 1 &UIC1 1f 4>;
  222. reg = <ef600a00 70>;
  223. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  224. mal-device = <&MAL0>;
  225. mal-tx-channel = <1>;
  226. mal-rx-channel = <1>;
  227. cell-index = <1>;
  228. max-frame-size = <2328>;
  229. rx-fifo-size = <1000>;
  230. tx-fifo-size = <800>;
  231. phy-mode = "rgmii";
  232. phy-map = <00000000>;
  233. rgmii-device = <&RGMII0>;
  234. rgmii-channel = <1>;
  235. has-inverted-stacr-oc;
  236. has-new-stacr-staopc;
  237. };
  238. };
  239. PCIE0: pciex@0a0000000 {
  240. device_type = "pci";
  241. #interrupt-cells = <1>;
  242. #size-cells = <2>;
  243. #address-cells = <3>;
  244. compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
  245. primary;
  246. port = <0>; /* port number */
  247. reg = <a0000000 20000000 /* Config space access */
  248. ef000000 00001000>; /* Registers */
  249. dcr-reg = <040 020>;
  250. sdr-base = <400>;
  251. /* Outbound ranges, one memory and one IO,
  252. * later cannot be changed
  253. */
  254. ranges = <02000000 0 80000000 90000000 0 08000000
  255. 01000000 0 00000000 e0000000 0 00010000>;
  256. /* Inbound 2GB range starting at 0 */
  257. dma-ranges = <42000000 0 0 0 0 80000000>;
  258. /* This drives busses 0x00 to 0x3f */
  259. bus-range = <00 3f>;
  260. /* Legacy interrupts (note the weird polarity, the bridge seems
  261. * to invert PCIe legacy interrupts).
  262. * We are de-swizzling here because the numbers are actually for
  263. * port of the root complex virtual P2P bridge. But I want
  264. * to avoid putting a node for it in the tree, so the numbers
  265. * below are basically de-swizzled numbers.
  266. * The real slot is on idsel 0, so the swizzling is 1:1
  267. */
  268. interrupt-map-mask = <0000 0 0 7>;
  269. interrupt-map = <
  270. 0000 0 0 1 &UIC2 0 4 /* swizzled int A */
  271. 0000 0 0 2 &UIC2 1 4 /* swizzled int B */
  272. 0000 0 0 3 &UIC2 2 4 /* swizzled int C */
  273. 0000 0 0 4 &UIC2 3 4 /* swizzled int D */>;
  274. };
  275. PCIE1: pciex@0c0000000 {
  276. device_type = "pci";
  277. #interrupt-cells = <1>;
  278. #size-cells = <2>;
  279. #address-cells = <3>;
  280. compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
  281. primary;
  282. port = <1>; /* port number */
  283. reg = <c0000000 20000000 /* Config space access */
  284. ef001000 00001000>; /* Registers */
  285. dcr-reg = <060 020>;
  286. sdr-base = <440>;
  287. /* Outbound ranges, one memory and one IO,
  288. * later cannot be changed
  289. */
  290. ranges = <02000000 0 80000000 98000000 0 08000000
  291. 01000000 0 00000000 e0010000 0 00010000>;
  292. /* Inbound 2GB range starting at 0 */
  293. dma-ranges = <42000000 0 0 0 0 80000000>;
  294. /* This drives busses 0x40 to 0x7f */
  295. bus-range = <40 7f>;
  296. /* Legacy interrupts (note the weird polarity, the bridge seems
  297. * to invert PCIe legacy interrupts).
  298. * We are de-swizzling here because the numbers are actually for
  299. * port of the root complex virtual P2P bridge. But I want
  300. * to avoid putting a node for it in the tree, so the numbers
  301. * below are basically de-swizzled numbers.
  302. * The real slot is on idsel 0, so the swizzling is 1:1
  303. */
  304. interrupt-map-mask = <0000 0 0 7>;
  305. interrupt-map = <
  306. 0000 0 0 1 &UIC2 b 4 /* swizzled int A */
  307. 0000 0 0 2 &UIC2 c 4 /* swizzled int B */
  308. 0000 0 0 3 &UIC2 d 4 /* swizzled int C */
  309. 0000 0 0 4 &UIC2 e 4 /* swizzled int D */>;
  310. };
  311. };
  312. };