katmai.dts 11 KB

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  1. /*
  2. * Device Tree Source for AMCC Katmai eval board
  3. *
  4. * Copyright (c) 2006, 2007 IBM Corp.
  5. * Benjamin Herrenschmidt <benh@kernel.crashing.org>
  6. *
  7. * Copyright (c) 2006, 2007 IBM Corp.
  8. * Josh Boyer <jwboyer@linux.vnet.ibm.com>
  9. *
  10. * This file is licensed under the terms of the GNU General Public
  11. * License version 2. This program is licensed "as is" without
  12. * any warranty of any kind, whether express or implied.
  13. */
  14. / {
  15. #address-cells = <2>;
  16. #size-cells = <1>;
  17. model = "amcc,katmai";
  18. compatible = "amcc,katmai";
  19. dcr-parent = <&/cpus/cpu@0>;
  20. aliases {
  21. ethernet0 = &EMAC0;
  22. serial0 = &UART0;
  23. serial1 = &UART1;
  24. serial2 = &UART2;
  25. };
  26. cpus {
  27. #address-cells = <1>;
  28. #size-cells = <0>;
  29. cpu@0 {
  30. device_type = "cpu";
  31. model = "PowerPC,440SPe";
  32. reg = <0>;
  33. clock-frequency = <0>; /* Filled in by zImage */
  34. timebase-frequency = <0>; /* Filled in by zImage */
  35. i-cache-line-size = <20>;
  36. d-cache-line-size = <20>;
  37. i-cache-size = <8000>;
  38. d-cache-size = <8000>;
  39. dcr-controller;
  40. dcr-access-method = "native";
  41. };
  42. };
  43. memory {
  44. device_type = "memory";
  45. reg = <0 0 0>; /* Filled in by zImage */
  46. };
  47. UIC0: interrupt-controller0 {
  48. compatible = "ibm,uic-440spe","ibm,uic";
  49. interrupt-controller;
  50. cell-index = <0>;
  51. dcr-reg = <0c0 009>;
  52. #address-cells = <0>;
  53. #size-cells = <0>;
  54. #interrupt-cells = <2>;
  55. };
  56. UIC1: interrupt-controller1 {
  57. compatible = "ibm,uic-440spe","ibm,uic";
  58. interrupt-controller;
  59. cell-index = <1>;
  60. dcr-reg = <0d0 009>;
  61. #address-cells = <0>;
  62. #size-cells = <0>;
  63. #interrupt-cells = <2>;
  64. interrupts = <1e 4 1f 4>; /* cascade */
  65. interrupt-parent = <&UIC0>;
  66. };
  67. UIC2: interrupt-controller2 {
  68. compatible = "ibm,uic-440spe","ibm,uic";
  69. interrupt-controller;
  70. cell-index = <2>;
  71. dcr-reg = <0e0 009>;
  72. #address-cells = <0>;
  73. #size-cells = <0>;
  74. #interrupt-cells = <2>;
  75. interrupts = <a 4 b 4>; /* cascade */
  76. interrupt-parent = <&UIC0>;
  77. };
  78. UIC3: interrupt-controller3 {
  79. compatible = "ibm,uic-440spe","ibm,uic";
  80. interrupt-controller;
  81. cell-index = <3>;
  82. dcr-reg = <0f0 009>;
  83. #address-cells = <0>;
  84. #size-cells = <0>;
  85. #interrupt-cells = <2>;
  86. interrupts = <10 4 11 4>; /* cascade */
  87. interrupt-parent = <&UIC0>;
  88. };
  89. SDR0: sdr {
  90. compatible = "ibm,sdr-440spe";
  91. dcr-reg = <00e 002>;
  92. };
  93. CPR0: cpr {
  94. compatible = "ibm,cpr-440spe";
  95. dcr-reg = <00c 002>;
  96. };
  97. plb {
  98. compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
  99. #address-cells = <2>;
  100. #size-cells = <1>;
  101. ranges;
  102. clock-frequency = <0>; /* Filled in by zImage */
  103. SDRAM0: sdram {
  104. compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
  105. dcr-reg = <010 2>;
  106. };
  107. MAL0: mcmal {
  108. compatible = "ibm,mcmal-440spe", "ibm,mcmal2";
  109. dcr-reg = <180 62>;
  110. num-tx-chans = <2>;
  111. num-rx-chans = <1>;
  112. interrupt-parent = <&MAL0>;
  113. interrupts = <0 1 2 3 4>;
  114. #interrupt-cells = <1>;
  115. #address-cells = <0>;
  116. #size-cells = <0>;
  117. interrupt-map = </*TXEOB*/ 0 &UIC1 6 4
  118. /*RXEOB*/ 1 &UIC1 7 4
  119. /*SERR*/ 2 &UIC1 1 4
  120. /*TXDE*/ 3 &UIC1 2 4
  121. /*RXDE*/ 4 &UIC1 3 4>;
  122. };
  123. POB0: opb {
  124. compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
  125. #address-cells = <1>;
  126. #size-cells = <1>;
  127. ranges = <00000000 4 e0000000 20000000>;
  128. clock-frequency = <0>; /* Filled in by zImage */
  129. EBC0: ebc {
  130. compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc";
  131. dcr-reg = <012 2>;
  132. #address-cells = <2>;
  133. #size-cells = <1>;
  134. clock-frequency = <0>; /* Filled in by zImage */
  135. interrupts = <5 1>;
  136. interrupt-parent = <&UIC1>;
  137. };
  138. UART0: serial@10000200 {
  139. device_type = "serial";
  140. compatible = "ns16550";
  141. reg = <10000200 8>;
  142. virtual-reg = <a0000200>;
  143. clock-frequency = <0>; /* Filled in by zImage */
  144. current-speed = <1c200>;
  145. interrupt-parent = <&UIC0>;
  146. interrupts = <0 4>;
  147. };
  148. UART1: serial@10000300 {
  149. device_type = "serial";
  150. compatible = "ns16550";
  151. reg = <10000300 8>;
  152. virtual-reg = <a0000300>;
  153. clock-frequency = <0>;
  154. current-speed = <0>;
  155. interrupt-parent = <&UIC0>;
  156. interrupts = <1 4>;
  157. };
  158. UART2: serial@10000600 {
  159. device_type = "serial";
  160. compatible = "ns16550";
  161. reg = <10000600 8>;
  162. virtual-reg = <a0000600>;
  163. clock-frequency = <0>;
  164. current-speed = <0>;
  165. interrupt-parent = <&UIC1>;
  166. interrupts = <5 4>;
  167. };
  168. IIC0: i2c@10000400 {
  169. compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
  170. reg = <10000400 14>;
  171. interrupt-parent = <&UIC0>;
  172. interrupts = <2 4>;
  173. };
  174. IIC1: i2c@10000500 {
  175. compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
  176. reg = <10000500 14>;
  177. interrupt-parent = <&UIC0>;
  178. interrupts = <3 4>;
  179. };
  180. EMAC0: ethernet@10000800 {
  181. linux,network-index = <0>;
  182. device_type = "network";
  183. compatible = "ibm,emac-440spe", "ibm,emac4";
  184. interrupt-parent = <&UIC1>;
  185. interrupts = <1c 4 1d 4>;
  186. reg = <10000800 70>;
  187. local-mac-address = [000000000000];
  188. mal-device = <&MAL0>;
  189. mal-tx-channel = <0>;
  190. mal-rx-channel = <0>;
  191. cell-index = <0>;
  192. max-frame-size = <2328>;
  193. rx-fifo-size = <1000>;
  194. tx-fifo-size = <800>;
  195. phy-mode = "gmii";
  196. phy-map = <00000000>;
  197. has-inverted-stacr-oc;
  198. has-new-stacr-staopc;
  199. };
  200. };
  201. PCIX0: pci@c0ec00000 {
  202. device_type = "pci";
  203. #interrupt-cells = <1>;
  204. #size-cells = <2>;
  205. #address-cells = <3>;
  206. compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix";
  207. primary;
  208. large-inbound-windows;
  209. enable-msi-hole;
  210. reg = <c 0ec00000 8 /* Config space access */
  211. 0 0 0 /* no IACK cycles */
  212. c 0ed00000 4 /* Special cycles */
  213. c 0ec80000 100 /* Internal registers */
  214. c 0ec80100 fc>; /* Internal messaging registers */
  215. /* Outbound ranges, one memory and one IO,
  216. * later cannot be changed
  217. */
  218. ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
  219. 01000000 0 00000000 0000000c 08000000 0 00010000>;
  220. /* Inbound 2GB range starting at 0 */
  221. dma-ranges = <42000000 0 0 0 0 0 80000000>;
  222. /* This drives busses 0 to 0xf */
  223. bus-range = <0 f>;
  224. /*
  225. * On Katmai, the following PCI-X interrupts signals
  226. * have to be enabled via jumpers (only INTA is
  227. * enabled per default):
  228. *
  229. * INTB: J3: 1-2
  230. * INTC: J2: 1-2
  231. * INTD: J1: 1-2
  232. */
  233. interrupt-map-mask = <f800 0 0 7>;
  234. interrupt-map = <
  235. /* IDSEL 1 */
  236. 0800 0 0 1 &UIC1 14 8
  237. 0800 0 0 2 &UIC1 13 8
  238. 0800 0 0 3 &UIC1 12 8
  239. 0800 0 0 4 &UIC1 11 8
  240. >;
  241. };
  242. PCIE0: pciex@d00000000 {
  243. device_type = "pci";
  244. #interrupt-cells = <1>;
  245. #size-cells = <2>;
  246. #address-cells = <3>;
  247. compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
  248. primary;
  249. port = <0>; /* port number */
  250. reg = <d 00000000 20000000 /* Config space access */
  251. c 10000000 00001000>; /* Registers */
  252. dcr-reg = <100 020>;
  253. sdr-base = <300>;
  254. /* Outbound ranges, one memory and one IO,
  255. * later cannot be changed
  256. */
  257. ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
  258. 01000000 0 00000000 0000000f 80000000 0 00010000>;
  259. /* Inbound 2GB range starting at 0 */
  260. dma-ranges = <42000000 0 0 0 0 0 80000000>;
  261. /* This drives busses 10 to 0x1f */
  262. bus-range = <10 1f>;
  263. /* Legacy interrupts (note the weird polarity, the bridge seems
  264. * to invert PCIe legacy interrupts).
  265. * We are de-swizzling here because the numbers are actually for
  266. * port of the root complex virtual P2P bridge. But I want
  267. * to avoid putting a node for it in the tree, so the numbers
  268. * below are basically de-swizzled numbers.
  269. * The real slot is on idsel 0, so the swizzling is 1:1
  270. */
  271. interrupt-map-mask = <0000 0 0 7>;
  272. interrupt-map = <
  273. 0000 0 0 1 &UIC3 0 4 /* swizzled int A */
  274. 0000 0 0 2 &UIC3 1 4 /* swizzled int B */
  275. 0000 0 0 3 &UIC3 2 4 /* swizzled int C */
  276. 0000 0 0 4 &UIC3 3 4 /* swizzled int D */>;
  277. };
  278. PCIE1: pciex@d20000000 {
  279. device_type = "pci";
  280. #interrupt-cells = <1>;
  281. #size-cells = <2>;
  282. #address-cells = <3>;
  283. compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
  284. primary;
  285. port = <1>; /* port number */
  286. reg = <d 20000000 20000000 /* Config space access */
  287. c 10001000 00001000>; /* Registers */
  288. dcr-reg = <120 020>;
  289. sdr-base = <340>;
  290. /* Outbound ranges, one memory and one IO,
  291. * later cannot be changed
  292. */
  293. ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
  294. 01000000 0 00000000 0000000f 80010000 0 00010000>;
  295. /* Inbound 2GB range starting at 0 */
  296. dma-ranges = <42000000 0 0 0 0 0 80000000>;
  297. /* This drives busses 10 to 0x1f */
  298. bus-range = <20 2f>;
  299. /* Legacy interrupts (note the weird polarity, the bridge seems
  300. * to invert PCIe legacy interrupts).
  301. * We are de-swizzling here because the numbers are actually for
  302. * port of the root complex virtual P2P bridge. But I want
  303. * to avoid putting a node for it in the tree, so the numbers
  304. * below are basically de-swizzled numbers.
  305. * The real slot is on idsel 0, so the swizzling is 1:1
  306. */
  307. interrupt-map-mask = <0000 0 0 7>;
  308. interrupt-map = <
  309. 0000 0 0 1 &UIC3 4 4 /* swizzled int A */
  310. 0000 0 0 2 &UIC3 5 4 /* swizzled int B */
  311. 0000 0 0 3 &UIC3 6 4 /* swizzled int C */
  312. 0000 0 0 4 &UIC3 7 4 /* swizzled int D */>;
  313. };
  314. PCIE2: pciex@d40000000 {
  315. device_type = "pci";
  316. #interrupt-cells = <1>;
  317. #size-cells = <2>;
  318. #address-cells = <3>;
  319. compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
  320. primary;
  321. port = <2>; /* port number */
  322. reg = <d 40000000 20000000 /* Config space access */
  323. c 10002000 00001000>; /* Registers */
  324. dcr-reg = <140 020>;
  325. sdr-base = <370>;
  326. /* Outbound ranges, one memory and one IO,
  327. * later cannot be changed
  328. */
  329. ranges = <02000000 0 80000000 0000000f 00000000 0 80000000
  330. 01000000 0 00000000 0000000f 80020000 0 00010000>;
  331. /* Inbound 2GB range starting at 0 */
  332. dma-ranges = <42000000 0 0 0 0 0 80000000>;
  333. /* This drives busses 10 to 0x1f */
  334. bus-range = <30 3f>;
  335. /* Legacy interrupts (note the weird polarity, the bridge seems
  336. * to invert PCIe legacy interrupts).
  337. * We are de-swizzling here because the numbers are actually for
  338. * port of the root complex virtual P2P bridge. But I want
  339. * to avoid putting a node for it in the tree, so the numbers
  340. * below are basically de-swizzled numbers.
  341. * The real slot is on idsel 0, so the swizzling is 1:1
  342. */
  343. interrupt-map-mask = <0000 0 0 7>;
  344. interrupt-map = <
  345. 0000 0 0 1 &UIC3 8 4 /* swizzled int A */
  346. 0000 0 0 2 &UIC3 9 4 /* swizzled int B */
  347. 0000 0 0 3 &UIC3 a 4 /* swizzled int C */
  348. 0000 0 0 4 &UIC3 b 4 /* swizzled int D */>;
  349. };
  350. };
  351. chosen {
  352. linux,stdout-path = "/plb/opb/serial@10000200";
  353. };
  354. };