glacier.dts 13 KB

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  1. /*
  2. * Device Tree Source for AMCC Glacier (460GT)
  3. *
  4. * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
  5. *
  6. * This file is licensed under the terms of the GNU General Public
  7. * License version 2. This program is licensed "as is" without
  8. * any warranty of any kind, whether express or implied.
  9. */
  10. / {
  11. #address-cells = <2>;
  12. #size-cells = <1>;
  13. model = "amcc,glacier";
  14. compatible = "amcc,glacier", "amcc,canyonlands";
  15. dcr-parent = <&/cpus/cpu@0>;
  16. aliases {
  17. ethernet0 = &EMAC0;
  18. ethernet1 = &EMAC1;
  19. ethernet2 = &EMAC2;
  20. ethernet3 = &EMAC3;
  21. serial0 = &UART0;
  22. serial1 = &UART1;
  23. };
  24. cpus {
  25. #address-cells = <1>;
  26. #size-cells = <0>;
  27. cpu@0 {
  28. device_type = "cpu";
  29. model = "PowerPC,460GT";
  30. reg = <0>;
  31. clock-frequency = <0>; /* Filled in by U-Boot */
  32. timebase-frequency = <0>; /* Filled in by U-Boot */
  33. i-cache-line-size = <20>;
  34. d-cache-line-size = <20>;
  35. i-cache-size = <8000>;
  36. d-cache-size = <8000>;
  37. dcr-controller;
  38. dcr-access-method = "native";
  39. };
  40. };
  41. memory {
  42. device_type = "memory";
  43. reg = <0 0 0>; /* Filled in by U-Boot */
  44. };
  45. UIC0: interrupt-controller0 {
  46. compatible = "ibm,uic-460gt","ibm,uic";
  47. interrupt-controller;
  48. cell-index = <0>;
  49. dcr-reg = <0c0 009>;
  50. #address-cells = <0>;
  51. #size-cells = <0>;
  52. #interrupt-cells = <2>;
  53. };
  54. UIC1: interrupt-controller1 {
  55. compatible = "ibm,uic-460gt","ibm,uic";
  56. interrupt-controller;
  57. cell-index = <1>;
  58. dcr-reg = <0d0 009>;
  59. #address-cells = <0>;
  60. #size-cells = <0>;
  61. #interrupt-cells = <2>;
  62. interrupts = <1e 4 1f 4>; /* cascade */
  63. interrupt-parent = <&UIC0>;
  64. };
  65. UIC2: interrupt-controller2 {
  66. compatible = "ibm,uic-460gt","ibm,uic";
  67. interrupt-controller;
  68. cell-index = <2>;
  69. dcr-reg = <0e0 009>;
  70. #address-cells = <0>;
  71. #size-cells = <0>;
  72. #interrupt-cells = <2>;
  73. interrupts = <a 4 b 4>; /* cascade */
  74. interrupt-parent = <&UIC0>;
  75. };
  76. UIC3: interrupt-controller3 {
  77. compatible = "ibm,uic-460gt","ibm,uic";
  78. interrupt-controller;
  79. cell-index = <3>;
  80. dcr-reg = <0f0 009>;
  81. #address-cells = <0>;
  82. #size-cells = <0>;
  83. #interrupt-cells = <2>;
  84. interrupts = <10 4 11 4>; /* cascade */
  85. interrupt-parent = <&UIC0>;
  86. };
  87. SDR0: sdr {
  88. compatible = "ibm,sdr-460gt";
  89. dcr-reg = <00e 002>;
  90. };
  91. CPR0: cpr {
  92. compatible = "ibm,cpr-460gt";
  93. dcr-reg = <00c 002>;
  94. };
  95. plb {
  96. compatible = "ibm,plb-460gt", "ibm,plb4";
  97. #address-cells = <2>;
  98. #size-cells = <1>;
  99. ranges;
  100. clock-frequency = <0>; /* Filled in by U-Boot */
  101. SDRAM0: sdram {
  102. compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
  103. dcr-reg = <010 2>;
  104. };
  105. MAL0: mcmal {
  106. compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
  107. dcr-reg = <180 62>;
  108. num-tx-chans = <4>;
  109. num-rx-chans = <20>;
  110. #address-cells = <0>;
  111. #size-cells = <0>;
  112. interrupt-parent = <&UIC2>;
  113. interrupts = < /*TXEOB*/ 6 4
  114. /*RXEOB*/ 7 4
  115. /*SERR*/ 3 4
  116. /*TXDE*/ 4 4
  117. /*RXDE*/ 5 4>;
  118. desc-base-addr-high = <8>;
  119. };
  120. POB0: opb {
  121. compatible = "ibm,opb-460gt", "ibm,opb";
  122. #address-cells = <1>;
  123. #size-cells = <1>;
  124. ranges = <b0000000 4 b0000000 50000000>;
  125. clock-frequency = <0>; /* Filled in by U-Boot */
  126. EBC0: ebc {
  127. compatible = "ibm,ebc-460gt", "ibm,ebc";
  128. dcr-reg = <012 2>;
  129. #address-cells = <2>;
  130. #size-cells = <1>;
  131. clock-frequency = <0>; /* Filled in by U-Boot */
  132. /* ranges property is supplied by U-Boot */
  133. interrupts = <6 4>;
  134. interrupt-parent = <&UIC1>;
  135. nor_flash@0,0 {
  136. compatible = "amd,s29gl512n", "cfi-flash";
  137. bank-width = <2>;
  138. reg = <0 000000 4000000>;
  139. #address-cells = <1>;
  140. #size-cells = <1>;
  141. partition@0 {
  142. label = "kernel";
  143. reg = <0 1e0000>;
  144. };
  145. partition@1e0000 {
  146. label = "dtb";
  147. reg = <1e0000 20000>;
  148. };
  149. partition@200000 {
  150. label = "ramdisk";
  151. reg = <200000 1400000>;
  152. };
  153. partition@1600000 {
  154. label = "jffs2";
  155. reg = <1600000 400000>;
  156. };
  157. partition@1a00000 {
  158. label = "user";
  159. reg = <1a00000 2560000>;
  160. };
  161. partition@3f60000 {
  162. label = "env";
  163. reg = <3f60000 40000>;
  164. };
  165. partition@3fa0000 {
  166. label = "u-boot";
  167. reg = <3fa0000 60000>;
  168. };
  169. };
  170. };
  171. UART0: serial@ef600300 {
  172. device_type = "serial";
  173. compatible = "ns16550";
  174. reg = <ef600300 8>;
  175. virtual-reg = <ef600300>;
  176. clock-frequency = <0>; /* Filled in by U-Boot */
  177. current-speed = <0>; /* Filled in by U-Boot */
  178. interrupt-parent = <&UIC1>;
  179. interrupts = <1 4>;
  180. };
  181. UART1: serial@ef600400 {
  182. device_type = "serial";
  183. compatible = "ns16550";
  184. reg = <ef600400 8>;
  185. virtual-reg = <ef600400>;
  186. clock-frequency = <0>; /* Filled in by U-Boot */
  187. current-speed = <0>; /* Filled in by U-Boot */
  188. interrupt-parent = <&UIC0>;
  189. interrupts = <1 4>;
  190. };
  191. UART2: serial@ef600500 {
  192. device_type = "serial";
  193. compatible = "ns16550";
  194. reg = <ef600500 8>;
  195. virtual-reg = <ef600500>;
  196. clock-frequency = <0>; /* Filled in by U-Boot */
  197. current-speed = <0>; /* Filled in by U-Boot */
  198. interrupt-parent = <&UIC1>;
  199. interrupts = <1d 4>;
  200. };
  201. UART3: serial@ef600600 {
  202. device_type = "serial";
  203. compatible = "ns16550";
  204. reg = <ef600600 8>;
  205. virtual-reg = <ef600600>;
  206. clock-frequency = <0>; /* Filled in by U-Boot */
  207. current-speed = <0>; /* Filled in by U-Boot */
  208. interrupt-parent = <&UIC1>;
  209. interrupts = <1e 4>;
  210. };
  211. IIC0: i2c@ef600700 {
  212. compatible = "ibm,iic-460gt", "ibm,iic";
  213. reg = <ef600700 14>;
  214. interrupt-parent = <&UIC0>;
  215. interrupts = <2 4>;
  216. };
  217. IIC1: i2c@ef600800 {
  218. compatible = "ibm,iic-460gt", "ibm,iic";
  219. reg = <ef600800 14>;
  220. interrupt-parent = <&UIC0>;
  221. interrupts = <3 4>;
  222. };
  223. ZMII0: emac-zmii@ef600d00 {
  224. compatible = "ibm,zmii-460gt", "ibm,zmii";
  225. reg = <ef600d00 c>;
  226. };
  227. RGMII0: emac-rgmii@ef601500 {
  228. compatible = "ibm,rgmii-460gt", "ibm,rgmii";
  229. reg = <ef601500 8>;
  230. has-mdio;
  231. };
  232. RGMII1: emac-rgmii@ef601600 {
  233. compatible = "ibm,rgmii-460gt", "ibm,rgmii";
  234. reg = <ef601600 8>;
  235. has-mdio;
  236. };
  237. TAH0: emac-tah@ef601350 {
  238. compatible = "ibm,tah-460gt", "ibm,tah";
  239. reg = <ef601350 30>;
  240. };
  241. TAH1: emac-tah@ef601450 {
  242. compatible = "ibm,tah-460gt", "ibm,tah";
  243. reg = <ef601450 30>;
  244. };
  245. EMAC0: ethernet@ef600e00 {
  246. device_type = "network";
  247. compatible = "ibm,emac-460gt", "ibm,emac4";
  248. interrupt-parent = <&EMAC0>;
  249. interrupts = <0 1>;
  250. #interrupt-cells = <1>;
  251. #address-cells = <0>;
  252. #size-cells = <0>;
  253. interrupt-map = </*Status*/ 0 &UIC2 10 4
  254. /*Wake*/ 1 &UIC2 14 4>;
  255. reg = <ef600e00 70>;
  256. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  257. mal-device = <&MAL0>;
  258. mal-tx-channel = <0>;
  259. mal-rx-channel = <0>;
  260. cell-index = <0>;
  261. max-frame-size = <2328>;
  262. rx-fifo-size = <1000>;
  263. tx-fifo-size = <800>;
  264. phy-mode = "rgmii";
  265. phy-map = <00000000>;
  266. rgmii-device = <&RGMII0>;
  267. rgmii-channel = <0>;
  268. tah-device = <&TAH0>;
  269. tah-channel = <0>;
  270. has-inverted-stacr-oc;
  271. has-new-stacr-staopc;
  272. };
  273. EMAC1: ethernet@ef600f00 {
  274. device_type = "network";
  275. compatible = "ibm,emac-460gt", "ibm,emac4";
  276. interrupt-parent = <&EMAC1>;
  277. interrupts = <0 1>;
  278. #interrupt-cells = <1>;
  279. #address-cells = <0>;
  280. #size-cells = <0>;
  281. interrupt-map = </*Status*/ 0 &UIC2 11 4
  282. /*Wake*/ 1 &UIC2 15 4>;
  283. reg = <ef600f00 70>;
  284. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  285. mal-device = <&MAL0>;
  286. mal-tx-channel = <1>;
  287. mal-rx-channel = <8>;
  288. cell-index = <1>;
  289. max-frame-size = <2328>;
  290. rx-fifo-size = <1000>;
  291. tx-fifo-size = <800>;
  292. phy-mode = "rgmii";
  293. phy-map = <00000000>;
  294. rgmii-device = <&RGMII0>;
  295. rgmii-channel = <1>;
  296. tah-device = <&TAH1>;
  297. tah-channel = <1>;
  298. has-inverted-stacr-oc;
  299. has-new-stacr-staopc;
  300. mdio-device = <&EMAC0>;
  301. };
  302. EMAC2: ethernet@ef601100 {
  303. device_type = "network";
  304. compatible = "ibm,emac-460gt", "ibm,emac4";
  305. interrupt-parent = <&EMAC2>;
  306. interrupts = <0 1>;
  307. #interrupt-cells = <1>;
  308. #address-cells = <0>;
  309. #size-cells = <0>;
  310. interrupt-map = </*Status*/ 0 &UIC2 12 4
  311. /*Wake*/ 1 &UIC2 16 4>;
  312. reg = <ef601100 70>;
  313. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  314. mal-device = <&MAL0>;
  315. mal-tx-channel = <2>;
  316. mal-rx-channel = <10>;
  317. cell-index = <2>;
  318. max-frame-size = <2328>;
  319. rx-fifo-size = <1000>;
  320. tx-fifo-size = <800>;
  321. phy-mode = "rgmii";
  322. phy-map = <00000000>;
  323. rgmii-device = <&RGMII1>;
  324. rgmii-channel = <0>;
  325. has-inverted-stacr-oc;
  326. has-new-stacr-staopc;
  327. mdio-device = <&EMAC0>;
  328. };
  329. EMAC3: ethernet@ef601200 {
  330. device_type = "network";
  331. compatible = "ibm,emac-460gt", "ibm,emac4";
  332. interrupt-parent = <&EMAC3>;
  333. interrupts = <0 1>;
  334. #interrupt-cells = <1>;
  335. #address-cells = <0>;
  336. #size-cells = <0>;
  337. interrupt-map = </*Status*/ 0 &UIC2 13 4
  338. /*Wake*/ 1 &UIC2 17 4>;
  339. reg = <ef601200 70>;
  340. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  341. mal-device = <&MAL0>;
  342. mal-tx-channel = <3>;
  343. mal-rx-channel = <18>;
  344. cell-index = <3>;
  345. max-frame-size = <2328>;
  346. rx-fifo-size = <1000>;
  347. tx-fifo-size = <800>;
  348. phy-mode = "rgmii";
  349. phy-map = <00000000>;
  350. rgmii-device = <&RGMII1>;
  351. rgmii-channel = <1>;
  352. has-inverted-stacr-oc;
  353. has-new-stacr-staopc;
  354. mdio-device = <&EMAC0>;
  355. };
  356. };
  357. PCIX0: pci@c0ec00000 {
  358. device_type = "pci";
  359. #interrupt-cells = <1>;
  360. #size-cells = <2>;
  361. #address-cells = <3>;
  362. compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix";
  363. primary;
  364. large-inbound-windows;
  365. enable-msi-hole;
  366. reg = <c 0ec00000 8 /* Config space access */
  367. 0 0 0 /* no IACK cycles */
  368. c 0ed00000 4 /* Special cycles */
  369. c 0ec80000 100 /* Internal registers */
  370. c 0ec80100 fc>; /* Internal messaging registers */
  371. /* Outbound ranges, one memory and one IO,
  372. * later cannot be changed
  373. */
  374. ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
  375. 01000000 0 00000000 0000000c 08000000 0 00010000>;
  376. /* Inbound 2GB range starting at 0 */
  377. dma-ranges = <42000000 0 0 0 0 0 80000000>;
  378. /* This drives busses 0 to 0x3f */
  379. bus-range = <0 3f>;
  380. /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
  381. interrupt-map-mask = <0000 0 0 0>;
  382. interrupt-map = < 0000 0 0 0 &UIC1 0 8 >;
  383. };
  384. PCIE0: pciex@d00000000 {
  385. device_type = "pci";
  386. #interrupt-cells = <1>;
  387. #size-cells = <2>;
  388. #address-cells = <3>;
  389. compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
  390. primary;
  391. port = <0>; /* port number */
  392. reg = <d 00000000 20000000 /* Config space access */
  393. c 08010000 00001000>; /* Registers */
  394. dcr-reg = <100 020>;
  395. sdr-base = <300>;
  396. /* Outbound ranges, one memory and one IO,
  397. * later cannot be changed
  398. */
  399. ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
  400. 01000000 0 00000000 0000000f 80000000 0 00010000>;
  401. /* Inbound 2GB range starting at 0 */
  402. dma-ranges = <42000000 0 0 0 0 0 80000000>;
  403. /* This drives busses 40 to 0x7f */
  404. bus-range = <40 7f>;
  405. /* Legacy interrupts (note the weird polarity, the bridge seems
  406. * to invert PCIe legacy interrupts).
  407. * We are de-swizzling here because the numbers are actually for
  408. * port of the root complex virtual P2P bridge. But I want
  409. * to avoid putting a node for it in the tree, so the numbers
  410. * below are basically de-swizzled numbers.
  411. * The real slot is on idsel 0, so the swizzling is 1:1
  412. */
  413. interrupt-map-mask = <0000 0 0 7>;
  414. interrupt-map = <
  415. 0000 0 0 1 &UIC3 c 4 /* swizzled int A */
  416. 0000 0 0 2 &UIC3 d 4 /* swizzled int B */
  417. 0000 0 0 3 &UIC3 e 4 /* swizzled int C */
  418. 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>;
  419. };
  420. PCIE1: pciex@d20000000 {
  421. device_type = "pci";
  422. #interrupt-cells = <1>;
  423. #size-cells = <2>;
  424. #address-cells = <3>;
  425. compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
  426. primary;
  427. port = <1>; /* port number */
  428. reg = <d 20000000 20000000 /* Config space access */
  429. c 08011000 00001000>; /* Registers */
  430. dcr-reg = <120 020>;
  431. sdr-base = <340>;
  432. /* Outbound ranges, one memory and one IO,
  433. * later cannot be changed
  434. */
  435. ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
  436. 01000000 0 00000000 0000000f 80010000 0 00010000>;
  437. /* Inbound 2GB range starting at 0 */
  438. dma-ranges = <42000000 0 0 0 0 0 80000000>;
  439. /* This drives busses 80 to 0xbf */
  440. bus-range = <80 bf>;
  441. /* Legacy interrupts (note the weird polarity, the bridge seems
  442. * to invert PCIe legacy interrupts).
  443. * We are de-swizzling here because the numbers are actually for
  444. * port of the root complex virtual P2P bridge. But I want
  445. * to avoid putting a node for it in the tree, so the numbers
  446. * below are basically de-swizzled numbers.
  447. * The real slot is on idsel 0, so the swizzling is 1:1
  448. */
  449. interrupt-map-mask = <0000 0 0 7>;
  450. interrupt-map = <
  451. 0000 0 0 1 &UIC3 10 4 /* swizzled int A */
  452. 0000 0 0 2 &UIC3 11 4 /* swizzled int B */
  453. 0000 0 0 3 &UIC3 12 4 /* swizzled int C */
  454. 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>;
  455. };
  456. };
  457. };