misalignment.c 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661
  1. /* MN10300 Misalignment fixup handler
  2. *
  3. * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
  4. * Written by David Howells (dhowells@redhat.com)
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public Licence
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the Licence, or (at your option) any later version.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/sched.h>
  13. #include <linux/kernel.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/ptrace.h>
  17. #include <linux/timer.h>
  18. #include <linux/mm.h>
  19. #include <linux/smp.h>
  20. #include <linux/smp_lock.h>
  21. #include <linux/init.h>
  22. #include <linux/delay.h>
  23. #include <linux/spinlock.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/pci.h>
  26. #include <asm/processor.h>
  27. #include <asm/system.h>
  28. #include <asm/uaccess.h>
  29. #include <asm/io.h>
  30. #include <asm/atomic.h>
  31. #include <asm/smp.h>
  32. #include <asm/pgalloc.h>
  33. #include <asm/cpu-regs.h>
  34. #include <asm/busctl-regs.h>
  35. #include <asm/fpu.h>
  36. #include <asm/gdb-stub.h>
  37. #include <asm/asm-offsets.h>
  38. #if 0
  39. #define kdebug(FMT, ...) printk(KERN_DEBUG FMT, ##__VA_ARGS__)
  40. #else
  41. #define kdebug(FMT, ...) do {} while (0)
  42. #endif
  43. static int misalignment_addr(unsigned long *registers, unsigned params,
  44. unsigned opcode, unsigned disp,
  45. void **_address, unsigned long **_postinc);
  46. static int misalignment_reg(unsigned long *registers, unsigned params,
  47. unsigned opcode, unsigned disp,
  48. unsigned long **_register);
  49. static inline unsigned int_log2(unsigned x)
  50. {
  51. unsigned y;
  52. asm("bsch %1,%0" : "=r"(y) : "r"(x), "0"(0));
  53. return y;
  54. }
  55. #define log2(x) int_log2(x)
  56. static const unsigned Dreg_index[] = {
  57. REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2
  58. };
  59. static const unsigned Areg_index[] = {
  60. REG_A0 >> 2, REG_A1 >> 2, REG_A2 >> 2, REG_A3 >> 2
  61. };
  62. static const unsigned Rreg_index[] = {
  63. REG_E0 >> 2, REG_E1 >> 2, REG_E2 >> 2, REG_E3 >> 2,
  64. REG_E4 >> 2, REG_E5 >> 2, REG_E6 >> 2, REG_E7 >> 2,
  65. REG_A0 >> 2, REG_A1 >> 2, REG_A2 >> 2, REG_A3 >> 2,
  66. REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2
  67. };
  68. enum format_id {
  69. FMT_S0,
  70. FMT_S1,
  71. FMT_S2,
  72. FMT_S4,
  73. FMT_D0,
  74. FMT_D1,
  75. FMT_D2,
  76. FMT_D4,
  77. FMT_D6,
  78. FMT_D7,
  79. FMT_D8,
  80. FMT_D9,
  81. };
  82. struct {
  83. u_int8_t opsz, dispsz;
  84. } format_tbl[16] = {
  85. [FMT_S0] = { 8, 0 },
  86. [FMT_S1] = { 8, 8 },
  87. [FMT_S2] = { 8, 16 },
  88. [FMT_S4] = { 8, 32 },
  89. [FMT_D0] = { 16, 0 },
  90. [FMT_D1] = { 16, 8 },
  91. [FMT_D2] = { 16, 16 },
  92. [FMT_D4] = { 16, 32 },
  93. [FMT_D6] = { 24, 0 },
  94. [FMT_D7] = { 24, 8 },
  95. [FMT_D8] = { 24, 24 },
  96. [FMT_D9] = { 24, 32 },
  97. };
  98. enum value_id {
  99. DM0, /* data reg in opcode in bits 0-1 */
  100. DM1, /* data reg in opcode in bits 2-3 */
  101. DM2, /* data reg in opcode in bits 4-5 */
  102. AM0, /* addr reg in opcode in bits 0-1 */
  103. AM1, /* addr reg in opcode in bits 2-3 */
  104. AM2, /* addr reg in opcode in bits 4-5 */
  105. RM0, /* reg in opcode in bits 0-3 */
  106. RM1, /* reg in opcode in bits 2-5 */
  107. RM2, /* reg in opcode in bits 4-7 */
  108. RM4, /* reg in opcode in bits 8-11 */
  109. RM6, /* reg in opcode in bits 12-15 */
  110. RD0, /* reg in displacement in bits 0-3 */
  111. RD2, /* reg in displacement in bits 4-7 */
  112. SP, /* stack pointer */
  113. SD8, /* 8-bit signed displacement */
  114. SD16, /* 16-bit signed displacement */
  115. SD24, /* 24-bit signed displacement */
  116. SIMM4_2, /* 4-bit signed displacement in opcode bits 4-7 */
  117. SIMM8, /* 8-bit signed immediate */
  118. IMM24, /* 24-bit unsigned immediate */
  119. IMM32, /* 32-bit unsigned immediate */
  120. IMM32_HIGH8, /* 32-bit unsigned immediate, high 8-bits in opcode */
  121. DN0 = DM0,
  122. DN1 = DM1,
  123. DN2 = DM2,
  124. AN0 = AM0,
  125. AN1 = AM1,
  126. AN2 = AM2,
  127. RN0 = RM0,
  128. RN1 = RM1,
  129. RN2 = RM2,
  130. RN4 = RM4,
  131. RN6 = RM6,
  132. DI = DM1,
  133. RI = RM2,
  134. };
  135. struct mn10300_opcode {
  136. const char *name;
  137. u_int32_t opcode;
  138. u_int32_t opmask;
  139. unsigned exclusion;
  140. enum format_id format;
  141. unsigned cpu_mask;
  142. #define AM33 330
  143. unsigned params[2];
  144. #define MEM(ADDR) (0x80000000 | (ADDR))
  145. #define MEM2(ADDR1, ADDR2) (0x80000000 | (ADDR1) << 8 | (ADDR2))
  146. #define MEMINC(ADDR) (0x81000000 | (ADDR))
  147. #define MEMINC2(ADDR, INC) (0x81000000 | (ADDR) << 8 | (INC))
  148. };
  149. /* LIBOPCODES EXCERPT
  150. Assemble Matsushita MN10300 instructions.
  151. Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
  152. This program is free software; you can redistribute it and/or modify
  153. it under the terms of the GNU General Public Licence as published by
  154. the Free Software Foundation; either version 2 of the Licence, or
  155. (at your option) any later version.
  156. This program is distributed in the hope that it will be useful,
  157. but WITHOUT ANY WARRANTY; without even the implied warranty of
  158. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  159. GNU General Public Licence for more details.
  160. You should have received a copy of the GNU General Public Licence
  161. along with this program; if not, write to the Free Software
  162. Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  163. */
  164. static const struct mn10300_opcode mn10300_opcodes[] = {
  165. { "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}},
  166. { "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}},
  167. { "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}},
  168. { "mov", 0xf010, 0xfff0, 0, FMT_D0, 0, {AM1, MEM(AN0)}},
  169. { "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
  170. { "mov", 0xf340, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
  171. { "mov", 0xf380, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), AN2}},
  172. { "mov", 0xf3c0, 0xffc0, 0, FMT_D0, 0, {AM2, MEM2(DI, AN0)}},
  173. { "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
  174. { "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
  175. { "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}},
  176. { "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}},
  177. { "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM33, {MEM2(SD8, AM0), SP}},
  178. { "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM33, {SP, MEM2(SD8, AN0)}},
  179. { "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
  180. { "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
  181. { "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
  182. { "mov", 0xf97a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
  183. { "mov", 0xfa000000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
  184. { "mov", 0xfa100000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
  185. { "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}},
  186. { "mov", 0xfa300000, 0xfff00000, 0, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}},
  187. { "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
  188. { "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
  189. { "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
  190. { "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
  191. { "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
  192. { "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
  193. { "mov", 0xfc000000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
  194. { "mov", 0xfc100000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
  195. { "mov", 0xfc200000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}},
  196. { "mov", 0xfc300000, 0xfff00000, 0, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}},
  197. { "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
  198. { "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
  199. { "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
  200. { "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
  201. { "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
  202. { "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
  203. { "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
  204. { "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
  205. { "movhu", 0xf060, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}},
  206. { "movhu", 0xf070, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}},
  207. { "movhu", 0xf480, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
  208. { "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
  209. { "movhu", 0xf86000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
  210. { "movhu", 0xf87000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
  211. { "movhu", 0xf94a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
  212. { "movhu", 0xf95a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
  213. { "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
  214. { "movhu", 0xf9fa00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
  215. { "movhu", 0xfa600000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
  216. { "movhu", 0xfa700000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
  217. { "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
  218. { "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
  219. { "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
  220. { "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
  221. { "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
  222. { "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
  223. { "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
  224. { "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
  225. { "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
  226. { "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
  227. { "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
  228. { "movhu", 0xfdfa0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
  229. { "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
  230. { "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
  231. { "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
  232. { "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
  233. { 0, 0, 0, 0, 0, 0, {0}},
  234. };
  235. /*
  236. * fix up misalignment problems where possible
  237. */
  238. asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code)
  239. {
  240. const struct exception_table_entry *fixup;
  241. const struct mn10300_opcode *pop;
  242. unsigned long *registers = (unsigned long *) regs;
  243. unsigned long data, *store, *postinc;
  244. mm_segment_t seg;
  245. siginfo_t info;
  246. uint32_t opcode, disp, noc, xo, xm;
  247. uint8_t *pc, byte;
  248. void *address;
  249. unsigned tmp, npop;
  250. kdebug("MISALIGN at %lx\n", regs->pc);
  251. if (in_interrupt())
  252. die("Misalignment trap in interrupt context", regs, code);
  253. if (regs->epsw & EPSW_IE)
  254. asm volatile("or %0,epsw" : : "i"(EPSW_IE));
  255. seg = get_fs();
  256. set_fs(KERNEL_DS);
  257. fixup = search_exception_tables(regs->pc);
  258. /* first thing to do is to match the opcode */
  259. pc = (u_int8_t *) regs->pc;
  260. if (__get_user(byte, pc) != 0)
  261. goto fetch_error;
  262. opcode = byte;
  263. noc = 8;
  264. for (pop = mn10300_opcodes; pop->name; pop++) {
  265. npop = log2(pop->opcode | pop->opmask);
  266. if (npop <= 0 || npop > 31)
  267. continue;
  268. npop = (npop + 8) & ~7;
  269. got_more_bits:
  270. if (npop == noc) {
  271. if ((opcode & pop->opmask) == pop->opcode)
  272. goto found_opcode;
  273. } else if (npop > noc) {
  274. xo = pop->opcode >> (npop - noc);
  275. xm = pop->opmask >> (npop - noc);
  276. if ((opcode & xm) != xo)
  277. continue;
  278. /* we've got a partial match (an exact match on the
  279. * first N bytes), so we need to get some more data */
  280. pc++;
  281. if (__get_user(byte, pc) != 0)
  282. goto fetch_error;
  283. opcode = opcode << 8 | byte;
  284. noc += 8;
  285. goto got_more_bits;
  286. } else {
  287. /* there's already been a partial match as long as the
  288. * complete match we're now considering, so this one
  289. * should't match */
  290. continue;
  291. }
  292. }
  293. /* didn't manage to find a fixup */
  294. if (!user_mode(regs))
  295. printk(KERN_CRIT "MISALIGN: %lx: unsupported instruction %x\n",
  296. regs->pc, opcode);
  297. failed:
  298. set_fs(seg);
  299. if (die_if_no_fixup("misalignment error", regs, code))
  300. return;
  301. info.si_signo = SIGBUS;
  302. info.si_errno = 0;
  303. info.si_code = BUS_ADRALN;
  304. info.si_addr = (void *) regs->pc;
  305. force_sig_info(SIGBUS, &info, current);
  306. return;
  307. /* error reading opcodes */
  308. fetch_error:
  309. if (!user_mode(regs))
  310. printk(KERN_CRIT
  311. "MISALIGN: %p: fault whilst reading instruction data\n",
  312. pc);
  313. goto failed;
  314. bad_addr_mode:
  315. if (!user_mode(regs))
  316. printk(KERN_CRIT
  317. "MISALIGN: %lx: unsupported addressing mode %x\n",
  318. regs->pc, opcode);
  319. goto failed;
  320. bad_reg_mode:
  321. if (!user_mode(regs))
  322. printk(KERN_CRIT
  323. "MISALIGN: %lx: unsupported register mode %x\n",
  324. regs->pc, opcode);
  325. goto failed;
  326. unsupported_instruction:
  327. if (!user_mode(regs))
  328. printk(KERN_CRIT
  329. "MISALIGN: %lx: unsupported instruction %x (%s)\n",
  330. regs->pc, opcode, pop->name);
  331. goto failed;
  332. transfer_failed:
  333. set_fs(seg);
  334. if (fixup) {
  335. regs->pc = fixup->fixup;
  336. return;
  337. }
  338. if (die_if_no_fixup("misalignment fixup", regs, code))
  339. return;
  340. info.si_signo = SIGSEGV;
  341. info.si_errno = 0;
  342. info.si_code = 0;
  343. info.si_addr = (void *) regs->pc;
  344. force_sig_info(SIGSEGV, &info, current);
  345. return;
  346. /* we matched the opcode */
  347. found_opcode:
  348. kdebug("MISALIGN: %lx: %x==%x { %x, %x }\n",
  349. regs->pc, opcode, pop->opcode, pop->params[0], pop->params[1]);
  350. tmp = format_tbl[pop->format].opsz;
  351. if (tmp > noc)
  352. BUG(); /* match was less complete than it ought to have been */
  353. if (tmp < noc) {
  354. tmp = noc - tmp;
  355. opcode >>= tmp;
  356. pc -= tmp >> 3;
  357. }
  358. /* grab the extra displacement (note it's LSB first) */
  359. disp = 0;
  360. tmp = format_tbl[pop->format].dispsz >> 3;
  361. while (tmp > 0) {
  362. tmp--;
  363. disp <<= 8;
  364. pc++;
  365. if (__get_user(byte, pc) != 0)
  366. goto fetch_error;
  367. disp |= byte;
  368. }
  369. set_fs(KERNEL_XDS);
  370. if (fixup || regs->epsw & EPSW_nSL)
  371. set_fs(seg);
  372. tmp = (pop->params[0] ^ pop->params[1]) & 0x80000000;
  373. if (!tmp) {
  374. if (!user_mode(regs))
  375. printk(KERN_CRIT
  376. "MISALIGN: %lx:"
  377. " insn not move to/from memory %x\n",
  378. regs->pc, opcode);
  379. goto failed;
  380. }
  381. if (pop->params[0] & 0x80000000) {
  382. /* move memory to register */
  383. if (!misalignment_addr(registers, pop->params[0], opcode, disp,
  384. &address, &postinc))
  385. goto bad_addr_mode;
  386. if (!misalignment_reg(registers, pop->params[1], opcode, disp,
  387. &store))
  388. goto bad_reg_mode;
  389. if (strcmp(pop->name, "mov") == 0) {
  390. kdebug("FIXUP: mov (%p),DARn\n", address);
  391. if (copy_from_user(&data, (void *) address, 4) != 0)
  392. goto transfer_failed;
  393. if (pop->params[0] & 0x1000000)
  394. *postinc += 4;
  395. } else if (strcmp(pop->name, "movhu") == 0) {
  396. kdebug("FIXUP: movhu (%p),DARn\n", address);
  397. data = 0;
  398. if (copy_from_user(&data, (void *) address, 2) != 0)
  399. goto transfer_failed;
  400. if (pop->params[0] & 0x1000000)
  401. *postinc += 2;
  402. } else {
  403. goto unsupported_instruction;
  404. }
  405. *store = data;
  406. } else {
  407. /* move register to memory */
  408. if (!misalignment_reg(registers, pop->params[0], opcode, disp,
  409. &store))
  410. goto bad_reg_mode;
  411. if (!misalignment_addr(registers, pop->params[1], opcode, disp,
  412. &address, &postinc))
  413. goto bad_addr_mode;
  414. data = *store;
  415. if (strcmp(pop->name, "mov") == 0) {
  416. kdebug("FIXUP: mov %lx,(%p)\n", data, address);
  417. if (copy_to_user((void *) address, &data, 4) != 0)
  418. goto transfer_failed;
  419. if (pop->params[1] & 0x1000000)
  420. *postinc += 4;
  421. } else if (strcmp(pop->name, "movhu") == 0) {
  422. kdebug("FIXUP: movhu %hx,(%p)\n",
  423. (uint16_t) data, address);
  424. if (copy_to_user((void *) address, &data, 2) != 0)
  425. goto transfer_failed;
  426. if (pop->params[1] & 0x1000000)
  427. *postinc += 2;
  428. } else {
  429. goto unsupported_instruction;
  430. }
  431. }
  432. tmp = format_tbl[pop->format].opsz + format_tbl[pop->format].dispsz;
  433. regs->pc += tmp >> 3;
  434. set_fs(seg);
  435. return;
  436. }
  437. /*
  438. * determine the address that was being accessed
  439. */
  440. static int misalignment_addr(unsigned long *registers, unsigned params,
  441. unsigned opcode, unsigned disp,
  442. void **_address, unsigned long **_postinc)
  443. {
  444. unsigned long *postinc = NULL, address = 0, tmp;
  445. params &= 0x7fffffff;
  446. do {
  447. switch (params & 0xff) {
  448. case DM0:
  449. postinc = &registers[Dreg_index[opcode & 0x03]];
  450. address += *postinc;
  451. break;
  452. case DM1:
  453. postinc = &registers[Dreg_index[opcode >> 2 & 0x0c]];
  454. address += *postinc;
  455. break;
  456. case DM2:
  457. postinc = &registers[Dreg_index[opcode >> 4 & 0x30]];
  458. address += *postinc;
  459. break;
  460. case AM0:
  461. postinc = &registers[Areg_index[opcode & 0x03]];
  462. address += *postinc;
  463. break;
  464. case AM1:
  465. postinc = &registers[Areg_index[opcode >> 2 & 0x0c]];
  466. address += *postinc;
  467. break;
  468. case AM2:
  469. postinc = &registers[Areg_index[opcode >> 4 & 0x30]];
  470. address += *postinc;
  471. break;
  472. case RM0:
  473. postinc = &registers[Rreg_index[opcode & 0x0f]];
  474. address += *postinc;
  475. break;
  476. case RM1:
  477. postinc = &registers[Rreg_index[opcode >> 2 & 0x0f]];
  478. address += *postinc;
  479. break;
  480. case RM2:
  481. postinc = &registers[Rreg_index[opcode >> 4 & 0x0f]];
  482. address += *postinc;
  483. break;
  484. case RM4:
  485. postinc = &registers[Rreg_index[opcode >> 8 & 0x0f]];
  486. address += *postinc;
  487. break;
  488. case RM6:
  489. postinc = &registers[Rreg_index[opcode >> 12 & 0x0f]];
  490. address += *postinc;
  491. break;
  492. case RD0:
  493. postinc = &registers[Rreg_index[disp & 0x0f]];
  494. address += *postinc;
  495. break;
  496. case RD2:
  497. postinc = &registers[Rreg_index[disp >> 4 & 0x0f]];
  498. address += *postinc;
  499. break;
  500. case SD8:
  501. case SIMM8:
  502. address += (int32_t) (int8_t) (disp & 0xff);
  503. break;
  504. case SD16:
  505. address += (int32_t) (int16_t) (disp & 0xffff);
  506. break;
  507. case SD24:
  508. tmp = disp << 8;
  509. asm("asr 8,%0" : "=r"(tmp) : "0"(tmp));
  510. address += tmp;
  511. break;
  512. case SIMM4_2:
  513. tmp = opcode >> 4 & 0x0f;
  514. tmp <<= 28;
  515. asm("asr 28,%0" : "=r"(tmp) : "0"(tmp));
  516. address += tmp;
  517. break;
  518. case IMM24:
  519. address += disp & 0x00ffffff;
  520. break;
  521. case IMM32:
  522. case IMM32_HIGH8:
  523. address += disp;
  524. break;
  525. default:
  526. return 0;
  527. }
  528. } while ((params >>= 8));
  529. *_address = (void *) address;
  530. *_postinc = postinc;
  531. return 1;
  532. }
  533. /*
  534. * determine the register that is acting as source/dest
  535. */
  536. static int misalignment_reg(unsigned long *registers, unsigned params,
  537. unsigned opcode, unsigned disp,
  538. unsigned long **_register)
  539. {
  540. params &= 0x7fffffff;
  541. if (params & 0xffffff00)
  542. return 0;
  543. switch (params & 0xff) {
  544. case DM0:
  545. *_register = &registers[Dreg_index[opcode & 0x03]];
  546. break;
  547. case DM1:
  548. *_register = &registers[Dreg_index[opcode >> 2 & 0x03]];
  549. break;
  550. case DM2:
  551. *_register = &registers[Dreg_index[opcode >> 4 & 0x03]];
  552. break;
  553. case AM0:
  554. *_register = &registers[Areg_index[opcode & 0x03]];
  555. break;
  556. case AM1:
  557. *_register = &registers[Areg_index[opcode >> 2 & 0x03]];
  558. break;
  559. case AM2:
  560. *_register = &registers[Areg_index[opcode >> 4 & 0x03]];
  561. break;
  562. case RM0:
  563. *_register = &registers[Rreg_index[opcode & 0x0f]];
  564. break;
  565. case RM1:
  566. *_register = &registers[Rreg_index[opcode >> 2 & 0x0f]];
  567. break;
  568. case RM2:
  569. *_register = &registers[Rreg_index[opcode >> 4 & 0x0f]];
  570. break;
  571. case RM4:
  572. *_register = &registers[Rreg_index[opcode >> 8 & 0x0f]];
  573. break;
  574. case RM6:
  575. *_register = &registers[Rreg_index[opcode >> 12 & 0x0f]];
  576. break;
  577. case RD0:
  578. *_register = &registers[Rreg_index[disp & 0x0f]];
  579. break;
  580. case RD2:
  581. *_register = &registers[Rreg_index[disp >> 4 & 0x0f]];
  582. break;
  583. case SP:
  584. *_register = &registers[REG_SP >> 2];
  585. break;
  586. default:
  587. return 0;
  588. }
  589. return 1;
  590. }