cm_bf533.c 11 KB

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  1. /*
  2. * File: arch/blackfin/mach-bf533/boards/cm_bf533.c
  3. * Based on: arch/blackfin/mach-bf533/boards/ezkit.c
  4. * Author: Aidan Williams <aidan@nicta.com.au> Copyright 2005
  5. *
  6. * Created: 2005
  7. * Description: Board description file
  8. *
  9. * Modified:
  10. * Copyright 2004-2006 Analog Devices Inc.
  11. *
  12. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, see the file COPYING, or write
  26. * to the Free Software Foundation, Inc.,
  27. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  28. */
  29. #include <linux/device.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/mtd/mtd.h>
  32. #include <linux/mtd/partitions.h>
  33. #include <linux/spi/spi.h>
  34. #include <linux/spi/flash.h>
  35. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  36. #include <linux/usb/isp1362.h>
  37. #endif
  38. #include <linux/ata_platform.h>
  39. #include <linux/irq.h>
  40. #include <asm/dma.h>
  41. #include <asm/bfin5xx_spi.h>
  42. #include <asm/portmux.h>
  43. #include <asm/dpmc.h>
  44. /*
  45. * Name the Board for the /proc/cpuinfo
  46. */
  47. const char bfin_board_name[] = "Bluetechnix CM BF533";
  48. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  49. /* all SPI peripherals info goes here */
  50. #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
  51. static struct mtd_partition bfin_spi_flash_partitions[] = {
  52. {
  53. .name = "bootloader",
  54. .size = 0x00020000,
  55. .offset = 0,
  56. .mask_flags = MTD_CAP_ROM
  57. }, {
  58. .name = "kernel",
  59. .size = 0xe0000,
  60. .offset = 0x20000
  61. }, {
  62. .name = "file system",
  63. .size = 0x700000,
  64. .offset = 0x00100000,
  65. }
  66. };
  67. static struct flash_platform_data bfin_spi_flash_data = {
  68. .name = "m25p80",
  69. .parts = bfin_spi_flash_partitions,
  70. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  71. .type = "m25p64",
  72. };
  73. /* SPI flash chip (m25p64) */
  74. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  75. .enable_dma = 0, /* use dma transfer with this chip*/
  76. .bits_per_word = 8,
  77. };
  78. #endif
  79. /* SPI ADC chip */
  80. #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
  81. static struct bfin5xx_spi_chip spi_adc_chip_info = {
  82. .enable_dma = 1, /* use dma transfer with this chip*/
  83. .bits_per_word = 16,
  84. };
  85. #endif
  86. #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
  87. static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
  88. .enable_dma = 0,
  89. .bits_per_word = 16,
  90. };
  91. #endif
  92. #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
  93. static struct bfin5xx_spi_chip spi_mmc_chip_info = {
  94. .enable_dma = 1,
  95. .bits_per_word = 8,
  96. };
  97. #endif
  98. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  99. #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
  100. {
  101. /* the modalias must be the same as spi device driver name */
  102. .modalias = "m25p80", /* Name of spi_driver for this device */
  103. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  104. .bus_num = 0, /* Framework bus number */
  105. .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
  106. .platform_data = &bfin_spi_flash_data,
  107. .controller_data = &spi_flash_chip_info,
  108. .mode = SPI_MODE_3,
  109. },
  110. #endif
  111. #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
  112. {
  113. .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
  114. .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
  115. .bus_num = 0, /* Framework bus number */
  116. .chip_select = 2, /* Framework chip select. */
  117. .platform_data = NULL, /* No spi_driver specific config */
  118. .controller_data = &spi_adc_chip_info,
  119. },
  120. #endif
  121. #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
  122. {
  123. .modalias = "ad1836-spi",
  124. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  125. .bus_num = 0,
  126. .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
  127. .controller_data = &ad1836_spi_chip_info,
  128. },
  129. #endif
  130. #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
  131. {
  132. .modalias = "spi_mmc_dummy",
  133. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  134. .bus_num = 0,
  135. .chip_select = 0,
  136. .platform_data = NULL,
  137. .controller_data = &spi_mmc_chip_info,
  138. .mode = SPI_MODE_3,
  139. },
  140. {
  141. .modalias = "spi_mmc",
  142. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  143. .bus_num = 0,
  144. .chip_select = CONFIG_SPI_MMC_CS_CHAN,
  145. .platform_data = NULL,
  146. .controller_data = &spi_mmc_chip_info,
  147. .mode = SPI_MODE_3,
  148. },
  149. #endif
  150. };
  151. /* SPI (0) */
  152. static struct resource bfin_spi0_resource[] = {
  153. [0] = {
  154. .start = SPI0_REGBASE,
  155. .end = SPI0_REGBASE + 0xFF,
  156. .flags = IORESOURCE_MEM,
  157. },
  158. [1] = {
  159. .start = CH_SPI,
  160. .end = CH_SPI,
  161. .flags = IORESOURCE_IRQ,
  162. }
  163. };
  164. /* SPI controller data */
  165. static struct bfin5xx_spi_master bfin_spi0_info = {
  166. .num_chipselect = 8,
  167. .enable_dma = 1, /* master has the ability to do dma transfer */
  168. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  169. };
  170. static struct platform_device bfin_spi0_device = {
  171. .name = "bfin-spi",
  172. .id = 0, /* Bus number */
  173. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  174. .resource = bfin_spi0_resource,
  175. .dev = {
  176. .platform_data = &bfin_spi0_info, /* Passed to driver */
  177. },
  178. };
  179. #endif /* spi master and devices */
  180. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  181. static struct platform_device rtc_device = {
  182. .name = "rtc-bfin",
  183. .id = -1,
  184. };
  185. #endif
  186. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  187. static struct resource smc91x_resources[] = {
  188. {
  189. .start = 0x20200300,
  190. .end = 0x20200300 + 16,
  191. .flags = IORESOURCE_MEM,
  192. }, {
  193. .start = IRQ_PF0,
  194. .end = IRQ_PF0,
  195. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  196. },
  197. };
  198. static struct platform_device smc91x_device = {
  199. .name = "smc91x",
  200. .id = 0,
  201. .num_resources = ARRAY_SIZE(smc91x_resources),
  202. .resource = smc91x_resources,
  203. };
  204. #endif
  205. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  206. static struct resource bfin_uart_resources[] = {
  207. {
  208. .start = 0xFFC00400,
  209. .end = 0xFFC004FF,
  210. .flags = IORESOURCE_MEM,
  211. },
  212. };
  213. static struct platform_device bfin_uart_device = {
  214. .name = "bfin-uart",
  215. .id = 1,
  216. .num_resources = ARRAY_SIZE(bfin_uart_resources),
  217. .resource = bfin_uart_resources,
  218. };
  219. #endif
  220. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  221. static struct resource bfin_sir_resources[] = {
  222. #ifdef CONFIG_BFIN_SIR0
  223. {
  224. .start = 0xFFC00400,
  225. .end = 0xFFC004FF,
  226. .flags = IORESOURCE_MEM,
  227. },
  228. #endif
  229. };
  230. static struct platform_device bfin_sir_device = {
  231. .name = "bfin_sir",
  232. .id = 0,
  233. .num_resources = ARRAY_SIZE(bfin_sir_resources),
  234. .resource = bfin_sir_resources,
  235. };
  236. #endif
  237. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  238. static struct platform_device bfin_sport0_uart_device = {
  239. .name = "bfin-sport-uart",
  240. .id = 0,
  241. };
  242. static struct platform_device bfin_sport1_uart_device = {
  243. .name = "bfin-sport-uart",
  244. .id = 1,
  245. };
  246. #endif
  247. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  248. static struct resource isp1362_hcd_resources[] = {
  249. {
  250. .start = 0x20308000,
  251. .end = 0x20308000,
  252. .flags = IORESOURCE_MEM,
  253. }, {
  254. .start = 0x20308004,
  255. .end = 0x20308004,
  256. .flags = IORESOURCE_MEM,
  257. }, {
  258. .start = IRQ_PF4,
  259. .end = IRQ_PF4,
  260. .flags = IORESOURCE_IRQ,
  261. },
  262. };
  263. static struct isp1362_platform_data isp1362_priv = {
  264. .sel15Kres = 1,
  265. .clknotstop = 0,
  266. .oc_enable = 0,
  267. .int_act_high = 0,
  268. .int_edge_triggered = 0,
  269. .remote_wakeup_connected = 0,
  270. .no_power_switching = 1,
  271. .power_switching_mode = 0,
  272. };
  273. static struct platform_device isp1362_hcd_device = {
  274. .name = "isp1362-hcd",
  275. .id = 0,
  276. .dev = {
  277. .platform_data = &isp1362_priv,
  278. },
  279. .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
  280. .resource = isp1362_hcd_resources,
  281. };
  282. #endif
  283. #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
  284. #define PATA_INT 38
  285. static struct pata_platform_info bfin_pata_platform_data = {
  286. .ioport_shift = 2,
  287. .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
  288. };
  289. static struct resource bfin_pata_resources[] = {
  290. {
  291. .start = 0x2030C000,
  292. .end = 0x2030C01F,
  293. .flags = IORESOURCE_MEM,
  294. },
  295. {
  296. .start = 0x2030D018,
  297. .end = 0x2030D01B,
  298. .flags = IORESOURCE_MEM,
  299. },
  300. {
  301. .start = PATA_INT,
  302. .end = PATA_INT,
  303. .flags = IORESOURCE_IRQ,
  304. },
  305. };
  306. static struct platform_device bfin_pata_device = {
  307. .name = "pata_platform",
  308. .id = -1,
  309. .num_resources = ARRAY_SIZE(bfin_pata_resources),
  310. .resource = bfin_pata_resources,
  311. .dev = {
  312. .platform_data = &bfin_pata_platform_data,
  313. }
  314. };
  315. #endif
  316. static const unsigned int cclk_vlev_datasheet[] =
  317. {
  318. VRPAIR(VLEV_085, 250000000),
  319. VRPAIR(VLEV_090, 376000000),
  320. VRPAIR(VLEV_095, 426000000),
  321. VRPAIR(VLEV_100, 426000000),
  322. VRPAIR(VLEV_105, 476000000),
  323. VRPAIR(VLEV_110, 476000000),
  324. VRPAIR(VLEV_115, 476000000),
  325. VRPAIR(VLEV_120, 600000000),
  326. VRPAIR(VLEV_125, 600000000),
  327. VRPAIR(VLEV_130, 600000000),
  328. };
  329. static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
  330. .tuple_tab = cclk_vlev_datasheet,
  331. .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
  332. .vr_settling_time = 25 /* us */,
  333. };
  334. static struct platform_device bfin_dpmc = {
  335. .name = "bfin dpmc",
  336. .dev = {
  337. .platform_data = &bfin_dmpc_vreg_data,
  338. },
  339. };
  340. static struct platform_device *cm_bf533_devices[] __initdata = {
  341. &bfin_dpmc,
  342. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  343. &bfin_uart_device,
  344. #endif
  345. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  346. &bfin_sir_device,
  347. #endif
  348. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  349. &bfin_sport0_uart_device,
  350. &bfin_sport1_uart_device,
  351. #endif
  352. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  353. &rtc_device,
  354. #endif
  355. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  356. &isp1362_hcd_device,
  357. #endif
  358. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  359. &smc91x_device,
  360. #endif
  361. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  362. &bfin_spi0_device,
  363. #endif
  364. #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
  365. &bfin_pata_device,
  366. #endif
  367. };
  368. static int __init cm_bf533_init(void)
  369. {
  370. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  371. platform_add_devices(cm_bf533_devices, ARRAY_SIZE(cm_bf533_devices));
  372. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  373. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  374. #endif
  375. #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
  376. irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
  377. #endif
  378. return 0;
  379. }
  380. arch_initcall(cm_bf533_init);