pcm038.c 4.9 KB

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  1. /*
  2. * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
  3. * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17. * MA 02110-1301, USA.
  18. */
  19. #include <linux/platform_device.h>
  20. #include <linux/mtd/physmap.h>
  21. #include <asm/mach/arch.h>
  22. #include <asm/mach-types.h>
  23. #include <asm/arch/common.h>
  24. #include <asm/hardware.h>
  25. #include <asm/arch/iomux-mx1-mx2.h>
  26. #include <asm/mach/time.h>
  27. #include <asm/arch/imx-uart.h>
  28. #include <asm/arch/board-pcm038.h>
  29. /*
  30. * Phytec's phyCORE-i.MX27 comes with 32MiB flash,
  31. * 16 bit width
  32. */
  33. static struct physmap_flash_data pcm038_flash_data = {
  34. .width = 2,
  35. };
  36. static struct resource pcm038_flash_resource = {
  37. .start = 0xc0000000,
  38. .end = 0xc1ffffff,
  39. .flags = IORESOURCE_MEM,
  40. };
  41. static struct platform_device pcm038_nor_mtd_device = {
  42. .name = "physmap-flash",
  43. .id = 0,
  44. .dev = {
  45. .platform_data = &pcm038_flash_data,
  46. },
  47. .num_resources = 1,
  48. .resource = &pcm038_flash_resource,
  49. };
  50. static int mxc_uart0_pins[] = {
  51. PE12_PF_UART1_TXD,
  52. PE13_PF_UART1_RXD,
  53. PE14_PF_UART1_CTS,
  54. PE15_PF_UART1_RTS
  55. };
  56. static int uart_mxc_port0_init(struct platform_device *pdev)
  57. {
  58. return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
  59. ARRAY_SIZE(mxc_uart0_pins),
  60. MXC_GPIO_ALLOC_MODE_NORMAL, "UART0");
  61. }
  62. static int uart_mxc_port0_exit(struct platform_device *pdev)
  63. {
  64. return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
  65. ARRAY_SIZE(mxc_uart0_pins),
  66. MXC_GPIO_ALLOC_MODE_RELEASE, "UART0");
  67. }
  68. static int mxc_uart1_pins[] = {
  69. PE3_PF_UART2_CTS,
  70. PE4_PF_UART2_RTS,
  71. PE6_PF_UART2_TXD,
  72. PE7_PF_UART2_RXD
  73. };
  74. static int uart_mxc_port1_init(struct platform_device *pdev)
  75. {
  76. return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
  77. ARRAY_SIZE(mxc_uart1_pins),
  78. MXC_GPIO_ALLOC_MODE_NORMAL, "UART1");
  79. }
  80. static int uart_mxc_port1_exit(struct platform_device *pdev)
  81. {
  82. return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
  83. ARRAY_SIZE(mxc_uart1_pins),
  84. MXC_GPIO_ALLOC_MODE_RELEASE, "UART1");
  85. }
  86. static int mxc_uart2_pins[] = { PE10_PF_UART3_CTS,
  87. PE9_PF_UART3_RXD,
  88. PE10_PF_UART3_CTS,
  89. PE9_PF_UART3_RXD };
  90. static int uart_mxc_port2_init(struct platform_device *pdev)
  91. {
  92. return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
  93. ARRAY_SIZE(mxc_uart2_pins),
  94. MXC_GPIO_ALLOC_MODE_NORMAL, "UART2");
  95. }
  96. static int uart_mxc_port2_exit(struct platform_device *pdev)
  97. {
  98. return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
  99. ARRAY_SIZE(mxc_uart2_pins),
  100. MXC_GPIO_ALLOC_MODE_RELEASE, "UART2");
  101. }
  102. static struct imxuart_platform_data uart_pdata[] = {
  103. {
  104. .init = uart_mxc_port0_init,
  105. .exit = uart_mxc_port0_exit,
  106. .flags = IMXUART_HAVE_RTSCTS,
  107. }, {
  108. .init = uart_mxc_port1_init,
  109. .exit = uart_mxc_port1_exit,
  110. .flags = IMXUART_HAVE_RTSCTS,
  111. }, {
  112. .init = uart_mxc_port2_init,
  113. .exit = uart_mxc_port2_exit,
  114. .flags = IMXUART_HAVE_RTSCTS,
  115. },
  116. };
  117. static int mxc_fec_pins[] = {
  118. PD0_AIN_FEC_TXD0,
  119. PD1_AIN_FEC_TXD1,
  120. PD2_AIN_FEC_TXD2,
  121. PD3_AIN_FEC_TXD3,
  122. PD4_AOUT_FEC_RX_ER,
  123. PD5_AOUT_FEC_RXD1,
  124. PD6_AOUT_FEC_RXD2,
  125. PD7_AOUT_FEC_RXD3,
  126. PD8_AF_FEC_MDIO,
  127. PD9_AIN_FEC_MDC,
  128. PD10_AOUT_FEC_CRS,
  129. PD11_AOUT_FEC_TX_CLK,
  130. PD12_AOUT_FEC_RXD0,
  131. PD13_AOUT_FEC_RX_DV,
  132. PD14_AOUT_FEC_CLR,
  133. PD15_AOUT_FEC_COL,
  134. PD16_AIN_FEC_TX_ER,
  135. PF23_AIN_FEC_TX_EN
  136. };
  137. static void gpio_fec_active(void)
  138. {
  139. mxc_gpio_setup_multiple_pins(mxc_fec_pins,
  140. ARRAY_SIZE(mxc_fec_pins),
  141. MXC_GPIO_ALLOC_MODE_NORMAL, "FEC");
  142. }
  143. static void gpio_fec_inactive(void)
  144. {
  145. mxc_gpio_setup_multiple_pins(mxc_fec_pins,
  146. ARRAY_SIZE(mxc_fec_pins),
  147. MXC_GPIO_ALLOC_MODE_RELEASE, "FEC");
  148. }
  149. static struct platform_device *platform_devices[] __initdata = {
  150. &pcm038_nor_mtd_device,
  151. };
  152. static void __init pcm038_init(void)
  153. {
  154. int i;
  155. gpio_fec_active();
  156. for (i = 0; i < 3; i++)
  157. imx_init_uart(i, &uart_pdata[i]);
  158. platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
  159. #ifdef CONFIG_MACH_PCM970_BASEBOARD
  160. pcm970_baseboard_init();
  161. #endif
  162. }
  163. static void __init pcm038_timer_init(void)
  164. {
  165. mxc_clocks_init(26000000);
  166. mxc_timer_init("gpt_clk.0");
  167. }
  168. struct sys_timer pcm038_timer = {
  169. .init = pcm038_timer_init,
  170. };
  171. MACHINE_START(PCM038, "phyCORE-i.MX27")
  172. .phys_io = AIPI_BASE_ADDR,
  173. .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
  174. .boot_params = PHYS_OFFSET + 0x100,
  175. .map_io = mxc_map_io,
  176. .init_irq = mxc_init_irq,
  177. .init_machine = pcm038_init,
  178. .timer = &pcm038_timer,
  179. MACHINE_END