at91sam9x5.dtsi 12 KB

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  1. /*
  2. * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
  3. * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
  4. * AT91SAM9X25, AT91SAM9X35 SoC
  5. *
  6. * Copyright (C) 2012 Atmel,
  7. * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. model = "Atmel AT91SAM9x5 family SoC";
  14. compatible = "atmel,at91sam9x5";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. gpio0 = &pioA;
  22. gpio1 = &pioB;
  23. gpio2 = &pioC;
  24. gpio3 = &pioD;
  25. tcb0 = &tcb0;
  26. tcb1 = &tcb1;
  27. i2c0 = &i2c0;
  28. i2c1 = &i2c1;
  29. i2c2 = &i2c2;
  30. };
  31. cpus {
  32. cpu@0 {
  33. compatible = "arm,arm926ejs";
  34. };
  35. };
  36. memory {
  37. reg = <0x20000000 0x10000000>;
  38. };
  39. ahb {
  40. compatible = "simple-bus";
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. ranges;
  44. apb {
  45. compatible = "simple-bus";
  46. #address-cells = <1>;
  47. #size-cells = <1>;
  48. ranges;
  49. aic: interrupt-controller@fffff000 {
  50. #interrupt-cells = <3>;
  51. compatible = "atmel,at91rm9200-aic";
  52. interrupt-controller;
  53. reg = <0xfffff000 0x200>;
  54. atmel,external-irqs = <31>;
  55. };
  56. ramc0: ramc@ffffe800 {
  57. compatible = "atmel,at91sam9g45-ddramc";
  58. reg = <0xffffe800 0x200>;
  59. };
  60. pmc: pmc@fffffc00 {
  61. compatible = "atmel,at91rm9200-pmc";
  62. reg = <0xfffffc00 0x100>;
  63. };
  64. rstc@fffffe00 {
  65. compatible = "atmel,at91sam9g45-rstc";
  66. reg = <0xfffffe00 0x10>;
  67. };
  68. shdwc@fffffe10 {
  69. compatible = "atmel,at91sam9x5-shdwc";
  70. reg = <0xfffffe10 0x10>;
  71. };
  72. pit: timer@fffffe30 {
  73. compatible = "atmel,at91sam9260-pit";
  74. reg = <0xfffffe30 0xf>;
  75. interrupts = <1 4 7>;
  76. };
  77. tcb0: timer@f8008000 {
  78. compatible = "atmel,at91sam9x5-tcb";
  79. reg = <0xf8008000 0x100>;
  80. interrupts = <17 4 0>;
  81. };
  82. tcb1: timer@f800c000 {
  83. compatible = "atmel,at91sam9x5-tcb";
  84. reg = <0xf800c000 0x100>;
  85. interrupts = <17 4 0>;
  86. };
  87. dma0: dma-controller@ffffec00 {
  88. compatible = "atmel,at91sam9g45-dma";
  89. reg = <0xffffec00 0x200>;
  90. interrupts = <20 4 0>;
  91. };
  92. dma1: dma-controller@ffffee00 {
  93. compatible = "atmel,at91sam9g45-dma";
  94. reg = <0xffffee00 0x200>;
  95. interrupts = <21 4 0>;
  96. };
  97. pinctrl@fffff400 {
  98. #address-cells = <1>;
  99. #size-cells = <1>;
  100. compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
  101. ranges = <0xfffff400 0xfffff400 0x800>;
  102. /* shared pinctrl settings */
  103. dbgu {
  104. pinctrl_dbgu: dbgu-0 {
  105. atmel,pins =
  106. <0 9 0x1 0x0 /* PA9 periph A */
  107. 0 10 0x1 0x1>; /* PA10 periph A with pullup */
  108. };
  109. };
  110. usart0 {
  111. pinctrl_usart0: usart0-0 {
  112. atmel,pins =
  113. <0 0 0x1 0x1 /* PA0 periph A with pullup */
  114. 0 1 0x1 0x0>; /* PA1 periph A */
  115. };
  116. pinctrl_usart0_rts: usart0_rts-0 {
  117. atmel,pins =
  118. <0 2 0x1 0x0>; /* PA2 periph A */
  119. };
  120. pinctrl_usart0_cts: usart0_cts-0 {
  121. atmel,pins =
  122. <0 3 0x1 0x0>; /* PA3 periph A */
  123. };
  124. };
  125. usart1 {
  126. pinctrl_usart1: usart1-0 {
  127. atmel,pins =
  128. <0 5 0x1 0x1 /* PA5 periph A with pullup */
  129. 0 6 0x1 0x0>; /* PA6 periph A */
  130. };
  131. pinctrl_usart1_rts: usart1_rts-0 {
  132. atmel,pins =
  133. <3 27 0x3 0x0>; /* PC27 periph C */
  134. };
  135. pinctrl_usart1_cts: usart1_cts-0 {
  136. atmel,pins =
  137. <3 28 0x3 0x0>; /* PC28 periph C */
  138. };
  139. };
  140. usart2 {
  141. pinctrl_usart2: usart2-0 {
  142. atmel,pins =
  143. <0 7 0x1 0x1 /* PA7 periph A with pullup */
  144. 0 8 0x1 0x0>; /* PA8 periph A */
  145. };
  146. pinctrl_uart2_rts: uart2_rts-0 {
  147. atmel,pins =
  148. <0 0 0x2 0x0>; /* PB0 periph B */
  149. };
  150. pinctrl_uart2_cts: uart2_cts-0 {
  151. atmel,pins =
  152. <0 1 0x2 0x0>; /* PB1 periph B */
  153. };
  154. };
  155. usart3 {
  156. pinctrl_uart3: usart3-0 {
  157. atmel,pins =
  158. <3 23 0x2 0x1 /* PC22 periph B with pullup */
  159. 3 23 0x2 0x0>; /* PC23 periph B */
  160. };
  161. pinctrl_usart3_rts: usart3_rts-0 {
  162. atmel,pins =
  163. <3 24 0x2 0x0>; /* PC24 periph B */
  164. };
  165. pinctrl_usart3_cts: usart3_cts-0 {
  166. atmel,pins =
  167. <3 25 0x2 0x0>; /* PC25 periph B */
  168. };
  169. };
  170. uart0 {
  171. pinctrl_uart0: uart0-0 {
  172. atmel,pins =
  173. <3 8 0x3 0x0 /* PC8 periph C */
  174. 3 9 0x3 0x1>; /* PC9 periph C with pullup */
  175. };
  176. };
  177. uart1 {
  178. pinctrl_uart1: uart1-0 {
  179. atmel,pins =
  180. <3 16 0x3 0x0 /* PC16 periph C */
  181. 3 17 0x3 0x1>; /* PC17 periph C with pullup */
  182. };
  183. };
  184. nand {
  185. pinctrl_nand: nand-0 {
  186. atmel,pins =
  187. <3 4 0x0 0x1 /* PD5 gpio RDY pin pull_up */
  188. 3 5 0x0 0x1>; /* PD4 gpio enable pin pull_up */
  189. };
  190. };
  191. macb0 {
  192. pinctrl_macb0_rmii: macb0_rmii-0 {
  193. atmel,pins =
  194. <1 0 0x1 0x0 /* PB0 periph A */
  195. 1 1 0x1 0x0 /* PB1 periph A */
  196. 1 2 0x1 0x0 /* PB2 periph A */
  197. 1 3 0x1 0x0 /* PB3 periph A */
  198. 1 4 0x1 0x0 /* PB4 periph A */
  199. 1 5 0x1 0x0 /* PB5 periph A */
  200. 1 6 0x1 0x0 /* PB6 periph A */
  201. 1 7 0x1 0x0 /* PB7 periph A */
  202. 1 9 0x1 0x0 /* PB9 periph A */
  203. 1 10 0x1 0x0>; /* PB10 periph A */
  204. };
  205. pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
  206. atmel,pins =
  207. <1 8 0x1 0x0 /* PA8 periph A */
  208. 1 11 0x1 0x0 /* PA11 periph A */
  209. 1 12 0x1 0x0 /* PA12 periph A */
  210. 1 13 0x1 0x0 /* PA13 periph A */
  211. 1 14 0x1 0x0 /* PA14 periph A */
  212. 1 15 0x1 0x0 /* PA15 periph A */
  213. 1 16 0x1 0x0 /* PA16 periph A */
  214. 1 17 0x1 0x0>; /* PA17 periph A */
  215. };
  216. };
  217. mmc0 {
  218. pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  219. atmel,pins =
  220. <0 17 0x1 0x0 /* PA17 periph A */
  221. 0 16 0x1 0x1 /* PA16 periph A with pullup */
  222. 0 15 0x1 0x1>; /* PA15 periph A with pullup */
  223. };
  224. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  225. atmel,pins =
  226. <0 18 0x1 0x1 /* PA18 periph A with pullup */
  227. 0 19 0x1 0x1 /* PA19 periph A with pullup */
  228. 0 20 0x1 0x1>; /* PA20 periph A with pullup */
  229. };
  230. };
  231. mmc1 {
  232. pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
  233. atmel,pins =
  234. <0 13 0x2 0x0 /* PA13 periph B */
  235. 0 12 0x2 0x1 /* PA12 periph B with pullup */
  236. 0 11 0x2 0x1>; /* PA11 periph B with pullup */
  237. };
  238. pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
  239. atmel,pins =
  240. <0 2 0x2 0x1 /* PA2 periph B with pullup */
  241. 0 3 0x2 0x1 /* PA3 periph B with pullup */
  242. 0 4 0x2 0x1>; /* PA4 periph B with pullup */
  243. };
  244. };
  245. pioA: gpio@fffff400 {
  246. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  247. reg = <0xfffff400 0x200>;
  248. interrupts = <2 4 1>;
  249. #gpio-cells = <2>;
  250. gpio-controller;
  251. interrupt-controller;
  252. #interrupt-cells = <2>;
  253. };
  254. pioB: gpio@fffff600 {
  255. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  256. reg = <0xfffff600 0x200>;
  257. interrupts = <2 4 1>;
  258. #gpio-cells = <2>;
  259. gpio-controller;
  260. #gpio-lines = <19>;
  261. interrupt-controller;
  262. #interrupt-cells = <2>;
  263. };
  264. pioC: gpio@fffff800 {
  265. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  266. reg = <0xfffff800 0x200>;
  267. interrupts = <3 4 1>;
  268. #gpio-cells = <2>;
  269. gpio-controller;
  270. interrupt-controller;
  271. #interrupt-cells = <2>;
  272. };
  273. pioD: gpio@fffffa00 {
  274. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  275. reg = <0xfffffa00 0x200>;
  276. interrupts = <3 4 1>;
  277. #gpio-cells = <2>;
  278. gpio-controller;
  279. #gpio-lines = <22>;
  280. interrupt-controller;
  281. #interrupt-cells = <2>;
  282. };
  283. };
  284. mmc0: mmc@f0008000 {
  285. compatible = "atmel,hsmci";
  286. reg = <0xf0008000 0x600>;
  287. interrupts = <12 4 0>;
  288. #address-cells = <1>;
  289. #size-cells = <0>;
  290. status = "disabled";
  291. };
  292. mmc1: mmc@f000c000 {
  293. compatible = "atmel,hsmci";
  294. reg = <0xf000c000 0x600>;
  295. interrupts = <26 4 0>;
  296. #address-cells = <1>;
  297. #size-cells = <0>;
  298. status = "disabled";
  299. };
  300. dbgu: serial@fffff200 {
  301. compatible = "atmel,at91sam9260-usart";
  302. reg = <0xfffff200 0x200>;
  303. interrupts = <1 4 7>;
  304. pinctrl-names = "default";
  305. pinctrl-0 = <&pinctrl_dbgu>;
  306. status = "disabled";
  307. };
  308. usart0: serial@f801c000 {
  309. compatible = "atmel,at91sam9260-usart";
  310. reg = <0xf801c000 0x200>;
  311. interrupts = <5 4 5>;
  312. atmel,use-dma-rx;
  313. atmel,use-dma-tx;
  314. pinctrl-names = "default";
  315. pinctrl-0 = <&pinctrl_usart0>;
  316. status = "disabled";
  317. };
  318. usart1: serial@f8020000 {
  319. compatible = "atmel,at91sam9260-usart";
  320. reg = <0xf8020000 0x200>;
  321. interrupts = <6 4 5>;
  322. atmel,use-dma-rx;
  323. atmel,use-dma-tx;
  324. pinctrl-names = "default";
  325. pinctrl-0 = <&pinctrl_usart1>;
  326. status = "disabled";
  327. };
  328. usart2: serial@f8024000 {
  329. compatible = "atmel,at91sam9260-usart";
  330. reg = <0xf8024000 0x200>;
  331. interrupts = <7 4 5>;
  332. atmel,use-dma-rx;
  333. atmel,use-dma-tx;
  334. pinctrl-names = "default";
  335. pinctrl-0 = <&pinctrl_usart2>;
  336. status = "disabled";
  337. };
  338. macb0: ethernet@f802c000 {
  339. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  340. reg = <0xf802c000 0x100>;
  341. interrupts = <24 4 3>;
  342. pinctrl-names = "default";
  343. pinctrl-0 = <&pinctrl_macb0_rmii>;
  344. status = "disabled";
  345. };
  346. macb1: ethernet@f8030000 {
  347. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  348. reg = <0xf8030000 0x100>;
  349. interrupts = <27 4 3>;
  350. status = "disabled";
  351. };
  352. i2c0: i2c@f8010000 {
  353. compatible = "atmel,at91sam9x5-i2c";
  354. reg = <0xf8010000 0x100>;
  355. interrupts = <9 4 6>;
  356. #address-cells = <1>;
  357. #size-cells = <0>;
  358. status = "disabled";
  359. };
  360. i2c1: i2c@f8014000 {
  361. compatible = "atmel,at91sam9x5-i2c";
  362. reg = <0xf8014000 0x100>;
  363. interrupts = <10 4 6>;
  364. #address-cells = <1>;
  365. #size-cells = <0>;
  366. status = "disabled";
  367. };
  368. i2c2: i2c@f8018000 {
  369. compatible = "atmel,at91sam9x5-i2c";
  370. reg = <0xf8018000 0x100>;
  371. interrupts = <11 4 6>;
  372. #address-cells = <1>;
  373. #size-cells = <0>;
  374. status = "disabled";
  375. };
  376. adc0: adc@f804c000 {
  377. compatible = "atmel,at91sam9260-adc";
  378. reg = <0xf804c000 0x100>;
  379. interrupts = <19 4 0>;
  380. atmel,adc-use-external;
  381. atmel,adc-channels-used = <0xffff>;
  382. atmel,adc-vref = <3300>;
  383. atmel,adc-num-channels = <12>;
  384. atmel,adc-startup-time = <40>;
  385. atmel,adc-channel-base = <0x50>;
  386. atmel,adc-drdy-mask = <0x1000000>;
  387. atmel,adc-status-register = <0x30>;
  388. atmel,adc-trigger-register = <0xc0>;
  389. trigger@0 {
  390. trigger-name = "external-rising";
  391. trigger-value = <0x1>;
  392. trigger-external;
  393. };
  394. trigger@1 {
  395. trigger-name = "external-falling";
  396. trigger-value = <0x2>;
  397. trigger-external;
  398. };
  399. trigger@2 {
  400. trigger-name = "external-any";
  401. trigger-value = <0x3>;
  402. trigger-external;
  403. };
  404. trigger@3 {
  405. trigger-name = "continuous";
  406. trigger-value = <0x6>;
  407. };
  408. };
  409. };
  410. nand0: nand@40000000 {
  411. compatible = "atmel,at91rm9200-nand";
  412. #address-cells = <1>;
  413. #size-cells = <1>;
  414. reg = <0x40000000 0x10000000
  415. >;
  416. atmel,nand-addr-offset = <21>;
  417. atmel,nand-cmd-offset = <22>;
  418. pinctrl-names = "default";
  419. pinctrl-0 = <&pinctrl_nand>;
  420. gpios = <&pioD 5 0
  421. &pioD 4 0
  422. 0
  423. >;
  424. status = "disabled";
  425. };
  426. usb0: ohci@00600000 {
  427. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  428. reg = <0x00600000 0x100000>;
  429. interrupts = <22 4 2>;
  430. status = "disabled";
  431. };
  432. usb1: ehci@00700000 {
  433. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  434. reg = <0x00700000 0x100000>;
  435. interrupts = <22 4 2>;
  436. status = "disabled";
  437. };
  438. };
  439. i2c@0 {
  440. compatible = "i2c-gpio";
  441. gpios = <&pioA 30 0 /* sda */
  442. &pioA 31 0 /* scl */
  443. >;
  444. i2c-gpio,sda-open-drain;
  445. i2c-gpio,scl-open-drain;
  446. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  447. #address-cells = <1>;
  448. #size-cells = <0>;
  449. status = "disabled";
  450. };
  451. i2c@1 {
  452. compatible = "i2c-gpio";
  453. gpios = <&pioC 0 0 /* sda */
  454. &pioC 1 0 /* scl */
  455. >;
  456. i2c-gpio,sda-open-drain;
  457. i2c-gpio,scl-open-drain;
  458. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  459. #address-cells = <1>;
  460. #size-cells = <0>;
  461. status = "disabled";
  462. };
  463. i2c@2 {
  464. compatible = "i2c-gpio";
  465. gpios = <&pioB 4 0 /* sda */
  466. &pioB 5 0 /* scl */
  467. >;
  468. i2c-gpio,sda-open-drain;
  469. i2c-gpio,scl-open-drain;
  470. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  471. #address-cells = <1>;
  472. #size-cells = <0>;
  473. status = "disabled";
  474. };
  475. };