spi-ti-qspi.c 13 KB

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  1. /*
  2. * TI QSPI driver
  3. *
  4. * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
  5. * Author: Sourav Poddar <sourav.poddar@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GPLv2.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/init.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/module.h>
  19. #include <linux/device.h>
  20. #include <linux/delay.h>
  21. #include <linux/dma-mapping.h>
  22. #include <linux/dmaengine.h>
  23. #include <linux/omap-dma.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/err.h>
  26. #include <linux/clk.h>
  27. #include <linux/io.h>
  28. #include <linux/slab.h>
  29. #include <linux/pm_runtime.h>
  30. #include <linux/of.h>
  31. #include <linux/of_device.h>
  32. #include <linux/pinctrl/consumer.h>
  33. #include <linux/spi/spi.h>
  34. struct ti_qspi_regs {
  35. u32 clkctrl;
  36. };
  37. struct ti_qspi {
  38. struct completion transfer_complete;
  39. /* IRQ synchronization */
  40. spinlock_t lock;
  41. /* list synchronization */
  42. struct mutex list_lock;
  43. struct spi_master *master;
  44. void __iomem *base;
  45. struct clk *fclk;
  46. struct device *dev;
  47. struct ti_qspi_regs ctx_reg;
  48. u32 spi_max_frequency;
  49. u32 cmd;
  50. u32 dc;
  51. u32 stat;
  52. };
  53. #define QSPI_PID (0x0)
  54. #define QSPI_SYSCONFIG (0x10)
  55. #define QSPI_INTR_STATUS_RAW_SET (0x20)
  56. #define QSPI_INTR_STATUS_ENABLED_CLEAR (0x24)
  57. #define QSPI_INTR_ENABLE_SET_REG (0x28)
  58. #define QSPI_INTR_ENABLE_CLEAR_REG (0x2c)
  59. #define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
  60. #define QSPI_SPI_DC_REG (0x44)
  61. #define QSPI_SPI_CMD_REG (0x48)
  62. #define QSPI_SPI_STATUS_REG (0x4c)
  63. #define QSPI_SPI_DATA_REG (0x50)
  64. #define QSPI_SPI_SETUP0_REG (0x54)
  65. #define QSPI_SPI_SWITCH_REG (0x64)
  66. #define QSPI_SPI_SETUP1_REG (0x58)
  67. #define QSPI_SPI_SETUP2_REG (0x5c)
  68. #define QSPI_SPI_SETUP3_REG (0x60)
  69. #define QSPI_SPI_DATA_REG_1 (0x68)
  70. #define QSPI_SPI_DATA_REG_2 (0x6c)
  71. #define QSPI_SPI_DATA_REG_3 (0x70)
  72. #define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
  73. #define QSPI_FCLK 192000000
  74. /* Clock Control */
  75. #define QSPI_CLK_EN (1 << 31)
  76. #define QSPI_CLK_DIV_MAX 0xffff
  77. /* Command */
  78. #define QSPI_EN_CS(n) (n << 28)
  79. #define QSPI_WLEN(n) ((n - 1) << 19)
  80. #define QSPI_3_PIN (1 << 18)
  81. #define QSPI_RD_SNGL (1 << 16)
  82. #define QSPI_WR_SNGL (2 << 16)
  83. #define QSPI_RD_DUAL (3 << 16)
  84. #define QSPI_RD_QUAD (7 << 16)
  85. #define QSPI_INVAL (4 << 16)
  86. #define QSPI_WC_CMD_INT_EN (1 << 14)
  87. #define QSPI_FLEN(n) ((n - 1) << 0)
  88. /* STATUS REGISTER */
  89. #define WC 0x02
  90. /* INTERRUPT REGISTER */
  91. #define QSPI_WC_INT_EN (1 << 1)
  92. #define QSPI_WC_INT_DISABLE (1 << 1)
  93. /* Device Control */
  94. #define QSPI_DD(m, n) (m << (3 + n * 8))
  95. #define QSPI_CKPHA(n) (1 << (2 + n * 8))
  96. #define QSPI_CSPOL(n) (1 << (1 + n * 8))
  97. #define QSPI_CKPOL(n) (1 << (n * 8))
  98. #define QSPI_FRAME 4096
  99. #define QSPI_AUTOSUSPEND_TIMEOUT 2000
  100. static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
  101. unsigned long reg)
  102. {
  103. return readl(qspi->base + reg);
  104. }
  105. static inline void ti_qspi_write(struct ti_qspi *qspi,
  106. unsigned long val, unsigned long reg)
  107. {
  108. writel(val, qspi->base + reg);
  109. }
  110. static int ti_qspi_setup(struct spi_device *spi)
  111. {
  112. struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
  113. struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
  114. int clk_div = 0, ret;
  115. u32 clk_ctrl_reg, clk_rate, clk_mask;
  116. if (spi->master->busy) {
  117. dev_dbg(qspi->dev, "master busy doing other trasnfers\n");
  118. return -EBUSY;
  119. }
  120. if (!qspi->spi_max_frequency) {
  121. dev_err(qspi->dev, "spi max frequency not defined\n");
  122. return -EINVAL;
  123. }
  124. clk_rate = clk_get_rate(qspi->fclk);
  125. clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
  126. if (clk_div < 0) {
  127. dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
  128. return -EINVAL;
  129. }
  130. if (clk_div > QSPI_CLK_DIV_MAX) {
  131. dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
  132. QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
  133. return -EINVAL;
  134. }
  135. dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
  136. qspi->spi_max_frequency, clk_div);
  137. ret = pm_runtime_get_sync(qspi->dev);
  138. if (ret) {
  139. dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
  140. return ret;
  141. }
  142. clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
  143. clk_ctrl_reg &= ~QSPI_CLK_EN;
  144. /* disable SCLK */
  145. ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
  146. /* enable SCLK */
  147. clk_mask = QSPI_CLK_EN | clk_div;
  148. ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
  149. ctx_reg->clkctrl = clk_mask;
  150. pm_runtime_mark_last_busy(qspi->dev);
  151. ret = pm_runtime_put_autosuspend(qspi->dev);
  152. if (ret < 0) {
  153. dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
  154. return ret;
  155. }
  156. return 0;
  157. }
  158. static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
  159. {
  160. struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
  161. ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
  162. }
  163. static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
  164. {
  165. int wlen, count, ret;
  166. unsigned int cmd;
  167. const u8 *txbuf;
  168. txbuf = t->tx_buf;
  169. cmd = qspi->cmd | QSPI_WR_SNGL;
  170. count = t->len;
  171. wlen = t->bits_per_word;
  172. while (count) {
  173. switch (wlen) {
  174. case 8:
  175. dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
  176. cmd, qspi->dc, *txbuf);
  177. writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
  178. ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
  179. ret = wait_for_completion_timeout(&qspi->transfer_complete,
  180. QSPI_COMPLETION_TIMEOUT);
  181. if (ret == 0) {
  182. dev_err(qspi->dev, "write timed out\n");
  183. return -ETIMEDOUT;
  184. }
  185. txbuf += 1;
  186. count -= 1;
  187. break;
  188. case 16:
  189. dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
  190. cmd, qspi->dc, *txbuf);
  191. writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
  192. ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
  193. ret = wait_for_completion_timeout(&qspi->transfer_complete,
  194. QSPI_COMPLETION_TIMEOUT);
  195. if (ret == 0) {
  196. dev_err(qspi->dev, "write timed out\n");
  197. return -ETIMEDOUT;
  198. }
  199. txbuf += 2;
  200. count -= 2;
  201. break;
  202. case 32:
  203. dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
  204. cmd, qspi->dc, *txbuf);
  205. writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
  206. ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
  207. ret = wait_for_completion_timeout(&qspi->transfer_complete,
  208. QSPI_COMPLETION_TIMEOUT);
  209. if (ret == 0) {
  210. dev_err(qspi->dev, "write timed out\n");
  211. return -ETIMEDOUT;
  212. }
  213. txbuf += 4;
  214. count -= 4;
  215. break;
  216. }
  217. }
  218. return 0;
  219. }
  220. static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
  221. {
  222. int wlen, count, ret;
  223. unsigned int cmd;
  224. u8 *rxbuf;
  225. rxbuf = t->rx_buf;
  226. cmd = qspi->cmd | QSPI_RD_SNGL;
  227. count = t->len;
  228. wlen = t->bits_per_word;
  229. while (count) {
  230. dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
  231. ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
  232. ret = wait_for_completion_timeout(&qspi->transfer_complete,
  233. QSPI_COMPLETION_TIMEOUT);
  234. if (ret == 0) {
  235. dev_err(qspi->dev, "read timed out\n");
  236. return -ETIMEDOUT;
  237. }
  238. switch (wlen) {
  239. case 8:
  240. *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
  241. rxbuf += 1;
  242. count -= 1;
  243. break;
  244. case 16:
  245. *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
  246. rxbuf += 2;
  247. count -= 2;
  248. break;
  249. case 32:
  250. *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
  251. rxbuf += 4;
  252. count -= 4;
  253. break;
  254. }
  255. }
  256. return 0;
  257. }
  258. static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t)
  259. {
  260. int ret;
  261. if (t->tx_buf) {
  262. ret = qspi_write_msg(qspi, t);
  263. if (ret) {
  264. dev_dbg(qspi->dev, "Error while writing\n");
  265. return ret;
  266. }
  267. }
  268. if (t->rx_buf) {
  269. ret = qspi_read_msg(qspi, t);
  270. if (ret) {
  271. dev_dbg(qspi->dev, "Error while reading\n");
  272. return ret;
  273. }
  274. }
  275. return 0;
  276. }
  277. static int ti_qspi_start_transfer_one(struct spi_master *master,
  278. struct spi_message *m)
  279. {
  280. struct ti_qspi *qspi = spi_master_get_devdata(master);
  281. struct spi_device *spi = m->spi;
  282. struct spi_transfer *t;
  283. int status = 0, ret;
  284. int frame_length;
  285. /* setup device control reg */
  286. qspi->dc = 0;
  287. if (spi->mode & SPI_CPHA)
  288. qspi->dc |= QSPI_CKPHA(spi->chip_select);
  289. if (spi->mode & SPI_CPOL)
  290. qspi->dc |= QSPI_CKPOL(spi->chip_select);
  291. if (spi->mode & SPI_CS_HIGH)
  292. qspi->dc |= QSPI_CSPOL(spi->chip_select);
  293. frame_length = (m->frame_length << 3) / spi->bits_per_word;
  294. frame_length = clamp(frame_length, 0, QSPI_FRAME);
  295. /* setup command reg */
  296. qspi->cmd = 0;
  297. qspi->cmd |= QSPI_EN_CS(spi->chip_select);
  298. qspi->cmd |= QSPI_FLEN(frame_length);
  299. qspi->cmd |= QSPI_WC_CMD_INT_EN;
  300. ti_qspi_write(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
  301. ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
  302. mutex_lock(&qspi->list_lock);
  303. list_for_each_entry(t, &m->transfers, transfer_list) {
  304. qspi->cmd |= QSPI_WLEN(t->bits_per_word);
  305. ret = qspi_transfer_msg(qspi, t);
  306. if (ret) {
  307. dev_dbg(qspi->dev, "transfer message failed\n");
  308. return -EINVAL;
  309. }
  310. m->actual_length += t->len;
  311. }
  312. mutex_unlock(&qspi->list_lock);
  313. m->status = status;
  314. spi_finalize_current_message(master);
  315. ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
  316. return status;
  317. }
  318. static irqreturn_t ti_qspi_isr(int irq, void *dev_id)
  319. {
  320. struct ti_qspi *qspi = dev_id;
  321. u16 int_stat;
  322. irqreturn_t ret = IRQ_HANDLED;
  323. spin_lock(&qspi->lock);
  324. int_stat = ti_qspi_read(qspi, QSPI_INTR_STATUS_ENABLED_CLEAR);
  325. qspi->stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
  326. if (!int_stat) {
  327. dev_dbg(qspi->dev, "No IRQ triggered\n");
  328. ret = IRQ_NONE;
  329. goto out;
  330. }
  331. ret = IRQ_WAKE_THREAD;
  332. ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, QSPI_INTR_ENABLE_CLEAR_REG);
  333. ti_qspi_write(qspi, QSPI_WC_INT_DISABLE,
  334. QSPI_INTR_STATUS_ENABLED_CLEAR);
  335. out:
  336. spin_unlock(&qspi->lock);
  337. return ret;
  338. }
  339. static irqreturn_t ti_qspi_threaded_isr(int this_irq, void *dev_id)
  340. {
  341. struct ti_qspi *qspi = dev_id;
  342. unsigned long flags;
  343. spin_lock_irqsave(&qspi->lock, flags);
  344. if (qspi->stat & WC)
  345. complete(&qspi->transfer_complete);
  346. spin_unlock_irqrestore(&qspi->lock, flags);
  347. ti_qspi_write(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
  348. return IRQ_HANDLED;
  349. }
  350. static int ti_qspi_runtime_resume(struct device *dev)
  351. {
  352. struct ti_qspi *qspi;
  353. struct spi_master *master;
  354. master = dev_get_drvdata(dev);
  355. qspi = spi_master_get_devdata(master);
  356. ti_qspi_restore_ctx(qspi);
  357. return 0;
  358. }
  359. static const struct of_device_id ti_qspi_match[] = {
  360. {.compatible = "ti,dra7xxx-qspi" },
  361. {},
  362. };
  363. MODULE_DEVICE_TABLE(of, dra7xxx_qspi_match);
  364. static int ti_qspi_probe(struct platform_device *pdev)
  365. {
  366. struct ti_qspi *qspi;
  367. struct spi_master *master;
  368. struct resource *r;
  369. struct device_node *np = pdev->dev.of_node;
  370. u32 max_freq;
  371. int ret = 0, num_cs, irq;
  372. master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
  373. if (!master)
  374. return -ENOMEM;
  375. master->mode_bits = SPI_CPOL | SPI_CPHA;
  376. master->bus_num = -1;
  377. master->flags = SPI_MASTER_HALF_DUPLEX;
  378. master->setup = ti_qspi_setup;
  379. master->auto_runtime_pm = true;
  380. master->transfer_one_message = ti_qspi_start_transfer_one;
  381. master->dev.of_node = pdev->dev.of_node;
  382. master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
  383. if (!of_property_read_u32(np, "num-cs", &num_cs))
  384. master->num_chipselect = num_cs;
  385. platform_set_drvdata(pdev, master);
  386. qspi = spi_master_get_devdata(master);
  387. qspi->master = master;
  388. qspi->dev = &pdev->dev;
  389. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  390. irq = platform_get_irq(pdev, 0);
  391. if (irq < 0) {
  392. dev_err(&pdev->dev, "no irq resource?\n");
  393. return irq;
  394. }
  395. spin_lock_init(&qspi->lock);
  396. mutex_init(&qspi->list_lock);
  397. qspi->base = devm_ioremap_resource(&pdev->dev, r);
  398. if (IS_ERR(qspi->base)) {
  399. ret = PTR_ERR(qspi->base);
  400. goto free_master;
  401. }
  402. ret = devm_request_threaded_irq(&pdev->dev, irq, ti_qspi_isr,
  403. ti_qspi_threaded_isr, 0,
  404. dev_name(&pdev->dev), qspi);
  405. if (ret < 0) {
  406. dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
  407. irq);
  408. goto free_master;
  409. }
  410. qspi->fclk = devm_clk_get(&pdev->dev, "fck");
  411. if (IS_ERR(qspi->fclk)) {
  412. ret = PTR_ERR(qspi->fclk);
  413. dev_err(&pdev->dev, "could not get clk: %d\n", ret);
  414. }
  415. init_completion(&qspi->transfer_complete);
  416. pm_runtime_use_autosuspend(&pdev->dev);
  417. pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
  418. pm_runtime_enable(&pdev->dev);
  419. if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
  420. qspi->spi_max_frequency = max_freq;
  421. ret = spi_register_master(master);
  422. if (ret)
  423. goto free_master;
  424. return 0;
  425. free_master:
  426. spi_master_put(master);
  427. return ret;
  428. }
  429. static int ti_qspi_remove(struct platform_device *pdev)
  430. {
  431. struct ti_qspi *qspi = platform_get_drvdata(pdev);
  432. spi_unregister_master(qspi->master);
  433. return 0;
  434. }
  435. static const struct dev_pm_ops ti_qspi_pm_ops = {
  436. .runtime_resume = ti_qspi_runtime_resume,
  437. };
  438. static struct platform_driver ti_qspi_driver = {
  439. .probe = ti_qspi_probe,
  440. .remove = ti_qspi_remove,
  441. .driver = {
  442. .name = "ti,dra7xxx-qspi",
  443. .owner = THIS_MODULE,
  444. .pm = &ti_qspi_pm_ops,
  445. .of_match_table = ti_qspi_match,
  446. }
  447. };
  448. module_platform_driver(ti_qspi_driver);
  449. MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
  450. MODULE_LICENSE("GPL v2");
  451. MODULE_DESCRIPTION("TI QSPI controller driver");