exynos_thermal.c 27 KB

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  1. /*
  2. * exynos_thermal.c - Samsung EXYNOS TMU (Thermal Management Unit)
  3. *
  4. * Copyright (C) 2011 Samsung Electronics
  5. * Donggeun Kim <dg77.kim@samsung.com>
  6. * Amit Daniel Kachhap <amit.kachhap@linaro.org>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. *
  22. */
  23. #include <linux/module.h>
  24. #include <linux/err.h>
  25. #include <linux/kernel.h>
  26. #include <linux/slab.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/clk.h>
  30. #include <linux/workqueue.h>
  31. #include <linux/sysfs.h>
  32. #include <linux/kobject.h>
  33. #include <linux/io.h>
  34. #include <linux/mutex.h>
  35. #include <linux/platform_data/exynos_thermal.h>
  36. #include <linux/thermal.h>
  37. #include <linux/cpufreq.h>
  38. #include <linux/cpu_cooling.h>
  39. #include <linux/of.h>
  40. /* Exynos generic registers */
  41. #define EXYNOS_TMU_REG_TRIMINFO 0x0
  42. #define EXYNOS_TMU_REG_CONTROL 0x20
  43. #define EXYNOS_TMU_REG_STATUS 0x28
  44. #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
  45. #define EXYNOS_TMU_REG_INTEN 0x70
  46. #define EXYNOS_TMU_REG_INTSTAT 0x74
  47. #define EXYNOS_TMU_REG_INTCLEAR 0x78
  48. #define EXYNOS_TMU_TRIM_TEMP_MASK 0xff
  49. #define EXYNOS_TMU_GAIN_SHIFT 8
  50. #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
  51. #define EXYNOS_TMU_CORE_ON 3
  52. #define EXYNOS_TMU_CORE_OFF 2
  53. #define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET 50
  54. /* Exynos4210 specific registers */
  55. #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
  56. #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
  57. #define EXYNOS4210_TMU_REG_TRIG_LEVEL1 0x54
  58. #define EXYNOS4210_TMU_REG_TRIG_LEVEL2 0x58
  59. #define EXYNOS4210_TMU_REG_TRIG_LEVEL3 0x5C
  60. #define EXYNOS4210_TMU_REG_PAST_TEMP0 0x60
  61. #define EXYNOS4210_TMU_REG_PAST_TEMP1 0x64
  62. #define EXYNOS4210_TMU_REG_PAST_TEMP2 0x68
  63. #define EXYNOS4210_TMU_REG_PAST_TEMP3 0x6C
  64. #define EXYNOS4210_TMU_TRIG_LEVEL0_MASK 0x1
  65. #define EXYNOS4210_TMU_TRIG_LEVEL1_MASK 0x10
  66. #define EXYNOS4210_TMU_TRIG_LEVEL2_MASK 0x100
  67. #define EXYNOS4210_TMU_TRIG_LEVEL3_MASK 0x1000
  68. #define EXYNOS4210_TMU_INTCLEAR_VAL 0x1111
  69. /* Exynos5250 and Exynos4412 specific registers */
  70. #define EXYNOS_TMU_TRIMINFO_CON 0x14
  71. #define EXYNOS_THD_TEMP_RISE 0x50
  72. #define EXYNOS_THD_TEMP_FALL 0x54
  73. #define EXYNOS_EMUL_CON 0x80
  74. #define EXYNOS_TRIMINFO_RELOAD 0x1
  75. #define EXYNOS_TMU_CLEAR_RISE_INT 0x111
  76. #define EXYNOS_TMU_CLEAR_FALL_INT (0x111 << 12)
  77. #define EXYNOS_MUX_ADDR_VALUE 6
  78. #define EXYNOS_MUX_ADDR_SHIFT 20
  79. #define EXYNOS_TMU_TRIP_MODE_SHIFT 13
  80. #define EFUSE_MIN_VALUE 40
  81. #define EFUSE_MAX_VALUE 100
  82. /* In-kernel thermal framework related macros & definations */
  83. #define SENSOR_NAME_LEN 16
  84. #define MAX_TRIP_COUNT 8
  85. #define MAX_COOLING_DEVICE 4
  86. #define MAX_THRESHOLD_LEVS 4
  87. #define ACTIVE_INTERVAL 500
  88. #define IDLE_INTERVAL 10000
  89. #define MCELSIUS 1000
  90. #ifdef CONFIG_THERMAL_EMULATION
  91. #define EXYNOS_EMUL_TIME 0x57F0
  92. #define EXYNOS_EMUL_TIME_SHIFT 16
  93. #define EXYNOS_EMUL_DATA_SHIFT 8
  94. #define EXYNOS_EMUL_DATA_MASK 0xFF
  95. #define EXYNOS_EMUL_ENABLE 0x1
  96. #endif /* CONFIG_THERMAL_EMULATION */
  97. /* CPU Zone information */
  98. #define PANIC_ZONE 4
  99. #define WARN_ZONE 3
  100. #define MONITOR_ZONE 2
  101. #define SAFE_ZONE 1
  102. #define GET_ZONE(trip) (trip + 2)
  103. #define GET_TRIP(zone) (zone - 2)
  104. #define EXYNOS_ZONE_COUNT 3
  105. struct exynos_tmu_data {
  106. struct exynos_tmu_platform_data *pdata;
  107. struct resource *mem;
  108. void __iomem *base;
  109. int irq;
  110. enum soc_type soc;
  111. struct work_struct irq_work;
  112. struct mutex lock;
  113. struct clk *clk;
  114. u8 temp_error1, temp_error2;
  115. };
  116. struct thermal_trip_point_conf {
  117. int trip_val[MAX_TRIP_COUNT];
  118. int trip_count;
  119. u8 trigger_falling;
  120. };
  121. struct thermal_cooling_conf {
  122. struct freq_clip_table freq_data[MAX_TRIP_COUNT];
  123. int freq_clip_count;
  124. };
  125. struct thermal_sensor_conf {
  126. char name[SENSOR_NAME_LEN];
  127. int (*read_temperature)(void *data);
  128. int (*write_emul_temp)(void *drv_data, unsigned long temp);
  129. struct thermal_trip_point_conf trip_data;
  130. struct thermal_cooling_conf cooling_data;
  131. void *private_data;
  132. };
  133. struct exynos_thermal_zone {
  134. enum thermal_device_mode mode;
  135. struct thermal_zone_device *therm_dev;
  136. struct thermal_cooling_device *cool_dev[MAX_COOLING_DEVICE];
  137. unsigned int cool_dev_size;
  138. struct platform_device *exynos4_dev;
  139. struct thermal_sensor_conf *sensor_conf;
  140. bool bind;
  141. };
  142. static struct exynos_thermal_zone *th_zone;
  143. static void exynos_unregister_thermal(void);
  144. static int exynos_register_thermal(struct thermal_sensor_conf *sensor_conf);
  145. /* Get mode callback functions for thermal zone */
  146. static int exynos_get_mode(struct thermal_zone_device *thermal,
  147. enum thermal_device_mode *mode)
  148. {
  149. if (th_zone)
  150. *mode = th_zone->mode;
  151. return 0;
  152. }
  153. /* Set mode callback functions for thermal zone */
  154. static int exynos_set_mode(struct thermal_zone_device *thermal,
  155. enum thermal_device_mode mode)
  156. {
  157. if (!th_zone->therm_dev) {
  158. pr_notice("thermal zone not registered\n");
  159. return 0;
  160. }
  161. mutex_lock(&th_zone->therm_dev->lock);
  162. if (mode == THERMAL_DEVICE_ENABLED &&
  163. !th_zone->sensor_conf->trip_data.trigger_falling)
  164. th_zone->therm_dev->polling_delay = IDLE_INTERVAL;
  165. else
  166. th_zone->therm_dev->polling_delay = 0;
  167. mutex_unlock(&th_zone->therm_dev->lock);
  168. th_zone->mode = mode;
  169. thermal_zone_device_update(th_zone->therm_dev);
  170. pr_info("thermal polling set for duration=%d msec\n",
  171. th_zone->therm_dev->polling_delay);
  172. return 0;
  173. }
  174. /* Get trip type callback functions for thermal zone */
  175. static int exynos_get_trip_type(struct thermal_zone_device *thermal, int trip,
  176. enum thermal_trip_type *type)
  177. {
  178. switch (GET_ZONE(trip)) {
  179. case MONITOR_ZONE:
  180. case WARN_ZONE:
  181. *type = THERMAL_TRIP_ACTIVE;
  182. break;
  183. case PANIC_ZONE:
  184. *type = THERMAL_TRIP_CRITICAL;
  185. break;
  186. default:
  187. return -EINVAL;
  188. }
  189. return 0;
  190. }
  191. /* Get trip temperature callback functions for thermal zone */
  192. static int exynos_get_trip_temp(struct thermal_zone_device *thermal, int trip,
  193. unsigned long *temp)
  194. {
  195. if (trip < GET_TRIP(MONITOR_ZONE) || trip > GET_TRIP(PANIC_ZONE))
  196. return -EINVAL;
  197. *temp = th_zone->sensor_conf->trip_data.trip_val[trip];
  198. /* convert the temperature into millicelsius */
  199. *temp = *temp * MCELSIUS;
  200. return 0;
  201. }
  202. /* Get critical temperature callback functions for thermal zone */
  203. static int exynos_get_crit_temp(struct thermal_zone_device *thermal,
  204. unsigned long *temp)
  205. {
  206. int ret;
  207. /* Panic zone */
  208. ret = exynos_get_trip_temp(thermal, GET_TRIP(PANIC_ZONE), temp);
  209. return ret;
  210. }
  211. /* Bind callback functions for thermal zone */
  212. static int exynos_bind(struct thermal_zone_device *thermal,
  213. struct thermal_cooling_device *cdev)
  214. {
  215. int ret = 0, i, tab_size, level;
  216. struct freq_clip_table *tab_ptr, *clip_data;
  217. struct thermal_sensor_conf *data = th_zone->sensor_conf;
  218. tab_ptr = (struct freq_clip_table *)data->cooling_data.freq_data;
  219. tab_size = data->cooling_data.freq_clip_count;
  220. if (tab_ptr == NULL || tab_size == 0)
  221. return -EINVAL;
  222. /* find the cooling device registered*/
  223. for (i = 0; i < th_zone->cool_dev_size; i++)
  224. if (cdev == th_zone->cool_dev[i])
  225. break;
  226. /* No matching cooling device */
  227. if (i == th_zone->cool_dev_size)
  228. return 0;
  229. /* Bind the thermal zone to the cpufreq cooling device */
  230. for (i = 0; i < tab_size; i++) {
  231. clip_data = (struct freq_clip_table *)&(tab_ptr[i]);
  232. level = cpufreq_cooling_get_level(0, clip_data->freq_clip_max);
  233. if (level == THERMAL_CSTATE_INVALID)
  234. return 0;
  235. switch (GET_ZONE(i)) {
  236. case MONITOR_ZONE:
  237. case WARN_ZONE:
  238. if (thermal_zone_bind_cooling_device(thermal, i, cdev,
  239. level, 0)) {
  240. pr_err("error binding cdev inst %d\n", i);
  241. ret = -EINVAL;
  242. }
  243. th_zone->bind = true;
  244. break;
  245. default:
  246. ret = -EINVAL;
  247. }
  248. }
  249. return ret;
  250. }
  251. /* Unbind callback functions for thermal zone */
  252. static int exynos_unbind(struct thermal_zone_device *thermal,
  253. struct thermal_cooling_device *cdev)
  254. {
  255. int ret = 0, i, tab_size;
  256. struct thermal_sensor_conf *data = th_zone->sensor_conf;
  257. if (th_zone->bind == false)
  258. return 0;
  259. tab_size = data->cooling_data.freq_clip_count;
  260. if (tab_size == 0)
  261. return -EINVAL;
  262. /* find the cooling device registered*/
  263. for (i = 0; i < th_zone->cool_dev_size; i++)
  264. if (cdev == th_zone->cool_dev[i])
  265. break;
  266. /* No matching cooling device */
  267. if (i == th_zone->cool_dev_size)
  268. return 0;
  269. /* Bind the thermal zone to the cpufreq cooling device */
  270. for (i = 0; i < tab_size; i++) {
  271. switch (GET_ZONE(i)) {
  272. case MONITOR_ZONE:
  273. case WARN_ZONE:
  274. if (thermal_zone_unbind_cooling_device(thermal, i,
  275. cdev)) {
  276. pr_err("error unbinding cdev inst=%d\n", i);
  277. ret = -EINVAL;
  278. }
  279. th_zone->bind = false;
  280. break;
  281. default:
  282. ret = -EINVAL;
  283. }
  284. }
  285. return ret;
  286. }
  287. /* Get temperature callback functions for thermal zone */
  288. static int exynos_get_temp(struct thermal_zone_device *thermal,
  289. unsigned long *temp)
  290. {
  291. void *data;
  292. if (!th_zone->sensor_conf) {
  293. pr_info("Temperature sensor not initialised\n");
  294. return -EINVAL;
  295. }
  296. data = th_zone->sensor_conf->private_data;
  297. *temp = th_zone->sensor_conf->read_temperature(data);
  298. /* convert the temperature into millicelsius */
  299. *temp = *temp * MCELSIUS;
  300. return 0;
  301. }
  302. /* Get temperature callback functions for thermal zone */
  303. static int exynos_set_emul_temp(struct thermal_zone_device *thermal,
  304. unsigned long temp)
  305. {
  306. void *data;
  307. int ret = -EINVAL;
  308. if (!th_zone->sensor_conf) {
  309. pr_info("Temperature sensor not initialised\n");
  310. return -EINVAL;
  311. }
  312. data = th_zone->sensor_conf->private_data;
  313. if (th_zone->sensor_conf->write_emul_temp)
  314. ret = th_zone->sensor_conf->write_emul_temp(data, temp);
  315. return ret;
  316. }
  317. /* Get the temperature trend */
  318. static int exynos_get_trend(struct thermal_zone_device *thermal,
  319. int trip, enum thermal_trend *trend)
  320. {
  321. int ret;
  322. unsigned long trip_temp;
  323. ret = exynos_get_trip_temp(thermal, trip, &trip_temp);
  324. if (ret < 0)
  325. return ret;
  326. if (thermal->temperature >= trip_temp)
  327. *trend = THERMAL_TREND_RAISE_FULL;
  328. else
  329. *trend = THERMAL_TREND_DROP_FULL;
  330. return 0;
  331. }
  332. /* Operation callback functions for thermal zone */
  333. static struct thermal_zone_device_ops const exynos_dev_ops = {
  334. .bind = exynos_bind,
  335. .unbind = exynos_unbind,
  336. .get_temp = exynos_get_temp,
  337. .set_emul_temp = exynos_set_emul_temp,
  338. .get_trend = exynos_get_trend,
  339. .get_mode = exynos_get_mode,
  340. .set_mode = exynos_set_mode,
  341. .get_trip_type = exynos_get_trip_type,
  342. .get_trip_temp = exynos_get_trip_temp,
  343. .get_crit_temp = exynos_get_crit_temp,
  344. };
  345. /*
  346. * This function may be called from interrupt based temperature sensor
  347. * when threshold is changed.
  348. */
  349. static void exynos_report_trigger(void)
  350. {
  351. unsigned int i;
  352. char data[10];
  353. char *envp[] = { data, NULL };
  354. if (!th_zone || !th_zone->therm_dev)
  355. return;
  356. if (th_zone->bind == false) {
  357. for (i = 0; i < th_zone->cool_dev_size; i++) {
  358. if (!th_zone->cool_dev[i])
  359. continue;
  360. exynos_bind(th_zone->therm_dev,
  361. th_zone->cool_dev[i]);
  362. }
  363. }
  364. thermal_zone_device_update(th_zone->therm_dev);
  365. mutex_lock(&th_zone->therm_dev->lock);
  366. /* Find the level for which trip happened */
  367. for (i = 0; i < th_zone->sensor_conf->trip_data.trip_count; i++) {
  368. if (th_zone->therm_dev->last_temperature <
  369. th_zone->sensor_conf->trip_data.trip_val[i] * MCELSIUS)
  370. break;
  371. }
  372. if (th_zone->mode == THERMAL_DEVICE_ENABLED &&
  373. !th_zone->sensor_conf->trip_data.trigger_falling) {
  374. if (i > 0)
  375. th_zone->therm_dev->polling_delay = ACTIVE_INTERVAL;
  376. else
  377. th_zone->therm_dev->polling_delay = IDLE_INTERVAL;
  378. }
  379. snprintf(data, sizeof(data), "%u", i);
  380. kobject_uevent_env(&th_zone->therm_dev->device.kobj, KOBJ_CHANGE, envp);
  381. mutex_unlock(&th_zone->therm_dev->lock);
  382. }
  383. /* Register with the in-kernel thermal management */
  384. static int exynos_register_thermal(struct thermal_sensor_conf *sensor_conf)
  385. {
  386. int ret;
  387. struct cpumask mask_val;
  388. if (!sensor_conf || !sensor_conf->read_temperature) {
  389. pr_err("Temperature sensor not initialised\n");
  390. return -EINVAL;
  391. }
  392. th_zone = kzalloc(sizeof(struct exynos_thermal_zone), GFP_KERNEL);
  393. if (!th_zone)
  394. return -ENOMEM;
  395. th_zone->sensor_conf = sensor_conf;
  396. cpumask_set_cpu(0, &mask_val);
  397. th_zone->cool_dev[0] = cpufreq_cooling_register(&mask_val);
  398. if (IS_ERR(th_zone->cool_dev[0])) {
  399. pr_err("Failed to register cpufreq cooling device\n");
  400. ret = -EINVAL;
  401. goto err_unregister;
  402. }
  403. th_zone->cool_dev_size++;
  404. th_zone->therm_dev = thermal_zone_device_register(sensor_conf->name,
  405. EXYNOS_ZONE_COUNT, 0, NULL, &exynos_dev_ops, NULL, 0,
  406. sensor_conf->trip_data.trigger_falling ?
  407. 0 : IDLE_INTERVAL);
  408. if (IS_ERR(th_zone->therm_dev)) {
  409. pr_err("Failed to register thermal zone device\n");
  410. ret = PTR_ERR(th_zone->therm_dev);
  411. goto err_unregister;
  412. }
  413. th_zone->mode = THERMAL_DEVICE_ENABLED;
  414. pr_info("Exynos: Kernel Thermal management registered\n");
  415. return 0;
  416. err_unregister:
  417. exynos_unregister_thermal();
  418. return ret;
  419. }
  420. /* Un-Register with the in-kernel thermal management */
  421. static void exynos_unregister_thermal(void)
  422. {
  423. int i;
  424. if (!th_zone)
  425. return;
  426. if (th_zone->therm_dev)
  427. thermal_zone_device_unregister(th_zone->therm_dev);
  428. for (i = 0; i < th_zone->cool_dev_size; i++) {
  429. if (th_zone->cool_dev[i])
  430. cpufreq_cooling_unregister(th_zone->cool_dev[i]);
  431. }
  432. kfree(th_zone);
  433. pr_info("Exynos: Kernel Thermal management unregistered\n");
  434. }
  435. /*
  436. * TMU treats temperature as a mapped temperature code.
  437. * The temperature is converted differently depending on the calibration type.
  438. */
  439. static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
  440. {
  441. struct exynos_tmu_platform_data *pdata = data->pdata;
  442. int temp_code;
  443. if (data->soc == SOC_ARCH_EXYNOS4210)
  444. /* temp should range between 25 and 125 */
  445. if (temp < 25 || temp > 125) {
  446. temp_code = -EINVAL;
  447. goto out;
  448. }
  449. switch (pdata->cal_type) {
  450. case TYPE_TWO_POINT_TRIMMING:
  451. temp_code = (temp - 25) *
  452. (data->temp_error2 - data->temp_error1) /
  453. (85 - 25) + data->temp_error1;
  454. break;
  455. case TYPE_ONE_POINT_TRIMMING:
  456. temp_code = temp + data->temp_error1 - 25;
  457. break;
  458. default:
  459. temp_code = temp + EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET;
  460. break;
  461. }
  462. out:
  463. return temp_code;
  464. }
  465. /*
  466. * Calculate a temperature value from a temperature code.
  467. * The unit of the temperature is degree Celsius.
  468. */
  469. static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
  470. {
  471. struct exynos_tmu_platform_data *pdata = data->pdata;
  472. int temp;
  473. if (data->soc == SOC_ARCH_EXYNOS4210)
  474. /* temp_code should range between 75 and 175 */
  475. if (temp_code < 75 || temp_code > 175) {
  476. temp = -ENODATA;
  477. goto out;
  478. }
  479. switch (pdata->cal_type) {
  480. case TYPE_TWO_POINT_TRIMMING:
  481. temp = (temp_code - data->temp_error1) * (85 - 25) /
  482. (data->temp_error2 - data->temp_error1) + 25;
  483. break;
  484. case TYPE_ONE_POINT_TRIMMING:
  485. temp = temp_code - data->temp_error1 + 25;
  486. break;
  487. default:
  488. temp = temp_code - EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET;
  489. break;
  490. }
  491. out:
  492. return temp;
  493. }
  494. static int exynos_tmu_initialize(struct platform_device *pdev)
  495. {
  496. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  497. struct exynos_tmu_platform_data *pdata = data->pdata;
  498. unsigned int status, trim_info;
  499. unsigned int rising_threshold = 0, falling_threshold = 0;
  500. int ret = 0, threshold_code, i, trigger_levs = 0;
  501. mutex_lock(&data->lock);
  502. clk_enable(data->clk);
  503. status = readb(data->base + EXYNOS_TMU_REG_STATUS);
  504. if (!status) {
  505. ret = -EBUSY;
  506. goto out;
  507. }
  508. if (data->soc == SOC_ARCH_EXYNOS) {
  509. __raw_writel(EXYNOS_TRIMINFO_RELOAD,
  510. data->base + EXYNOS_TMU_TRIMINFO_CON);
  511. }
  512. /* Save trimming info in order to perform calibration */
  513. trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
  514. data->temp_error1 = trim_info & EXYNOS_TMU_TRIM_TEMP_MASK;
  515. data->temp_error2 = ((trim_info >> 8) & EXYNOS_TMU_TRIM_TEMP_MASK);
  516. if ((EFUSE_MIN_VALUE > data->temp_error1) ||
  517. (data->temp_error1 > EFUSE_MAX_VALUE) ||
  518. (data->temp_error2 != 0))
  519. data->temp_error1 = pdata->efuse_value;
  520. /* Count trigger levels to be enabled */
  521. for (i = 0; i < MAX_THRESHOLD_LEVS; i++)
  522. if (pdata->trigger_levels[i])
  523. trigger_levs++;
  524. if (data->soc == SOC_ARCH_EXYNOS4210) {
  525. /* Write temperature code for threshold */
  526. threshold_code = temp_to_code(data, pdata->threshold);
  527. if (threshold_code < 0) {
  528. ret = threshold_code;
  529. goto out;
  530. }
  531. writeb(threshold_code,
  532. data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
  533. for (i = 0; i < trigger_levs; i++)
  534. writeb(pdata->trigger_levels[i],
  535. data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4);
  536. writel(EXYNOS4210_TMU_INTCLEAR_VAL,
  537. data->base + EXYNOS_TMU_REG_INTCLEAR);
  538. } else if (data->soc == SOC_ARCH_EXYNOS) {
  539. /* Write temperature code for rising and falling threshold */
  540. for (i = 0; i < trigger_levs; i++) {
  541. threshold_code = temp_to_code(data,
  542. pdata->trigger_levels[i]);
  543. if (threshold_code < 0) {
  544. ret = threshold_code;
  545. goto out;
  546. }
  547. rising_threshold |= threshold_code << 8 * i;
  548. if (pdata->threshold_falling) {
  549. threshold_code = temp_to_code(data,
  550. pdata->trigger_levels[i] -
  551. pdata->threshold_falling);
  552. if (threshold_code > 0)
  553. falling_threshold |=
  554. threshold_code << 8 * i;
  555. }
  556. }
  557. writel(rising_threshold,
  558. data->base + EXYNOS_THD_TEMP_RISE);
  559. writel(falling_threshold,
  560. data->base + EXYNOS_THD_TEMP_FALL);
  561. writel(EXYNOS_TMU_CLEAR_RISE_INT | EXYNOS_TMU_CLEAR_FALL_INT,
  562. data->base + EXYNOS_TMU_REG_INTCLEAR);
  563. }
  564. out:
  565. clk_disable(data->clk);
  566. mutex_unlock(&data->lock);
  567. return ret;
  568. }
  569. static void exynos_tmu_control(struct platform_device *pdev, bool on)
  570. {
  571. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  572. struct exynos_tmu_platform_data *pdata = data->pdata;
  573. unsigned int con, interrupt_en;
  574. mutex_lock(&data->lock);
  575. clk_enable(data->clk);
  576. con = pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT |
  577. pdata->gain << EXYNOS_TMU_GAIN_SHIFT;
  578. if (data->soc == SOC_ARCH_EXYNOS) {
  579. con |= pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT;
  580. con |= (EXYNOS_MUX_ADDR_VALUE << EXYNOS_MUX_ADDR_SHIFT);
  581. }
  582. if (on) {
  583. con |= EXYNOS_TMU_CORE_ON;
  584. interrupt_en = pdata->trigger_level3_en << 12 |
  585. pdata->trigger_level2_en << 8 |
  586. pdata->trigger_level1_en << 4 |
  587. pdata->trigger_level0_en;
  588. if (pdata->threshold_falling)
  589. interrupt_en |= interrupt_en << 16;
  590. } else {
  591. con |= EXYNOS_TMU_CORE_OFF;
  592. interrupt_en = 0; /* Disable all interrupts */
  593. }
  594. writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
  595. writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
  596. clk_disable(data->clk);
  597. mutex_unlock(&data->lock);
  598. }
  599. static int exynos_tmu_read(struct exynos_tmu_data *data)
  600. {
  601. u8 temp_code;
  602. int temp;
  603. mutex_lock(&data->lock);
  604. clk_enable(data->clk);
  605. temp_code = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
  606. temp = code_to_temp(data, temp_code);
  607. clk_disable(data->clk);
  608. mutex_unlock(&data->lock);
  609. return temp;
  610. }
  611. #ifdef CONFIG_THERMAL_EMULATION
  612. static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
  613. {
  614. struct exynos_tmu_data *data = drv_data;
  615. unsigned int reg;
  616. int ret = -EINVAL;
  617. if (data->soc == SOC_ARCH_EXYNOS4210)
  618. goto out;
  619. if (temp && temp < MCELSIUS)
  620. goto out;
  621. mutex_lock(&data->lock);
  622. clk_enable(data->clk);
  623. reg = readl(data->base + EXYNOS_EMUL_CON);
  624. if (temp) {
  625. temp /= MCELSIUS;
  626. reg = (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT) |
  627. (temp_to_code(data, temp)
  628. << EXYNOS_EMUL_DATA_SHIFT) | EXYNOS_EMUL_ENABLE;
  629. } else {
  630. reg &= ~EXYNOS_EMUL_ENABLE;
  631. }
  632. writel(reg, data->base + EXYNOS_EMUL_CON);
  633. clk_disable(data->clk);
  634. mutex_unlock(&data->lock);
  635. return 0;
  636. out:
  637. return ret;
  638. }
  639. #else
  640. static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
  641. { return -EINVAL; }
  642. #endif/*CONFIG_THERMAL_EMULATION*/
  643. static void exynos_tmu_work(struct work_struct *work)
  644. {
  645. struct exynos_tmu_data *data = container_of(work,
  646. struct exynos_tmu_data, irq_work);
  647. exynos_report_trigger();
  648. mutex_lock(&data->lock);
  649. clk_enable(data->clk);
  650. if (data->soc == SOC_ARCH_EXYNOS)
  651. writel(EXYNOS_TMU_CLEAR_RISE_INT |
  652. EXYNOS_TMU_CLEAR_FALL_INT,
  653. data->base + EXYNOS_TMU_REG_INTCLEAR);
  654. else
  655. writel(EXYNOS4210_TMU_INTCLEAR_VAL,
  656. data->base + EXYNOS_TMU_REG_INTCLEAR);
  657. clk_disable(data->clk);
  658. mutex_unlock(&data->lock);
  659. enable_irq(data->irq);
  660. }
  661. static irqreturn_t exynos_tmu_irq(int irq, void *id)
  662. {
  663. struct exynos_tmu_data *data = id;
  664. disable_irq_nosync(irq);
  665. schedule_work(&data->irq_work);
  666. return IRQ_HANDLED;
  667. }
  668. static struct thermal_sensor_conf exynos_sensor_conf = {
  669. .name = "exynos-therm",
  670. .read_temperature = (int (*)(void *))exynos_tmu_read,
  671. .write_emul_temp = exynos_tmu_set_emulation,
  672. };
  673. #if defined(CONFIG_CPU_EXYNOS4210)
  674. static struct exynos_tmu_platform_data const exynos4210_default_tmu_data = {
  675. .threshold = 80,
  676. .trigger_levels[0] = 5,
  677. .trigger_levels[1] = 20,
  678. .trigger_levels[2] = 30,
  679. .trigger_level0_en = 1,
  680. .trigger_level1_en = 1,
  681. .trigger_level2_en = 1,
  682. .trigger_level3_en = 0,
  683. .gain = 15,
  684. .reference_voltage = 7,
  685. .cal_type = TYPE_ONE_POINT_TRIMMING,
  686. .freq_tab[0] = {
  687. .freq_clip_max = 800 * 1000,
  688. .temp_level = 85,
  689. },
  690. .freq_tab[1] = {
  691. .freq_clip_max = 200 * 1000,
  692. .temp_level = 100,
  693. },
  694. .freq_tab_count = 2,
  695. .type = SOC_ARCH_EXYNOS4210,
  696. };
  697. #define EXYNOS4210_TMU_DRV_DATA (&exynos4210_default_tmu_data)
  698. #else
  699. #define EXYNOS4210_TMU_DRV_DATA (NULL)
  700. #endif
  701. #if defined(CONFIG_SOC_EXYNOS5250) || defined(CONFIG_SOC_EXYNOS4412) || \
  702. defined(CONFIG_SOC_EXYNOS4212)
  703. static struct exynos_tmu_platform_data const exynos_default_tmu_data = {
  704. .threshold_falling = 10,
  705. .trigger_levels[0] = 85,
  706. .trigger_levels[1] = 103,
  707. .trigger_levels[2] = 110,
  708. .trigger_level0_en = 1,
  709. .trigger_level1_en = 1,
  710. .trigger_level2_en = 1,
  711. .trigger_level3_en = 0,
  712. .gain = 8,
  713. .reference_voltage = 16,
  714. .noise_cancel_mode = 4,
  715. .cal_type = TYPE_ONE_POINT_TRIMMING,
  716. .efuse_value = 55,
  717. .freq_tab[0] = {
  718. .freq_clip_max = 800 * 1000,
  719. .temp_level = 85,
  720. },
  721. .freq_tab[1] = {
  722. .freq_clip_max = 200 * 1000,
  723. .temp_level = 103,
  724. },
  725. .freq_tab_count = 2,
  726. .type = SOC_ARCH_EXYNOS,
  727. };
  728. #define EXYNOS_TMU_DRV_DATA (&exynos_default_tmu_data)
  729. #else
  730. #define EXYNOS_TMU_DRV_DATA (NULL)
  731. #endif
  732. #ifdef CONFIG_OF
  733. static const struct of_device_id exynos_tmu_match[] = {
  734. {
  735. .compatible = "samsung,exynos4210-tmu",
  736. .data = (void *)EXYNOS4210_TMU_DRV_DATA,
  737. },
  738. {
  739. .compatible = "samsung,exynos4412-tmu",
  740. .data = (void *)EXYNOS_TMU_DRV_DATA,
  741. },
  742. {
  743. .compatible = "samsung,exynos5250-tmu",
  744. .data = (void *)EXYNOS_TMU_DRV_DATA,
  745. },
  746. {},
  747. };
  748. MODULE_DEVICE_TABLE(of, exynos_tmu_match);
  749. #endif
  750. static struct platform_device_id exynos_tmu_driver_ids[] = {
  751. {
  752. .name = "exynos4210-tmu",
  753. .driver_data = (kernel_ulong_t)EXYNOS4210_TMU_DRV_DATA,
  754. },
  755. {
  756. .name = "exynos5250-tmu",
  757. .driver_data = (kernel_ulong_t)EXYNOS_TMU_DRV_DATA,
  758. },
  759. { },
  760. };
  761. MODULE_DEVICE_TABLE(platform, exynos_tmu_driver_ids);
  762. static inline struct exynos_tmu_platform_data *exynos_get_driver_data(
  763. struct platform_device *pdev)
  764. {
  765. #ifdef CONFIG_OF
  766. if (pdev->dev.of_node) {
  767. const struct of_device_id *match;
  768. match = of_match_node(exynos_tmu_match, pdev->dev.of_node);
  769. if (!match)
  770. return NULL;
  771. return (struct exynos_tmu_platform_data *) match->data;
  772. }
  773. #endif
  774. return (struct exynos_tmu_platform_data *)
  775. platform_get_device_id(pdev)->driver_data;
  776. }
  777. static int exynos_tmu_probe(struct platform_device *pdev)
  778. {
  779. struct exynos_tmu_data *data;
  780. struct exynos_tmu_platform_data *pdata = pdev->dev.platform_data;
  781. int ret, i;
  782. if (!pdata)
  783. pdata = exynos_get_driver_data(pdev);
  784. if (!pdata) {
  785. dev_err(&pdev->dev, "No platform init data supplied.\n");
  786. return -ENODEV;
  787. }
  788. data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
  789. GFP_KERNEL);
  790. if (!data) {
  791. dev_err(&pdev->dev, "Failed to allocate driver structure\n");
  792. return -ENOMEM;
  793. }
  794. data->irq = platform_get_irq(pdev, 0);
  795. if (data->irq < 0) {
  796. dev_err(&pdev->dev, "Failed to get platform irq\n");
  797. return data->irq;
  798. }
  799. INIT_WORK(&data->irq_work, exynos_tmu_work);
  800. data->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  801. data->base = devm_ioremap_resource(&pdev->dev, data->mem);
  802. if (IS_ERR(data->base))
  803. return PTR_ERR(data->base);
  804. ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
  805. IRQF_TRIGGER_RISING, "exynos-tmu", data);
  806. if (ret) {
  807. dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
  808. return ret;
  809. }
  810. data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
  811. if (IS_ERR(data->clk)) {
  812. dev_err(&pdev->dev, "Failed to get clock\n");
  813. return PTR_ERR(data->clk);
  814. }
  815. ret = clk_prepare(data->clk);
  816. if (ret)
  817. return ret;
  818. if (pdata->type == SOC_ARCH_EXYNOS ||
  819. pdata->type == SOC_ARCH_EXYNOS4210)
  820. data->soc = pdata->type;
  821. else {
  822. ret = -EINVAL;
  823. dev_err(&pdev->dev, "Platform not supported\n");
  824. goto err_clk;
  825. }
  826. data->pdata = pdata;
  827. platform_set_drvdata(pdev, data);
  828. mutex_init(&data->lock);
  829. ret = exynos_tmu_initialize(pdev);
  830. if (ret) {
  831. dev_err(&pdev->dev, "Failed to initialize TMU\n");
  832. goto err_clk;
  833. }
  834. exynos_tmu_control(pdev, true);
  835. /* Register the sensor with thermal management interface */
  836. (&exynos_sensor_conf)->private_data = data;
  837. exynos_sensor_conf.trip_data.trip_count = pdata->trigger_level0_en +
  838. pdata->trigger_level1_en + pdata->trigger_level2_en +
  839. pdata->trigger_level3_en;
  840. for (i = 0; i < exynos_sensor_conf.trip_data.trip_count; i++)
  841. exynos_sensor_conf.trip_data.trip_val[i] =
  842. pdata->threshold + pdata->trigger_levels[i];
  843. exynos_sensor_conf.trip_data.trigger_falling = pdata->threshold_falling;
  844. exynos_sensor_conf.cooling_data.freq_clip_count =
  845. pdata->freq_tab_count;
  846. for (i = 0; i < pdata->freq_tab_count; i++) {
  847. exynos_sensor_conf.cooling_data.freq_data[i].freq_clip_max =
  848. pdata->freq_tab[i].freq_clip_max;
  849. exynos_sensor_conf.cooling_data.freq_data[i].temp_level =
  850. pdata->freq_tab[i].temp_level;
  851. }
  852. ret = exynos_register_thermal(&exynos_sensor_conf);
  853. if (ret) {
  854. dev_err(&pdev->dev, "Failed to register thermal interface\n");
  855. goto err_clk;
  856. }
  857. return 0;
  858. err_clk:
  859. clk_unprepare(data->clk);
  860. return ret;
  861. }
  862. static int exynos_tmu_remove(struct platform_device *pdev)
  863. {
  864. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  865. exynos_tmu_control(pdev, false);
  866. exynos_unregister_thermal();
  867. clk_unprepare(data->clk);
  868. return 0;
  869. }
  870. #ifdef CONFIG_PM_SLEEP
  871. static int exynos_tmu_suspend(struct device *dev)
  872. {
  873. exynos_tmu_control(to_platform_device(dev), false);
  874. return 0;
  875. }
  876. static int exynos_tmu_resume(struct device *dev)
  877. {
  878. struct platform_device *pdev = to_platform_device(dev);
  879. exynos_tmu_initialize(pdev);
  880. exynos_tmu_control(pdev, true);
  881. return 0;
  882. }
  883. static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
  884. exynos_tmu_suspend, exynos_tmu_resume);
  885. #define EXYNOS_TMU_PM (&exynos_tmu_pm)
  886. #else
  887. #define EXYNOS_TMU_PM NULL
  888. #endif
  889. static struct platform_driver exynos_tmu_driver = {
  890. .driver = {
  891. .name = "exynos-tmu",
  892. .owner = THIS_MODULE,
  893. .pm = EXYNOS_TMU_PM,
  894. .of_match_table = of_match_ptr(exynos_tmu_match),
  895. },
  896. .probe = exynos_tmu_probe,
  897. .remove = exynos_tmu_remove,
  898. .id_table = exynos_tmu_driver_ids,
  899. };
  900. module_platform_driver(exynos_tmu_driver);
  901. MODULE_DESCRIPTION("EXYNOS TMU Driver");
  902. MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
  903. MODULE_LICENSE("GPL");
  904. MODULE_ALIAS("platform:exynos-tmu");