tvp7002.c 33 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092
  1. /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
  2. * Digitizer with Horizontal PLL registers
  3. *
  4. * Copyright (C) 2009 Texas Instruments Inc
  5. * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
  6. *
  7. * This code is partially based upon the TVP5150 driver
  8. * written by Mauro Carvalho Chehab (mchehab@infradead.org),
  9. * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com>
  10. * and the TVP7002 driver in the TI LSP 2.10.00.14. Revisions by
  11. * Muralidharan Karicheri and Snehaprabha Narnakaje (TI).
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation; either version 2 of the License, or
  16. * (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26. */
  27. #include <linux/delay.h>
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <linux/videodev2.h>
  31. #include <linux/module.h>
  32. #include <linux/v4l2-dv-timings.h>
  33. #include <media/tvp7002.h>
  34. #include <media/v4l2-device.h>
  35. #include <media/v4l2-common.h>
  36. #include <media/v4l2-ctrls.h>
  37. #include "tvp7002_reg.h"
  38. MODULE_DESCRIPTION("TI TVP7002 Video and Graphics Digitizer driver");
  39. MODULE_AUTHOR("Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>");
  40. MODULE_LICENSE("GPL");
  41. /* I2C retry attempts */
  42. #define I2C_RETRY_COUNT (5)
  43. /* End of registers */
  44. #define TVP7002_EOR 0x5c
  45. /* Read write definition for registers */
  46. #define TVP7002_READ 0
  47. #define TVP7002_WRITE 1
  48. #define TVP7002_RESERVED 2
  49. /* Interlaced vs progressive mask and shift */
  50. #define TVP7002_IP_SHIFT 5
  51. #define TVP7002_INPR_MASK (0x01 << TVP7002_IP_SHIFT)
  52. /* Shift for CPL and LPF registers */
  53. #define TVP7002_CL_SHIFT 8
  54. #define TVP7002_CL_MASK 0x0f
  55. /* Debug functions */
  56. static bool debug;
  57. module_param(debug, bool, 0644);
  58. MODULE_PARM_DESC(debug, "Debug level (0-2)");
  59. /* Structure for register values */
  60. struct i2c_reg_value {
  61. u8 reg;
  62. u8 value;
  63. u8 type;
  64. };
  65. /*
  66. * Register default values (according to tvp7002 datasheet)
  67. * In the case of read-only registers, the value (0xff) is
  68. * never written. R/W functionality is controlled by the
  69. * writable bit in the register struct definition.
  70. */
  71. static const struct i2c_reg_value tvp7002_init_default[] = {
  72. { TVP7002_CHIP_REV, 0xff, TVP7002_READ },
  73. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE },
  74. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE },
  75. { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE },
  76. { TVP7002_HPLL_PHASE_SEL, 0x80, TVP7002_WRITE },
  77. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  78. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  79. { TVP7002_HSYNC_OUT_W, 0x60, TVP7002_WRITE },
  80. { TVP7002_B_FINE_GAIN, 0x00, TVP7002_WRITE },
  81. { TVP7002_G_FINE_GAIN, 0x00, TVP7002_WRITE },
  82. { TVP7002_R_FINE_GAIN, 0x00, TVP7002_WRITE },
  83. { TVP7002_B_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
  84. { TVP7002_G_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
  85. { TVP7002_R_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
  86. { TVP7002_SYNC_CTL_1, 0x20, TVP7002_WRITE },
  87. { TVP7002_HPLL_AND_CLAMP_CTL, 0x2e, TVP7002_WRITE },
  88. { TVP7002_SYNC_ON_G_THRS, 0x5d, TVP7002_WRITE },
  89. { TVP7002_SYNC_SEPARATOR_THRS, 0x47, TVP7002_WRITE },
  90. { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE },
  91. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  92. { TVP7002_SYNC_DETECT_STAT, 0xff, TVP7002_READ },
  93. { TVP7002_OUT_FORMATTER, 0x47, TVP7002_WRITE },
  94. { TVP7002_MISC_CTL_1, 0x01, TVP7002_WRITE },
  95. { TVP7002_MISC_CTL_2, 0x00, TVP7002_WRITE },
  96. { TVP7002_MISC_CTL_3, 0x01, TVP7002_WRITE },
  97. { TVP7002_IN_MUX_SEL_1, 0x00, TVP7002_WRITE },
  98. { TVP7002_IN_MUX_SEL_2, 0x67, TVP7002_WRITE },
  99. { TVP7002_B_AND_G_COARSE_GAIN, 0x77, TVP7002_WRITE },
  100. { TVP7002_R_COARSE_GAIN, 0x07, TVP7002_WRITE },
  101. { TVP7002_FINE_OFF_LSBS, 0x00, TVP7002_WRITE },
  102. { TVP7002_B_COARSE_OFF, 0x10, TVP7002_WRITE },
  103. { TVP7002_G_COARSE_OFF, 0x10, TVP7002_WRITE },
  104. { TVP7002_R_COARSE_OFF, 0x10, TVP7002_WRITE },
  105. { TVP7002_HSOUT_OUT_START, 0x08, TVP7002_WRITE },
  106. { TVP7002_MISC_CTL_4, 0x00, TVP7002_WRITE },
  107. { TVP7002_B_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
  108. { TVP7002_G_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
  109. { TVP7002_R_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
  110. { TVP7002_AUTO_LVL_CTL_ENABLE, 0x80, TVP7002_WRITE },
  111. { TVP7002_DGTL_ALC_OUT_MSBS, 0xff, TVP7002_READ },
  112. { TVP7002_AUTO_LVL_CTL_FILTER, 0x53, TVP7002_WRITE },
  113. { 0x29, 0x08, TVP7002_RESERVED },
  114. { TVP7002_FINE_CLAMP_CTL, 0x07, TVP7002_WRITE },
  115. /* PWR_CTL is controlled only by the probe and reset functions */
  116. { TVP7002_PWR_CTL, 0x00, TVP7002_RESERVED },
  117. { TVP7002_ADC_SETUP, 0x50, TVP7002_WRITE },
  118. { TVP7002_COARSE_CLAMP_CTL, 0x00, TVP7002_WRITE },
  119. { TVP7002_SOG_CLAMP, 0x80, TVP7002_WRITE },
  120. { TVP7002_RGB_COARSE_CLAMP_CTL, 0x8c, TVP7002_WRITE },
  121. { TVP7002_SOG_COARSE_CLAMP_CTL, 0x04, TVP7002_WRITE },
  122. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  123. { 0x32, 0x18, TVP7002_RESERVED },
  124. { 0x33, 0x60, TVP7002_RESERVED },
  125. { TVP7002_MVIS_STRIPPER_W, 0xff, TVP7002_RESERVED },
  126. { TVP7002_VSYNC_ALGN, 0x10, TVP7002_WRITE },
  127. { TVP7002_SYNC_BYPASS, 0x00, TVP7002_WRITE },
  128. { TVP7002_L_FRAME_STAT_LSBS, 0xff, TVP7002_READ },
  129. { TVP7002_L_FRAME_STAT_MSBS, 0xff, TVP7002_READ },
  130. { TVP7002_CLK_L_STAT_LSBS, 0xff, TVP7002_READ },
  131. { TVP7002_CLK_L_STAT_MSBS, 0xff, TVP7002_READ },
  132. { TVP7002_HSYNC_W, 0xff, TVP7002_READ },
  133. { TVP7002_VSYNC_W, 0xff, TVP7002_READ },
  134. { TVP7002_L_LENGTH_TOL, 0x03, TVP7002_WRITE },
  135. { 0x3e, 0x60, TVP7002_RESERVED },
  136. { TVP7002_VIDEO_BWTH_CTL, 0x01, TVP7002_WRITE },
  137. { TVP7002_AVID_START_PIXEL_LSBS, 0x01, TVP7002_WRITE },
  138. { TVP7002_AVID_START_PIXEL_MSBS, 0x2c, TVP7002_WRITE },
  139. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x06, TVP7002_WRITE },
  140. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x2c, TVP7002_WRITE },
  141. { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
  142. { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
  143. { TVP7002_VBLK_F_0_DURATION, 0x1e, TVP7002_WRITE },
  144. { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
  145. { TVP7002_FBIT_F_0_START_L_OFF, 0x00, TVP7002_WRITE },
  146. { TVP7002_FBIT_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
  147. { TVP7002_YUV_Y_G_COEF_LSBS, 0xe3, TVP7002_WRITE },
  148. { TVP7002_YUV_Y_G_COEF_MSBS, 0x16, TVP7002_WRITE },
  149. { TVP7002_YUV_Y_B_COEF_LSBS, 0x4f, TVP7002_WRITE },
  150. { TVP7002_YUV_Y_B_COEF_MSBS, 0x02, TVP7002_WRITE },
  151. { TVP7002_YUV_Y_R_COEF_LSBS, 0xce, TVP7002_WRITE },
  152. { TVP7002_YUV_Y_R_COEF_MSBS, 0x06, TVP7002_WRITE },
  153. { TVP7002_YUV_U_G_COEF_LSBS, 0xab, TVP7002_WRITE },
  154. { TVP7002_YUV_U_G_COEF_MSBS, 0xf3, TVP7002_WRITE },
  155. { TVP7002_YUV_U_B_COEF_LSBS, 0x00, TVP7002_WRITE },
  156. { TVP7002_YUV_U_B_COEF_MSBS, 0x10, TVP7002_WRITE },
  157. { TVP7002_YUV_U_R_COEF_LSBS, 0x55, TVP7002_WRITE },
  158. { TVP7002_YUV_U_R_COEF_MSBS, 0xfc, TVP7002_WRITE },
  159. { TVP7002_YUV_V_G_COEF_LSBS, 0x78, TVP7002_WRITE },
  160. { TVP7002_YUV_V_G_COEF_MSBS, 0xf1, TVP7002_WRITE },
  161. { TVP7002_YUV_V_B_COEF_LSBS, 0x88, TVP7002_WRITE },
  162. { TVP7002_YUV_V_B_COEF_MSBS, 0xfe, TVP7002_WRITE },
  163. { TVP7002_YUV_V_R_COEF_LSBS, 0x00, TVP7002_WRITE },
  164. { TVP7002_YUV_V_R_COEF_MSBS, 0x10, TVP7002_WRITE },
  165. /* This signals end of register values */
  166. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  167. };
  168. /* Register parameters for 480P */
  169. static const struct i2c_reg_value tvp7002_parms_480P[] = {
  170. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x35, TVP7002_WRITE },
  171. { TVP7002_HPLL_FDBK_DIV_LSBS, 0xa0, TVP7002_WRITE },
  172. { TVP7002_HPLL_CRTL, 0x02, TVP7002_WRITE },
  173. { TVP7002_AVID_START_PIXEL_LSBS, 0x91, TVP7002_WRITE },
  174. { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE },
  175. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0B, TVP7002_WRITE },
  176. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE },
  177. { TVP7002_VBLK_F_0_START_L_OFF, 0x03, TVP7002_WRITE },
  178. { TVP7002_VBLK_F_1_START_L_OFF, 0x01, TVP7002_WRITE },
  179. { TVP7002_VBLK_F_0_DURATION, 0x13, TVP7002_WRITE },
  180. { TVP7002_VBLK_F_1_DURATION, 0x13, TVP7002_WRITE },
  181. { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE },
  182. { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE },
  183. { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE },
  184. { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE },
  185. { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE },
  186. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  187. };
  188. /* Register parameters for 576P */
  189. static const struct i2c_reg_value tvp7002_parms_576P[] = {
  190. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x36, TVP7002_WRITE },
  191. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE },
  192. { TVP7002_HPLL_CRTL, 0x18, TVP7002_WRITE },
  193. { TVP7002_AVID_START_PIXEL_LSBS, 0x9B, TVP7002_WRITE },
  194. { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE },
  195. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0F, TVP7002_WRITE },
  196. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE },
  197. { TVP7002_VBLK_F_0_START_L_OFF, 0x00, TVP7002_WRITE },
  198. { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
  199. { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
  200. { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
  201. { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE },
  202. { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE },
  203. { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE },
  204. { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE },
  205. { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE },
  206. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  207. };
  208. /* Register parameters for 1080I60 */
  209. static const struct i2c_reg_value tvp7002_parms_1080I60[] = {
  210. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
  211. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE },
  212. { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
  213. { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
  214. { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
  215. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
  216. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
  217. { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
  218. { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
  219. { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
  220. { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
  221. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  222. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  223. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  224. { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
  225. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  226. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  227. };
  228. /* Register parameters for 1080P60 */
  229. static const struct i2c_reg_value tvp7002_parms_1080P60[] = {
  230. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
  231. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE },
  232. { TVP7002_HPLL_CRTL, 0xE0, TVP7002_WRITE },
  233. { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
  234. { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
  235. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
  236. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
  237. { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
  238. { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
  239. { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
  240. { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
  241. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  242. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  243. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  244. { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
  245. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  246. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  247. };
  248. /* Register parameters for 1080I50 */
  249. static const struct i2c_reg_value tvp7002_parms_1080I50[] = {
  250. { TVP7002_HPLL_FDBK_DIV_MSBS, 0xa5, TVP7002_WRITE },
  251. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE },
  252. { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
  253. { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
  254. { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
  255. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
  256. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
  257. { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
  258. { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
  259. { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
  260. { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
  261. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  262. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  263. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  264. { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
  265. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  266. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  267. };
  268. /* Register parameters for 720P60 */
  269. static const struct i2c_reg_value tvp7002_parms_720P60[] = {
  270. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE },
  271. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE },
  272. { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE },
  273. { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE },
  274. { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
  275. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE },
  276. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE },
  277. { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
  278. { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
  279. { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
  280. { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
  281. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  282. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  283. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  284. { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE },
  285. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  286. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  287. };
  288. /* Register parameters for 720P50 */
  289. static const struct i2c_reg_value tvp7002_parms_720P50[] = {
  290. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x7b, TVP7002_WRITE },
  291. { TVP7002_HPLL_FDBK_DIV_LSBS, 0xc0, TVP7002_WRITE },
  292. { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
  293. { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE },
  294. { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
  295. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE },
  296. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE },
  297. { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
  298. { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
  299. { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
  300. { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
  301. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  302. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  303. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  304. { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
  305. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  306. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  307. };
  308. /* Timings definition for handling device operation */
  309. struct tvp7002_timings_definition {
  310. struct v4l2_dv_timings timings;
  311. const struct i2c_reg_value *p_settings;
  312. enum v4l2_colorspace color_space;
  313. enum v4l2_field scanmode;
  314. u16 progressive;
  315. u16 lines_per_frame;
  316. u16 cpl_min;
  317. u16 cpl_max;
  318. };
  319. /* Struct list for digital video timings */
  320. static const struct tvp7002_timings_definition tvp7002_timings[] = {
  321. {
  322. V4L2_DV_BT_CEA_1280X720P60,
  323. tvp7002_parms_720P60,
  324. V4L2_COLORSPACE_REC709,
  325. V4L2_FIELD_NONE,
  326. 1,
  327. 0x2EE,
  328. 135,
  329. 153
  330. },
  331. {
  332. V4L2_DV_BT_CEA_1920X1080I60,
  333. tvp7002_parms_1080I60,
  334. V4L2_COLORSPACE_REC709,
  335. V4L2_FIELD_INTERLACED,
  336. 0,
  337. 0x465,
  338. 181,
  339. 205
  340. },
  341. {
  342. V4L2_DV_BT_CEA_1920X1080I50,
  343. tvp7002_parms_1080I50,
  344. V4L2_COLORSPACE_REC709,
  345. V4L2_FIELD_INTERLACED,
  346. 0,
  347. 0x465,
  348. 217,
  349. 245
  350. },
  351. {
  352. V4L2_DV_BT_CEA_1280X720P50,
  353. tvp7002_parms_720P50,
  354. V4L2_COLORSPACE_REC709,
  355. V4L2_FIELD_NONE,
  356. 1,
  357. 0x2EE,
  358. 163,
  359. 183
  360. },
  361. {
  362. V4L2_DV_BT_CEA_1920X1080P60,
  363. tvp7002_parms_1080P60,
  364. V4L2_COLORSPACE_REC709,
  365. V4L2_FIELD_NONE,
  366. 1,
  367. 0x465,
  368. 90,
  369. 102
  370. },
  371. {
  372. V4L2_DV_BT_CEA_720X480P59_94,
  373. tvp7002_parms_480P,
  374. V4L2_COLORSPACE_SMPTE170M,
  375. V4L2_FIELD_NONE,
  376. 1,
  377. 0x20D,
  378. 0xffff,
  379. 0xffff
  380. },
  381. {
  382. V4L2_DV_BT_CEA_720X576P50,
  383. tvp7002_parms_576P,
  384. V4L2_COLORSPACE_SMPTE170M,
  385. V4L2_FIELD_NONE,
  386. 1,
  387. 0x271,
  388. 0xffff,
  389. 0xffff
  390. }
  391. };
  392. #define NUM_TIMINGS ARRAY_SIZE(tvp7002_timings)
  393. /* Device definition */
  394. struct tvp7002 {
  395. struct v4l2_subdev sd;
  396. struct v4l2_ctrl_handler hdl;
  397. const struct tvp7002_config *pdata;
  398. int ver;
  399. int streaming;
  400. const struct tvp7002_timings_definition *current_timings;
  401. struct media_pad pad;
  402. };
  403. /*
  404. * to_tvp7002 - Obtain device handler TVP7002
  405. * @sd: ptr to v4l2_subdev struct
  406. *
  407. * Returns device handler tvp7002.
  408. */
  409. static inline struct tvp7002 *to_tvp7002(struct v4l2_subdev *sd)
  410. {
  411. return container_of(sd, struct tvp7002, sd);
  412. }
  413. static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
  414. {
  415. return &container_of(ctrl->handler, struct tvp7002, hdl)->sd;
  416. }
  417. /*
  418. * tvp7002_read - Read a value from a register in an TVP7002
  419. * @sd: ptr to v4l2_subdev struct
  420. * @addr: TVP7002 register address
  421. * @dst: pointer to 8-bit destination
  422. *
  423. * Returns value read if successful, or non-zero (-1) otherwise.
  424. */
  425. static int tvp7002_read(struct v4l2_subdev *sd, u8 addr, u8 *dst)
  426. {
  427. struct i2c_client *c = v4l2_get_subdevdata(sd);
  428. int retry;
  429. int error;
  430. for (retry = 0; retry < I2C_RETRY_COUNT; retry++) {
  431. error = i2c_smbus_read_byte_data(c, addr);
  432. if (error >= 0) {
  433. *dst = (u8)error;
  434. return 0;
  435. }
  436. msleep_interruptible(10);
  437. }
  438. v4l2_err(sd, "TVP7002 read error %d\n", error);
  439. return error;
  440. }
  441. /*
  442. * tvp7002_read_err() - Read a register value with error code
  443. * @sd: pointer to standard V4L2 sub-device structure
  444. * @reg: destination register
  445. * @val: value to be read
  446. * @err: pointer to error value
  447. *
  448. * Read a value in a register and save error value in pointer.
  449. * Also update the register table if successful
  450. */
  451. static inline void tvp7002_read_err(struct v4l2_subdev *sd, u8 reg,
  452. u8 *dst, int *err)
  453. {
  454. if (!*err)
  455. *err = tvp7002_read(sd, reg, dst);
  456. }
  457. /*
  458. * tvp7002_write() - Write a value to a register in TVP7002
  459. * @sd: ptr to v4l2_subdev struct
  460. * @addr: TVP7002 register address
  461. * @value: value to be written to the register
  462. *
  463. * Write a value to a register in an TVP7002 decoder device.
  464. * Returns zero if successful, or non-zero otherwise.
  465. */
  466. static int tvp7002_write(struct v4l2_subdev *sd, u8 addr, u8 value)
  467. {
  468. struct i2c_client *c;
  469. int retry;
  470. int error;
  471. c = v4l2_get_subdevdata(sd);
  472. for (retry = 0; retry < I2C_RETRY_COUNT; retry++) {
  473. error = i2c_smbus_write_byte_data(c, addr, value);
  474. if (error >= 0)
  475. return 0;
  476. v4l2_warn(sd, "Write: retry ... %d\n", retry);
  477. msleep_interruptible(10);
  478. }
  479. v4l2_err(sd, "TVP7002 write error %d\n", error);
  480. return error;
  481. }
  482. /*
  483. * tvp7002_write_err() - Write a register value with error code
  484. * @sd: pointer to standard V4L2 sub-device structure
  485. * @reg: destination register
  486. * @val: value to be written
  487. * @err: pointer to error value
  488. *
  489. * Write a value in a register and save error value in pointer.
  490. * Also update the register table if successful
  491. */
  492. static inline void tvp7002_write_err(struct v4l2_subdev *sd, u8 reg,
  493. u8 val, int *err)
  494. {
  495. if (!*err)
  496. *err = tvp7002_write(sd, reg, val);
  497. }
  498. /*
  499. * tvp7002_write_inittab() - Write initialization values
  500. * @sd: ptr to v4l2_subdev struct
  501. * @regs: ptr to i2c_reg_value struct
  502. *
  503. * Write initialization values.
  504. * Returns zero or -EINVAL if read operation fails.
  505. */
  506. static int tvp7002_write_inittab(struct v4l2_subdev *sd,
  507. const struct i2c_reg_value *regs)
  508. {
  509. int error = 0;
  510. /* Initialize the first (defined) registers */
  511. while (TVP7002_EOR != regs->reg) {
  512. if (TVP7002_WRITE == regs->type)
  513. tvp7002_write_err(sd, regs->reg, regs->value, &error);
  514. regs++;
  515. }
  516. return error;
  517. }
  518. static int tvp7002_s_dv_timings(struct v4l2_subdev *sd,
  519. struct v4l2_dv_timings *dv_timings)
  520. {
  521. struct tvp7002 *device = to_tvp7002(sd);
  522. const struct v4l2_bt_timings *bt = &dv_timings->bt;
  523. int i;
  524. if (dv_timings->type != V4L2_DV_BT_656_1120)
  525. return -EINVAL;
  526. for (i = 0; i < NUM_TIMINGS; i++) {
  527. const struct v4l2_bt_timings *t = &tvp7002_timings[i].timings.bt;
  528. if (!memcmp(bt, t, &bt->standards - &bt->width)) {
  529. device->current_timings = &tvp7002_timings[i];
  530. return tvp7002_write_inittab(sd, tvp7002_timings[i].p_settings);
  531. }
  532. }
  533. return -EINVAL;
  534. }
  535. static int tvp7002_g_dv_timings(struct v4l2_subdev *sd,
  536. struct v4l2_dv_timings *dv_timings)
  537. {
  538. struct tvp7002 *device = to_tvp7002(sd);
  539. *dv_timings = device->current_timings->timings;
  540. return 0;
  541. }
  542. /*
  543. * tvp7002_s_ctrl() - Set a control
  544. * @ctrl: ptr to v4l2_ctrl struct
  545. *
  546. * Set a control in TVP7002 decoder device.
  547. * Returns zero when successful or -EINVAL if register access fails.
  548. */
  549. static int tvp7002_s_ctrl(struct v4l2_ctrl *ctrl)
  550. {
  551. struct v4l2_subdev *sd = to_sd(ctrl);
  552. int error = 0;
  553. switch (ctrl->id) {
  554. case V4L2_CID_GAIN:
  555. tvp7002_write_err(sd, TVP7002_R_FINE_GAIN, ctrl->val, &error);
  556. tvp7002_write_err(sd, TVP7002_G_FINE_GAIN, ctrl->val, &error);
  557. tvp7002_write_err(sd, TVP7002_B_FINE_GAIN, ctrl->val, &error);
  558. return error;
  559. }
  560. return -EINVAL;
  561. }
  562. /*
  563. * tvp7002_mbus_fmt() - V4L2 decoder interface handler for try/s/g_mbus_fmt
  564. * @sd: pointer to standard V4L2 sub-device structure
  565. * @f: pointer to mediabus format structure
  566. *
  567. * Negotiate the image capture size and mediabus format.
  568. * There is only one possible format, so this single function works for
  569. * get, set and try.
  570. */
  571. static int tvp7002_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *f)
  572. {
  573. struct tvp7002 *device = to_tvp7002(sd);
  574. const struct v4l2_bt_timings *bt = &device->current_timings->timings.bt;
  575. f->width = bt->width;
  576. f->height = bt->height;
  577. f->code = V4L2_MBUS_FMT_YUYV10_1X20;
  578. f->field = device->current_timings->scanmode;
  579. f->colorspace = device->current_timings->color_space;
  580. v4l2_dbg(1, debug, sd, "MBUS_FMT: Width - %d, Height - %d",
  581. f->width, f->height);
  582. return 0;
  583. }
  584. /*
  585. * tvp7002_query_dv() - query DV timings
  586. * @sd: pointer to standard V4L2 sub-device structure
  587. * @index: index into the tvp7002_timings array
  588. *
  589. * Returns the current DV timings detected by TVP7002. If no active input is
  590. * detected, returns -EINVAL
  591. */
  592. static int tvp7002_query_dv(struct v4l2_subdev *sd, int *index)
  593. {
  594. const struct tvp7002_timings_definition *timings = tvp7002_timings;
  595. u8 progressive;
  596. u32 lpfr;
  597. u32 cpln;
  598. int error = 0;
  599. u8 lpf_lsb;
  600. u8 lpf_msb;
  601. u8 cpl_lsb;
  602. u8 cpl_msb;
  603. /* Return invalid index if no active input is detected */
  604. *index = NUM_TIMINGS;
  605. /* Read standards from device registers */
  606. tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_LSBS, &lpf_lsb, &error);
  607. tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_MSBS, &lpf_msb, &error);
  608. if (error < 0)
  609. return error;
  610. tvp7002_read_err(sd, TVP7002_CLK_L_STAT_LSBS, &cpl_lsb, &error);
  611. tvp7002_read_err(sd, TVP7002_CLK_L_STAT_MSBS, &cpl_msb, &error);
  612. if (error < 0)
  613. return error;
  614. /* Get lines per frame, clocks per line and interlaced/progresive */
  615. lpfr = lpf_lsb | ((TVP7002_CL_MASK & lpf_msb) << TVP7002_CL_SHIFT);
  616. cpln = cpl_lsb | ((TVP7002_CL_MASK & cpl_msb) << TVP7002_CL_SHIFT);
  617. progressive = (lpf_msb & TVP7002_INPR_MASK) >> TVP7002_IP_SHIFT;
  618. /* Do checking of video modes */
  619. for (*index = 0; *index < NUM_TIMINGS; (*index)++, timings++)
  620. if (lpfr == timings->lines_per_frame &&
  621. progressive == timings->progressive) {
  622. if (timings->cpl_min == 0xffff)
  623. break;
  624. if (cpln >= timings->cpl_min && cpln <= timings->cpl_max)
  625. break;
  626. }
  627. if (*index == NUM_TIMINGS) {
  628. v4l2_dbg(1, debug, sd, "detection failed: lpf = %x, cpl = %x\n",
  629. lpfr, cpln);
  630. return -ENOLINK;
  631. }
  632. /* Update lines per frame and clocks per line info */
  633. v4l2_dbg(1, debug, sd, "detected timings: %d\n", *index);
  634. return 0;
  635. }
  636. static int tvp7002_query_dv_timings(struct v4l2_subdev *sd,
  637. struct v4l2_dv_timings *timings)
  638. {
  639. int index;
  640. int err = tvp7002_query_dv(sd, &index);
  641. if (err)
  642. return err;
  643. *timings = tvp7002_timings[index].timings;
  644. return 0;
  645. }
  646. #ifdef CONFIG_VIDEO_ADV_DEBUG
  647. /*
  648. * tvp7002_g_register() - Get the value of a register
  649. * @sd: ptr to v4l2_subdev struct
  650. * @reg: ptr to v4l2_dbg_register struct
  651. *
  652. * Get the value of a TVP7002 decoder device register.
  653. * Returns zero when successful, -EINVAL if register read fails or
  654. * access to I2C client fails.
  655. */
  656. static int tvp7002_g_register(struct v4l2_subdev *sd,
  657. struct v4l2_dbg_register *reg)
  658. {
  659. u8 val;
  660. int ret;
  661. ret = tvp7002_read(sd, reg->reg & 0xff, &val);
  662. reg->val = val;
  663. reg->size = 1;
  664. return ret;
  665. }
  666. /*
  667. * tvp7002_s_register() - set a control
  668. * @sd: ptr to v4l2_subdev struct
  669. * @reg: ptr to v4l2_dbg_register struct
  670. *
  671. * Get the value of a TVP7002 decoder device register.
  672. * Returns zero when successful, -EINVAL if register read fails.
  673. */
  674. static int tvp7002_s_register(struct v4l2_subdev *sd,
  675. const struct v4l2_dbg_register *reg)
  676. {
  677. return tvp7002_write(sd, reg->reg & 0xff, reg->val & 0xff);
  678. }
  679. #endif
  680. /*
  681. * tvp7002_enum_mbus_fmt() - Enum supported mediabus formats
  682. * @sd: pointer to standard V4L2 sub-device structure
  683. * @index: format index
  684. * @code: pointer to mediabus format
  685. *
  686. * Enumerate supported mediabus formats.
  687. */
  688. static int tvp7002_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index,
  689. enum v4l2_mbus_pixelcode *code)
  690. {
  691. /* Check requested format index is within range */
  692. if (index)
  693. return -EINVAL;
  694. *code = V4L2_MBUS_FMT_YUYV10_1X20;
  695. return 0;
  696. }
  697. /*
  698. * tvp7002_s_stream() - V4L2 decoder i/f handler for s_stream
  699. * @sd: pointer to standard V4L2 sub-device structure
  700. * @enable: streaming enable or disable
  701. *
  702. * Sets streaming to enable or disable, if possible.
  703. */
  704. static int tvp7002_s_stream(struct v4l2_subdev *sd, int enable)
  705. {
  706. struct tvp7002 *device = to_tvp7002(sd);
  707. int error = 0;
  708. if (device->streaming == enable)
  709. return 0;
  710. if (enable) {
  711. /* Set output state on (low impedance means stream on) */
  712. error = tvp7002_write(sd, TVP7002_MISC_CTL_2, 0x00);
  713. device->streaming = enable;
  714. } else {
  715. /* Set output state off (high impedance means stream off) */
  716. error = tvp7002_write(sd, TVP7002_MISC_CTL_2, 0x03);
  717. if (error)
  718. v4l2_dbg(1, debug, sd, "Unable to stop streaming\n");
  719. device->streaming = enable;
  720. }
  721. return error;
  722. }
  723. /*
  724. * tvp7002_log_status() - Print information about register settings
  725. * @sd: ptr to v4l2_subdev struct
  726. *
  727. * Log register values of a TVP7002 decoder device.
  728. * Returns zero or -EINVAL if read operation fails.
  729. */
  730. static int tvp7002_log_status(struct v4l2_subdev *sd)
  731. {
  732. struct tvp7002 *device = to_tvp7002(sd);
  733. const struct v4l2_bt_timings *bt;
  734. int detected;
  735. /* Find my current timings */
  736. tvp7002_query_dv(sd, &detected);
  737. bt = &device->current_timings->timings.bt;
  738. v4l2_info(sd, "Selected DV Timings: %ux%u\n", bt->width, bt->height);
  739. if (detected == NUM_TIMINGS) {
  740. v4l2_info(sd, "Detected DV Timings: None\n");
  741. } else {
  742. bt = &tvp7002_timings[detected].timings.bt;
  743. v4l2_info(sd, "Detected DV Timings: %ux%u\n",
  744. bt->width, bt->height);
  745. }
  746. v4l2_info(sd, "Streaming enabled: %s\n",
  747. device->streaming ? "yes" : "no");
  748. /* Print the current value of the gain control */
  749. v4l2_ctrl_handler_log_status(&device->hdl, sd->name);
  750. return 0;
  751. }
  752. static int tvp7002_enum_dv_timings(struct v4l2_subdev *sd,
  753. struct v4l2_enum_dv_timings *timings)
  754. {
  755. /* Check requested format index is within range */
  756. if (timings->index >= NUM_TIMINGS)
  757. return -EINVAL;
  758. timings->timings = tvp7002_timings[timings->index].timings;
  759. return 0;
  760. }
  761. static const struct v4l2_ctrl_ops tvp7002_ctrl_ops = {
  762. .s_ctrl = tvp7002_s_ctrl,
  763. };
  764. /*
  765. * tvp7002_enum_mbus_code() - Enum supported digital video format on pad
  766. * @sd: pointer to standard V4L2 sub-device structure
  767. * @fh: file handle for the subdev
  768. * @code: pointer to subdev enum mbus code struct
  769. *
  770. * Enumerate supported digital video formats for pad.
  771. */
  772. static int
  773. tvp7002_enum_mbus_code(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
  774. struct v4l2_subdev_mbus_code_enum *code)
  775. {
  776. /* Check requested format index is within range */
  777. if (code->index != 0)
  778. return -EINVAL;
  779. code->code = V4L2_MBUS_FMT_YUYV10_1X20;
  780. return 0;
  781. }
  782. /*
  783. * tvp7002_get_pad_format() - get video format on pad
  784. * @sd: pointer to standard V4L2 sub-device structure
  785. * @fh: file handle for the subdev
  786. * @fmt: pointer to subdev format struct
  787. *
  788. * get video format for pad.
  789. */
  790. static int
  791. tvp7002_get_pad_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
  792. struct v4l2_subdev_format *fmt)
  793. {
  794. struct tvp7002 *tvp7002 = to_tvp7002(sd);
  795. fmt->format.code = V4L2_MBUS_FMT_YUYV10_1X20;
  796. fmt->format.width = tvp7002->current_timings->timings.bt.width;
  797. fmt->format.height = tvp7002->current_timings->timings.bt.height;
  798. fmt->format.field = tvp7002->current_timings->scanmode;
  799. fmt->format.colorspace = tvp7002->current_timings->color_space;
  800. return 0;
  801. }
  802. /*
  803. * tvp7002_set_pad_format() - set video format on pad
  804. * @sd: pointer to standard V4L2 sub-device structure
  805. * @fh: file handle for the subdev
  806. * @fmt: pointer to subdev format struct
  807. *
  808. * set video format for pad.
  809. */
  810. static int
  811. tvp7002_set_pad_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
  812. struct v4l2_subdev_format *fmt)
  813. {
  814. return tvp7002_get_pad_format(sd, fh, fmt);
  815. }
  816. /* V4L2 core operation handlers */
  817. static const struct v4l2_subdev_core_ops tvp7002_core_ops = {
  818. .log_status = tvp7002_log_status,
  819. .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
  820. .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
  821. .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
  822. .g_ctrl = v4l2_subdev_g_ctrl,
  823. .s_ctrl = v4l2_subdev_s_ctrl,
  824. .queryctrl = v4l2_subdev_queryctrl,
  825. .querymenu = v4l2_subdev_querymenu,
  826. #ifdef CONFIG_VIDEO_ADV_DEBUG
  827. .g_register = tvp7002_g_register,
  828. .s_register = tvp7002_s_register,
  829. #endif
  830. };
  831. /* Specific video subsystem operation handlers */
  832. static const struct v4l2_subdev_video_ops tvp7002_video_ops = {
  833. .g_dv_timings = tvp7002_g_dv_timings,
  834. .s_dv_timings = tvp7002_s_dv_timings,
  835. .enum_dv_timings = tvp7002_enum_dv_timings,
  836. .query_dv_timings = tvp7002_query_dv_timings,
  837. .s_stream = tvp7002_s_stream,
  838. .g_mbus_fmt = tvp7002_mbus_fmt,
  839. .try_mbus_fmt = tvp7002_mbus_fmt,
  840. .s_mbus_fmt = tvp7002_mbus_fmt,
  841. .enum_mbus_fmt = tvp7002_enum_mbus_fmt,
  842. };
  843. /* media pad related operation handlers */
  844. static const struct v4l2_subdev_pad_ops tvp7002_pad_ops = {
  845. .enum_mbus_code = tvp7002_enum_mbus_code,
  846. .get_fmt = tvp7002_get_pad_format,
  847. .set_fmt = tvp7002_set_pad_format,
  848. };
  849. /* V4L2 top level operation handlers */
  850. static const struct v4l2_subdev_ops tvp7002_ops = {
  851. .core = &tvp7002_core_ops,
  852. .video = &tvp7002_video_ops,
  853. .pad = &tvp7002_pad_ops,
  854. };
  855. /*
  856. * tvp7002_probe - Probe a TVP7002 device
  857. * @c: ptr to i2c_client struct
  858. * @id: ptr to i2c_device_id struct
  859. *
  860. * Initialize the TVP7002 device
  861. * Returns zero when successful, -EINVAL if register read fails or
  862. * -EIO if i2c access is not available.
  863. */
  864. static int tvp7002_probe(struct i2c_client *c, const struct i2c_device_id *id)
  865. {
  866. struct v4l2_subdev *sd;
  867. struct tvp7002 *device;
  868. struct v4l2_dv_timings timings;
  869. int polarity_a;
  870. int polarity_b;
  871. u8 revision;
  872. int error;
  873. /* Check if the adapter supports the needed features */
  874. if (!i2c_check_functionality(c->adapter,
  875. I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
  876. return -EIO;
  877. if (!c->dev.platform_data) {
  878. v4l_err(c, "No platform data!!\n");
  879. return -ENODEV;
  880. }
  881. device = devm_kzalloc(&c->dev, sizeof(struct tvp7002), GFP_KERNEL);
  882. if (!device)
  883. return -ENOMEM;
  884. sd = &device->sd;
  885. device->pdata = c->dev.platform_data;
  886. device->current_timings = tvp7002_timings;
  887. /* Tell v4l2 the device is ready */
  888. v4l2_i2c_subdev_init(sd, c, &tvp7002_ops);
  889. v4l_info(c, "tvp7002 found @ 0x%02x (%s)\n",
  890. c->addr, c->adapter->name);
  891. error = tvp7002_read(sd, TVP7002_CHIP_REV, &revision);
  892. if (error < 0)
  893. return error;
  894. /* Get revision number */
  895. v4l2_info(sd, "Rev. %02x detected.\n", revision);
  896. if (revision != 0x02)
  897. v4l2_info(sd, "Unknown revision detected.\n");
  898. /* Initializes TVP7002 to its default values */
  899. error = tvp7002_write_inittab(sd, tvp7002_init_default);
  900. if (error < 0)
  901. return error;
  902. /* Set polarity information after registers have been set */
  903. polarity_a = 0x20 | device->pdata->hs_polarity << 5
  904. | device->pdata->vs_polarity << 2;
  905. error = tvp7002_write(sd, TVP7002_SYNC_CTL_1, polarity_a);
  906. if (error < 0)
  907. return error;
  908. polarity_b = 0x01 | device->pdata->fid_polarity << 2
  909. | device->pdata->sog_polarity << 1
  910. | device->pdata->clk_polarity;
  911. error = tvp7002_write(sd, TVP7002_MISC_CTL_3, polarity_b);
  912. if (error < 0)
  913. return error;
  914. /* Set registers according to default video mode */
  915. timings = device->current_timings->timings;
  916. error = tvp7002_s_dv_timings(sd, &timings);
  917. #if defined(CONFIG_MEDIA_CONTROLLER)
  918. device->pad.flags = MEDIA_PAD_FL_SOURCE;
  919. device->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  920. device->sd.entity.flags |= MEDIA_ENT_T_V4L2_SUBDEV_DECODER;
  921. error = media_entity_init(&device->sd.entity, 1, &device->pad, 0);
  922. if (error < 0)
  923. return error;
  924. #endif
  925. v4l2_ctrl_handler_init(&device->hdl, 1);
  926. v4l2_ctrl_new_std(&device->hdl, &tvp7002_ctrl_ops,
  927. V4L2_CID_GAIN, 0, 255, 1, 0);
  928. sd->ctrl_handler = &device->hdl;
  929. if (device->hdl.error) {
  930. error = device->hdl.error;
  931. goto error;
  932. }
  933. v4l2_ctrl_handler_setup(&device->hdl);
  934. return 0;
  935. error:
  936. v4l2_ctrl_handler_free(&device->hdl);
  937. #if defined(CONFIG_MEDIA_CONTROLLER)
  938. media_entity_cleanup(&device->sd.entity);
  939. #endif
  940. return error;
  941. }
  942. /*
  943. * tvp7002_remove - Remove TVP7002 device support
  944. * @c: ptr to i2c_client struct
  945. *
  946. * Reset the TVP7002 device
  947. * Returns zero.
  948. */
  949. static int tvp7002_remove(struct i2c_client *c)
  950. {
  951. struct v4l2_subdev *sd = i2c_get_clientdata(c);
  952. struct tvp7002 *device = to_tvp7002(sd);
  953. v4l2_dbg(1, debug, sd, "Removing tvp7002 adapter"
  954. "on address 0x%x\n", c->addr);
  955. #if defined(CONFIG_MEDIA_CONTROLLER)
  956. media_entity_cleanup(&device->sd.entity);
  957. #endif
  958. v4l2_device_unregister_subdev(sd);
  959. v4l2_ctrl_handler_free(&device->hdl);
  960. return 0;
  961. }
  962. /* I2C Device ID table */
  963. static const struct i2c_device_id tvp7002_id[] = {
  964. { "tvp7002", 0 },
  965. { }
  966. };
  967. MODULE_DEVICE_TABLE(i2c, tvp7002_id);
  968. /* I2C driver data */
  969. static struct i2c_driver tvp7002_driver = {
  970. .driver = {
  971. .owner = THIS_MODULE,
  972. .name = TVP7002_MODULE_NAME,
  973. },
  974. .probe = tvp7002_probe,
  975. .remove = tvp7002_remove,
  976. .id_table = tvp7002_id,
  977. };
  978. module_i2c_driver(tvp7002_driver);