coretemp.c 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860
  1. /*
  2. * coretemp.c - Linux kernel module for hardware monitoring
  3. *
  4. * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
  5. *
  6. * Inspired from many hwmon drivers
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  20. * 02110-1301 USA.
  21. */
  22. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  23. #include <linux/module.h>
  24. #include <linux/init.h>
  25. #include <linux/slab.h>
  26. #include <linux/jiffies.h>
  27. #include <linux/hwmon.h>
  28. #include <linux/sysfs.h>
  29. #include <linux/hwmon-sysfs.h>
  30. #include <linux/err.h>
  31. #include <linux/mutex.h>
  32. #include <linux/list.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/cpu.h>
  35. #include <linux/smp.h>
  36. #include <linux/moduleparam.h>
  37. #include <asm/msr.h>
  38. #include <asm/processor.h>
  39. #include <asm/cpu_device_id.h>
  40. #define DRVNAME "coretemp"
  41. /*
  42. * force_tjmax only matters when TjMax can't be read from the CPU itself.
  43. * When set, it replaces the driver's suboptimal heuristic.
  44. */
  45. static int force_tjmax;
  46. module_param_named(tjmax, force_tjmax, int, 0444);
  47. MODULE_PARM_DESC(tjmax, "TjMax value in degrees Celsius");
  48. #define BASE_SYSFS_ATTR_NO 2 /* Sysfs Base attr no for coretemp */
  49. #define NUM_REAL_CORES 32 /* Number of Real cores per cpu */
  50. #define CORETEMP_NAME_LENGTH 17 /* String Length of attrs */
  51. #define MAX_CORE_ATTRS 4 /* Maximum no of basic attrs */
  52. #define TOTAL_ATTRS (MAX_CORE_ATTRS + 1)
  53. #define MAX_CORE_DATA (NUM_REAL_CORES + BASE_SYSFS_ATTR_NO)
  54. #define TO_PHYS_ID(cpu) (cpu_data(cpu).phys_proc_id)
  55. #define TO_CORE_ID(cpu) (cpu_data(cpu).cpu_core_id)
  56. #define TO_ATTR_NO(cpu) (TO_CORE_ID(cpu) + BASE_SYSFS_ATTR_NO)
  57. #ifdef CONFIG_SMP
  58. #define for_each_sibling(i, cpu) for_each_cpu(i, cpu_sibling_mask(cpu))
  59. #else
  60. #define for_each_sibling(i, cpu) for (i = 0; false; )
  61. #endif
  62. /*
  63. * Per-Core Temperature Data
  64. * @last_updated: The time when the current temperature value was updated
  65. * earlier (in jiffies).
  66. * @cpu_core_id: The CPU Core from which temperature values should be read
  67. * This value is passed as "id" field to rdmsr/wrmsr functions.
  68. * @status_reg: One of IA32_THERM_STATUS or IA32_PACKAGE_THERM_STATUS,
  69. * from where the temperature values should be read.
  70. * @attr_size: Total number of pre-core attrs displayed in the sysfs.
  71. * @is_pkg_data: If this is 1, the temp_data holds pkgtemp data.
  72. * Otherwise, temp_data holds coretemp data.
  73. * @valid: If this is 1, the current temperature is valid.
  74. */
  75. struct temp_data {
  76. int temp;
  77. int ttarget;
  78. int tjmax;
  79. unsigned long last_updated;
  80. unsigned int cpu;
  81. u32 cpu_core_id;
  82. u32 status_reg;
  83. int attr_size;
  84. bool is_pkg_data;
  85. bool valid;
  86. struct sensor_device_attribute sd_attrs[TOTAL_ATTRS];
  87. char attr_name[TOTAL_ATTRS][CORETEMP_NAME_LENGTH];
  88. struct mutex update_lock;
  89. };
  90. /* Platform Data per Physical CPU */
  91. struct platform_data {
  92. struct device *hwmon_dev;
  93. u16 phys_proc_id;
  94. struct temp_data *core_data[MAX_CORE_DATA];
  95. struct device_attribute name_attr;
  96. };
  97. struct pdev_entry {
  98. struct list_head list;
  99. struct platform_device *pdev;
  100. u16 phys_proc_id;
  101. };
  102. static LIST_HEAD(pdev_list);
  103. static DEFINE_MUTEX(pdev_list_mutex);
  104. static ssize_t show_name(struct device *dev,
  105. struct device_attribute *devattr, char *buf)
  106. {
  107. return sprintf(buf, "%s\n", DRVNAME);
  108. }
  109. static ssize_t show_label(struct device *dev,
  110. struct device_attribute *devattr, char *buf)
  111. {
  112. struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  113. struct platform_data *pdata = dev_get_drvdata(dev);
  114. struct temp_data *tdata = pdata->core_data[attr->index];
  115. if (tdata->is_pkg_data)
  116. return sprintf(buf, "Physical id %u\n", pdata->phys_proc_id);
  117. return sprintf(buf, "Core %u\n", tdata->cpu_core_id);
  118. }
  119. static ssize_t show_crit_alarm(struct device *dev,
  120. struct device_attribute *devattr, char *buf)
  121. {
  122. u32 eax, edx;
  123. struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  124. struct platform_data *pdata = dev_get_drvdata(dev);
  125. struct temp_data *tdata = pdata->core_data[attr->index];
  126. rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx);
  127. return sprintf(buf, "%d\n", (eax >> 5) & 1);
  128. }
  129. static ssize_t show_tjmax(struct device *dev,
  130. struct device_attribute *devattr, char *buf)
  131. {
  132. struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  133. struct platform_data *pdata = dev_get_drvdata(dev);
  134. return sprintf(buf, "%d\n", pdata->core_data[attr->index]->tjmax);
  135. }
  136. static ssize_t show_ttarget(struct device *dev,
  137. struct device_attribute *devattr, char *buf)
  138. {
  139. struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  140. struct platform_data *pdata = dev_get_drvdata(dev);
  141. return sprintf(buf, "%d\n", pdata->core_data[attr->index]->ttarget);
  142. }
  143. static ssize_t show_temp(struct device *dev,
  144. struct device_attribute *devattr, char *buf)
  145. {
  146. u32 eax, edx;
  147. struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  148. struct platform_data *pdata = dev_get_drvdata(dev);
  149. struct temp_data *tdata = pdata->core_data[attr->index];
  150. mutex_lock(&tdata->update_lock);
  151. /* Check whether the time interval has elapsed */
  152. if (!tdata->valid || time_after(jiffies, tdata->last_updated + HZ)) {
  153. rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx);
  154. tdata->valid = 0;
  155. /* Check whether the data is valid */
  156. if (eax & 0x80000000) {
  157. tdata->temp = tdata->tjmax -
  158. ((eax >> 16) & 0x7f) * 1000;
  159. tdata->valid = 1;
  160. }
  161. tdata->last_updated = jiffies;
  162. }
  163. mutex_unlock(&tdata->update_lock);
  164. return tdata->valid ? sprintf(buf, "%d\n", tdata->temp) : -EAGAIN;
  165. }
  166. struct tjmax {
  167. char const *id;
  168. int tjmax;
  169. };
  170. static const struct tjmax tjmax_table[] = {
  171. { "CPU 230", 100000 }, /* Model 0x1c, stepping 2 */
  172. { "CPU 330", 125000 }, /* Model 0x1c, stepping 2 */
  173. { "CPU CE4110", 110000 }, /* Model 0x1c, stepping 10 Sodaville */
  174. { "CPU CE4150", 110000 }, /* Model 0x1c, stepping 10 */
  175. { "CPU CE4170", 110000 }, /* Model 0x1c, stepping 10 */
  176. };
  177. struct tjmax_model {
  178. u8 model;
  179. u8 mask;
  180. int tjmax;
  181. };
  182. #define ANY 0xff
  183. static const struct tjmax_model tjmax_model_table[] = {
  184. { 0x1c, 10, 100000 }, /* D4xx, K4xx, N4xx, D5xx, K5xx, N5xx */
  185. { 0x1c, ANY, 90000 }, /* Z5xx, N2xx, possibly others
  186. * Note: Also matches 230 and 330,
  187. * which are covered by tjmax_table
  188. */
  189. { 0x26, ANY, 90000 }, /* Atom Tunnel Creek (Exx), Lincroft (Z6xx)
  190. * Note: TjMax for E6xxT is 110C, but CPU type
  191. * is undetectable by software
  192. */
  193. { 0x27, ANY, 90000 }, /* Atom Medfield (Z2460) */
  194. { 0x35, ANY, 90000 }, /* Atom Clover Trail/Cloverview (Z2760) */
  195. { 0x36, ANY, 100000 }, /* Atom Cedar Trail/Cedarview (N2xxx, D2xxx) */
  196. };
  197. static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
  198. {
  199. /* The 100C is default for both mobile and non mobile CPUs */
  200. int tjmax = 100000;
  201. int tjmax_ee = 85000;
  202. int usemsr_ee = 1;
  203. int err;
  204. u32 eax, edx;
  205. int i;
  206. /* explicit tjmax table entries override heuristics */
  207. for (i = 0; i < ARRAY_SIZE(tjmax_table); i++) {
  208. if (strstr(c->x86_model_id, tjmax_table[i].id))
  209. return tjmax_table[i].tjmax;
  210. }
  211. for (i = 0; i < ARRAY_SIZE(tjmax_model_table); i++) {
  212. const struct tjmax_model *tm = &tjmax_model_table[i];
  213. if (c->x86_model == tm->model &&
  214. (tm->mask == ANY || c->x86_mask == tm->mask))
  215. return tm->tjmax;
  216. }
  217. /* Early chips have no MSR for TjMax */
  218. if (c->x86_model == 0xf && c->x86_mask < 4)
  219. usemsr_ee = 0;
  220. if (c->x86_model > 0xe && usemsr_ee) {
  221. u8 platform_id;
  222. /*
  223. * Now we can detect the mobile CPU using Intel provided table
  224. * http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
  225. * For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU
  226. */
  227. err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx);
  228. if (err) {
  229. dev_warn(dev,
  230. "Unable to access MSR 0x17, assuming desktop"
  231. " CPU\n");
  232. usemsr_ee = 0;
  233. } else if (c->x86_model < 0x17 && !(eax & 0x10000000)) {
  234. /*
  235. * Trust bit 28 up to Penryn, I could not find any
  236. * documentation on that; if you happen to know
  237. * someone at Intel please ask
  238. */
  239. usemsr_ee = 0;
  240. } else {
  241. /* Platform ID bits 52:50 (EDX starts at bit 32) */
  242. platform_id = (edx >> 18) & 0x7;
  243. /*
  244. * Mobile Penryn CPU seems to be platform ID 7 or 5
  245. * (guesswork)
  246. */
  247. if (c->x86_model == 0x17 &&
  248. (platform_id == 5 || platform_id == 7)) {
  249. /*
  250. * If MSR EE bit is set, set it to 90 degrees C,
  251. * otherwise 105 degrees C
  252. */
  253. tjmax_ee = 90000;
  254. tjmax = 105000;
  255. }
  256. }
  257. }
  258. if (usemsr_ee) {
  259. err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx);
  260. if (err) {
  261. dev_warn(dev,
  262. "Unable to access MSR 0xEE, for Tjmax, left"
  263. " at default\n");
  264. } else if (eax & 0x40000000) {
  265. tjmax = tjmax_ee;
  266. }
  267. } else if (tjmax == 100000) {
  268. /*
  269. * If we don't use msr EE it means we are desktop CPU
  270. * (with exeception of Atom)
  271. */
  272. dev_warn(dev, "Using relative temperature scale!\n");
  273. }
  274. return tjmax;
  275. }
  276. static int get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
  277. {
  278. int err;
  279. u32 eax, edx;
  280. u32 val;
  281. /*
  282. * A new feature of current Intel(R) processors, the
  283. * IA32_TEMPERATURE_TARGET contains the TjMax value
  284. */
  285. err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
  286. if (err) {
  287. if (c->x86_model > 0xe && c->x86_model != 0x1c)
  288. dev_warn(dev, "Unable to read TjMax from CPU %u\n", id);
  289. } else {
  290. val = (eax >> 16) & 0xff;
  291. /*
  292. * If the TjMax is not plausible, an assumption
  293. * will be used
  294. */
  295. if (val) {
  296. dev_dbg(dev, "TjMax is %d degrees C\n", val);
  297. return val * 1000;
  298. }
  299. }
  300. if (force_tjmax) {
  301. dev_notice(dev, "TjMax forced to %d degrees C by user\n",
  302. force_tjmax);
  303. return force_tjmax * 1000;
  304. }
  305. /*
  306. * An assumption is made for early CPUs and unreadable MSR.
  307. * NOTE: the calculated value may not be correct.
  308. */
  309. return adjust_tjmax(c, id, dev);
  310. }
  311. static int create_name_attr(struct platform_data *pdata,
  312. struct device *dev)
  313. {
  314. sysfs_attr_init(&pdata->name_attr.attr);
  315. pdata->name_attr.attr.name = "name";
  316. pdata->name_attr.attr.mode = S_IRUGO;
  317. pdata->name_attr.show = show_name;
  318. return device_create_file(dev, &pdata->name_attr);
  319. }
  320. static int create_core_attrs(struct temp_data *tdata, struct device *dev,
  321. int attr_no)
  322. {
  323. int err, i;
  324. static ssize_t (*const rd_ptr[TOTAL_ATTRS]) (struct device *dev,
  325. struct device_attribute *devattr, char *buf) = {
  326. show_label, show_crit_alarm, show_temp, show_tjmax,
  327. show_ttarget };
  328. static const char *const names[TOTAL_ATTRS] = {
  329. "temp%d_label", "temp%d_crit_alarm",
  330. "temp%d_input", "temp%d_crit",
  331. "temp%d_max" };
  332. for (i = 0; i < tdata->attr_size; i++) {
  333. snprintf(tdata->attr_name[i], CORETEMP_NAME_LENGTH, names[i],
  334. attr_no);
  335. sysfs_attr_init(&tdata->sd_attrs[i].dev_attr.attr);
  336. tdata->sd_attrs[i].dev_attr.attr.name = tdata->attr_name[i];
  337. tdata->sd_attrs[i].dev_attr.attr.mode = S_IRUGO;
  338. tdata->sd_attrs[i].dev_attr.show = rd_ptr[i];
  339. tdata->sd_attrs[i].index = attr_no;
  340. err = device_create_file(dev, &tdata->sd_attrs[i].dev_attr);
  341. if (err)
  342. goto exit_free;
  343. }
  344. return 0;
  345. exit_free:
  346. while (--i >= 0)
  347. device_remove_file(dev, &tdata->sd_attrs[i].dev_attr);
  348. return err;
  349. }
  350. static int chk_ucode_version(unsigned int cpu)
  351. {
  352. struct cpuinfo_x86 *c = &cpu_data(cpu);
  353. /*
  354. * Check if we have problem with errata AE18 of Core processors:
  355. * Readings might stop update when processor visited too deep sleep,
  356. * fixed for stepping D0 (6EC).
  357. */
  358. if (c->x86_model == 0xe && c->x86_mask < 0xc && c->microcode < 0x39) {
  359. pr_err("Errata AE18 not fixed, update BIOS or microcode of the CPU!\n");
  360. return -ENODEV;
  361. }
  362. return 0;
  363. }
  364. static struct platform_device *coretemp_get_pdev(unsigned int cpu)
  365. {
  366. u16 phys_proc_id = TO_PHYS_ID(cpu);
  367. struct pdev_entry *p;
  368. mutex_lock(&pdev_list_mutex);
  369. list_for_each_entry(p, &pdev_list, list)
  370. if (p->phys_proc_id == phys_proc_id) {
  371. mutex_unlock(&pdev_list_mutex);
  372. return p->pdev;
  373. }
  374. mutex_unlock(&pdev_list_mutex);
  375. return NULL;
  376. }
  377. static struct temp_data *init_temp_data(unsigned int cpu, int pkg_flag)
  378. {
  379. struct temp_data *tdata;
  380. tdata = kzalloc(sizeof(struct temp_data), GFP_KERNEL);
  381. if (!tdata)
  382. return NULL;
  383. tdata->status_reg = pkg_flag ? MSR_IA32_PACKAGE_THERM_STATUS :
  384. MSR_IA32_THERM_STATUS;
  385. tdata->is_pkg_data = pkg_flag;
  386. tdata->cpu = cpu;
  387. tdata->cpu_core_id = TO_CORE_ID(cpu);
  388. tdata->attr_size = MAX_CORE_ATTRS;
  389. mutex_init(&tdata->update_lock);
  390. return tdata;
  391. }
  392. static int create_core_data(struct platform_device *pdev, unsigned int cpu,
  393. int pkg_flag)
  394. {
  395. struct temp_data *tdata;
  396. struct platform_data *pdata = platform_get_drvdata(pdev);
  397. struct cpuinfo_x86 *c = &cpu_data(cpu);
  398. u32 eax, edx;
  399. int err, attr_no;
  400. /*
  401. * Find attr number for sysfs:
  402. * We map the attr number to core id of the CPU
  403. * The attr number is always core id + 2
  404. * The Pkgtemp will always show up as temp1_*, if available
  405. */
  406. attr_no = pkg_flag ? 1 : TO_ATTR_NO(cpu);
  407. if (attr_no > MAX_CORE_DATA - 1)
  408. return -ERANGE;
  409. /*
  410. * Provide a single set of attributes for all HT siblings of a core
  411. * to avoid duplicate sensors (the processor ID and core ID of all
  412. * HT siblings of a core are the same).
  413. * Skip if a HT sibling of this core is already registered.
  414. * This is not an error.
  415. */
  416. if (pdata->core_data[attr_no] != NULL)
  417. return 0;
  418. tdata = init_temp_data(cpu, pkg_flag);
  419. if (!tdata)
  420. return -ENOMEM;
  421. /* Test if we can access the status register */
  422. err = rdmsr_safe_on_cpu(cpu, tdata->status_reg, &eax, &edx);
  423. if (err)
  424. goto exit_free;
  425. /* We can access status register. Get Critical Temperature */
  426. tdata->tjmax = get_tjmax(c, cpu, &pdev->dev);
  427. /*
  428. * Read the still undocumented bits 8:15 of IA32_TEMPERATURE_TARGET.
  429. * The target temperature is available on older CPUs but not in this
  430. * register. Atoms don't have the register at all.
  431. */
  432. if (c->x86_model > 0xe && c->x86_model != 0x1c) {
  433. err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET,
  434. &eax, &edx);
  435. if (!err) {
  436. tdata->ttarget
  437. = tdata->tjmax - ((eax >> 8) & 0xff) * 1000;
  438. tdata->attr_size++;
  439. }
  440. }
  441. pdata->core_data[attr_no] = tdata;
  442. /* Create sysfs interfaces */
  443. err = create_core_attrs(tdata, &pdev->dev, attr_no);
  444. if (err)
  445. goto exit_free;
  446. return 0;
  447. exit_free:
  448. pdata->core_data[attr_no] = NULL;
  449. kfree(tdata);
  450. return err;
  451. }
  452. static void coretemp_add_core(unsigned int cpu, int pkg_flag)
  453. {
  454. struct platform_device *pdev = coretemp_get_pdev(cpu);
  455. int err;
  456. if (!pdev)
  457. return;
  458. err = create_core_data(pdev, cpu, pkg_flag);
  459. if (err)
  460. dev_err(&pdev->dev, "Adding Core %u failed\n", cpu);
  461. }
  462. static void coretemp_remove_core(struct platform_data *pdata,
  463. struct device *dev, int indx)
  464. {
  465. int i;
  466. struct temp_data *tdata = pdata->core_data[indx];
  467. /* Remove the sysfs attributes */
  468. for (i = 0; i < tdata->attr_size; i++)
  469. device_remove_file(dev, &tdata->sd_attrs[i].dev_attr);
  470. kfree(pdata->core_data[indx]);
  471. pdata->core_data[indx] = NULL;
  472. }
  473. static int coretemp_probe(struct platform_device *pdev)
  474. {
  475. struct platform_data *pdata;
  476. int err;
  477. /* Initialize the per-package data structures */
  478. pdata = kzalloc(sizeof(struct platform_data), GFP_KERNEL);
  479. if (!pdata)
  480. return -ENOMEM;
  481. err = create_name_attr(pdata, &pdev->dev);
  482. if (err)
  483. goto exit_free;
  484. pdata->phys_proc_id = pdev->id;
  485. platform_set_drvdata(pdev, pdata);
  486. pdata->hwmon_dev = hwmon_device_register(&pdev->dev);
  487. if (IS_ERR(pdata->hwmon_dev)) {
  488. err = PTR_ERR(pdata->hwmon_dev);
  489. dev_err(&pdev->dev, "Class registration failed (%d)\n", err);
  490. goto exit_name;
  491. }
  492. return 0;
  493. exit_name:
  494. device_remove_file(&pdev->dev, &pdata->name_attr);
  495. exit_free:
  496. kfree(pdata);
  497. return err;
  498. }
  499. static int coretemp_remove(struct platform_device *pdev)
  500. {
  501. struct platform_data *pdata = platform_get_drvdata(pdev);
  502. int i;
  503. for (i = MAX_CORE_DATA - 1; i >= 0; --i)
  504. if (pdata->core_data[i])
  505. coretemp_remove_core(pdata, &pdev->dev, i);
  506. device_remove_file(&pdev->dev, &pdata->name_attr);
  507. hwmon_device_unregister(pdata->hwmon_dev);
  508. kfree(pdata);
  509. return 0;
  510. }
  511. static struct platform_driver coretemp_driver = {
  512. .driver = {
  513. .owner = THIS_MODULE,
  514. .name = DRVNAME,
  515. },
  516. .probe = coretemp_probe,
  517. .remove = coretemp_remove,
  518. };
  519. static int coretemp_device_add(unsigned int cpu)
  520. {
  521. int err;
  522. struct platform_device *pdev;
  523. struct pdev_entry *pdev_entry;
  524. mutex_lock(&pdev_list_mutex);
  525. pdev = platform_device_alloc(DRVNAME, TO_PHYS_ID(cpu));
  526. if (!pdev) {
  527. err = -ENOMEM;
  528. pr_err("Device allocation failed\n");
  529. goto exit;
  530. }
  531. pdev_entry = kzalloc(sizeof(struct pdev_entry), GFP_KERNEL);
  532. if (!pdev_entry) {
  533. err = -ENOMEM;
  534. goto exit_device_put;
  535. }
  536. err = platform_device_add(pdev);
  537. if (err) {
  538. pr_err("Device addition failed (%d)\n", err);
  539. goto exit_device_free;
  540. }
  541. pdev_entry->pdev = pdev;
  542. pdev_entry->phys_proc_id = pdev->id;
  543. list_add_tail(&pdev_entry->list, &pdev_list);
  544. mutex_unlock(&pdev_list_mutex);
  545. return 0;
  546. exit_device_free:
  547. kfree(pdev_entry);
  548. exit_device_put:
  549. platform_device_put(pdev);
  550. exit:
  551. mutex_unlock(&pdev_list_mutex);
  552. return err;
  553. }
  554. static void coretemp_device_remove(unsigned int cpu)
  555. {
  556. struct pdev_entry *p, *n;
  557. u16 phys_proc_id = TO_PHYS_ID(cpu);
  558. mutex_lock(&pdev_list_mutex);
  559. list_for_each_entry_safe(p, n, &pdev_list, list) {
  560. if (p->phys_proc_id != phys_proc_id)
  561. continue;
  562. platform_device_unregister(p->pdev);
  563. list_del(&p->list);
  564. kfree(p);
  565. }
  566. mutex_unlock(&pdev_list_mutex);
  567. }
  568. static bool is_any_core_online(struct platform_data *pdata)
  569. {
  570. int i;
  571. /* Find online cores, except pkgtemp data */
  572. for (i = MAX_CORE_DATA - 1; i >= 0; --i) {
  573. if (pdata->core_data[i] &&
  574. !pdata->core_data[i]->is_pkg_data) {
  575. return true;
  576. }
  577. }
  578. return false;
  579. }
  580. static void get_core_online(unsigned int cpu)
  581. {
  582. struct cpuinfo_x86 *c = &cpu_data(cpu);
  583. struct platform_device *pdev = coretemp_get_pdev(cpu);
  584. int err;
  585. /*
  586. * CPUID.06H.EAX[0] indicates whether the CPU has thermal
  587. * sensors. We check this bit only, all the early CPUs
  588. * without thermal sensors will be filtered out.
  589. */
  590. if (!cpu_has(c, X86_FEATURE_DTHERM))
  591. return;
  592. if (!pdev) {
  593. /* Check the microcode version of the CPU */
  594. if (chk_ucode_version(cpu))
  595. return;
  596. /*
  597. * Alright, we have DTS support.
  598. * We are bringing the _first_ core in this pkg
  599. * online. So, initialize per-pkg data structures and
  600. * then bring this core online.
  601. */
  602. err = coretemp_device_add(cpu);
  603. if (err)
  604. return;
  605. /*
  606. * Check whether pkgtemp support is available.
  607. * If so, add interfaces for pkgtemp.
  608. */
  609. if (cpu_has(c, X86_FEATURE_PTS))
  610. coretemp_add_core(cpu, 1);
  611. }
  612. /*
  613. * Physical CPU device already exists.
  614. * So, just add interfaces for this core.
  615. */
  616. coretemp_add_core(cpu, 0);
  617. }
  618. static void put_core_offline(unsigned int cpu)
  619. {
  620. int i, indx;
  621. struct platform_data *pdata;
  622. struct platform_device *pdev = coretemp_get_pdev(cpu);
  623. /* If the physical CPU device does not exist, just return */
  624. if (!pdev)
  625. return;
  626. pdata = platform_get_drvdata(pdev);
  627. indx = TO_ATTR_NO(cpu);
  628. /* The core id is too big, just return */
  629. if (indx > MAX_CORE_DATA - 1)
  630. return;
  631. if (pdata->core_data[indx] && pdata->core_data[indx]->cpu == cpu)
  632. coretemp_remove_core(pdata, &pdev->dev, indx);
  633. /*
  634. * If a HT sibling of a core is taken offline, but another HT sibling
  635. * of the same core is still online, register the alternate sibling.
  636. * This ensures that exactly one set of attributes is provided as long
  637. * as at least one HT sibling of a core is online.
  638. */
  639. for_each_sibling(i, cpu) {
  640. if (i != cpu) {
  641. get_core_online(i);
  642. /*
  643. * Display temperature sensor data for one HT sibling
  644. * per core only, so abort the loop after one such
  645. * sibling has been found.
  646. */
  647. break;
  648. }
  649. }
  650. /*
  651. * If all cores in this pkg are offline, remove the device.
  652. * coretemp_device_remove calls unregister_platform_device,
  653. * which in turn calls coretemp_remove. This removes the
  654. * pkgtemp entry and does other clean ups.
  655. */
  656. if (!is_any_core_online(pdata))
  657. coretemp_device_remove(cpu);
  658. }
  659. static int coretemp_cpu_callback(struct notifier_block *nfb,
  660. unsigned long action, void *hcpu)
  661. {
  662. unsigned int cpu = (unsigned long) hcpu;
  663. switch (action) {
  664. case CPU_ONLINE:
  665. case CPU_DOWN_FAILED:
  666. get_core_online(cpu);
  667. break;
  668. case CPU_DOWN_PREPARE:
  669. put_core_offline(cpu);
  670. break;
  671. }
  672. return NOTIFY_OK;
  673. }
  674. static struct notifier_block coretemp_cpu_notifier __refdata = {
  675. .notifier_call = coretemp_cpu_callback,
  676. };
  677. static const struct x86_cpu_id __initconst coretemp_ids[] = {
  678. { X86_VENDOR_INTEL, X86_FAMILY_ANY, X86_MODEL_ANY, X86_FEATURE_DTHERM },
  679. {}
  680. };
  681. MODULE_DEVICE_TABLE(x86cpu, coretemp_ids);
  682. static int __init coretemp_init(void)
  683. {
  684. int i, err;
  685. /*
  686. * CPUID.06H.EAX[0] indicates whether the CPU has thermal
  687. * sensors. We check this bit only, all the early CPUs
  688. * without thermal sensors will be filtered out.
  689. */
  690. if (!x86_match_cpu(coretemp_ids))
  691. return -ENODEV;
  692. err = platform_driver_register(&coretemp_driver);
  693. if (err)
  694. goto exit;
  695. get_online_cpus();
  696. for_each_online_cpu(i)
  697. get_core_online(i);
  698. #ifndef CONFIG_HOTPLUG_CPU
  699. if (list_empty(&pdev_list)) {
  700. put_online_cpus();
  701. err = -ENODEV;
  702. goto exit_driver_unreg;
  703. }
  704. #endif
  705. register_hotcpu_notifier(&coretemp_cpu_notifier);
  706. put_online_cpus();
  707. return 0;
  708. #ifndef CONFIG_HOTPLUG_CPU
  709. exit_driver_unreg:
  710. platform_driver_unregister(&coretemp_driver);
  711. #endif
  712. exit:
  713. return err;
  714. }
  715. static void __exit coretemp_exit(void)
  716. {
  717. struct pdev_entry *p, *n;
  718. get_online_cpus();
  719. unregister_hotcpu_notifier(&coretemp_cpu_notifier);
  720. mutex_lock(&pdev_list_mutex);
  721. list_for_each_entry_safe(p, n, &pdev_list, list) {
  722. platform_device_unregister(p->pdev);
  723. list_del(&p->list);
  724. kfree(p);
  725. }
  726. mutex_unlock(&pdev_list_mutex);
  727. put_online_cpus();
  728. platform_driver_unregister(&coretemp_driver);
  729. }
  730. MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>");
  731. MODULE_DESCRIPTION("Intel Core temperature monitor");
  732. MODULE_LICENSE("GPL");
  733. module_init(coretemp_init)
  734. module_exit(coretemp_exit)