dma.h 11 KB

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  1. /*
  2. * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 2 of the License, or (at your option)
  7. * any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59
  16. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called COPYING.
  20. */
  21. #ifndef IOATDMA_H
  22. #define IOATDMA_H
  23. #include <linux/dmaengine.h>
  24. #include "hw.h"
  25. #include "registers.h"
  26. #include <linux/init.h>
  27. #include <linux/dmapool.h>
  28. #include <linux/cache.h>
  29. #include <linux/pci_ids.h>
  30. #include <net/tcp.h>
  31. #define IOAT_DMA_VERSION "4.00"
  32. #define IOAT_LOW_COMPLETION_MASK 0xffffffc0
  33. #define IOAT_DMA_DCA_ANY_CPU ~0
  34. #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
  35. #define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
  36. #define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd)
  37. #define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev)
  38. #define to_pdev(ioat_chan) ((ioat_chan)->device->pdev)
  39. #define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
  40. /*
  41. * workaround for IOAT ver.3.0 null descriptor issue
  42. * (channel returns error when size is 0)
  43. */
  44. #define NULL_DESC_BUFFER_SIZE 1
  45. enum ioat_irq_mode {
  46. IOAT_NOIRQ = 0,
  47. IOAT_MSIX,
  48. IOAT_MSIX_SINGLE,
  49. IOAT_MSI,
  50. IOAT_INTX
  51. };
  52. /**
  53. * struct ioatdma_device - internal representation of a IOAT device
  54. * @pdev: PCI-Express device
  55. * @reg_base: MMIO register space base address
  56. * @dma_pool: for allocating DMA descriptors
  57. * @common: embedded struct dma_device
  58. * @version: version of ioatdma device
  59. * @msix_entries: irq handlers
  60. * @idx: per channel data
  61. * @dca: direct cache access context
  62. * @intr_quirk: interrupt setup quirk (for ioat_v1 devices)
  63. * @enumerate_channels: hw version specific channel enumeration
  64. * @reset_hw: hw version specific channel (re)initialization
  65. * @cleanup_fn: select between the v2 and v3 cleanup routines
  66. * @timer_fn: select between the v2 and v3 timer watchdog routines
  67. * @self_test: hardware version specific self test for each supported op type
  68. *
  69. * Note: the v3 cleanup routine supports raid operations
  70. */
  71. struct ioatdma_device {
  72. struct pci_dev *pdev;
  73. void __iomem *reg_base;
  74. struct pci_pool *dma_pool;
  75. struct pci_pool *completion_pool;
  76. #define MAX_SED_POOLS 5
  77. struct dma_pool *sed_hw_pool[MAX_SED_POOLS];
  78. struct kmem_cache *sed_pool;
  79. struct dma_device common;
  80. u8 version;
  81. struct msix_entry msix_entries[4];
  82. struct ioat_chan_common *idx[4];
  83. struct dca_provider *dca;
  84. enum ioat_irq_mode irq_mode;
  85. u32 cap;
  86. void (*intr_quirk)(struct ioatdma_device *device);
  87. int (*enumerate_channels)(struct ioatdma_device *device);
  88. int (*reset_hw)(struct ioat_chan_common *chan);
  89. void (*cleanup_fn)(unsigned long data);
  90. void (*timer_fn)(unsigned long data);
  91. int (*self_test)(struct ioatdma_device *device);
  92. };
  93. struct ioat_chan_common {
  94. struct dma_chan common;
  95. void __iomem *reg_base;
  96. dma_addr_t last_completion;
  97. spinlock_t cleanup_lock;
  98. unsigned long state;
  99. #define IOAT_COMPLETION_PENDING 0
  100. #define IOAT_COMPLETION_ACK 1
  101. #define IOAT_RESET_PENDING 2
  102. #define IOAT_KOBJ_INIT_FAIL 3
  103. #define IOAT_RESHAPE_PENDING 4
  104. #define IOAT_RUN 5
  105. #define IOAT_CHAN_ACTIVE 6
  106. struct timer_list timer;
  107. #define COMPLETION_TIMEOUT msecs_to_jiffies(100)
  108. #define IDLE_TIMEOUT msecs_to_jiffies(2000)
  109. #define RESET_DELAY msecs_to_jiffies(100)
  110. struct ioatdma_device *device;
  111. dma_addr_t completion_dma;
  112. u64 *completion;
  113. struct tasklet_struct cleanup_task;
  114. struct kobject kobj;
  115. };
  116. struct ioat_sysfs_entry {
  117. struct attribute attr;
  118. ssize_t (*show)(struct dma_chan *, char *);
  119. };
  120. /**
  121. * struct ioat_dma_chan - internal representation of a DMA channel
  122. */
  123. struct ioat_dma_chan {
  124. struct ioat_chan_common base;
  125. size_t xfercap; /* XFERCAP register value expanded out */
  126. spinlock_t desc_lock;
  127. struct list_head free_desc;
  128. struct list_head used_desc;
  129. int pending;
  130. u16 desccount;
  131. u16 active;
  132. };
  133. /**
  134. * struct ioat_sed_ent - wrapper around super extended hardware descriptor
  135. * @hw: hardware SED
  136. * @sed_dma: dma address for the SED
  137. * @list: list member
  138. * @parent: point to the dma descriptor that's the parent
  139. */
  140. struct ioat_sed_ent {
  141. struct ioat_sed_raw_descriptor *hw;
  142. dma_addr_t dma;
  143. struct ioat_ring_ent *parent;
  144. unsigned int hw_pool;
  145. };
  146. static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c)
  147. {
  148. return container_of(c, struct ioat_chan_common, common);
  149. }
  150. static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c)
  151. {
  152. struct ioat_chan_common *chan = to_chan_common(c);
  153. return container_of(chan, struct ioat_dma_chan, base);
  154. }
  155. /* wrapper around hardware descriptor format + additional software fields */
  156. /**
  157. * struct ioat_desc_sw - wrapper around hardware descriptor
  158. * @hw: hardware DMA descriptor (for memcpy)
  159. * @node: this descriptor will either be on the free list,
  160. * or attached to a transaction list (tx_list)
  161. * @txd: the generic software descriptor for all engines
  162. * @id: identifier for debug
  163. */
  164. struct ioat_desc_sw {
  165. struct ioat_dma_descriptor *hw;
  166. struct list_head node;
  167. size_t len;
  168. struct list_head tx_list;
  169. struct dma_async_tx_descriptor txd;
  170. #ifdef DEBUG
  171. int id;
  172. #endif
  173. };
  174. #ifdef DEBUG
  175. #define set_desc_id(desc, i) ((desc)->id = (i))
  176. #define desc_id(desc) ((desc)->id)
  177. #else
  178. #define set_desc_id(desc, i)
  179. #define desc_id(desc) (0)
  180. #endif
  181. static inline void
  182. __dump_desc_dbg(struct ioat_chan_common *chan, struct ioat_dma_descriptor *hw,
  183. struct dma_async_tx_descriptor *tx, int id)
  184. {
  185. struct device *dev = to_dev(chan);
  186. dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x"
  187. " ctl: %#10.8x (op: %#x int_en: %d compl: %d)\n", id,
  188. (unsigned long long) tx->phys,
  189. (unsigned long long) hw->next, tx->cookie, tx->flags,
  190. hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write);
  191. }
  192. #define dump_desc_dbg(c, d) \
  193. ({ if (d) __dump_desc_dbg(&c->base, d->hw, &d->txd, desc_id(d)); 0; })
  194. static inline void ioat_set_tcp_copy_break(unsigned long copybreak)
  195. {
  196. #ifdef CONFIG_NET_DMA
  197. sysctl_tcp_dma_copybreak = copybreak;
  198. #endif
  199. }
  200. static inline struct ioat_chan_common *
  201. ioat_chan_by_index(struct ioatdma_device *device, int index)
  202. {
  203. return device->idx[index];
  204. }
  205. static inline u64 ioat_chansts_32(struct ioat_chan_common *chan)
  206. {
  207. u8 ver = chan->device->version;
  208. u64 status;
  209. u32 status_lo;
  210. /* We need to read the low address first as this causes the
  211. * chipset to latch the upper bits for the subsequent read
  212. */
  213. status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver));
  214. status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver));
  215. status <<= 32;
  216. status |= status_lo;
  217. return status;
  218. }
  219. #if BITS_PER_LONG == 64
  220. static inline u64 ioat_chansts(struct ioat_chan_common *chan)
  221. {
  222. u8 ver = chan->device->version;
  223. u64 status;
  224. /* With IOAT v3.3 the status register is 64bit. */
  225. if (ver >= IOAT_VER_3_3)
  226. status = readq(chan->reg_base + IOAT_CHANSTS_OFFSET(ver));
  227. else
  228. status = ioat_chansts_32(chan);
  229. return status;
  230. }
  231. #else
  232. #define ioat_chansts ioat_chansts_32
  233. #endif
  234. static inline void ioat_start(struct ioat_chan_common *chan)
  235. {
  236. u8 ver = chan->device->version;
  237. writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
  238. }
  239. static inline u64 ioat_chansts_to_addr(u64 status)
  240. {
  241. return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
  242. }
  243. static inline u32 ioat_chanerr(struct ioat_chan_common *chan)
  244. {
  245. return readl(chan->reg_base + IOAT_CHANERR_OFFSET);
  246. }
  247. static inline void ioat_suspend(struct ioat_chan_common *chan)
  248. {
  249. u8 ver = chan->device->version;
  250. writeb(IOAT_CHANCMD_SUSPEND, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
  251. }
  252. static inline void ioat_reset(struct ioat_chan_common *chan)
  253. {
  254. u8 ver = chan->device->version;
  255. writeb(IOAT_CHANCMD_RESET, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
  256. }
  257. static inline bool ioat_reset_pending(struct ioat_chan_common *chan)
  258. {
  259. u8 ver = chan->device->version;
  260. u8 cmd;
  261. cmd = readb(chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
  262. return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET;
  263. }
  264. static inline void ioat_set_chainaddr(struct ioat_dma_chan *ioat, u64 addr)
  265. {
  266. struct ioat_chan_common *chan = &ioat->base;
  267. writel(addr & 0x00000000FFFFFFFF,
  268. chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
  269. writel(addr >> 32,
  270. chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
  271. }
  272. static inline bool is_ioat_active(unsigned long status)
  273. {
  274. return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE);
  275. }
  276. static inline bool is_ioat_idle(unsigned long status)
  277. {
  278. return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE);
  279. }
  280. static inline bool is_ioat_halted(unsigned long status)
  281. {
  282. return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED);
  283. }
  284. static inline bool is_ioat_suspended(unsigned long status)
  285. {
  286. return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED);
  287. }
  288. /* channel was fatally programmed */
  289. static inline bool is_ioat_bug(unsigned long err)
  290. {
  291. return !!err;
  292. }
  293. static inline void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len,
  294. int direction, enum dma_ctrl_flags flags, bool dst)
  295. {
  296. if ((dst && (flags & DMA_COMPL_DEST_UNMAP_SINGLE)) ||
  297. (!dst && (flags & DMA_COMPL_SRC_UNMAP_SINGLE)))
  298. pci_unmap_single(pdev, addr, len, direction);
  299. else
  300. pci_unmap_page(pdev, addr, len, direction);
  301. }
  302. int ioat_probe(struct ioatdma_device *device);
  303. int ioat_register(struct ioatdma_device *device);
  304. int ioat1_dma_probe(struct ioatdma_device *dev, int dca);
  305. int ioat_dma_self_test(struct ioatdma_device *device);
  306. void ioat_dma_remove(struct ioatdma_device *device);
  307. struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
  308. dma_addr_t ioat_get_current_completion(struct ioat_chan_common *chan);
  309. void ioat_init_channel(struct ioatdma_device *device,
  310. struct ioat_chan_common *chan, int idx);
  311. enum dma_status ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
  312. struct dma_tx_state *txstate);
  313. void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags,
  314. size_t len, struct ioat_dma_descriptor *hw);
  315. bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
  316. dma_addr_t *phys_complete);
  317. void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type);
  318. void ioat_kobject_del(struct ioatdma_device *device);
  319. int ioat_dma_setup_interrupts(struct ioatdma_device *device);
  320. extern const struct sysfs_ops ioat_sysfs_ops;
  321. extern struct ioat_sysfs_entry ioat_version_attr;
  322. extern struct ioat_sysfs_entry ioat_cap_attr;
  323. #endif /* IOATDMA_H */