imx6q-cpufreq.c 8.8 KB

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  1. /*
  2. * Copyright (C) 2013 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/cpufreq.h>
  10. #include <linux/delay.h>
  11. #include <linux/err.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/opp.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/regulator/consumer.h>
  17. #define PU_SOC_VOLTAGE_NORMAL 1250000
  18. #define PU_SOC_VOLTAGE_HIGH 1275000
  19. #define FREQ_1P2_GHZ 1200000000
  20. static struct regulator *arm_reg;
  21. static struct regulator *pu_reg;
  22. static struct regulator *soc_reg;
  23. static struct clk *arm_clk;
  24. static struct clk *pll1_sys_clk;
  25. static struct clk *pll1_sw_clk;
  26. static struct clk *step_clk;
  27. static struct clk *pll2_pfd2_396m_clk;
  28. static struct device *cpu_dev;
  29. static struct cpufreq_frequency_table *freq_table;
  30. static unsigned int transition_latency;
  31. static int imx6q_verify_speed(struct cpufreq_policy *policy)
  32. {
  33. return cpufreq_frequency_table_verify(policy, freq_table);
  34. }
  35. static unsigned int imx6q_get_speed(unsigned int cpu)
  36. {
  37. return clk_get_rate(arm_clk) / 1000;
  38. }
  39. static int imx6q_set_target(struct cpufreq_policy *policy,
  40. unsigned int target_freq, unsigned int relation)
  41. {
  42. struct cpufreq_freqs freqs;
  43. struct opp *opp;
  44. unsigned long freq_hz, volt, volt_old;
  45. unsigned int index;
  46. int ret;
  47. ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
  48. relation, &index);
  49. if (ret) {
  50. dev_err(cpu_dev, "failed to match target frequency %d: %d\n",
  51. target_freq, ret);
  52. return ret;
  53. }
  54. freqs.new = freq_table[index].frequency;
  55. freq_hz = freqs.new * 1000;
  56. freqs.old = clk_get_rate(arm_clk) / 1000;
  57. if (freqs.old == freqs.new)
  58. return 0;
  59. rcu_read_lock();
  60. opp = opp_find_freq_ceil(cpu_dev, &freq_hz);
  61. if (IS_ERR(opp)) {
  62. rcu_read_unlock();
  63. dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
  64. return PTR_ERR(opp);
  65. }
  66. volt = opp_get_voltage(opp);
  67. rcu_read_unlock();
  68. volt_old = regulator_get_voltage(arm_reg);
  69. dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
  70. freqs.old / 1000, volt_old / 1000,
  71. freqs.new / 1000, volt / 1000);
  72. cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
  73. /* scaling up? scale voltage before frequency */
  74. if (freqs.new > freqs.old) {
  75. ret = regulator_set_voltage_tol(arm_reg, volt, 0);
  76. if (ret) {
  77. dev_err(cpu_dev,
  78. "failed to scale vddarm up: %d\n", ret);
  79. freqs.new = freqs.old;
  80. goto post_notify;
  81. }
  82. /*
  83. * Need to increase vddpu and vddsoc for safety
  84. * if we are about to run at 1.2 GHz.
  85. */
  86. if (freqs.new == FREQ_1P2_GHZ / 1000) {
  87. regulator_set_voltage_tol(pu_reg,
  88. PU_SOC_VOLTAGE_HIGH, 0);
  89. regulator_set_voltage_tol(soc_reg,
  90. PU_SOC_VOLTAGE_HIGH, 0);
  91. }
  92. }
  93. /*
  94. * The setpoints are selected per PLL/PDF frequencies, so we need to
  95. * reprogram PLL for frequency scaling. The procedure of reprogramming
  96. * PLL1 is as below.
  97. *
  98. * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
  99. * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
  100. * - Disable pll2_pfd2_396m_clk
  101. */
  102. clk_prepare_enable(pll2_pfd2_396m_clk);
  103. clk_set_parent(step_clk, pll2_pfd2_396m_clk);
  104. clk_set_parent(pll1_sw_clk, step_clk);
  105. if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
  106. clk_set_rate(pll1_sys_clk, freqs.new * 1000);
  107. /*
  108. * If we are leaving 396 MHz set-point, we need to enable
  109. * pll1_sys_clk and disable pll2_pfd2_396m_clk to keep
  110. * their use count correct.
  111. */
  112. if (freqs.old * 1000 <= clk_get_rate(pll2_pfd2_396m_clk)) {
  113. clk_prepare_enable(pll1_sys_clk);
  114. clk_disable_unprepare(pll2_pfd2_396m_clk);
  115. }
  116. clk_set_parent(pll1_sw_clk, pll1_sys_clk);
  117. clk_disable_unprepare(pll2_pfd2_396m_clk);
  118. } else {
  119. /*
  120. * Disable pll1_sys_clk if pll2_pfd2_396m_clk is sufficient
  121. * to provide the frequency.
  122. */
  123. clk_disable_unprepare(pll1_sys_clk);
  124. }
  125. /* Ensure the arm clock divider is what we expect */
  126. ret = clk_set_rate(arm_clk, freqs.new * 1000);
  127. if (ret) {
  128. dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
  129. regulator_set_voltage_tol(arm_reg, volt_old, 0);
  130. freqs.new = freqs.old;
  131. goto post_notify;
  132. }
  133. /* scaling down? scale voltage after frequency */
  134. if (freqs.new < freqs.old) {
  135. ret = regulator_set_voltage_tol(arm_reg, volt, 0);
  136. if (ret) {
  137. dev_warn(cpu_dev,
  138. "failed to scale vddarm down: %d\n", ret);
  139. ret = 0;
  140. }
  141. if (freqs.old == FREQ_1P2_GHZ / 1000) {
  142. regulator_set_voltage_tol(pu_reg,
  143. PU_SOC_VOLTAGE_NORMAL, 0);
  144. regulator_set_voltage_tol(soc_reg,
  145. PU_SOC_VOLTAGE_NORMAL, 0);
  146. }
  147. }
  148. post_notify:
  149. cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
  150. return ret;
  151. }
  152. static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
  153. {
  154. int ret;
  155. ret = cpufreq_frequency_table_cpuinfo(policy, freq_table);
  156. if (ret) {
  157. dev_err(cpu_dev, "invalid frequency table: %d\n", ret);
  158. return ret;
  159. }
  160. policy->cpuinfo.transition_latency = transition_latency;
  161. policy->cur = clk_get_rate(arm_clk) / 1000;
  162. cpumask_setall(policy->cpus);
  163. cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
  164. return 0;
  165. }
  166. static int imx6q_cpufreq_exit(struct cpufreq_policy *policy)
  167. {
  168. cpufreq_frequency_table_put_attr(policy->cpu);
  169. return 0;
  170. }
  171. static struct freq_attr *imx6q_cpufreq_attr[] = {
  172. &cpufreq_freq_attr_scaling_available_freqs,
  173. NULL,
  174. };
  175. static struct cpufreq_driver imx6q_cpufreq_driver = {
  176. .verify = imx6q_verify_speed,
  177. .target = imx6q_set_target,
  178. .get = imx6q_get_speed,
  179. .init = imx6q_cpufreq_init,
  180. .exit = imx6q_cpufreq_exit,
  181. .name = "imx6q-cpufreq",
  182. .attr = imx6q_cpufreq_attr,
  183. };
  184. static int imx6q_cpufreq_probe(struct platform_device *pdev)
  185. {
  186. struct device_node *np;
  187. struct opp *opp;
  188. unsigned long min_volt, max_volt;
  189. int num, ret;
  190. cpu_dev = &pdev->dev;
  191. np = of_find_node_by_path("/cpus/cpu@0");
  192. if (!np) {
  193. dev_err(cpu_dev, "failed to find cpu0 node\n");
  194. return -ENOENT;
  195. }
  196. cpu_dev->of_node = np;
  197. arm_clk = devm_clk_get(cpu_dev, "arm");
  198. pll1_sys_clk = devm_clk_get(cpu_dev, "pll1_sys");
  199. pll1_sw_clk = devm_clk_get(cpu_dev, "pll1_sw");
  200. step_clk = devm_clk_get(cpu_dev, "step");
  201. pll2_pfd2_396m_clk = devm_clk_get(cpu_dev, "pll2_pfd2_396m");
  202. if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
  203. IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
  204. dev_err(cpu_dev, "failed to get clocks\n");
  205. ret = -ENOENT;
  206. goto put_node;
  207. }
  208. arm_reg = devm_regulator_get(cpu_dev, "arm");
  209. pu_reg = devm_regulator_get(cpu_dev, "pu");
  210. soc_reg = devm_regulator_get(cpu_dev, "soc");
  211. if (IS_ERR(arm_reg) || IS_ERR(pu_reg) || IS_ERR(soc_reg)) {
  212. dev_err(cpu_dev, "failed to get regulators\n");
  213. ret = -ENOENT;
  214. goto put_node;
  215. }
  216. /* We expect an OPP table supplied by platform */
  217. num = opp_get_opp_count(cpu_dev);
  218. if (num < 0) {
  219. ret = num;
  220. dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
  221. goto put_node;
  222. }
  223. ret = opp_init_cpufreq_table(cpu_dev, &freq_table);
  224. if (ret) {
  225. dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
  226. goto put_node;
  227. }
  228. if (of_property_read_u32(np, "clock-latency", &transition_latency))
  229. transition_latency = CPUFREQ_ETERNAL;
  230. /*
  231. * OPP is maintained in order of increasing frequency, and
  232. * freq_table initialised from OPP is therefore sorted in the
  233. * same order.
  234. */
  235. rcu_read_lock();
  236. opp = opp_find_freq_exact(cpu_dev,
  237. freq_table[0].frequency * 1000, true);
  238. min_volt = opp_get_voltage(opp);
  239. opp = opp_find_freq_exact(cpu_dev,
  240. freq_table[--num].frequency * 1000, true);
  241. max_volt = opp_get_voltage(opp);
  242. rcu_read_unlock();
  243. ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
  244. if (ret > 0)
  245. transition_latency += ret * 1000;
  246. /* Count vddpu and vddsoc latency in for 1.2 GHz support */
  247. if (freq_table[num].frequency == FREQ_1P2_GHZ / 1000) {
  248. ret = regulator_set_voltage_time(pu_reg, PU_SOC_VOLTAGE_NORMAL,
  249. PU_SOC_VOLTAGE_HIGH);
  250. if (ret > 0)
  251. transition_latency += ret * 1000;
  252. ret = regulator_set_voltage_time(soc_reg, PU_SOC_VOLTAGE_NORMAL,
  253. PU_SOC_VOLTAGE_HIGH);
  254. if (ret > 0)
  255. transition_latency += ret * 1000;
  256. }
  257. ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
  258. if (ret) {
  259. dev_err(cpu_dev, "failed register driver: %d\n", ret);
  260. goto free_freq_table;
  261. }
  262. of_node_put(np);
  263. return 0;
  264. free_freq_table:
  265. opp_free_cpufreq_table(cpu_dev, &freq_table);
  266. put_node:
  267. of_node_put(np);
  268. return ret;
  269. }
  270. static int imx6q_cpufreq_remove(struct platform_device *pdev)
  271. {
  272. cpufreq_unregister_driver(&imx6q_cpufreq_driver);
  273. opp_free_cpufreq_table(cpu_dev, &freq_table);
  274. return 0;
  275. }
  276. static struct platform_driver imx6q_cpufreq_platdrv = {
  277. .driver = {
  278. .name = "imx6q-cpufreq",
  279. .owner = THIS_MODULE,
  280. },
  281. .probe = imx6q_cpufreq_probe,
  282. .remove = imx6q_cpufreq_remove,
  283. };
  284. module_platform_driver(imx6q_cpufreq_platdrv);
  285. MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
  286. MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
  287. MODULE_LICENSE("GPL");