main.c 58 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static void ath9k_set_assoc_state(struct ath_softc *sc,
  21. struct ieee80211_vif *vif);
  22. u8 ath9k_parse_mpdudensity(u8 mpdudensity)
  23. {
  24. /*
  25. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  26. * 0 for no restriction
  27. * 1 for 1/4 us
  28. * 2 for 1/2 us
  29. * 3 for 1 us
  30. * 4 for 2 us
  31. * 5 for 4 us
  32. * 6 for 8 us
  33. * 7 for 16 us
  34. */
  35. switch (mpdudensity) {
  36. case 0:
  37. return 0;
  38. case 1:
  39. case 2:
  40. case 3:
  41. /* Our lower layer calculations limit our precision to
  42. 1 microsecond */
  43. return 1;
  44. case 4:
  45. return 2;
  46. case 5:
  47. return 4;
  48. case 6:
  49. return 8;
  50. case 7:
  51. return 16;
  52. default:
  53. return 0;
  54. }
  55. }
  56. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  57. {
  58. bool pending = false;
  59. spin_lock_bh(&txq->axq_lock);
  60. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  61. pending = true;
  62. spin_unlock_bh(&txq->axq_lock);
  63. return pending;
  64. }
  65. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  66. {
  67. unsigned long flags;
  68. bool ret;
  69. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  70. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  71. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  72. return ret;
  73. }
  74. void ath9k_ps_wakeup(struct ath_softc *sc)
  75. {
  76. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  77. unsigned long flags;
  78. enum ath9k_power_mode power_mode;
  79. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  80. if (++sc->ps_usecount != 1)
  81. goto unlock;
  82. power_mode = sc->sc_ah->power_mode;
  83. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  84. /*
  85. * While the hardware is asleep, the cycle counters contain no
  86. * useful data. Better clear them now so that they don't mess up
  87. * survey data results.
  88. */
  89. if (power_mode != ATH9K_PM_AWAKE) {
  90. spin_lock(&common->cc_lock);
  91. ath_hw_cycle_counters_update(common);
  92. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  93. memset(&common->cc_ani, 0, sizeof(common->cc_ani));
  94. spin_unlock(&common->cc_lock);
  95. }
  96. unlock:
  97. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  98. }
  99. void ath9k_ps_restore(struct ath_softc *sc)
  100. {
  101. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  102. enum ath9k_power_mode mode;
  103. unsigned long flags;
  104. bool reset;
  105. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  106. if (--sc->ps_usecount != 0)
  107. goto unlock;
  108. if (sc->ps_idle) {
  109. ath9k_hw_setrxabort(sc->sc_ah, 1);
  110. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  111. mode = ATH9K_PM_FULL_SLEEP;
  112. } else if (sc->ps_enabled &&
  113. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  114. PS_WAIT_FOR_CAB |
  115. PS_WAIT_FOR_PSPOLL_DATA |
  116. PS_WAIT_FOR_TX_ACK |
  117. PS_WAIT_FOR_ANI))) {
  118. mode = ATH9K_PM_NETWORK_SLEEP;
  119. if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
  120. ath9k_btcoex_stop_gen_timer(sc);
  121. } else {
  122. goto unlock;
  123. }
  124. spin_lock(&common->cc_lock);
  125. ath_hw_cycle_counters_update(common);
  126. spin_unlock(&common->cc_lock);
  127. ath9k_hw_setpower(sc->sc_ah, mode);
  128. unlock:
  129. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  130. }
  131. static void __ath_cancel_work(struct ath_softc *sc)
  132. {
  133. cancel_work_sync(&sc->paprd_work);
  134. cancel_work_sync(&sc->hw_check_work);
  135. cancel_delayed_work_sync(&sc->tx_complete_work);
  136. cancel_delayed_work_sync(&sc->hw_pll_work);
  137. #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
  138. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  139. cancel_work_sync(&sc->mci_work);
  140. #endif
  141. }
  142. static void ath_cancel_work(struct ath_softc *sc)
  143. {
  144. __ath_cancel_work(sc);
  145. cancel_work_sync(&sc->hw_reset_work);
  146. }
  147. static void ath_restart_work(struct ath_softc *sc)
  148. {
  149. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  150. if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
  151. AR_SREV_9550(sc->sc_ah))
  152. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
  153. msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
  154. ath_start_rx_poll(sc, 3);
  155. ath_start_ani(sc);
  156. }
  157. static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
  158. {
  159. struct ath_hw *ah = sc->sc_ah;
  160. bool ret = true;
  161. ieee80211_stop_queues(sc->hw);
  162. sc->hw_busy_count = 0;
  163. ath_stop_ani(sc);
  164. del_timer_sync(&sc->rx_poll_timer);
  165. ath9k_debug_samp_bb_mac(sc);
  166. ath9k_hw_disable_interrupts(ah);
  167. if (!ath_stoprecv(sc))
  168. ret = false;
  169. if (!ath_drain_all_txq(sc, retry_tx))
  170. ret = false;
  171. if (!flush) {
  172. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  173. ath_rx_tasklet(sc, 1, true);
  174. ath_rx_tasklet(sc, 1, false);
  175. } else {
  176. ath_flushrecv(sc);
  177. }
  178. return ret;
  179. }
  180. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  181. {
  182. struct ath_hw *ah = sc->sc_ah;
  183. struct ath_common *common = ath9k_hw_common(ah);
  184. unsigned long flags;
  185. if (ath_startrecv(sc) != 0) {
  186. ath_err(common, "Unable to restart recv logic\n");
  187. return false;
  188. }
  189. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  190. sc->config.txpowlimit, &sc->curtxpow);
  191. clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
  192. ath9k_hw_set_interrupts(ah);
  193. ath9k_hw_enable_interrupts(ah);
  194. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
  195. if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
  196. goto work;
  197. ath9k_set_beacon(sc);
  198. if (ah->opmode == NL80211_IFTYPE_STATION &&
  199. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  200. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  201. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  202. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  203. }
  204. work:
  205. ath_restart_work(sc);
  206. }
  207. if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
  208. ath_ant_comb_update(sc);
  209. ieee80211_wake_queues(sc->hw);
  210. return true;
  211. }
  212. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
  213. bool retry_tx)
  214. {
  215. struct ath_hw *ah = sc->sc_ah;
  216. struct ath_common *common = ath9k_hw_common(ah);
  217. struct ath9k_hw_cal_data *caldata = NULL;
  218. bool fastcc = true;
  219. bool flush = false;
  220. int r;
  221. __ath_cancel_work(sc);
  222. spin_lock_bh(&sc->sc_pcu_lock);
  223. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
  224. fastcc = false;
  225. caldata = &sc->caldata;
  226. }
  227. if (!hchan) {
  228. fastcc = false;
  229. flush = true;
  230. hchan = ah->curchan;
  231. }
  232. if (!ath_prepare_reset(sc, retry_tx, flush))
  233. fastcc = false;
  234. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  235. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  236. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  237. if (r) {
  238. ath_err(common,
  239. "Unable to reset channel, reset status %d\n", r);
  240. goto out;
  241. }
  242. if (!ath_complete_reset(sc, true))
  243. r = -EIO;
  244. out:
  245. spin_unlock_bh(&sc->sc_pcu_lock);
  246. return r;
  247. }
  248. /*
  249. * Set/change channels. If the channel is really being changed, it's done
  250. * by reseting the chip. To accomplish this we must first cleanup any pending
  251. * DMA, then restart stuff.
  252. */
  253. static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  254. struct ath9k_channel *hchan)
  255. {
  256. int r;
  257. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  258. return -EIO;
  259. r = ath_reset_internal(sc, hchan, false);
  260. return r;
  261. }
  262. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  263. struct ieee80211_vif *vif)
  264. {
  265. struct ath_node *an;
  266. u8 density;
  267. an = (struct ath_node *)sta->drv_priv;
  268. #ifdef CONFIG_ATH9K_DEBUGFS
  269. spin_lock(&sc->nodes_lock);
  270. list_add(&an->list, &sc->nodes);
  271. spin_unlock(&sc->nodes_lock);
  272. #endif
  273. an->sta = sta;
  274. an->vif = vif;
  275. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  276. ath_tx_node_init(sc, an);
  277. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  278. sta->ht_cap.ampdu_factor);
  279. density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
  280. an->mpdudensity = density;
  281. }
  282. }
  283. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  284. {
  285. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  286. #ifdef CONFIG_ATH9K_DEBUGFS
  287. spin_lock(&sc->nodes_lock);
  288. list_del(&an->list);
  289. spin_unlock(&sc->nodes_lock);
  290. an->sta = NULL;
  291. #endif
  292. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  293. ath_tx_node_cleanup(sc, an);
  294. }
  295. void ath9k_tasklet(unsigned long data)
  296. {
  297. struct ath_softc *sc = (struct ath_softc *)data;
  298. struct ath_hw *ah = sc->sc_ah;
  299. struct ath_common *common = ath9k_hw_common(ah);
  300. enum ath_reset_type type;
  301. unsigned long flags;
  302. u32 status = sc->intrstatus;
  303. u32 rxmask;
  304. ath9k_ps_wakeup(sc);
  305. spin_lock(&sc->sc_pcu_lock);
  306. if ((status & ATH9K_INT_FATAL) ||
  307. (status & ATH9K_INT_BB_WATCHDOG)) {
  308. if (status & ATH9K_INT_FATAL)
  309. type = RESET_TYPE_FATAL_INT;
  310. else
  311. type = RESET_TYPE_BB_WATCHDOG;
  312. ath9k_queue_reset(sc, type);
  313. goto out;
  314. }
  315. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  316. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  317. /*
  318. * TSF sync does not look correct; remain awake to sync with
  319. * the next Beacon.
  320. */
  321. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  322. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  323. }
  324. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  325. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  326. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  327. ATH9K_INT_RXORN);
  328. else
  329. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  330. if (status & rxmask) {
  331. /* Check for high priority Rx first */
  332. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  333. (status & ATH9K_INT_RXHP))
  334. ath_rx_tasklet(sc, 0, true);
  335. ath_rx_tasklet(sc, 0, false);
  336. }
  337. if (status & ATH9K_INT_TX) {
  338. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  339. ath_tx_edma_tasklet(sc);
  340. else
  341. ath_tx_tasklet(sc);
  342. }
  343. ath9k_btcoex_handle_interrupt(sc, status);
  344. out:
  345. /* re-enable hardware interrupt */
  346. ath9k_hw_enable_interrupts(ah);
  347. spin_unlock(&sc->sc_pcu_lock);
  348. ath9k_ps_restore(sc);
  349. }
  350. irqreturn_t ath_isr(int irq, void *dev)
  351. {
  352. #define SCHED_INTR ( \
  353. ATH9K_INT_FATAL | \
  354. ATH9K_INT_BB_WATCHDOG | \
  355. ATH9K_INT_RXORN | \
  356. ATH9K_INT_RXEOL | \
  357. ATH9K_INT_RX | \
  358. ATH9K_INT_RXLP | \
  359. ATH9K_INT_RXHP | \
  360. ATH9K_INT_TX | \
  361. ATH9K_INT_BMISS | \
  362. ATH9K_INT_CST | \
  363. ATH9K_INT_TSFOOR | \
  364. ATH9K_INT_GENTIMER | \
  365. ATH9K_INT_MCI)
  366. struct ath_softc *sc = dev;
  367. struct ath_hw *ah = sc->sc_ah;
  368. struct ath_common *common = ath9k_hw_common(ah);
  369. enum ath9k_int status;
  370. bool sched = false;
  371. /*
  372. * The hardware is not ready/present, don't
  373. * touch anything. Note this can happen early
  374. * on if the IRQ is shared.
  375. */
  376. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  377. return IRQ_NONE;
  378. /* shared irq, not for us */
  379. if (!ath9k_hw_intrpend(ah))
  380. return IRQ_NONE;
  381. if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
  382. ath9k_hw_kill_interrupts(ah);
  383. return IRQ_HANDLED;
  384. }
  385. /*
  386. * Figure out the reason(s) for the interrupt. Note
  387. * that the hal returns a pseudo-ISR that may include
  388. * bits we haven't explicitly enabled so we mask the
  389. * value to insure we only process bits we requested.
  390. */
  391. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  392. status &= ah->imask; /* discard unasked-for bits */
  393. /*
  394. * If there are no status bits set, then this interrupt was not
  395. * for me (should have been caught above).
  396. */
  397. if (!status)
  398. return IRQ_NONE;
  399. /* Cache the status */
  400. sc->intrstatus = status;
  401. if (status & SCHED_INTR)
  402. sched = true;
  403. #ifdef CONFIG_PM_SLEEP
  404. if (status & ATH9K_INT_BMISS) {
  405. if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
  406. ath_dbg(common, ANY, "during WoW we got a BMISS\n");
  407. atomic_inc(&sc->wow_got_bmiss_intr);
  408. atomic_dec(&sc->wow_sleep_proc_intr);
  409. }
  410. ath_dbg(common, INTERRUPT, "beacon miss interrupt\n");
  411. }
  412. #endif
  413. /*
  414. * If a FATAL or RXORN interrupt is received, we have to reset the
  415. * chip immediately.
  416. */
  417. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  418. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  419. goto chip_reset;
  420. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  421. (status & ATH9K_INT_BB_WATCHDOG)) {
  422. spin_lock(&common->cc_lock);
  423. ath_hw_cycle_counters_update(common);
  424. ar9003_hw_bb_watchdog_dbg_info(ah);
  425. spin_unlock(&common->cc_lock);
  426. goto chip_reset;
  427. }
  428. if (status & ATH9K_INT_SWBA)
  429. tasklet_schedule(&sc->bcon_tasklet);
  430. if (status & ATH9K_INT_TXURN)
  431. ath9k_hw_updatetxtriglevel(ah, true);
  432. if (status & ATH9K_INT_RXEOL) {
  433. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  434. ath9k_hw_set_interrupts(ah);
  435. }
  436. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  437. if (status & ATH9K_INT_TIM_TIMER) {
  438. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  439. goto chip_reset;
  440. /* Clear RxAbort bit so that we can
  441. * receive frames */
  442. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  443. spin_lock(&sc->sc_pm_lock);
  444. ath9k_hw_setrxabort(sc->sc_ah, 0);
  445. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  446. spin_unlock(&sc->sc_pm_lock);
  447. }
  448. chip_reset:
  449. ath_debug_stat_interrupt(sc, status);
  450. if (sched) {
  451. /* turn off every interrupt */
  452. ath9k_hw_disable_interrupts(ah);
  453. tasklet_schedule(&sc->intr_tq);
  454. }
  455. return IRQ_HANDLED;
  456. #undef SCHED_INTR
  457. }
  458. static int ath_reset(struct ath_softc *sc, bool retry_tx)
  459. {
  460. int r;
  461. ath9k_ps_wakeup(sc);
  462. r = ath_reset_internal(sc, NULL, retry_tx);
  463. if (retry_tx) {
  464. int i;
  465. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  466. if (ATH_TXQ_SETUP(sc, i)) {
  467. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  468. ath_txq_schedule(sc, &sc->tx.txq[i]);
  469. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  470. }
  471. }
  472. }
  473. ath9k_ps_restore(sc);
  474. return r;
  475. }
  476. void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
  477. {
  478. #ifdef CONFIG_ATH9K_DEBUGFS
  479. RESET_STAT_INC(sc, type);
  480. #endif
  481. set_bit(SC_OP_HW_RESET, &sc->sc_flags);
  482. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  483. }
  484. void ath_reset_work(struct work_struct *work)
  485. {
  486. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  487. ath_reset(sc, true);
  488. }
  489. /**********************/
  490. /* mac80211 callbacks */
  491. /**********************/
  492. static int ath9k_start(struct ieee80211_hw *hw)
  493. {
  494. struct ath_softc *sc = hw->priv;
  495. struct ath_hw *ah = sc->sc_ah;
  496. struct ath_common *common = ath9k_hw_common(ah);
  497. struct ieee80211_channel *curchan = hw->conf.channel;
  498. struct ath9k_channel *init_channel;
  499. int r;
  500. ath_dbg(common, CONFIG,
  501. "Starting driver with initial channel: %d MHz\n",
  502. curchan->center_freq);
  503. ath9k_ps_wakeup(sc);
  504. mutex_lock(&sc->mutex);
  505. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  506. /* Reset SERDES registers */
  507. ath9k_hw_configpcipowersave(ah, false);
  508. /*
  509. * The basic interface to setting the hardware in a good
  510. * state is ``reset''. On return the hardware is known to
  511. * be powered up and with interrupts disabled. This must
  512. * be followed by initialization of the appropriate bits
  513. * and then setup of the interrupt mask.
  514. */
  515. spin_lock_bh(&sc->sc_pcu_lock);
  516. atomic_set(&ah->intr_ref_cnt, -1);
  517. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  518. if (r) {
  519. ath_err(common,
  520. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  521. r, curchan->center_freq);
  522. ah->reset_power_on = false;
  523. }
  524. /* Setup our intr mask. */
  525. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  526. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  527. ATH9K_INT_GLOBAL;
  528. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  529. ah->imask |= ATH9K_INT_RXHP |
  530. ATH9K_INT_RXLP |
  531. ATH9K_INT_BB_WATCHDOG;
  532. else
  533. ah->imask |= ATH9K_INT_RX;
  534. ah->imask |= ATH9K_INT_GTT;
  535. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  536. ah->imask |= ATH9K_INT_CST;
  537. ath_mci_enable(sc);
  538. clear_bit(SC_OP_INVALID, &sc->sc_flags);
  539. sc->sc_ah->is_monitoring = false;
  540. if (!ath_complete_reset(sc, false))
  541. ah->reset_power_on = false;
  542. if (ah->led_pin >= 0) {
  543. ath9k_hw_cfg_output(ah, ah->led_pin,
  544. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  545. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  546. }
  547. /*
  548. * Reset key cache to sane defaults (all entries cleared) instead of
  549. * semi-random values after suspend/resume.
  550. */
  551. ath9k_cmn_init_crypto(sc->sc_ah);
  552. spin_unlock_bh(&sc->sc_pcu_lock);
  553. if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
  554. common->bus_ops->extn_synch_en(common);
  555. mutex_unlock(&sc->mutex);
  556. ath9k_ps_restore(sc);
  557. return 0;
  558. }
  559. static void ath9k_tx(struct ieee80211_hw *hw,
  560. struct ieee80211_tx_control *control,
  561. struct sk_buff *skb)
  562. {
  563. struct ath_softc *sc = hw->priv;
  564. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  565. struct ath_tx_control txctl;
  566. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  567. unsigned long flags;
  568. if (sc->ps_enabled) {
  569. /*
  570. * mac80211 does not set PM field for normal data frames, so we
  571. * need to update that based on the current PS mode.
  572. */
  573. if (ieee80211_is_data(hdr->frame_control) &&
  574. !ieee80211_is_nullfunc(hdr->frame_control) &&
  575. !ieee80211_has_pm(hdr->frame_control)) {
  576. ath_dbg(common, PS,
  577. "Add PM=1 for a TX frame while in PS mode\n");
  578. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  579. }
  580. }
  581. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  582. /*
  583. * We are using PS-Poll and mac80211 can request TX while in
  584. * power save mode. Need to wake up hardware for the TX to be
  585. * completed and if needed, also for RX of buffered frames.
  586. */
  587. ath9k_ps_wakeup(sc);
  588. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  589. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  590. ath9k_hw_setrxabort(sc->sc_ah, 0);
  591. if (ieee80211_is_pspoll(hdr->frame_control)) {
  592. ath_dbg(common, PS,
  593. "Sending PS-Poll to pick a buffered frame\n");
  594. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  595. } else {
  596. ath_dbg(common, PS, "Wake up to complete TX\n");
  597. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  598. }
  599. /*
  600. * The actual restore operation will happen only after
  601. * the ps_flags bit is cleared. We are just dropping
  602. * the ps_usecount here.
  603. */
  604. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  605. ath9k_ps_restore(sc);
  606. }
  607. /*
  608. * Cannot tx while the hardware is in full sleep, it first needs a full
  609. * chip reset to recover from that
  610. */
  611. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  612. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  613. goto exit;
  614. }
  615. memset(&txctl, 0, sizeof(struct ath_tx_control));
  616. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  617. txctl.sta = control->sta;
  618. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  619. if (ath_tx_start(hw, skb, &txctl) != 0) {
  620. ath_dbg(common, XMIT, "TX failed\n");
  621. TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
  622. goto exit;
  623. }
  624. return;
  625. exit:
  626. ieee80211_free_txskb(hw, skb);
  627. }
  628. static void ath9k_stop(struct ieee80211_hw *hw)
  629. {
  630. struct ath_softc *sc = hw->priv;
  631. struct ath_hw *ah = sc->sc_ah;
  632. struct ath_common *common = ath9k_hw_common(ah);
  633. bool prev_idle;
  634. mutex_lock(&sc->mutex);
  635. ath_cancel_work(sc);
  636. del_timer_sync(&sc->rx_poll_timer);
  637. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  638. ath_dbg(common, ANY, "Device not present\n");
  639. mutex_unlock(&sc->mutex);
  640. return;
  641. }
  642. /* Ensure HW is awake when we try to shut it down. */
  643. ath9k_ps_wakeup(sc);
  644. spin_lock_bh(&sc->sc_pcu_lock);
  645. /* prevent tasklets to enable interrupts once we disable them */
  646. ah->imask &= ~ATH9K_INT_GLOBAL;
  647. /* make sure h/w will not generate any interrupt
  648. * before setting the invalid flag. */
  649. ath9k_hw_disable_interrupts(ah);
  650. spin_unlock_bh(&sc->sc_pcu_lock);
  651. /* we can now sync irq and kill any running tasklets, since we already
  652. * disabled interrupts and not holding a spin lock */
  653. synchronize_irq(sc->irq);
  654. tasklet_kill(&sc->intr_tq);
  655. tasklet_kill(&sc->bcon_tasklet);
  656. prev_idle = sc->ps_idle;
  657. sc->ps_idle = true;
  658. spin_lock_bh(&sc->sc_pcu_lock);
  659. if (ah->led_pin >= 0) {
  660. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  661. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  662. }
  663. ath_prepare_reset(sc, false, true);
  664. if (sc->rx.frag) {
  665. dev_kfree_skb_any(sc->rx.frag);
  666. sc->rx.frag = NULL;
  667. }
  668. if (!ah->curchan)
  669. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  670. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  671. ath9k_hw_phy_disable(ah);
  672. ath9k_hw_configpcipowersave(ah, true);
  673. spin_unlock_bh(&sc->sc_pcu_lock);
  674. ath9k_ps_restore(sc);
  675. set_bit(SC_OP_INVALID, &sc->sc_flags);
  676. sc->ps_idle = prev_idle;
  677. mutex_unlock(&sc->mutex);
  678. ath_dbg(common, CONFIG, "Driver halt\n");
  679. }
  680. bool ath9k_uses_beacons(int type)
  681. {
  682. switch (type) {
  683. case NL80211_IFTYPE_AP:
  684. case NL80211_IFTYPE_ADHOC:
  685. case NL80211_IFTYPE_MESH_POINT:
  686. return true;
  687. default:
  688. return false;
  689. }
  690. }
  691. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  692. {
  693. struct ath9k_vif_iter_data *iter_data = data;
  694. int i;
  695. if (iter_data->hw_macaddr)
  696. for (i = 0; i < ETH_ALEN; i++)
  697. iter_data->mask[i] &=
  698. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  699. switch (vif->type) {
  700. case NL80211_IFTYPE_AP:
  701. iter_data->naps++;
  702. break;
  703. case NL80211_IFTYPE_STATION:
  704. iter_data->nstations++;
  705. break;
  706. case NL80211_IFTYPE_ADHOC:
  707. iter_data->nadhocs++;
  708. break;
  709. case NL80211_IFTYPE_MESH_POINT:
  710. iter_data->nmeshes++;
  711. break;
  712. case NL80211_IFTYPE_WDS:
  713. iter_data->nwds++;
  714. break;
  715. default:
  716. break;
  717. }
  718. }
  719. static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  720. {
  721. struct ath_softc *sc = data;
  722. struct ath_vif *avp = (void *)vif->drv_priv;
  723. if (vif->type != NL80211_IFTYPE_STATION)
  724. return;
  725. if (avp->primary_sta_vif)
  726. ath9k_set_assoc_state(sc, vif);
  727. }
  728. /* Called with sc->mutex held. */
  729. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  730. struct ieee80211_vif *vif,
  731. struct ath9k_vif_iter_data *iter_data)
  732. {
  733. struct ath_softc *sc = hw->priv;
  734. struct ath_hw *ah = sc->sc_ah;
  735. struct ath_common *common = ath9k_hw_common(ah);
  736. /*
  737. * Use the hardware MAC address as reference, the hardware uses it
  738. * together with the BSSID mask when matching addresses.
  739. */
  740. memset(iter_data, 0, sizeof(*iter_data));
  741. iter_data->hw_macaddr = common->macaddr;
  742. memset(&iter_data->mask, 0xff, ETH_ALEN);
  743. if (vif)
  744. ath9k_vif_iter(iter_data, vif->addr, vif);
  745. /* Get list of all active MAC addresses */
  746. ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
  747. iter_data);
  748. }
  749. /* Called with sc->mutex held. */
  750. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  751. struct ieee80211_vif *vif)
  752. {
  753. struct ath_softc *sc = hw->priv;
  754. struct ath_hw *ah = sc->sc_ah;
  755. struct ath_common *common = ath9k_hw_common(ah);
  756. struct ath9k_vif_iter_data iter_data;
  757. enum nl80211_iftype old_opmode = ah->opmode;
  758. ath9k_calculate_iter_data(hw, vif, &iter_data);
  759. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  760. ath_hw_setbssidmask(common);
  761. if (iter_data.naps > 0) {
  762. ath9k_hw_set_tsfadjust(ah, true);
  763. ah->opmode = NL80211_IFTYPE_AP;
  764. } else {
  765. ath9k_hw_set_tsfadjust(ah, false);
  766. if (iter_data.nmeshes)
  767. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  768. else if (iter_data.nwds)
  769. ah->opmode = NL80211_IFTYPE_AP;
  770. else if (iter_data.nadhocs)
  771. ah->opmode = NL80211_IFTYPE_ADHOC;
  772. else
  773. ah->opmode = NL80211_IFTYPE_STATION;
  774. }
  775. ath9k_hw_setopmode(ah);
  776. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
  777. ah->imask |= ATH9K_INT_TSFOOR;
  778. else
  779. ah->imask &= ~ATH9K_INT_TSFOOR;
  780. ath9k_hw_set_interrupts(ah);
  781. /*
  782. * If we are changing the opmode to STATION,
  783. * a beacon sync needs to be done.
  784. */
  785. if (ah->opmode == NL80211_IFTYPE_STATION &&
  786. old_opmode == NL80211_IFTYPE_AP &&
  787. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  788. ieee80211_iterate_active_interfaces_atomic(sc->hw,
  789. ath9k_sta_vif_iter, sc);
  790. }
  791. }
  792. static int ath9k_add_interface(struct ieee80211_hw *hw,
  793. struct ieee80211_vif *vif)
  794. {
  795. struct ath_softc *sc = hw->priv;
  796. struct ath_hw *ah = sc->sc_ah;
  797. struct ath_common *common = ath9k_hw_common(ah);
  798. mutex_lock(&sc->mutex);
  799. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  800. sc->nvifs++;
  801. ath9k_ps_wakeup(sc);
  802. ath9k_calculate_summary_state(hw, vif);
  803. ath9k_ps_restore(sc);
  804. if (ath9k_uses_beacons(vif->type))
  805. ath9k_beacon_assign_slot(sc, vif);
  806. mutex_unlock(&sc->mutex);
  807. return 0;
  808. }
  809. static int ath9k_change_interface(struct ieee80211_hw *hw,
  810. struct ieee80211_vif *vif,
  811. enum nl80211_iftype new_type,
  812. bool p2p)
  813. {
  814. struct ath_softc *sc = hw->priv;
  815. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  816. ath_dbg(common, CONFIG, "Change Interface\n");
  817. mutex_lock(&sc->mutex);
  818. if (ath9k_uses_beacons(vif->type))
  819. ath9k_beacon_remove_slot(sc, vif);
  820. vif->type = new_type;
  821. vif->p2p = p2p;
  822. ath9k_ps_wakeup(sc);
  823. ath9k_calculate_summary_state(hw, vif);
  824. ath9k_ps_restore(sc);
  825. if (ath9k_uses_beacons(vif->type))
  826. ath9k_beacon_assign_slot(sc, vif);
  827. mutex_unlock(&sc->mutex);
  828. return 0;
  829. }
  830. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  831. struct ieee80211_vif *vif)
  832. {
  833. struct ath_softc *sc = hw->priv;
  834. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  835. ath_dbg(common, CONFIG, "Detach Interface\n");
  836. mutex_lock(&sc->mutex);
  837. sc->nvifs--;
  838. if (ath9k_uses_beacons(vif->type))
  839. ath9k_beacon_remove_slot(sc, vif);
  840. ath9k_ps_wakeup(sc);
  841. ath9k_calculate_summary_state(hw, NULL);
  842. ath9k_ps_restore(sc);
  843. mutex_unlock(&sc->mutex);
  844. }
  845. static void ath9k_enable_ps(struct ath_softc *sc)
  846. {
  847. struct ath_hw *ah = sc->sc_ah;
  848. struct ath_common *common = ath9k_hw_common(ah);
  849. sc->ps_enabled = true;
  850. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  851. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  852. ah->imask |= ATH9K_INT_TIM_TIMER;
  853. ath9k_hw_set_interrupts(ah);
  854. }
  855. ath9k_hw_setrxabort(ah, 1);
  856. }
  857. ath_dbg(common, PS, "PowerSave enabled\n");
  858. }
  859. static void ath9k_disable_ps(struct ath_softc *sc)
  860. {
  861. struct ath_hw *ah = sc->sc_ah;
  862. struct ath_common *common = ath9k_hw_common(ah);
  863. sc->ps_enabled = false;
  864. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  865. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  866. ath9k_hw_setrxabort(ah, 0);
  867. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  868. PS_WAIT_FOR_CAB |
  869. PS_WAIT_FOR_PSPOLL_DATA |
  870. PS_WAIT_FOR_TX_ACK);
  871. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  872. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  873. ath9k_hw_set_interrupts(ah);
  874. }
  875. }
  876. ath_dbg(common, PS, "PowerSave disabled\n");
  877. }
  878. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  879. {
  880. struct ath_softc *sc = hw->priv;
  881. struct ath_hw *ah = sc->sc_ah;
  882. struct ath_common *common = ath9k_hw_common(ah);
  883. struct ieee80211_conf *conf = &hw->conf;
  884. bool reset_channel = false;
  885. ath9k_ps_wakeup(sc);
  886. mutex_lock(&sc->mutex);
  887. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  888. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  889. if (sc->ps_idle) {
  890. ath_cancel_work(sc);
  891. ath9k_stop_btcoex(sc);
  892. } else {
  893. ath9k_start_btcoex(sc);
  894. /*
  895. * The chip needs a reset to properly wake up from
  896. * full sleep
  897. */
  898. reset_channel = ah->chip_fullsleep;
  899. }
  900. }
  901. /*
  902. * We just prepare to enable PS. We have to wait until our AP has
  903. * ACK'd our null data frame to disable RX otherwise we'll ignore
  904. * those ACKs and end up retransmitting the same null data frames.
  905. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  906. */
  907. if (changed & IEEE80211_CONF_CHANGE_PS) {
  908. unsigned long flags;
  909. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  910. if (conf->flags & IEEE80211_CONF_PS)
  911. ath9k_enable_ps(sc);
  912. else
  913. ath9k_disable_ps(sc);
  914. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  915. }
  916. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  917. if (conf->flags & IEEE80211_CONF_MONITOR) {
  918. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  919. sc->sc_ah->is_monitoring = true;
  920. } else {
  921. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  922. sc->sc_ah->is_monitoring = false;
  923. }
  924. }
  925. if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
  926. struct ieee80211_channel *curchan = hw->conf.channel;
  927. int pos = curchan->hw_value;
  928. int old_pos = -1;
  929. unsigned long flags;
  930. if (ah->curchan)
  931. old_pos = ah->curchan - &ah->channels[0];
  932. ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
  933. curchan->center_freq, conf->channel_type);
  934. /* update survey stats for the old channel before switching */
  935. spin_lock_irqsave(&common->cc_lock, flags);
  936. ath_update_survey_stats(sc);
  937. spin_unlock_irqrestore(&common->cc_lock, flags);
  938. /*
  939. * Preserve the current channel values, before updating
  940. * the same channel
  941. */
  942. if (ah->curchan && (old_pos == pos))
  943. ath9k_hw_getnf(ah, ah->curchan);
  944. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  945. curchan, conf->channel_type);
  946. /*
  947. * If the operating channel changes, change the survey in-use flags
  948. * along with it.
  949. * Reset the survey data for the new channel, unless we're switching
  950. * back to the operating channel from an off-channel operation.
  951. */
  952. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  953. sc->cur_survey != &sc->survey[pos]) {
  954. if (sc->cur_survey)
  955. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  956. sc->cur_survey = &sc->survey[pos];
  957. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  958. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  959. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  960. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  961. }
  962. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  963. ath_err(common, "Unable to set channel\n");
  964. mutex_unlock(&sc->mutex);
  965. ath9k_ps_restore(sc);
  966. return -EINVAL;
  967. }
  968. /*
  969. * The most recent snapshot of channel->noisefloor for the old
  970. * channel is only available after the hardware reset. Copy it to
  971. * the survey stats now.
  972. */
  973. if (old_pos >= 0)
  974. ath_update_survey_nf(sc, old_pos);
  975. }
  976. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  977. ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
  978. sc->config.txpowlimit = 2 * conf->power_level;
  979. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  980. sc->config.txpowlimit, &sc->curtxpow);
  981. }
  982. mutex_unlock(&sc->mutex);
  983. ath9k_ps_restore(sc);
  984. return 0;
  985. }
  986. #define SUPPORTED_FILTERS \
  987. (FIF_PROMISC_IN_BSS | \
  988. FIF_ALLMULTI | \
  989. FIF_CONTROL | \
  990. FIF_PSPOLL | \
  991. FIF_OTHER_BSS | \
  992. FIF_BCN_PRBRESP_PROMISC | \
  993. FIF_PROBE_REQ | \
  994. FIF_FCSFAIL)
  995. /* FIXME: sc->sc_full_reset ? */
  996. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  997. unsigned int changed_flags,
  998. unsigned int *total_flags,
  999. u64 multicast)
  1000. {
  1001. struct ath_softc *sc = hw->priv;
  1002. u32 rfilt;
  1003. changed_flags &= SUPPORTED_FILTERS;
  1004. *total_flags &= SUPPORTED_FILTERS;
  1005. sc->rx.rxfilter = *total_flags;
  1006. ath9k_ps_wakeup(sc);
  1007. rfilt = ath_calcrxfilter(sc);
  1008. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1009. ath9k_ps_restore(sc);
  1010. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1011. rfilt);
  1012. }
  1013. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1014. struct ieee80211_vif *vif,
  1015. struct ieee80211_sta *sta)
  1016. {
  1017. struct ath_softc *sc = hw->priv;
  1018. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1019. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1020. struct ieee80211_key_conf ps_key = { };
  1021. ath_node_attach(sc, sta, vif);
  1022. if (vif->type != NL80211_IFTYPE_AP &&
  1023. vif->type != NL80211_IFTYPE_AP_VLAN)
  1024. return 0;
  1025. an->ps_key = ath_key_config(common, vif, sta, &ps_key);
  1026. return 0;
  1027. }
  1028. static void ath9k_del_ps_key(struct ath_softc *sc,
  1029. struct ieee80211_vif *vif,
  1030. struct ieee80211_sta *sta)
  1031. {
  1032. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1033. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1034. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1035. if (!an->ps_key)
  1036. return;
  1037. ath_key_delete(common, &ps_key);
  1038. }
  1039. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1040. struct ieee80211_vif *vif,
  1041. struct ieee80211_sta *sta)
  1042. {
  1043. struct ath_softc *sc = hw->priv;
  1044. ath9k_del_ps_key(sc, vif, sta);
  1045. ath_node_detach(sc, sta);
  1046. return 0;
  1047. }
  1048. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1049. struct ieee80211_vif *vif,
  1050. enum sta_notify_cmd cmd,
  1051. struct ieee80211_sta *sta)
  1052. {
  1053. struct ath_softc *sc = hw->priv;
  1054. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1055. if (!sta->ht_cap.ht_supported)
  1056. return;
  1057. switch (cmd) {
  1058. case STA_NOTIFY_SLEEP:
  1059. an->sleeping = true;
  1060. ath_tx_aggr_sleep(sta, sc, an);
  1061. break;
  1062. case STA_NOTIFY_AWAKE:
  1063. an->sleeping = false;
  1064. ath_tx_aggr_wakeup(sc, an);
  1065. break;
  1066. }
  1067. }
  1068. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1069. struct ieee80211_vif *vif, u16 queue,
  1070. const struct ieee80211_tx_queue_params *params)
  1071. {
  1072. struct ath_softc *sc = hw->priv;
  1073. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1074. struct ath_txq *txq;
  1075. struct ath9k_tx_queue_info qi;
  1076. int ret = 0;
  1077. if (queue >= WME_NUM_AC)
  1078. return 0;
  1079. txq = sc->tx.txq_map[queue];
  1080. ath9k_ps_wakeup(sc);
  1081. mutex_lock(&sc->mutex);
  1082. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1083. qi.tqi_aifs = params->aifs;
  1084. qi.tqi_cwmin = params->cw_min;
  1085. qi.tqi_cwmax = params->cw_max;
  1086. qi.tqi_burstTime = params->txop * 32;
  1087. ath_dbg(common, CONFIG,
  1088. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1089. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1090. params->cw_max, params->txop);
  1091. ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
  1092. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1093. if (ret)
  1094. ath_err(common, "TXQ Update failed\n");
  1095. mutex_unlock(&sc->mutex);
  1096. ath9k_ps_restore(sc);
  1097. return ret;
  1098. }
  1099. static int ath9k_set_key(struct ieee80211_hw *hw,
  1100. enum set_key_cmd cmd,
  1101. struct ieee80211_vif *vif,
  1102. struct ieee80211_sta *sta,
  1103. struct ieee80211_key_conf *key)
  1104. {
  1105. struct ath_softc *sc = hw->priv;
  1106. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1107. int ret = 0;
  1108. if (ath9k_modparam_nohwcrypt)
  1109. return -ENOSPC;
  1110. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1111. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1112. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1113. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1114. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1115. /*
  1116. * For now, disable hw crypto for the RSN IBSS group keys. This
  1117. * could be optimized in the future to use a modified key cache
  1118. * design to support per-STA RX GTK, but until that gets
  1119. * implemented, use of software crypto for group addressed
  1120. * frames is a acceptable to allow RSN IBSS to be used.
  1121. */
  1122. return -EOPNOTSUPP;
  1123. }
  1124. mutex_lock(&sc->mutex);
  1125. ath9k_ps_wakeup(sc);
  1126. ath_dbg(common, CONFIG, "Set HW Key\n");
  1127. switch (cmd) {
  1128. case SET_KEY:
  1129. if (sta)
  1130. ath9k_del_ps_key(sc, vif, sta);
  1131. ret = ath_key_config(common, vif, sta, key);
  1132. if (ret >= 0) {
  1133. key->hw_key_idx = ret;
  1134. /* push IV and Michael MIC generation to stack */
  1135. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1136. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1137. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1138. if (sc->sc_ah->sw_mgmt_crypto &&
  1139. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1140. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
  1141. ret = 0;
  1142. }
  1143. break;
  1144. case DISABLE_KEY:
  1145. ath_key_delete(common, key);
  1146. break;
  1147. default:
  1148. ret = -EINVAL;
  1149. }
  1150. ath9k_ps_restore(sc);
  1151. mutex_unlock(&sc->mutex);
  1152. return ret;
  1153. }
  1154. static void ath9k_set_assoc_state(struct ath_softc *sc,
  1155. struct ieee80211_vif *vif)
  1156. {
  1157. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1158. struct ath_vif *avp = (void *)vif->drv_priv;
  1159. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1160. unsigned long flags;
  1161. set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1162. avp->primary_sta_vif = true;
  1163. /*
  1164. * Set the AID, BSSID and do beacon-sync only when
  1165. * the HW opmode is STATION.
  1166. *
  1167. * But the primary bit is set above in any case.
  1168. */
  1169. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1170. return;
  1171. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1172. common->curaid = bss_conf->aid;
  1173. ath9k_hw_write_associd(sc->sc_ah);
  1174. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1175. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1176. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1177. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1178. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1179. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1180. ath9k_mci_update_wlan_channels(sc, false);
  1181. ath_dbg(common, CONFIG,
  1182. "Primary Station interface: %pM, BSSID: %pM\n",
  1183. vif->addr, common->curbssid);
  1184. }
  1185. static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1186. {
  1187. struct ath_softc *sc = data;
  1188. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1189. if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
  1190. return;
  1191. if (bss_conf->assoc)
  1192. ath9k_set_assoc_state(sc, vif);
  1193. }
  1194. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1195. struct ieee80211_vif *vif,
  1196. struct ieee80211_bss_conf *bss_conf,
  1197. u32 changed)
  1198. {
  1199. #define CHECK_ANI \
  1200. (BSS_CHANGED_ASSOC | \
  1201. BSS_CHANGED_IBSS | \
  1202. BSS_CHANGED_BEACON_ENABLED)
  1203. struct ath_softc *sc = hw->priv;
  1204. struct ath_hw *ah = sc->sc_ah;
  1205. struct ath_common *common = ath9k_hw_common(ah);
  1206. struct ath_vif *avp = (void *)vif->drv_priv;
  1207. int slottime;
  1208. ath9k_ps_wakeup(sc);
  1209. mutex_lock(&sc->mutex);
  1210. if (changed & BSS_CHANGED_ASSOC) {
  1211. ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
  1212. bss_conf->bssid, bss_conf->assoc);
  1213. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1214. clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1215. avp->primary_sta_vif = false;
  1216. if (ah->opmode == NL80211_IFTYPE_STATION)
  1217. clear_bit(SC_OP_BEACONS, &sc->sc_flags);
  1218. }
  1219. ieee80211_iterate_active_interfaces_atomic(sc->hw,
  1220. ath9k_bss_assoc_iter, sc);
  1221. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
  1222. ah->opmode == NL80211_IFTYPE_STATION) {
  1223. memset(common->curbssid, 0, ETH_ALEN);
  1224. common->curaid = 0;
  1225. ath9k_hw_write_associd(sc->sc_ah);
  1226. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1227. ath9k_mci_update_wlan_channels(sc, true);
  1228. }
  1229. }
  1230. if (changed & BSS_CHANGED_IBSS) {
  1231. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1232. common->curaid = bss_conf->aid;
  1233. ath9k_hw_write_associd(sc->sc_ah);
  1234. }
  1235. if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
  1236. (changed & BSS_CHANGED_BEACON_INT)) {
  1237. if (ah->opmode == NL80211_IFTYPE_AP &&
  1238. bss_conf->enable_beacon)
  1239. ath9k_set_tsfadjust(sc, vif);
  1240. if (ath9k_allow_beacon_config(sc, vif))
  1241. ath9k_beacon_config(sc, vif, changed);
  1242. }
  1243. if (changed & BSS_CHANGED_ERP_SLOT) {
  1244. if (bss_conf->use_short_slot)
  1245. slottime = 9;
  1246. else
  1247. slottime = 20;
  1248. if (vif->type == NL80211_IFTYPE_AP) {
  1249. /*
  1250. * Defer update, so that connected stations can adjust
  1251. * their settings at the same time.
  1252. * See beacon.c for more details
  1253. */
  1254. sc->beacon.slottime = slottime;
  1255. sc->beacon.updateslot = UPDATE;
  1256. } else {
  1257. ah->slottime = slottime;
  1258. ath9k_hw_init_global_settings(ah);
  1259. }
  1260. }
  1261. if (changed & CHECK_ANI)
  1262. ath_check_ani(sc);
  1263. mutex_unlock(&sc->mutex);
  1264. ath9k_ps_restore(sc);
  1265. #undef CHECK_ANI
  1266. }
  1267. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1268. {
  1269. struct ath_softc *sc = hw->priv;
  1270. u64 tsf;
  1271. mutex_lock(&sc->mutex);
  1272. ath9k_ps_wakeup(sc);
  1273. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1274. ath9k_ps_restore(sc);
  1275. mutex_unlock(&sc->mutex);
  1276. return tsf;
  1277. }
  1278. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1279. struct ieee80211_vif *vif,
  1280. u64 tsf)
  1281. {
  1282. struct ath_softc *sc = hw->priv;
  1283. mutex_lock(&sc->mutex);
  1284. ath9k_ps_wakeup(sc);
  1285. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1286. ath9k_ps_restore(sc);
  1287. mutex_unlock(&sc->mutex);
  1288. }
  1289. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1290. {
  1291. struct ath_softc *sc = hw->priv;
  1292. mutex_lock(&sc->mutex);
  1293. ath9k_ps_wakeup(sc);
  1294. ath9k_hw_reset_tsf(sc->sc_ah);
  1295. ath9k_ps_restore(sc);
  1296. mutex_unlock(&sc->mutex);
  1297. }
  1298. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1299. struct ieee80211_vif *vif,
  1300. enum ieee80211_ampdu_mlme_action action,
  1301. struct ieee80211_sta *sta,
  1302. u16 tid, u16 *ssn, u8 buf_size)
  1303. {
  1304. struct ath_softc *sc = hw->priv;
  1305. int ret = 0;
  1306. local_bh_disable();
  1307. switch (action) {
  1308. case IEEE80211_AMPDU_RX_START:
  1309. break;
  1310. case IEEE80211_AMPDU_RX_STOP:
  1311. break;
  1312. case IEEE80211_AMPDU_TX_START:
  1313. ath9k_ps_wakeup(sc);
  1314. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1315. if (!ret)
  1316. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1317. ath9k_ps_restore(sc);
  1318. break;
  1319. case IEEE80211_AMPDU_TX_STOP:
  1320. ath9k_ps_wakeup(sc);
  1321. ath_tx_aggr_stop(sc, sta, tid);
  1322. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1323. ath9k_ps_restore(sc);
  1324. break;
  1325. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1326. ath9k_ps_wakeup(sc);
  1327. ath_tx_aggr_resume(sc, sta, tid);
  1328. ath9k_ps_restore(sc);
  1329. break;
  1330. default:
  1331. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1332. }
  1333. local_bh_enable();
  1334. return ret;
  1335. }
  1336. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1337. struct survey_info *survey)
  1338. {
  1339. struct ath_softc *sc = hw->priv;
  1340. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1341. struct ieee80211_supported_band *sband;
  1342. struct ieee80211_channel *chan;
  1343. unsigned long flags;
  1344. int pos;
  1345. spin_lock_irqsave(&common->cc_lock, flags);
  1346. if (idx == 0)
  1347. ath_update_survey_stats(sc);
  1348. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1349. if (sband && idx >= sband->n_channels) {
  1350. idx -= sband->n_channels;
  1351. sband = NULL;
  1352. }
  1353. if (!sband)
  1354. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1355. if (!sband || idx >= sband->n_channels) {
  1356. spin_unlock_irqrestore(&common->cc_lock, flags);
  1357. return -ENOENT;
  1358. }
  1359. chan = &sband->channels[idx];
  1360. pos = chan->hw_value;
  1361. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1362. survey->channel = chan;
  1363. spin_unlock_irqrestore(&common->cc_lock, flags);
  1364. return 0;
  1365. }
  1366. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1367. {
  1368. struct ath_softc *sc = hw->priv;
  1369. struct ath_hw *ah = sc->sc_ah;
  1370. mutex_lock(&sc->mutex);
  1371. ah->coverage_class = coverage_class;
  1372. ath9k_ps_wakeup(sc);
  1373. ath9k_hw_init_global_settings(ah);
  1374. ath9k_ps_restore(sc);
  1375. mutex_unlock(&sc->mutex);
  1376. }
  1377. static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
  1378. {
  1379. struct ath_softc *sc = hw->priv;
  1380. struct ath_hw *ah = sc->sc_ah;
  1381. struct ath_common *common = ath9k_hw_common(ah);
  1382. int timeout = 200; /* ms */
  1383. int i, j;
  1384. bool drain_txq;
  1385. mutex_lock(&sc->mutex);
  1386. cancel_delayed_work_sync(&sc->tx_complete_work);
  1387. if (ah->ah_flags & AH_UNPLUGGED) {
  1388. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1389. mutex_unlock(&sc->mutex);
  1390. return;
  1391. }
  1392. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1393. ath_dbg(common, ANY, "Device not present\n");
  1394. mutex_unlock(&sc->mutex);
  1395. return;
  1396. }
  1397. for (j = 0; j < timeout; j++) {
  1398. bool npend = false;
  1399. if (j)
  1400. usleep_range(1000, 2000);
  1401. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1402. if (!ATH_TXQ_SETUP(sc, i))
  1403. continue;
  1404. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1405. if (npend)
  1406. break;
  1407. }
  1408. if (!npend)
  1409. break;
  1410. }
  1411. if (drop) {
  1412. ath9k_ps_wakeup(sc);
  1413. spin_lock_bh(&sc->sc_pcu_lock);
  1414. drain_txq = ath_drain_all_txq(sc, false);
  1415. spin_unlock_bh(&sc->sc_pcu_lock);
  1416. if (!drain_txq)
  1417. ath_reset(sc, false);
  1418. ath9k_ps_restore(sc);
  1419. ieee80211_wake_queues(hw);
  1420. }
  1421. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1422. mutex_unlock(&sc->mutex);
  1423. }
  1424. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1425. {
  1426. struct ath_softc *sc = hw->priv;
  1427. int i;
  1428. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1429. if (!ATH_TXQ_SETUP(sc, i))
  1430. continue;
  1431. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1432. return true;
  1433. }
  1434. return false;
  1435. }
  1436. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1437. {
  1438. struct ath_softc *sc = hw->priv;
  1439. struct ath_hw *ah = sc->sc_ah;
  1440. struct ieee80211_vif *vif;
  1441. struct ath_vif *avp;
  1442. struct ath_buf *bf;
  1443. struct ath_tx_status ts;
  1444. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1445. int status;
  1446. vif = sc->beacon.bslot[0];
  1447. if (!vif)
  1448. return 0;
  1449. if (!vif->bss_conf.enable_beacon)
  1450. return 0;
  1451. avp = (void *)vif->drv_priv;
  1452. if (!sc->beacon.tx_processed && !edma) {
  1453. tasklet_disable(&sc->bcon_tasklet);
  1454. bf = avp->av_bcbuf;
  1455. if (!bf || !bf->bf_mpdu)
  1456. goto skip;
  1457. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1458. if (status == -EINPROGRESS)
  1459. goto skip;
  1460. sc->beacon.tx_processed = true;
  1461. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1462. skip:
  1463. tasklet_enable(&sc->bcon_tasklet);
  1464. }
  1465. return sc->beacon.tx_last;
  1466. }
  1467. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1468. struct ieee80211_low_level_stats *stats)
  1469. {
  1470. struct ath_softc *sc = hw->priv;
  1471. struct ath_hw *ah = sc->sc_ah;
  1472. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1473. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1474. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1475. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1476. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1477. return 0;
  1478. }
  1479. static u32 fill_chainmask(u32 cap, u32 new)
  1480. {
  1481. u32 filled = 0;
  1482. int i;
  1483. for (i = 0; cap && new; i++, cap >>= 1) {
  1484. if (!(cap & BIT(0)))
  1485. continue;
  1486. if (new & BIT(0))
  1487. filled |= BIT(i);
  1488. new >>= 1;
  1489. }
  1490. return filled;
  1491. }
  1492. static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
  1493. {
  1494. switch (val & 0x7) {
  1495. case 0x1:
  1496. case 0x3:
  1497. case 0x7:
  1498. return true;
  1499. case 0x2:
  1500. return (ah->caps.rx_chainmask == 1);
  1501. default:
  1502. return false;
  1503. }
  1504. }
  1505. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1506. {
  1507. struct ath_softc *sc = hw->priv;
  1508. struct ath_hw *ah = sc->sc_ah;
  1509. if (ah->caps.rx_chainmask != 1)
  1510. rx_ant |= tx_ant;
  1511. if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
  1512. return -EINVAL;
  1513. sc->ant_rx = rx_ant;
  1514. sc->ant_tx = tx_ant;
  1515. if (ah->caps.rx_chainmask == 1)
  1516. return 0;
  1517. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1518. if (AR_SREV_9100(ah))
  1519. ah->rxchainmask = 0x7;
  1520. else
  1521. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1522. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1523. ath9k_reload_chainmask_settings(sc);
  1524. return 0;
  1525. }
  1526. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1527. {
  1528. struct ath_softc *sc = hw->priv;
  1529. *tx_ant = sc->ant_tx;
  1530. *rx_ant = sc->ant_rx;
  1531. return 0;
  1532. }
  1533. #ifdef CONFIG_ATH9K_DEBUGFS
  1534. /* Ethtool support for get-stats */
  1535. #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO"
  1536. static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = {
  1537. "tx_pkts_nic",
  1538. "tx_bytes_nic",
  1539. "rx_pkts_nic",
  1540. "rx_bytes_nic",
  1541. AMKSTR(d_tx_pkts),
  1542. AMKSTR(d_tx_bytes),
  1543. AMKSTR(d_tx_mpdus_queued),
  1544. AMKSTR(d_tx_mpdus_completed),
  1545. AMKSTR(d_tx_mpdu_xretries),
  1546. AMKSTR(d_tx_aggregates),
  1547. AMKSTR(d_tx_ampdus_queued_hw),
  1548. AMKSTR(d_tx_ampdus_queued_sw),
  1549. AMKSTR(d_tx_ampdus_completed),
  1550. AMKSTR(d_tx_ampdu_retries),
  1551. AMKSTR(d_tx_ampdu_xretries),
  1552. AMKSTR(d_tx_fifo_underrun),
  1553. AMKSTR(d_tx_op_exceeded),
  1554. AMKSTR(d_tx_timer_expiry),
  1555. AMKSTR(d_tx_desc_cfg_err),
  1556. AMKSTR(d_tx_data_underrun),
  1557. AMKSTR(d_tx_delim_underrun),
  1558. "d_rx_decrypt_crc_err",
  1559. "d_rx_phy_err",
  1560. "d_rx_mic_err",
  1561. "d_rx_pre_delim_crc_err",
  1562. "d_rx_post_delim_crc_err",
  1563. "d_rx_decrypt_busy_err",
  1564. "d_rx_phyerr_radar",
  1565. "d_rx_phyerr_ofdm_timing",
  1566. "d_rx_phyerr_cck_timing",
  1567. };
  1568. #define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats)
  1569. static void ath9k_get_et_strings(struct ieee80211_hw *hw,
  1570. struct ieee80211_vif *vif,
  1571. u32 sset, u8 *data)
  1572. {
  1573. if (sset == ETH_SS_STATS)
  1574. memcpy(data, *ath9k_gstrings_stats,
  1575. sizeof(ath9k_gstrings_stats));
  1576. }
  1577. static int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
  1578. struct ieee80211_vif *vif, int sset)
  1579. {
  1580. if (sset == ETH_SS_STATS)
  1581. return ATH9K_SSTATS_LEN;
  1582. return 0;
  1583. }
  1584. #define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum)
  1585. #define AWDATA(elem) \
  1586. do { \
  1587. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \
  1588. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \
  1589. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \
  1590. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \
  1591. } while (0)
  1592. #define AWDATA_RX(elem) \
  1593. do { \
  1594. data[i++] = sc->debug.stats.rxstats.elem; \
  1595. } while (0)
  1596. static void ath9k_get_et_stats(struct ieee80211_hw *hw,
  1597. struct ieee80211_vif *vif,
  1598. struct ethtool_stats *stats, u64 *data)
  1599. {
  1600. struct ath_softc *sc = hw->priv;
  1601. int i = 0;
  1602. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all +
  1603. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all +
  1604. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all +
  1605. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all);
  1606. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all +
  1607. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all +
  1608. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all +
  1609. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all);
  1610. AWDATA_RX(rx_pkts_all);
  1611. AWDATA_RX(rx_bytes_all);
  1612. AWDATA(tx_pkts_all);
  1613. AWDATA(tx_bytes_all);
  1614. AWDATA(queued);
  1615. AWDATA(completed);
  1616. AWDATA(xretries);
  1617. AWDATA(a_aggr);
  1618. AWDATA(a_queued_hw);
  1619. AWDATA(a_queued_sw);
  1620. AWDATA(a_completed);
  1621. AWDATA(a_retries);
  1622. AWDATA(a_xretries);
  1623. AWDATA(fifo_underrun);
  1624. AWDATA(xtxop);
  1625. AWDATA(timer_exp);
  1626. AWDATA(desc_cfg_err);
  1627. AWDATA(data_underrun);
  1628. AWDATA(delim_underrun);
  1629. AWDATA_RX(decrypt_crc_err);
  1630. AWDATA_RX(phy_err);
  1631. AWDATA_RX(mic_err);
  1632. AWDATA_RX(pre_delim_crc_err);
  1633. AWDATA_RX(post_delim_crc_err);
  1634. AWDATA_RX(decrypt_busy_err);
  1635. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]);
  1636. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]);
  1637. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]);
  1638. WARN_ON(i != ATH9K_SSTATS_LEN);
  1639. }
  1640. /* End of ethtool get-stats functions */
  1641. #endif
  1642. #ifdef CONFIG_PM_SLEEP
  1643. static void ath9k_wow_map_triggers(struct ath_softc *sc,
  1644. struct cfg80211_wowlan *wowlan,
  1645. u32 *wow_triggers)
  1646. {
  1647. if (wowlan->disconnect)
  1648. *wow_triggers |= AH_WOW_LINK_CHANGE |
  1649. AH_WOW_BEACON_MISS;
  1650. if (wowlan->magic_pkt)
  1651. *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
  1652. if (wowlan->n_patterns)
  1653. *wow_triggers |= AH_WOW_USER_PATTERN_EN;
  1654. sc->wow_enabled = *wow_triggers;
  1655. }
  1656. static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
  1657. {
  1658. struct ath_hw *ah = sc->sc_ah;
  1659. struct ath_common *common = ath9k_hw_common(ah);
  1660. struct ath9k_hw_capabilities *pcaps = &ah->caps;
  1661. int pattern_count = 0;
  1662. int i, byte_cnt;
  1663. u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
  1664. u8 dis_deauth_mask[MAX_PATTERN_SIZE];
  1665. memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
  1666. memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
  1667. /*
  1668. * Create Dissassociate / Deauthenticate packet filter
  1669. *
  1670. * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
  1671. * +--------------+----------+---------+--------+--------+----
  1672. * + Frame Control+ Duration + DA + SA + BSSID +
  1673. * +--------------+----------+---------+--------+--------+----
  1674. *
  1675. * The above is the management frame format for disassociate/
  1676. * deauthenticate pattern, from this we need to match the first byte
  1677. * of 'Frame Control' and DA, SA, and BSSID fields
  1678. * (skipping 2nd byte of FC and Duration feild.
  1679. *
  1680. * Disassociate pattern
  1681. * --------------------
  1682. * Frame control = 00 00 1010
  1683. * DA, SA, BSSID = x:x:x:x:x:x
  1684. * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1685. * | x:x:x:x:x:x -- 22 bytes
  1686. *
  1687. * Deauthenticate pattern
  1688. * ----------------------
  1689. * Frame control = 00 00 1100
  1690. * DA, SA, BSSID = x:x:x:x:x:x
  1691. * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1692. * | x:x:x:x:x:x -- 22 bytes
  1693. */
  1694. /* Create Disassociate Pattern first */
  1695. byte_cnt = 0;
  1696. /* Fill out the mask with all FF's */
  1697. for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
  1698. dis_deauth_mask[i] = 0xff;
  1699. /* copy the first byte of frame control field */
  1700. dis_deauth_pattern[byte_cnt] = 0xa0;
  1701. byte_cnt++;
  1702. /* skip 2nd byte of frame control and Duration field */
  1703. byte_cnt += 3;
  1704. /*
  1705. * need not match the destination mac address, it can be a broadcast
  1706. * mac address or an unicast to this station
  1707. */
  1708. byte_cnt += 6;
  1709. /* copy the source mac address */
  1710. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1711. byte_cnt += 6;
  1712. /* copy the bssid, its same as the source mac address */
  1713. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1714. /* Create Disassociate pattern mask */
  1715. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
  1716. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
  1717. /*
  1718. * for AR9280, because of hardware limitation, the
  1719. * first 4 bytes have to be matched for all patterns.
  1720. * the mask for disassociation and de-auth pattern
  1721. * matching need to enable the first 4 bytes.
  1722. * also the duration field needs to be filled.
  1723. */
  1724. dis_deauth_mask[0] = 0xf0;
  1725. /*
  1726. * fill in duration field
  1727. FIXME: what is the exact value ?
  1728. */
  1729. dis_deauth_pattern[2] = 0xff;
  1730. dis_deauth_pattern[3] = 0xff;
  1731. } else {
  1732. dis_deauth_mask[0] = 0xfe;
  1733. }
  1734. dis_deauth_mask[1] = 0x03;
  1735. dis_deauth_mask[2] = 0xc0;
  1736. } else {
  1737. dis_deauth_mask[0] = 0xef;
  1738. dis_deauth_mask[1] = 0x3f;
  1739. dis_deauth_mask[2] = 0x00;
  1740. dis_deauth_mask[3] = 0xfc;
  1741. }
  1742. ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
  1743. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1744. pattern_count, byte_cnt);
  1745. pattern_count++;
  1746. /*
  1747. * for de-authenticate pattern, only the first byte of the frame
  1748. * control field gets changed from 0xA0 to 0xC0
  1749. */
  1750. dis_deauth_pattern[0] = 0xC0;
  1751. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1752. pattern_count, byte_cnt);
  1753. }
  1754. static void ath9k_wow_add_pattern(struct ath_softc *sc,
  1755. struct cfg80211_wowlan *wowlan)
  1756. {
  1757. struct ath_hw *ah = sc->sc_ah;
  1758. struct ath9k_wow_pattern *wow_pattern = NULL;
  1759. struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
  1760. int mask_len;
  1761. s8 i = 0;
  1762. if (!wowlan->n_patterns)
  1763. return;
  1764. /*
  1765. * Add the new user configured patterns
  1766. */
  1767. for (i = 0; i < wowlan->n_patterns; i++) {
  1768. wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
  1769. if (!wow_pattern)
  1770. return;
  1771. /*
  1772. * TODO: convert the generic user space pattern to
  1773. * appropriate chip specific/802.11 pattern.
  1774. */
  1775. mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
  1776. memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
  1777. memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
  1778. memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
  1779. patterns[i].pattern_len);
  1780. memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
  1781. wow_pattern->pattern_len = patterns[i].pattern_len;
  1782. /*
  1783. * just need to take care of deauth and disssoc pattern,
  1784. * make sure we don't overwrite them.
  1785. */
  1786. ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
  1787. wow_pattern->mask_bytes,
  1788. i + 2,
  1789. wow_pattern->pattern_len);
  1790. kfree(wow_pattern);
  1791. }
  1792. }
  1793. static int ath9k_suspend(struct ieee80211_hw *hw,
  1794. struct cfg80211_wowlan *wowlan)
  1795. {
  1796. struct ath_softc *sc = hw->priv;
  1797. struct ath_hw *ah = sc->sc_ah;
  1798. struct ath_common *common = ath9k_hw_common(ah);
  1799. u32 wow_triggers_enabled = 0;
  1800. int ret = 0;
  1801. mutex_lock(&sc->mutex);
  1802. ath_cancel_work(sc);
  1803. ath_stop_ani(sc);
  1804. del_timer_sync(&sc->rx_poll_timer);
  1805. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1806. ath_dbg(common, ANY, "Device not present\n");
  1807. ret = -EINVAL;
  1808. goto fail_wow;
  1809. }
  1810. if (WARN_ON(!wowlan)) {
  1811. ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
  1812. ret = -EINVAL;
  1813. goto fail_wow;
  1814. }
  1815. if (!device_can_wakeup(sc->dev)) {
  1816. ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
  1817. ret = 1;
  1818. goto fail_wow;
  1819. }
  1820. /*
  1821. * none of the sta vifs are associated
  1822. * and we are not currently handling multivif
  1823. * cases, for instance we have to seperately
  1824. * configure 'keep alive frame' for each
  1825. * STA.
  1826. */
  1827. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  1828. ath_dbg(common, WOW, "None of the STA vifs are associated\n");
  1829. ret = 1;
  1830. goto fail_wow;
  1831. }
  1832. if (sc->nvifs > 1) {
  1833. ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
  1834. ret = 1;
  1835. goto fail_wow;
  1836. }
  1837. ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
  1838. ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
  1839. wow_triggers_enabled);
  1840. ath9k_ps_wakeup(sc);
  1841. ath9k_stop_btcoex(sc);
  1842. /*
  1843. * Enable wake up on recieving disassoc/deauth
  1844. * frame by default.
  1845. */
  1846. ath9k_wow_add_disassoc_deauth_pattern(sc);
  1847. if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
  1848. ath9k_wow_add_pattern(sc, wowlan);
  1849. spin_lock_bh(&sc->sc_pcu_lock);
  1850. /*
  1851. * To avoid false wake, we enable beacon miss interrupt only
  1852. * when we go to sleep. We save the current interrupt mask
  1853. * so we can restore it after the system wakes up
  1854. */
  1855. sc->wow_intr_before_sleep = ah->imask;
  1856. ah->imask &= ~ATH9K_INT_GLOBAL;
  1857. ath9k_hw_disable_interrupts(ah);
  1858. ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
  1859. ath9k_hw_set_interrupts(ah);
  1860. ath9k_hw_enable_interrupts(ah);
  1861. spin_unlock_bh(&sc->sc_pcu_lock);
  1862. /*
  1863. * we can now sync irq and kill any running tasklets, since we already
  1864. * disabled interrupts and not holding a spin lock
  1865. */
  1866. synchronize_irq(sc->irq);
  1867. tasklet_kill(&sc->intr_tq);
  1868. ath9k_hw_wow_enable(ah, wow_triggers_enabled);
  1869. ath9k_ps_restore(sc);
  1870. ath_dbg(common, ANY, "WoW enabled in ath9k\n");
  1871. atomic_inc(&sc->wow_sleep_proc_intr);
  1872. fail_wow:
  1873. mutex_unlock(&sc->mutex);
  1874. return ret;
  1875. }
  1876. static int ath9k_resume(struct ieee80211_hw *hw)
  1877. {
  1878. struct ath_softc *sc = hw->priv;
  1879. struct ath_hw *ah = sc->sc_ah;
  1880. struct ath_common *common = ath9k_hw_common(ah);
  1881. u32 wow_status;
  1882. mutex_lock(&sc->mutex);
  1883. ath9k_ps_wakeup(sc);
  1884. spin_lock_bh(&sc->sc_pcu_lock);
  1885. ath9k_hw_disable_interrupts(ah);
  1886. ah->imask = sc->wow_intr_before_sleep;
  1887. ath9k_hw_set_interrupts(ah);
  1888. ath9k_hw_enable_interrupts(ah);
  1889. spin_unlock_bh(&sc->sc_pcu_lock);
  1890. wow_status = ath9k_hw_wow_wakeup(ah);
  1891. if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
  1892. /*
  1893. * some devices may not pick beacon miss
  1894. * as the reason they woke up so we add
  1895. * that here for that shortcoming.
  1896. */
  1897. wow_status |= AH_WOW_BEACON_MISS;
  1898. atomic_dec(&sc->wow_got_bmiss_intr);
  1899. ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
  1900. }
  1901. atomic_dec(&sc->wow_sleep_proc_intr);
  1902. if (wow_status) {
  1903. ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
  1904. ath9k_hw_wow_event_to_string(wow_status), wow_status);
  1905. }
  1906. ath_restart_work(sc);
  1907. ath9k_start_btcoex(sc);
  1908. ath9k_ps_restore(sc);
  1909. mutex_unlock(&sc->mutex);
  1910. return 0;
  1911. }
  1912. static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
  1913. {
  1914. struct ath_softc *sc = hw->priv;
  1915. mutex_lock(&sc->mutex);
  1916. device_init_wakeup(sc->dev, 1);
  1917. device_set_wakeup_enable(sc->dev, enabled);
  1918. mutex_unlock(&sc->mutex);
  1919. }
  1920. #endif
  1921. struct ieee80211_ops ath9k_ops = {
  1922. .tx = ath9k_tx,
  1923. .start = ath9k_start,
  1924. .stop = ath9k_stop,
  1925. .add_interface = ath9k_add_interface,
  1926. .change_interface = ath9k_change_interface,
  1927. .remove_interface = ath9k_remove_interface,
  1928. .config = ath9k_config,
  1929. .configure_filter = ath9k_configure_filter,
  1930. .sta_add = ath9k_sta_add,
  1931. .sta_remove = ath9k_sta_remove,
  1932. .sta_notify = ath9k_sta_notify,
  1933. .conf_tx = ath9k_conf_tx,
  1934. .bss_info_changed = ath9k_bss_info_changed,
  1935. .set_key = ath9k_set_key,
  1936. .get_tsf = ath9k_get_tsf,
  1937. .set_tsf = ath9k_set_tsf,
  1938. .reset_tsf = ath9k_reset_tsf,
  1939. .ampdu_action = ath9k_ampdu_action,
  1940. .get_survey = ath9k_get_survey,
  1941. .rfkill_poll = ath9k_rfkill_poll_state,
  1942. .set_coverage_class = ath9k_set_coverage_class,
  1943. .flush = ath9k_flush,
  1944. .tx_frames_pending = ath9k_tx_frames_pending,
  1945. .tx_last_beacon = ath9k_tx_last_beacon,
  1946. .get_stats = ath9k_get_stats,
  1947. .set_antenna = ath9k_set_antenna,
  1948. .get_antenna = ath9k_get_antenna,
  1949. #ifdef CONFIG_PM_SLEEP
  1950. .suspend = ath9k_suspend,
  1951. .resume = ath9k_resume,
  1952. .set_wakeup = ath9k_set_wakeup,
  1953. #endif
  1954. #ifdef CONFIG_ATH9K_DEBUGFS
  1955. .get_et_sset_count = ath9k_get_et_sset_count,
  1956. .get_et_stats = ath9k_get_et_stats,
  1957. .get_et_strings = ath9k_get_et_strings,
  1958. #endif
  1959. };