mdio-bitbang.c 4.2 KB

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  1. /*
  2. * Bitbanged MDIO support.
  3. *
  4. * Author: Scott Wood <scottwood@freescale.com>
  5. * Copyright (c) 2007 Freescale Semiconductor
  6. *
  7. * Based on CPM2 MDIO code which is:
  8. *
  9. * Copyright (c) 2003 Intracom S.A.
  10. * by Pantelis Antoniou <panto@intracom.gr>
  11. *
  12. * 2005 (c) MontaVista Software, Inc.
  13. * Vitaly Bordug <vbordug@ru.mvista.com>
  14. *
  15. * This file is licensed under the terms of the GNU General Public License
  16. * version 2. This program is licensed "as is" without any warranty of any
  17. * kind, whether express or implied.
  18. */
  19. #include <linux/module.h>
  20. #include <linux/mdio-bitbang.h>
  21. #include <linux/types.h>
  22. #include <linux/delay.h>
  23. #define MDIO_READ 1
  24. #define MDIO_WRITE 0
  25. #define MDIO_SETUP_TIME 10
  26. #define MDIO_HOLD_TIME 10
  27. /* Minimum MDC period is 400 ns, plus some margin for error. MDIO_DELAY
  28. * is done twice per period.
  29. */
  30. #define MDIO_DELAY 250
  31. /* The PHY may take up to 300 ns to produce data, plus some margin
  32. * for error.
  33. */
  34. #define MDIO_READ_DELAY 350
  35. /* MDIO must already be configured as output. */
  36. static void mdiobb_send_bit(struct mdiobb_ctrl *ctrl, int val)
  37. {
  38. const struct mdiobb_ops *ops = ctrl->ops;
  39. ops->set_mdio_data(ctrl, val);
  40. ndelay(MDIO_DELAY);
  41. ops->set_mdc(ctrl, 1);
  42. ndelay(MDIO_DELAY);
  43. ops->set_mdc(ctrl, 0);
  44. }
  45. /* MDIO must already be configured as input. */
  46. static int mdiobb_get_bit(struct mdiobb_ctrl *ctrl)
  47. {
  48. const struct mdiobb_ops *ops = ctrl->ops;
  49. ndelay(MDIO_DELAY);
  50. ops->set_mdc(ctrl, 1);
  51. ndelay(MDIO_READ_DELAY);
  52. ops->set_mdc(ctrl, 0);
  53. return ops->get_mdio_data(ctrl);
  54. }
  55. /* MDIO must already be configured as output. */
  56. static void mdiobb_send_num(struct mdiobb_ctrl *ctrl, u16 val, int bits)
  57. {
  58. int i;
  59. for (i = bits - 1; i >= 0; i--)
  60. mdiobb_send_bit(ctrl, (val >> i) & 1);
  61. }
  62. /* MDIO must already be configured as input. */
  63. static u16 mdiobb_get_num(struct mdiobb_ctrl *ctrl, int bits)
  64. {
  65. int i;
  66. u16 ret = 0;
  67. for (i = bits - 1; i >= 0; i--) {
  68. ret <<= 1;
  69. ret |= mdiobb_get_bit(ctrl);
  70. }
  71. return ret;
  72. }
  73. /* Utility to send the preamble, address, and
  74. * register (common to read and write).
  75. */
  76. static void mdiobb_cmd(struct mdiobb_ctrl *ctrl, int read, u8 phy, u8 reg)
  77. {
  78. const struct mdiobb_ops *ops = ctrl->ops;
  79. int i;
  80. ops->set_mdio_dir(ctrl, 1);
  81. /*
  82. * Send a 32 bit preamble ('1's) with an extra '1' bit for good
  83. * measure. The IEEE spec says this is a PHY optional
  84. * requirement. The AMD 79C874 requires one after power up and
  85. * one after a MII communications error. This means that we are
  86. * doing more preambles than we need, but it is safer and will be
  87. * much more robust.
  88. */
  89. for (i = 0; i < 32; i++)
  90. mdiobb_send_bit(ctrl, 1);
  91. /* send the start bit (01) and the read opcode (10) or write (10) */
  92. mdiobb_send_bit(ctrl, 0);
  93. mdiobb_send_bit(ctrl, 1);
  94. mdiobb_send_bit(ctrl, read);
  95. mdiobb_send_bit(ctrl, !read);
  96. mdiobb_send_num(ctrl, phy, 5);
  97. mdiobb_send_num(ctrl, reg, 5);
  98. }
  99. static int mdiobb_read(struct mii_bus *bus, int phy, int reg)
  100. {
  101. struct mdiobb_ctrl *ctrl = bus->priv;
  102. int ret, i;
  103. mdiobb_cmd(ctrl, MDIO_READ, phy, reg);
  104. ctrl->ops->set_mdio_dir(ctrl, 0);
  105. /* check the turnaround bit: the PHY should be driving it to zero */
  106. if (mdiobb_get_bit(ctrl) != 0) {
  107. /* PHY didn't drive TA low -- flush any bits it
  108. * may be trying to send.
  109. */
  110. for (i = 0; i < 32; i++)
  111. mdiobb_get_bit(ctrl);
  112. return 0xffff;
  113. }
  114. ret = mdiobb_get_num(ctrl, 16);
  115. mdiobb_get_bit(ctrl);
  116. return ret;
  117. }
  118. static int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val)
  119. {
  120. struct mdiobb_ctrl *ctrl = bus->priv;
  121. mdiobb_cmd(ctrl, MDIO_WRITE, phy, reg);
  122. /* send the turnaround (10) */
  123. mdiobb_send_bit(ctrl, 1);
  124. mdiobb_send_bit(ctrl, 0);
  125. mdiobb_send_num(ctrl, val, 16);
  126. ctrl->ops->set_mdio_dir(ctrl, 0);
  127. mdiobb_get_bit(ctrl);
  128. return 0;
  129. }
  130. struct mii_bus *alloc_mdio_bitbang(struct mdiobb_ctrl *ctrl)
  131. {
  132. struct mii_bus *bus;
  133. bus = mdiobus_alloc();
  134. if (!bus)
  135. return NULL;
  136. __module_get(ctrl->ops->owner);
  137. bus->read = mdiobb_read;
  138. bus->write = mdiobb_write;
  139. bus->priv = ctrl;
  140. return bus;
  141. }
  142. EXPORT_SYMBOL(alloc_mdio_bitbang);
  143. void free_mdio_bitbang(struct mii_bus *bus)
  144. {
  145. struct mdiobb_ctrl *ctrl = bus->priv;
  146. module_put(ctrl->ops->owner);
  147. mdiobus_free(bus);
  148. }
  149. EXPORT_SYMBOL(free_mdio_bitbang);
  150. MODULE_LICENSE("GPL");