dma.h 6.8 KB

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  1. /*
  2. * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 2 of the License, or (at your option)
  7. * any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59
  16. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called COPYING.
  20. */
  21. #ifndef IOATDMA_H
  22. #define IOATDMA_H
  23. #include <linux/dmaengine.h>
  24. #include "hw.h"
  25. #include <linux/init.h>
  26. #include <linux/dmapool.h>
  27. #include <linux/cache.h>
  28. #include <linux/pci_ids.h>
  29. #include <net/tcp.h>
  30. #define IOAT_DMA_VERSION "3.64"
  31. #define IOAT_LOW_COMPLETION_MASK 0xffffffc0
  32. #define IOAT_DMA_DCA_ANY_CPU ~0
  33. #define IOAT_WATCHDOG_PERIOD (2 * HZ)
  34. #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
  35. #define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
  36. #define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd)
  37. #define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev)
  38. #define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
  39. #define RESET_DELAY msecs_to_jiffies(100)
  40. #define WATCHDOG_DELAY round_jiffies(msecs_to_jiffies(2000))
  41. /*
  42. * workaround for IOAT ver.3.0 null descriptor issue
  43. * (channel returns error when size is 0)
  44. */
  45. #define NULL_DESC_BUFFER_SIZE 1
  46. /**
  47. * struct ioatdma_device - internal representation of a IOAT device
  48. * @pdev: PCI-Express device
  49. * @reg_base: MMIO register space base address
  50. * @dma_pool: for allocating DMA descriptors
  51. * @common: embedded struct dma_device
  52. * @version: version of ioatdma device
  53. * @msix_entries: irq handlers
  54. * @idx: per channel data
  55. * @dca: direct cache access context
  56. * @intr_quirk: interrupt setup quirk (for ioat_v1 devices)
  57. * @enumerate_channels: hw version specific channel enumeration
  58. */
  59. struct ioatdma_device {
  60. struct pci_dev *pdev;
  61. void __iomem *reg_base;
  62. struct pci_pool *dma_pool;
  63. struct pci_pool *completion_pool;
  64. struct dma_device common;
  65. u8 version;
  66. struct delayed_work work;
  67. struct msix_entry msix_entries[4];
  68. struct ioat_chan_common *idx[4];
  69. struct dca_provider *dca;
  70. void (*intr_quirk)(struct ioatdma_device *device);
  71. int (*enumerate_channels)(struct ioatdma_device *device);
  72. };
  73. struct ioat_chan_common {
  74. void __iomem *reg_base;
  75. unsigned long last_completion;
  76. unsigned long last_completion_time;
  77. spinlock_t cleanup_lock;
  78. dma_cookie_t completed_cookie;
  79. unsigned long watchdog_completion;
  80. int watchdog_tcp_cookie;
  81. u32 watchdog_last_tcp_cookie;
  82. struct delayed_work work;
  83. struct ioatdma_device *device;
  84. struct dma_chan common;
  85. dma_addr_t completion_dma;
  86. u64 *completion;
  87. unsigned long last_compl_desc_addr_hw;
  88. struct tasklet_struct cleanup_task;
  89. };
  90. /**
  91. * struct ioat_dma_chan - internal representation of a DMA channel
  92. */
  93. struct ioat_dma_chan {
  94. struct ioat_chan_common base;
  95. size_t xfercap; /* XFERCAP register value expanded out */
  96. spinlock_t desc_lock;
  97. struct list_head free_desc;
  98. struct list_head used_desc;
  99. int pending;
  100. u16 desccount;
  101. };
  102. static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c)
  103. {
  104. return container_of(c, struct ioat_chan_common, common);
  105. }
  106. static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c)
  107. {
  108. struct ioat_chan_common *chan = to_chan_common(c);
  109. return container_of(chan, struct ioat_dma_chan, base);
  110. }
  111. /**
  112. * ioat_is_complete - poll the status of an ioat transaction
  113. * @c: channel handle
  114. * @cookie: transaction identifier
  115. * @done: if set, updated with last completed transaction
  116. * @used: if set, updated with last used transaction
  117. */
  118. static inline enum dma_status
  119. ioat_is_complete(struct dma_chan *c, dma_cookie_t cookie,
  120. dma_cookie_t *done, dma_cookie_t *used)
  121. {
  122. struct ioat_chan_common *chan = to_chan_common(c);
  123. dma_cookie_t last_used;
  124. dma_cookie_t last_complete;
  125. last_used = c->cookie;
  126. last_complete = chan->completed_cookie;
  127. chan->watchdog_tcp_cookie = cookie;
  128. if (done)
  129. *done = last_complete;
  130. if (used)
  131. *used = last_used;
  132. return dma_async_is_complete(cookie, last_complete, last_used);
  133. }
  134. /* wrapper around hardware descriptor format + additional software fields */
  135. /**
  136. * struct ioat_desc_sw - wrapper around hardware descriptor
  137. * @hw: hardware DMA descriptor
  138. * @node: this descriptor will either be on the free list,
  139. * or attached to a transaction list (async_tx.tx_list)
  140. * @tx_cnt: number of descriptors required to complete the transaction
  141. * @txd: the generic software descriptor for all engines
  142. * @id: identifier for debug
  143. */
  144. struct ioat_desc_sw {
  145. struct ioat_dma_descriptor *hw;
  146. struct list_head node;
  147. int tx_cnt;
  148. size_t len;
  149. struct dma_async_tx_descriptor txd;
  150. #ifdef DEBUG
  151. int id;
  152. #endif
  153. };
  154. #ifdef DEBUG
  155. #define set_desc_id(desc, i) ((desc)->id = (i))
  156. #define desc_id(desc) ((desc)->id)
  157. #else
  158. #define set_desc_id(desc, i)
  159. #define desc_id(desc) (0)
  160. #endif
  161. static inline void
  162. __dump_desc_dbg(struct ioat_chan_common *chan, struct ioat_dma_descriptor *hw,
  163. struct dma_async_tx_descriptor *tx, int id)
  164. {
  165. struct device *dev = to_dev(chan);
  166. dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x"
  167. " ctl: %#x (op: %d int_en: %d compl: %d)\n", id,
  168. (unsigned long long) tx->phys,
  169. (unsigned long long) hw->next, tx->cookie, tx->flags,
  170. hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write);
  171. }
  172. #define dump_desc_dbg(c, d) \
  173. ({ if (d) __dump_desc_dbg(&c->base, d->hw, &d->txd, desc_id(d)); 0; })
  174. static inline void ioat_set_tcp_copy_break(unsigned long copybreak)
  175. {
  176. #ifdef CONFIG_NET_DMA
  177. sysctl_tcp_dma_copybreak = copybreak;
  178. #endif
  179. }
  180. static inline struct ioat_chan_common *
  181. ioat_chan_by_index(struct ioatdma_device *device, int index)
  182. {
  183. return device->idx[index];
  184. }
  185. int ioat_probe(struct ioatdma_device *device);
  186. int ioat_register(struct ioatdma_device *device);
  187. int ioat1_dma_probe(struct ioatdma_device *dev, int dca);
  188. void ioat_dma_remove(struct ioatdma_device *device);
  189. struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
  190. unsigned long ioat_get_current_completion(struct ioat_chan_common *chan);
  191. void ioat_init_channel(struct ioatdma_device *device,
  192. struct ioat_chan_common *chan, int idx,
  193. work_func_t work_fn, void (*tasklet)(unsigned long),
  194. unsigned long tasklet_data);
  195. void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags,
  196. size_t len, struct ioat_dma_descriptor *hw);
  197. #endif /* IOATDMA_H */