p3060si-post.dtsi 7.4 KB

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  1. /*
  2. * P3060 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2011 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. &lbc {
  35. compatible = "fsl,p3060-elbc", "fsl,elbc", "simple-bus";
  36. interrupts = <25 2 0 0>;
  37. #address-cells = <2>;
  38. #size-cells = <1>;
  39. };
  40. /* controller at 0x200000 */
  41. &pci0 {
  42. compatible = "fsl,p3060-pcie", "fsl,qoriq-pcie-v2.2";
  43. device_type = "pci";
  44. #size-cells = <2>;
  45. #address-cells = <3>;
  46. bus-range = <0x0 0xff>;
  47. clock-frequency = <33333333>;
  48. interrupts = <16 2 1 15>;
  49. pcie@0 {
  50. reg = <0 0 0 0 0>;
  51. #interrupt-cells = <1>;
  52. #size-cells = <2>;
  53. #address-cells = <3>;
  54. device_type = "pci";
  55. interrupts = <16 2 1 15>;
  56. interrupt-map-mask = <0xf800 0 0 7>;
  57. interrupt-map = <
  58. /* IDSEL 0x0 */
  59. 0000 0 0 1 &mpic 40 1 0 0
  60. 0000 0 0 2 &mpic 1 1 0 0
  61. 0000 0 0 3 &mpic 2 1 0 0
  62. 0000 0 0 4 &mpic 3 1 0 0
  63. >;
  64. };
  65. };
  66. /* controller at 0x201000 */
  67. &pci1 {
  68. compatible = "fsl,p3060-pcie", "fsl,qoriq-pcie-v2.2";
  69. device_type = "pci";
  70. #size-cells = <2>;
  71. #address-cells = <3>;
  72. bus-range = <0 0xff>;
  73. clock-frequency = <33333333>;
  74. interrupts = <16 2 1 14>;
  75. pcie@0 {
  76. reg = <0 0 0 0 0>;
  77. #interrupt-cells = <1>;
  78. #size-cells = <2>;
  79. #address-cells = <3>;
  80. device_type = "pci";
  81. interrupts = <16 2 1 14>;
  82. interrupt-map-mask = <0xf800 0 0 7>;
  83. interrupt-map = <
  84. /* IDSEL 0x0 */
  85. 0000 0 0 1 &mpic 41 1 0 0
  86. 0000 0 0 2 &mpic 5 1 0 0
  87. 0000 0 0 3 &mpic 6 1 0 0
  88. 0000 0 0 4 &mpic 7 1 0 0
  89. >;
  90. };
  91. };
  92. &rio {
  93. compatible = "fsl,srio";
  94. interrupts = <16 2 1 11>;
  95. #address-cells = <2>;
  96. #size-cells = <2>;
  97. fsl,srio-rmu-handle = <&rmu>;
  98. ranges;
  99. port1 {
  100. #address-cells = <2>;
  101. #size-cells = <2>;
  102. cell-index = <1>;
  103. };
  104. port2 {
  105. #address-cells = <2>;
  106. #size-cells = <2>;
  107. cell-index = <2>;
  108. };
  109. };
  110. &dcsr {
  111. #address-cells = <1>;
  112. #size-cells = <1>;
  113. compatible = "fsl,dcsr", "simple-bus";
  114. dcsr-epu@0 {
  115. compatible = "fsl,dcsr-epu";
  116. interrupts = <52 2 0 0
  117. 84 2 0 0
  118. 85 2 0 0>;
  119. reg = <0x0 0x1000>;
  120. };
  121. dcsr-npc {
  122. compatible = "fsl,dcsr-npc";
  123. reg = <0x1000 0x1000 0x1000000 0x8000>;
  124. };
  125. dcsr-nxc@2000 {
  126. compatible = "fsl,dcsr-nxc";
  127. reg = <0x2000 0x1000>;
  128. };
  129. dcsr-corenet {
  130. compatible = "fsl,dcsr-corenet";
  131. reg = <0x8000 0x1000 0xB0000 0x1000>;
  132. };
  133. dcsr-dpaa@9000 {
  134. compatible = "fsl,p3060-dcsr-dpaa", "fsl,dcsr-dpaa";
  135. reg = <0x9000 0x1000>;
  136. };
  137. dcsr-ocn@11000 {
  138. compatible = "fsl,p3060-dcsr-ocn", "fsl,dcsr-ocn";
  139. reg = <0x11000 0x1000>;
  140. };
  141. dcsr-ddr@12000 {
  142. compatible = "fsl,dcsr-ddr";
  143. dev-handle = <&ddr1>;
  144. reg = <0x12000 0x1000>;
  145. };
  146. dcsr-nal@18000 {
  147. compatible = "fsl,p3060-dcsr-nal", "fsl,dcsr-nal";
  148. reg = <0x18000 0x1000>;
  149. };
  150. dcsr-rcpm@22000 {
  151. compatible = "fsl,p3060-dcsr-rcpm", "fsl,dcsr-rcpm";
  152. reg = <0x22000 0x1000>;
  153. };
  154. dcsr-cpu-sb-proxy@40000 {
  155. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  156. cpu-handle = <&cpu0>;
  157. reg = <0x40000 0x1000>;
  158. };
  159. dcsr-cpu-sb-proxy@41000 {
  160. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  161. cpu-handle = <&cpu1>;
  162. reg = <0x41000 0x1000>;
  163. };
  164. dcsr-cpu-sb-proxy@44000 {
  165. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  166. cpu-handle = <&cpu4>;
  167. reg = <0x44000 0x1000>;
  168. };
  169. dcsr-cpu-sb-proxy@45000 {
  170. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  171. cpu-handle = <&cpu5>;
  172. reg = <0x45000 0x1000>;
  173. };
  174. dcsr-cpu-sb-proxy@46000 {
  175. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  176. cpu-handle = <&cpu6>;
  177. reg = <0x46000 0x1000>;
  178. };
  179. dcsr-cpu-sb-proxy@47000 {
  180. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  181. cpu-handle = <&cpu7>;
  182. reg = <0x47000 0x1000>;
  183. };
  184. };
  185. &soc {
  186. #address-cells = <1>;
  187. #size-cells = <1>;
  188. device_type = "soc";
  189. compatible = "simple-bus";
  190. soc-sram-error {
  191. compatible = "fsl,soc-sram-error";
  192. interrupts = <16 2 1 29>;
  193. };
  194. corenet-law@0 {
  195. compatible = "fsl,corenet-law";
  196. reg = <0x0 0x1000>;
  197. fsl,num-laws = <32>;
  198. };
  199. ddr1: memory-controller@8000 {
  200. compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
  201. reg = <0x8000 0x1000>;
  202. interrupts = <16 2 1 23>;
  203. };
  204. cpc: l3-cache-controller@10000 {
  205. compatible = "fsl,p3060-l3-cache-controller", "cache";
  206. reg = <0x10000 0x1000
  207. 0x11000 0x1000>;
  208. interrupts = <16 2 1 27
  209. 16 2 1 26>;
  210. };
  211. corenet-cf@18000 {
  212. compatible = "fsl,corenet-cf";
  213. reg = <0x18000 0x1000>;
  214. interrupts = <16 2 1 31>;
  215. fsl,ccf-num-csdids = <32>;
  216. fsl,ccf-num-snoopids = <32>;
  217. };
  218. iommu@20000 {
  219. compatible = "fsl,pamu-v1.0", "fsl,pamu";
  220. reg = <0x20000 0x5000>;
  221. interrupts = <
  222. 24 2 0 0
  223. 16 2 1 30>;
  224. };
  225. /include/ "qoriq-rmu-0.dtsi"
  226. /include/ "qoriq-mpic.dtsi"
  227. guts: global-utilities@e0000 {
  228. compatible = "fsl,qoriq-device-config-1.0";
  229. reg = <0xe0000 0xe00>;
  230. fsl,has-rstcr;
  231. #sleep-cells = <1>;
  232. fsl,liodn-bits = <12>;
  233. };
  234. pins: global-utilities@e0e00 {
  235. compatible = "fsl,qoriq-pin-control-1.0";
  236. reg = <0xe0e00 0x200>;
  237. #sleep-cells = <2>;
  238. };
  239. clockgen: global-utilities@e1000 {
  240. compatible = "fsl,p3060-clockgen", "fsl,qoriq-clockgen-1.0";
  241. reg = <0xe1000 0x1000>;
  242. clock-frequency = <0>;
  243. };
  244. rcpm: global-utilities@e2000 {
  245. compatible = "fsl,qoriq-rcpm-1.0";
  246. reg = <0xe2000 0x1000>;
  247. #sleep-cells = <1>;
  248. };
  249. sfp: sfp@e8000 {
  250. compatible = "fsl,p3060-sfp", "fsl,qoriq-sfp-1.0";
  251. reg = <0xe8000 0x1000>;
  252. };
  253. serdes: serdes@ea000 {
  254. compatible = "fsl,p3060-serdes";
  255. reg = <0xea000 0x1000>;
  256. };
  257. /include/ "qoriq-dma-0.dtsi"
  258. /include/ "qoriq-dma-1.dtsi"
  259. /include/ "qoriq-espi-0.dtsi"
  260. spi@110000 {
  261. fsl,espi-num-chipselects = <4>;
  262. };
  263. /include/ "qoriq-i2c-0.dtsi"
  264. /include/ "qoriq-i2c-1.dtsi"
  265. /include/ "qoriq-duart-0.dtsi"
  266. /include/ "qoriq-duart-1.dtsi"
  267. /include/ "qoriq-gpio-0.dtsi"
  268. /include/ "qoriq-usb2-mph-0.dtsi"
  269. /include/ "qoriq-usb2-dr-0.dtsi"
  270. /include/ "qoriq-sec4.1-0.dtsi"
  271. };