intel_sdvo.c 86 KB

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  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2007 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. */
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <linux/delay.h>
  31. #include <linux/export.h>
  32. #include <drm/drmP.h>
  33. #include <drm/drm_crtc.h>
  34. #include <drm/drm_edid.h>
  35. #include "intel_drv.h"
  36. #include <drm/i915_drm.h>
  37. #include "i915_drv.h"
  38. #include "intel_sdvo_regs.h"
  39. #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
  40. #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
  41. #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
  42. #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
  43. #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
  44. SDVO_TV_MASK)
  45. #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
  46. #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
  47. #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
  48. #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
  49. #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
  50. static const char *tv_format_names[] = {
  51. "NTSC_M" , "NTSC_J" , "NTSC_443",
  52. "PAL_B" , "PAL_D" , "PAL_G" ,
  53. "PAL_H" , "PAL_I" , "PAL_M" ,
  54. "PAL_N" , "PAL_NC" , "PAL_60" ,
  55. "SECAM_B" , "SECAM_D" , "SECAM_G" ,
  56. "SECAM_K" , "SECAM_K1", "SECAM_L" ,
  57. "SECAM_60"
  58. };
  59. #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
  60. struct intel_sdvo {
  61. struct intel_encoder base;
  62. struct i2c_adapter *i2c;
  63. u8 slave_addr;
  64. struct i2c_adapter ddc;
  65. /* Register for the SDVO device: SDVOB or SDVOC */
  66. uint32_t sdvo_reg;
  67. /* Active outputs controlled by this SDVO output */
  68. uint16_t controlled_output;
  69. /*
  70. * Capabilities of the SDVO device returned by
  71. * i830_sdvo_get_capabilities()
  72. */
  73. struct intel_sdvo_caps caps;
  74. /* Pixel clock limitations reported by the SDVO device, in kHz */
  75. int pixel_clock_min, pixel_clock_max;
  76. /*
  77. * For multiple function SDVO device,
  78. * this is for current attached outputs.
  79. */
  80. uint16_t attached_output;
  81. /*
  82. * Hotplug activation bits for this device
  83. */
  84. uint16_t hotplug_active;
  85. /**
  86. * This is used to select the color range of RBG outputs in HDMI mode.
  87. * It is only valid when using TMDS encoding and 8 bit per color mode.
  88. */
  89. uint32_t color_range;
  90. bool color_range_auto;
  91. /**
  92. * This is set if we're going to treat the device as TV-out.
  93. *
  94. * While we have these nice friendly flags for output types that ought
  95. * to decide this for us, the S-Video output on our HDMI+S-Video card
  96. * shows up as RGB1 (VGA).
  97. */
  98. bool is_tv;
  99. /* On different gens SDVOB is at different places. */
  100. bool is_sdvob;
  101. /* This is for current tv format name */
  102. int tv_format_index;
  103. /**
  104. * This is set if we treat the device as HDMI, instead of DVI.
  105. */
  106. bool is_hdmi;
  107. bool has_hdmi_monitor;
  108. bool has_hdmi_audio;
  109. bool rgb_quant_range_selectable;
  110. /**
  111. * This is set if we detect output of sdvo device as LVDS and
  112. * have a valid fixed mode to use with the panel.
  113. */
  114. bool is_lvds;
  115. /**
  116. * This is sdvo fixed pannel mode pointer
  117. */
  118. struct drm_display_mode *sdvo_lvds_fixed_mode;
  119. /* DDC bus used by this SDVO encoder */
  120. uint8_t ddc_bus;
  121. /*
  122. * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
  123. */
  124. uint8_t dtd_sdvo_flags;
  125. };
  126. struct intel_sdvo_connector {
  127. struct intel_connector base;
  128. /* Mark the type of connector */
  129. uint16_t output_flag;
  130. enum hdmi_force_audio force_audio;
  131. /* This contains all current supported TV format */
  132. u8 tv_format_supported[TV_FORMAT_NUM];
  133. int format_supported_num;
  134. struct drm_property *tv_format;
  135. /* add the property for the SDVO-TV */
  136. struct drm_property *left;
  137. struct drm_property *right;
  138. struct drm_property *top;
  139. struct drm_property *bottom;
  140. struct drm_property *hpos;
  141. struct drm_property *vpos;
  142. struct drm_property *contrast;
  143. struct drm_property *saturation;
  144. struct drm_property *hue;
  145. struct drm_property *sharpness;
  146. struct drm_property *flicker_filter;
  147. struct drm_property *flicker_filter_adaptive;
  148. struct drm_property *flicker_filter_2d;
  149. struct drm_property *tv_chroma_filter;
  150. struct drm_property *tv_luma_filter;
  151. struct drm_property *dot_crawl;
  152. /* add the property for the SDVO-TV/LVDS */
  153. struct drm_property *brightness;
  154. /* Add variable to record current setting for the above property */
  155. u32 left_margin, right_margin, top_margin, bottom_margin;
  156. /* this is to get the range of margin.*/
  157. u32 max_hscan, max_vscan;
  158. u32 max_hpos, cur_hpos;
  159. u32 max_vpos, cur_vpos;
  160. u32 cur_brightness, max_brightness;
  161. u32 cur_contrast, max_contrast;
  162. u32 cur_saturation, max_saturation;
  163. u32 cur_hue, max_hue;
  164. u32 cur_sharpness, max_sharpness;
  165. u32 cur_flicker_filter, max_flicker_filter;
  166. u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
  167. u32 cur_flicker_filter_2d, max_flicker_filter_2d;
  168. u32 cur_tv_chroma_filter, max_tv_chroma_filter;
  169. u32 cur_tv_luma_filter, max_tv_luma_filter;
  170. u32 cur_dot_crawl, max_dot_crawl;
  171. };
  172. static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
  173. {
  174. return container_of(encoder, struct intel_sdvo, base.base);
  175. }
  176. static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
  177. {
  178. return container_of(intel_attached_encoder(connector),
  179. struct intel_sdvo, base);
  180. }
  181. static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
  182. {
  183. return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
  184. }
  185. static bool
  186. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
  187. static bool
  188. intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  189. struct intel_sdvo_connector *intel_sdvo_connector,
  190. int type);
  191. static bool
  192. intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  193. struct intel_sdvo_connector *intel_sdvo_connector);
  194. /**
  195. * Writes the SDVOB or SDVOC with the given value, but always writes both
  196. * SDVOB and SDVOC to work around apparent hardware issues (according to
  197. * comments in the BIOS).
  198. */
  199. static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
  200. {
  201. struct drm_device *dev = intel_sdvo->base.base.dev;
  202. struct drm_i915_private *dev_priv = dev->dev_private;
  203. u32 bval = val, cval = val;
  204. int i;
  205. if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
  206. I915_WRITE(intel_sdvo->sdvo_reg, val);
  207. I915_READ(intel_sdvo->sdvo_reg);
  208. return;
  209. }
  210. if (intel_sdvo->sdvo_reg == GEN3_SDVOB)
  211. cval = I915_READ(GEN3_SDVOC);
  212. else
  213. bval = I915_READ(GEN3_SDVOB);
  214. /*
  215. * Write the registers twice for luck. Sometimes,
  216. * writing them only once doesn't appear to 'stick'.
  217. * The BIOS does this too. Yay, magic
  218. */
  219. for (i = 0; i < 2; i++)
  220. {
  221. I915_WRITE(GEN3_SDVOB, bval);
  222. I915_READ(GEN3_SDVOB);
  223. I915_WRITE(GEN3_SDVOC, cval);
  224. I915_READ(GEN3_SDVOC);
  225. }
  226. }
  227. static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
  228. {
  229. struct i2c_msg msgs[] = {
  230. {
  231. .addr = intel_sdvo->slave_addr,
  232. .flags = 0,
  233. .len = 1,
  234. .buf = &addr,
  235. },
  236. {
  237. .addr = intel_sdvo->slave_addr,
  238. .flags = I2C_M_RD,
  239. .len = 1,
  240. .buf = ch,
  241. }
  242. };
  243. int ret;
  244. if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
  245. return true;
  246. DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
  247. return false;
  248. }
  249. #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
  250. /** Mapping of command numbers to names, for debug output */
  251. static const struct _sdvo_cmd_name {
  252. u8 cmd;
  253. const char *name;
  254. } sdvo_cmd_names[] = {
  255. SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
  256. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
  257. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
  258. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
  259. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
  260. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
  261. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
  262. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
  263. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
  264. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
  265. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
  266. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
  267. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
  268. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
  269. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
  270. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
  271. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
  272. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  273. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
  274. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  275. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
  276. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
  277. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
  278. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
  279. SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
  280. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
  281. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
  282. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
  283. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
  284. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
  285. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
  286. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
  287. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
  288. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
  289. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
  290. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
  291. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
  292. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
  293. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
  294. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
  295. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
  296. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
  297. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
  298. /* Add the op code for SDVO enhancements */
  299. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
  300. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
  301. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
  302. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
  303. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
  304. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
  305. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
  306. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
  307. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
  308. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
  309. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
  310. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
  311. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
  312. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
  313. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
  314. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
  315. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
  316. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
  317. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
  318. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
  319. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
  320. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
  321. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
  322. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
  323. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
  324. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
  325. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
  326. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
  327. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
  328. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
  329. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
  330. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
  331. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
  332. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
  333. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
  334. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
  335. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
  336. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
  337. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
  338. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
  339. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
  340. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
  341. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
  342. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
  343. /* HDMI op code */
  344. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
  345. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
  346. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
  347. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
  348. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
  349. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
  350. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
  351. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
  352. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
  353. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
  354. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
  355. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
  356. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
  357. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
  358. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
  359. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
  360. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
  361. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
  362. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
  363. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
  364. };
  365. #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
  366. static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
  367. const void *args, int args_len)
  368. {
  369. int i;
  370. DRM_DEBUG_KMS("%s: W: %02X ",
  371. SDVO_NAME(intel_sdvo), cmd);
  372. for (i = 0; i < args_len; i++)
  373. DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
  374. for (; i < 8; i++)
  375. DRM_LOG_KMS(" ");
  376. for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
  377. if (cmd == sdvo_cmd_names[i].cmd) {
  378. DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
  379. break;
  380. }
  381. }
  382. if (i == ARRAY_SIZE(sdvo_cmd_names))
  383. DRM_LOG_KMS("(%02X)", cmd);
  384. DRM_LOG_KMS("\n");
  385. }
  386. static const char *cmd_status_names[] = {
  387. "Power on",
  388. "Success",
  389. "Not supported",
  390. "Invalid arg",
  391. "Pending",
  392. "Target not specified",
  393. "Scaling not supported"
  394. };
  395. static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
  396. const void *args, int args_len)
  397. {
  398. u8 *buf, status;
  399. struct i2c_msg *msgs;
  400. int i, ret = true;
  401. /* Would be simpler to allocate both in one go ? */
  402. buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL);
  403. if (!buf)
  404. return false;
  405. msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
  406. if (!msgs) {
  407. kfree(buf);
  408. return false;
  409. }
  410. intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
  411. for (i = 0; i < args_len; i++) {
  412. msgs[i].addr = intel_sdvo->slave_addr;
  413. msgs[i].flags = 0;
  414. msgs[i].len = 2;
  415. msgs[i].buf = buf + 2 *i;
  416. buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
  417. buf[2*i + 1] = ((u8*)args)[i];
  418. }
  419. msgs[i].addr = intel_sdvo->slave_addr;
  420. msgs[i].flags = 0;
  421. msgs[i].len = 2;
  422. msgs[i].buf = buf + 2*i;
  423. buf[2*i + 0] = SDVO_I2C_OPCODE;
  424. buf[2*i + 1] = cmd;
  425. /* the following two are to read the response */
  426. status = SDVO_I2C_CMD_STATUS;
  427. msgs[i+1].addr = intel_sdvo->slave_addr;
  428. msgs[i+1].flags = 0;
  429. msgs[i+1].len = 1;
  430. msgs[i+1].buf = &status;
  431. msgs[i+2].addr = intel_sdvo->slave_addr;
  432. msgs[i+2].flags = I2C_M_RD;
  433. msgs[i+2].len = 1;
  434. msgs[i+2].buf = &status;
  435. ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
  436. if (ret < 0) {
  437. DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
  438. ret = false;
  439. goto out;
  440. }
  441. if (ret != i+3) {
  442. /* failure in I2C transfer */
  443. DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
  444. ret = false;
  445. }
  446. out:
  447. kfree(msgs);
  448. kfree(buf);
  449. return ret;
  450. }
  451. static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
  452. void *response, int response_len)
  453. {
  454. u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
  455. u8 status;
  456. int i;
  457. DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
  458. /*
  459. * The documentation states that all commands will be
  460. * processed within 15µs, and that we need only poll
  461. * the status byte a maximum of 3 times in order for the
  462. * command to be complete.
  463. *
  464. * Check 5 times in case the hardware failed to read the docs.
  465. *
  466. * Also beware that the first response by many devices is to
  467. * reply PENDING and stall for time. TVs are notorious for
  468. * requiring longer than specified to complete their replies.
  469. * Originally (in the DDX long ago), the delay was only ever 15ms
  470. * with an additional delay of 30ms applied for TVs added later after
  471. * many experiments. To accommodate both sets of delays, we do a
  472. * sequence of slow checks if the device is falling behind and fails
  473. * to reply within 5*15µs.
  474. */
  475. if (!intel_sdvo_read_byte(intel_sdvo,
  476. SDVO_I2C_CMD_STATUS,
  477. &status))
  478. goto log_fail;
  479. while (status == SDVO_CMD_STATUS_PENDING && --retry) {
  480. if (retry < 10)
  481. msleep(15);
  482. else
  483. udelay(15);
  484. if (!intel_sdvo_read_byte(intel_sdvo,
  485. SDVO_I2C_CMD_STATUS,
  486. &status))
  487. goto log_fail;
  488. }
  489. if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
  490. DRM_LOG_KMS("(%s)", cmd_status_names[status]);
  491. else
  492. DRM_LOG_KMS("(??? %d)", status);
  493. if (status != SDVO_CMD_STATUS_SUCCESS)
  494. goto log_fail;
  495. /* Read the command response */
  496. for (i = 0; i < response_len; i++) {
  497. if (!intel_sdvo_read_byte(intel_sdvo,
  498. SDVO_I2C_RETURN_0 + i,
  499. &((u8 *)response)[i]))
  500. goto log_fail;
  501. DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
  502. }
  503. DRM_LOG_KMS("\n");
  504. return true;
  505. log_fail:
  506. DRM_LOG_KMS("... failed\n");
  507. return false;
  508. }
  509. static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
  510. {
  511. if (mode->clock >= 100000)
  512. return 1;
  513. else if (mode->clock >= 50000)
  514. return 2;
  515. else
  516. return 4;
  517. }
  518. static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
  519. u8 ddc_bus)
  520. {
  521. /* This must be the immediately preceding write before the i2c xfer */
  522. return intel_sdvo_write_cmd(intel_sdvo,
  523. SDVO_CMD_SET_CONTROL_BUS_SWITCH,
  524. &ddc_bus, 1);
  525. }
  526. static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
  527. {
  528. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
  529. return false;
  530. return intel_sdvo_read_response(intel_sdvo, NULL, 0);
  531. }
  532. static bool
  533. intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
  534. {
  535. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
  536. return false;
  537. return intel_sdvo_read_response(intel_sdvo, value, len);
  538. }
  539. static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
  540. {
  541. struct intel_sdvo_set_target_input_args targets = {0};
  542. return intel_sdvo_set_value(intel_sdvo,
  543. SDVO_CMD_SET_TARGET_INPUT,
  544. &targets, sizeof(targets));
  545. }
  546. /**
  547. * Return whether each input is trained.
  548. *
  549. * This function is making an assumption about the layout of the response,
  550. * which should be checked against the docs.
  551. */
  552. static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
  553. {
  554. struct intel_sdvo_get_trained_inputs_response response;
  555. BUILD_BUG_ON(sizeof(response) != 1);
  556. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
  557. &response, sizeof(response)))
  558. return false;
  559. *input_1 = response.input0_trained;
  560. *input_2 = response.input1_trained;
  561. return true;
  562. }
  563. static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
  564. u16 outputs)
  565. {
  566. return intel_sdvo_set_value(intel_sdvo,
  567. SDVO_CMD_SET_ACTIVE_OUTPUTS,
  568. &outputs, sizeof(outputs));
  569. }
  570. static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
  571. u16 *outputs)
  572. {
  573. return intel_sdvo_get_value(intel_sdvo,
  574. SDVO_CMD_GET_ACTIVE_OUTPUTS,
  575. outputs, sizeof(*outputs));
  576. }
  577. static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
  578. int mode)
  579. {
  580. u8 state = SDVO_ENCODER_STATE_ON;
  581. switch (mode) {
  582. case DRM_MODE_DPMS_ON:
  583. state = SDVO_ENCODER_STATE_ON;
  584. break;
  585. case DRM_MODE_DPMS_STANDBY:
  586. state = SDVO_ENCODER_STATE_STANDBY;
  587. break;
  588. case DRM_MODE_DPMS_SUSPEND:
  589. state = SDVO_ENCODER_STATE_SUSPEND;
  590. break;
  591. case DRM_MODE_DPMS_OFF:
  592. state = SDVO_ENCODER_STATE_OFF;
  593. break;
  594. }
  595. return intel_sdvo_set_value(intel_sdvo,
  596. SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
  597. }
  598. static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
  599. int *clock_min,
  600. int *clock_max)
  601. {
  602. struct intel_sdvo_pixel_clock_range clocks;
  603. BUILD_BUG_ON(sizeof(clocks) != 4);
  604. if (!intel_sdvo_get_value(intel_sdvo,
  605. SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
  606. &clocks, sizeof(clocks)))
  607. return false;
  608. /* Convert the values from units of 10 kHz to kHz. */
  609. *clock_min = clocks.min * 10;
  610. *clock_max = clocks.max * 10;
  611. return true;
  612. }
  613. static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
  614. u16 outputs)
  615. {
  616. return intel_sdvo_set_value(intel_sdvo,
  617. SDVO_CMD_SET_TARGET_OUTPUT,
  618. &outputs, sizeof(outputs));
  619. }
  620. static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
  621. struct intel_sdvo_dtd *dtd)
  622. {
  623. return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
  624. intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  625. }
  626. static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
  627. struct intel_sdvo_dtd *dtd)
  628. {
  629. return intel_sdvo_set_timing(intel_sdvo,
  630. SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
  631. }
  632. static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
  633. struct intel_sdvo_dtd *dtd)
  634. {
  635. return intel_sdvo_set_timing(intel_sdvo,
  636. SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
  637. }
  638. static bool
  639. intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  640. uint16_t clock,
  641. uint16_t width,
  642. uint16_t height)
  643. {
  644. struct intel_sdvo_preferred_input_timing_args args;
  645. memset(&args, 0, sizeof(args));
  646. args.clock = clock;
  647. args.width = width;
  648. args.height = height;
  649. args.interlace = 0;
  650. if (intel_sdvo->is_lvds &&
  651. (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
  652. intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
  653. args.scaled = 1;
  654. return intel_sdvo_set_value(intel_sdvo,
  655. SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
  656. &args, sizeof(args));
  657. }
  658. static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  659. struct intel_sdvo_dtd *dtd)
  660. {
  661. BUILD_BUG_ON(sizeof(dtd->part1) != 8);
  662. BUILD_BUG_ON(sizeof(dtd->part2) != 8);
  663. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
  664. &dtd->part1, sizeof(dtd->part1)) &&
  665. intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
  666. &dtd->part2, sizeof(dtd->part2));
  667. }
  668. static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
  669. {
  670. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
  671. }
  672. static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
  673. const struct drm_display_mode *mode)
  674. {
  675. uint16_t width, height;
  676. uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
  677. uint16_t h_sync_offset, v_sync_offset;
  678. int mode_clock;
  679. width = mode->hdisplay;
  680. height = mode->vdisplay;
  681. /* do some mode translations */
  682. h_blank_len = mode->htotal - mode->hdisplay;
  683. h_sync_len = mode->hsync_end - mode->hsync_start;
  684. v_blank_len = mode->vtotal - mode->vdisplay;
  685. v_sync_len = mode->vsync_end - mode->vsync_start;
  686. h_sync_offset = mode->hsync_start - mode->hdisplay;
  687. v_sync_offset = mode->vsync_start - mode->vdisplay;
  688. mode_clock = mode->clock;
  689. mode_clock /= intel_mode_get_pixel_multiplier(mode) ?: 1;
  690. mode_clock /= 10;
  691. dtd->part1.clock = mode_clock;
  692. dtd->part1.h_active = width & 0xff;
  693. dtd->part1.h_blank = h_blank_len & 0xff;
  694. dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
  695. ((h_blank_len >> 8) & 0xf);
  696. dtd->part1.v_active = height & 0xff;
  697. dtd->part1.v_blank = v_blank_len & 0xff;
  698. dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
  699. ((v_blank_len >> 8) & 0xf);
  700. dtd->part2.h_sync_off = h_sync_offset & 0xff;
  701. dtd->part2.h_sync_width = h_sync_len & 0xff;
  702. dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
  703. (v_sync_len & 0xf);
  704. dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
  705. ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
  706. ((v_sync_len & 0x30) >> 4);
  707. dtd->part2.dtd_flags = 0x18;
  708. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  709. dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
  710. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  711. dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
  712. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  713. dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
  714. dtd->part2.sdvo_flags = 0;
  715. dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
  716. dtd->part2.reserved = 0;
  717. }
  718. static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
  719. const struct intel_sdvo_dtd *dtd)
  720. {
  721. mode->hdisplay = dtd->part1.h_active;
  722. mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
  723. mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
  724. mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
  725. mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
  726. mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
  727. mode->htotal = mode->hdisplay + dtd->part1.h_blank;
  728. mode->htotal += (dtd->part1.h_high & 0xf) << 8;
  729. mode->vdisplay = dtd->part1.v_active;
  730. mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
  731. mode->vsync_start = mode->vdisplay;
  732. mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
  733. mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
  734. mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
  735. mode->vsync_end = mode->vsync_start +
  736. (dtd->part2.v_sync_off_width & 0xf);
  737. mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
  738. mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
  739. mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
  740. mode->clock = dtd->part1.clock * 10;
  741. mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  742. if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
  743. mode->flags |= DRM_MODE_FLAG_INTERLACE;
  744. if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
  745. mode->flags |= DRM_MODE_FLAG_PHSYNC;
  746. if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
  747. mode->flags |= DRM_MODE_FLAG_PVSYNC;
  748. }
  749. static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
  750. {
  751. struct intel_sdvo_encode encode;
  752. BUILD_BUG_ON(sizeof(encode) != 2);
  753. return intel_sdvo_get_value(intel_sdvo,
  754. SDVO_CMD_GET_SUPP_ENCODE,
  755. &encode, sizeof(encode));
  756. }
  757. static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
  758. uint8_t mode)
  759. {
  760. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
  761. }
  762. static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
  763. uint8_t mode)
  764. {
  765. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
  766. }
  767. #if 0
  768. static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
  769. {
  770. int i, j;
  771. uint8_t set_buf_index[2];
  772. uint8_t av_split;
  773. uint8_t buf_size;
  774. uint8_t buf[48];
  775. uint8_t *pos;
  776. intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
  777. for (i = 0; i <= av_split; i++) {
  778. set_buf_index[0] = i; set_buf_index[1] = 0;
  779. intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
  780. set_buf_index, 2);
  781. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
  782. intel_sdvo_read_response(encoder, &buf_size, 1);
  783. pos = buf;
  784. for (j = 0; j <= buf_size; j += 8) {
  785. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
  786. NULL, 0);
  787. intel_sdvo_read_response(encoder, pos, 8);
  788. pos += 8;
  789. }
  790. }
  791. }
  792. #endif
  793. static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
  794. unsigned if_index, uint8_t tx_rate,
  795. uint8_t *data, unsigned length)
  796. {
  797. uint8_t set_buf_index[2] = { if_index, 0 };
  798. uint8_t hbuf_size, tmp[8];
  799. int i;
  800. if (!intel_sdvo_set_value(intel_sdvo,
  801. SDVO_CMD_SET_HBUF_INDEX,
  802. set_buf_index, 2))
  803. return false;
  804. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
  805. &hbuf_size, 1))
  806. return false;
  807. /* Buffer size is 0 based, hooray! */
  808. hbuf_size++;
  809. DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
  810. if_index, length, hbuf_size);
  811. for (i = 0; i < hbuf_size; i += 8) {
  812. memset(tmp, 0, 8);
  813. if (i < length)
  814. memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
  815. if (!intel_sdvo_set_value(intel_sdvo,
  816. SDVO_CMD_SET_HBUF_DATA,
  817. tmp, 8))
  818. return false;
  819. }
  820. return intel_sdvo_set_value(intel_sdvo,
  821. SDVO_CMD_SET_HBUF_TXRATE,
  822. &tx_rate, 1);
  823. }
  824. static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
  825. const struct drm_display_mode *adjusted_mode)
  826. {
  827. struct dip_infoframe avi_if = {
  828. .type = DIP_TYPE_AVI,
  829. .ver = DIP_VERSION_AVI,
  830. .len = DIP_LEN_AVI,
  831. };
  832. uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
  833. if (intel_sdvo->rgb_quant_range_selectable) {
  834. if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
  835. avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED;
  836. else
  837. avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL;
  838. }
  839. intel_dip_infoframe_csum(&avi_if);
  840. /* sdvo spec says that the ecc is handled by the hw, and it looks like
  841. * we must not send the ecc field, either. */
  842. memcpy(sdvo_data, &avi_if, 3);
  843. sdvo_data[3] = avi_if.checksum;
  844. memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
  845. return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
  846. SDVO_HBUF_TX_VSYNC,
  847. sdvo_data, sizeof(sdvo_data));
  848. }
  849. static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
  850. {
  851. struct intel_sdvo_tv_format format;
  852. uint32_t format_map;
  853. format_map = 1 << intel_sdvo->tv_format_index;
  854. memset(&format, 0, sizeof(format));
  855. memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
  856. BUILD_BUG_ON(sizeof(format) != 6);
  857. return intel_sdvo_set_value(intel_sdvo,
  858. SDVO_CMD_SET_TV_FORMAT,
  859. &format, sizeof(format));
  860. }
  861. static bool
  862. intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
  863. const struct drm_display_mode *mode)
  864. {
  865. struct intel_sdvo_dtd output_dtd;
  866. if (!intel_sdvo_set_target_output(intel_sdvo,
  867. intel_sdvo->attached_output))
  868. return false;
  869. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  870. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  871. return false;
  872. return true;
  873. }
  874. /* Asks the sdvo controller for the preferred input mode given the output mode.
  875. * Unfortunately we have to set up the full output mode to do that. */
  876. static bool
  877. intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
  878. const struct drm_display_mode *mode,
  879. struct drm_display_mode *adjusted_mode)
  880. {
  881. struct intel_sdvo_dtd input_dtd;
  882. /* Reset the input timing to the screen. Assume always input 0. */
  883. if (!intel_sdvo_set_target_input(intel_sdvo))
  884. return false;
  885. if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
  886. mode->clock / 10,
  887. mode->hdisplay,
  888. mode->vdisplay))
  889. return false;
  890. if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
  891. &input_dtd))
  892. return false;
  893. intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
  894. intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
  895. return true;
  896. }
  897. static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
  898. const struct drm_display_mode *mode,
  899. struct drm_display_mode *adjusted_mode)
  900. {
  901. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  902. int multiplier;
  903. /* We need to construct preferred input timings based on our
  904. * output timings. To do that, we have to set the output
  905. * timings, even though this isn't really the right place in
  906. * the sequence to do it. Oh well.
  907. */
  908. if (intel_sdvo->is_tv) {
  909. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
  910. return false;
  911. (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
  912. mode,
  913. adjusted_mode);
  914. } else if (intel_sdvo->is_lvds) {
  915. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
  916. intel_sdvo->sdvo_lvds_fixed_mode))
  917. return false;
  918. (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
  919. mode,
  920. adjusted_mode);
  921. }
  922. /* Make the CRTC code factor in the SDVO pixel multiplier. The
  923. * SDVO device will factor out the multiplier during mode_set.
  924. */
  925. multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
  926. intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
  927. if (intel_sdvo->color_range_auto) {
  928. /* See CEA-861-E - 5.1 Default Encoding Parameters */
  929. /* FIXME: This bit is only valid when using TMDS encoding and 8
  930. * bit per color mode. */
  931. if (intel_sdvo->has_hdmi_monitor &&
  932. drm_mode_cea_vic(adjusted_mode) > 1)
  933. intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
  934. else
  935. intel_sdvo->color_range = 0;
  936. }
  937. if (intel_sdvo->color_range)
  938. adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE;
  939. return true;
  940. }
  941. static void intel_sdvo_mode_set(struct drm_encoder *encoder,
  942. struct drm_display_mode *mode,
  943. struct drm_display_mode *adjusted_mode)
  944. {
  945. struct drm_device *dev = encoder->dev;
  946. struct drm_i915_private *dev_priv = dev->dev_private;
  947. struct drm_crtc *crtc = encoder->crtc;
  948. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  949. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  950. u32 sdvox;
  951. struct intel_sdvo_in_out_map in_out;
  952. struct intel_sdvo_dtd input_dtd, output_dtd;
  953. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  954. int rate;
  955. if (!mode)
  956. return;
  957. /* First, set the input mapping for the first input to our controlled
  958. * output. This is only correct if we're a single-input device, in
  959. * which case the first input is the output from the appropriate SDVO
  960. * channel on the motherboard. In a two-input device, the first input
  961. * will be SDVOB and the second SDVOC.
  962. */
  963. in_out.in0 = intel_sdvo->attached_output;
  964. in_out.in1 = 0;
  965. intel_sdvo_set_value(intel_sdvo,
  966. SDVO_CMD_SET_IN_OUT_MAP,
  967. &in_out, sizeof(in_out));
  968. /* Set the output timings to the screen */
  969. if (!intel_sdvo_set_target_output(intel_sdvo,
  970. intel_sdvo->attached_output))
  971. return;
  972. /* lvds has a special fixed output timing. */
  973. if (intel_sdvo->is_lvds)
  974. intel_sdvo_get_dtd_from_mode(&output_dtd,
  975. intel_sdvo->sdvo_lvds_fixed_mode);
  976. else
  977. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  978. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  979. DRM_INFO("Setting output timings on %s failed\n",
  980. SDVO_NAME(intel_sdvo));
  981. /* Set the input timing to the screen. Assume always input 0. */
  982. if (!intel_sdvo_set_target_input(intel_sdvo))
  983. return;
  984. if (intel_sdvo->has_hdmi_monitor) {
  985. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
  986. intel_sdvo_set_colorimetry(intel_sdvo,
  987. SDVO_COLORIMETRY_RGB256);
  988. intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
  989. } else
  990. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
  991. if (intel_sdvo->is_tv &&
  992. !intel_sdvo_set_tv_format(intel_sdvo))
  993. return;
  994. /* We have tried to get input timing in mode_fixup, and filled into
  995. * adjusted_mode.
  996. */
  997. intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
  998. if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
  999. input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
  1000. if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
  1001. DRM_INFO("Setting input timings on %s failed\n",
  1002. SDVO_NAME(intel_sdvo));
  1003. switch (pixel_multiplier) {
  1004. default:
  1005. case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
  1006. case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
  1007. case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
  1008. }
  1009. if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
  1010. return;
  1011. /* Set the SDVO control regs. */
  1012. if (INTEL_INFO(dev)->gen >= 4) {
  1013. /* The real mode polarity is set by the SDVO commands, using
  1014. * struct intel_sdvo_dtd. */
  1015. sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
  1016. if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi)
  1017. sdvox |= intel_sdvo->color_range;
  1018. if (INTEL_INFO(dev)->gen < 5)
  1019. sdvox |= SDVO_BORDER_ENABLE;
  1020. } else {
  1021. sdvox = I915_READ(intel_sdvo->sdvo_reg);
  1022. switch (intel_sdvo->sdvo_reg) {
  1023. case GEN3_SDVOB:
  1024. sdvox &= SDVOB_PRESERVE_MASK;
  1025. break;
  1026. case GEN3_SDVOC:
  1027. sdvox &= SDVOC_PRESERVE_MASK;
  1028. break;
  1029. }
  1030. sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
  1031. }
  1032. if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
  1033. sdvox |= SDVO_PIPE_SEL_CPT(intel_crtc->pipe);
  1034. else
  1035. sdvox |= SDVO_PIPE_SEL(intel_crtc->pipe);
  1036. if (intel_sdvo->has_hdmi_audio)
  1037. sdvox |= SDVO_AUDIO_ENABLE;
  1038. if (INTEL_INFO(dev)->gen >= 4) {
  1039. /* done in crtc_mode_set as the dpll_md reg must be written early */
  1040. } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  1041. /* done in crtc_mode_set as it lives inside the dpll register */
  1042. } else {
  1043. sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
  1044. }
  1045. if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
  1046. INTEL_INFO(dev)->gen < 5)
  1047. sdvox |= SDVO_STALL_SELECT;
  1048. intel_sdvo_write_sdvox(intel_sdvo, sdvox);
  1049. }
  1050. static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
  1051. {
  1052. struct intel_sdvo_connector *intel_sdvo_connector =
  1053. to_intel_sdvo_connector(&connector->base);
  1054. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
  1055. u16 active_outputs;
  1056. intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
  1057. if (active_outputs & intel_sdvo_connector->output_flag)
  1058. return true;
  1059. else
  1060. return false;
  1061. }
  1062. static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
  1063. enum pipe *pipe)
  1064. {
  1065. struct drm_device *dev = encoder->base.dev;
  1066. struct drm_i915_private *dev_priv = dev->dev_private;
  1067. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1068. u32 tmp;
  1069. tmp = I915_READ(intel_sdvo->sdvo_reg);
  1070. if (!(tmp & SDVO_ENABLE))
  1071. return false;
  1072. if (HAS_PCH_CPT(dev))
  1073. *pipe = PORT_TO_PIPE_CPT(tmp);
  1074. else
  1075. *pipe = PORT_TO_PIPE(tmp);
  1076. return true;
  1077. }
  1078. static void intel_disable_sdvo(struct intel_encoder *encoder)
  1079. {
  1080. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  1081. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1082. u32 temp;
  1083. intel_sdvo_set_active_outputs(intel_sdvo, 0);
  1084. if (0)
  1085. intel_sdvo_set_encoder_power_state(intel_sdvo,
  1086. DRM_MODE_DPMS_OFF);
  1087. temp = I915_READ(intel_sdvo->sdvo_reg);
  1088. if ((temp & SDVO_ENABLE) != 0) {
  1089. /* HW workaround for IBX, we need to move the port to
  1090. * transcoder A before disabling it. */
  1091. if (HAS_PCH_IBX(encoder->base.dev)) {
  1092. struct drm_crtc *crtc = encoder->base.crtc;
  1093. int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
  1094. if (temp & SDVO_PIPE_B_SELECT) {
  1095. temp &= ~SDVO_PIPE_B_SELECT;
  1096. I915_WRITE(intel_sdvo->sdvo_reg, temp);
  1097. POSTING_READ(intel_sdvo->sdvo_reg);
  1098. /* Again we need to write this twice. */
  1099. I915_WRITE(intel_sdvo->sdvo_reg, temp);
  1100. POSTING_READ(intel_sdvo->sdvo_reg);
  1101. /* Transcoder selection bits only update
  1102. * effectively on vblank. */
  1103. if (crtc)
  1104. intel_wait_for_vblank(encoder->base.dev, pipe);
  1105. else
  1106. msleep(50);
  1107. }
  1108. }
  1109. intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
  1110. }
  1111. }
  1112. static void intel_enable_sdvo(struct intel_encoder *encoder)
  1113. {
  1114. struct drm_device *dev = encoder->base.dev;
  1115. struct drm_i915_private *dev_priv = dev->dev_private;
  1116. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1117. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  1118. u32 temp;
  1119. bool input1, input2;
  1120. int i;
  1121. u8 status;
  1122. temp = I915_READ(intel_sdvo->sdvo_reg);
  1123. if ((temp & SDVO_ENABLE) == 0) {
  1124. /* HW workaround for IBX, we need to move the port
  1125. * to transcoder A before disabling it, so restore it here. */
  1126. if (HAS_PCH_IBX(dev))
  1127. temp |= SDVO_PIPE_SEL(intel_crtc->pipe);
  1128. intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
  1129. }
  1130. for (i = 0; i < 2; i++)
  1131. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1132. status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
  1133. /* Warn if the device reported failure to sync.
  1134. * A lot of SDVO devices fail to notify of sync, but it's
  1135. * a given it the status is a success, we succeeded.
  1136. */
  1137. if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
  1138. DRM_DEBUG_KMS("First %s output reported failure to "
  1139. "sync\n", SDVO_NAME(intel_sdvo));
  1140. }
  1141. if (0)
  1142. intel_sdvo_set_encoder_power_state(intel_sdvo,
  1143. DRM_MODE_DPMS_ON);
  1144. intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
  1145. }
  1146. static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
  1147. {
  1148. struct drm_crtc *crtc;
  1149. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1150. /* dvo supports only 2 dpms states. */
  1151. if (mode != DRM_MODE_DPMS_ON)
  1152. mode = DRM_MODE_DPMS_OFF;
  1153. if (mode == connector->dpms)
  1154. return;
  1155. connector->dpms = mode;
  1156. /* Only need to change hw state when actually enabled */
  1157. crtc = intel_sdvo->base.base.crtc;
  1158. if (!crtc) {
  1159. intel_sdvo->base.connectors_active = false;
  1160. return;
  1161. }
  1162. if (mode != DRM_MODE_DPMS_ON) {
  1163. intel_sdvo_set_active_outputs(intel_sdvo, 0);
  1164. if (0)
  1165. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  1166. intel_sdvo->base.connectors_active = false;
  1167. intel_crtc_update_dpms(crtc);
  1168. } else {
  1169. intel_sdvo->base.connectors_active = true;
  1170. intel_crtc_update_dpms(crtc);
  1171. if (0)
  1172. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  1173. intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
  1174. }
  1175. intel_modeset_check_state(connector->dev);
  1176. }
  1177. static int intel_sdvo_mode_valid(struct drm_connector *connector,
  1178. struct drm_display_mode *mode)
  1179. {
  1180. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1181. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  1182. return MODE_NO_DBLESCAN;
  1183. if (intel_sdvo->pixel_clock_min > mode->clock)
  1184. return MODE_CLOCK_LOW;
  1185. if (intel_sdvo->pixel_clock_max < mode->clock)
  1186. return MODE_CLOCK_HIGH;
  1187. if (intel_sdvo->is_lvds) {
  1188. if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
  1189. return MODE_PANEL;
  1190. if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
  1191. return MODE_PANEL;
  1192. }
  1193. return MODE_OK;
  1194. }
  1195. static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
  1196. {
  1197. BUILD_BUG_ON(sizeof(*caps) != 8);
  1198. if (!intel_sdvo_get_value(intel_sdvo,
  1199. SDVO_CMD_GET_DEVICE_CAPS,
  1200. caps, sizeof(*caps)))
  1201. return false;
  1202. DRM_DEBUG_KMS("SDVO capabilities:\n"
  1203. " vendor_id: %d\n"
  1204. " device_id: %d\n"
  1205. " device_rev_id: %d\n"
  1206. " sdvo_version_major: %d\n"
  1207. " sdvo_version_minor: %d\n"
  1208. " sdvo_inputs_mask: %d\n"
  1209. " smooth_scaling: %d\n"
  1210. " sharp_scaling: %d\n"
  1211. " up_scaling: %d\n"
  1212. " down_scaling: %d\n"
  1213. " stall_support: %d\n"
  1214. " output_flags: %d\n",
  1215. caps->vendor_id,
  1216. caps->device_id,
  1217. caps->device_rev_id,
  1218. caps->sdvo_version_major,
  1219. caps->sdvo_version_minor,
  1220. caps->sdvo_inputs_mask,
  1221. caps->smooth_scaling,
  1222. caps->sharp_scaling,
  1223. caps->up_scaling,
  1224. caps->down_scaling,
  1225. caps->stall_support,
  1226. caps->output_flags);
  1227. return true;
  1228. }
  1229. static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
  1230. {
  1231. struct drm_device *dev = intel_sdvo->base.base.dev;
  1232. uint16_t hotplug;
  1233. /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
  1234. * on the line. */
  1235. if (IS_I945G(dev) || IS_I945GM(dev))
  1236. return 0;
  1237. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
  1238. &hotplug, sizeof(hotplug)))
  1239. return 0;
  1240. return hotplug;
  1241. }
  1242. static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
  1243. {
  1244. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1245. intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
  1246. &intel_sdvo->hotplug_active, 2);
  1247. }
  1248. static bool
  1249. intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
  1250. {
  1251. /* Is there more than one type of output? */
  1252. return hweight16(intel_sdvo->caps.output_flags) > 1;
  1253. }
  1254. static struct edid *
  1255. intel_sdvo_get_edid(struct drm_connector *connector)
  1256. {
  1257. struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
  1258. return drm_get_edid(connector, &sdvo->ddc);
  1259. }
  1260. /* Mac mini hack -- use the same DDC as the analog connector */
  1261. static struct edid *
  1262. intel_sdvo_get_analog_edid(struct drm_connector *connector)
  1263. {
  1264. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1265. return drm_get_edid(connector,
  1266. intel_gmbus_get_adapter(dev_priv,
  1267. dev_priv->crt_ddc_pin));
  1268. }
  1269. static enum drm_connector_status
  1270. intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
  1271. {
  1272. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1273. enum drm_connector_status status;
  1274. struct edid *edid;
  1275. edid = intel_sdvo_get_edid(connector);
  1276. if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
  1277. u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
  1278. /*
  1279. * Don't use the 1 as the argument of DDC bus switch to get
  1280. * the EDID. It is used for SDVO SPD ROM.
  1281. */
  1282. for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
  1283. intel_sdvo->ddc_bus = ddc;
  1284. edid = intel_sdvo_get_edid(connector);
  1285. if (edid)
  1286. break;
  1287. }
  1288. /*
  1289. * If we found the EDID on the other bus,
  1290. * assume that is the correct DDC bus.
  1291. */
  1292. if (edid == NULL)
  1293. intel_sdvo->ddc_bus = saved_ddc;
  1294. }
  1295. /*
  1296. * When there is no edid and no monitor is connected with VGA
  1297. * port, try to use the CRT ddc to read the EDID for DVI-connector.
  1298. */
  1299. if (edid == NULL)
  1300. edid = intel_sdvo_get_analog_edid(connector);
  1301. status = connector_status_unknown;
  1302. if (edid != NULL) {
  1303. /* DDC bus is shared, match EDID to connector type */
  1304. if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  1305. status = connector_status_connected;
  1306. if (intel_sdvo->is_hdmi) {
  1307. intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
  1308. intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
  1309. intel_sdvo->rgb_quant_range_selectable =
  1310. drm_rgb_quant_range_selectable(edid);
  1311. }
  1312. } else
  1313. status = connector_status_disconnected;
  1314. kfree(edid);
  1315. }
  1316. if (status == connector_status_connected) {
  1317. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1318. if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
  1319. intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
  1320. }
  1321. return status;
  1322. }
  1323. static bool
  1324. intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
  1325. struct edid *edid)
  1326. {
  1327. bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
  1328. bool connector_is_digital = !!IS_DIGITAL(sdvo);
  1329. DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
  1330. connector_is_digital, monitor_is_digital);
  1331. return connector_is_digital == monitor_is_digital;
  1332. }
  1333. static enum drm_connector_status
  1334. intel_sdvo_detect(struct drm_connector *connector, bool force)
  1335. {
  1336. uint16_t response;
  1337. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1338. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1339. enum drm_connector_status ret;
  1340. if (!intel_sdvo_get_value(intel_sdvo,
  1341. SDVO_CMD_GET_ATTACHED_DISPLAYS,
  1342. &response, 2))
  1343. return connector_status_unknown;
  1344. DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
  1345. response & 0xff, response >> 8,
  1346. intel_sdvo_connector->output_flag);
  1347. if (response == 0)
  1348. return connector_status_disconnected;
  1349. intel_sdvo->attached_output = response;
  1350. intel_sdvo->has_hdmi_monitor = false;
  1351. intel_sdvo->has_hdmi_audio = false;
  1352. intel_sdvo->rgb_quant_range_selectable = false;
  1353. if ((intel_sdvo_connector->output_flag & response) == 0)
  1354. ret = connector_status_disconnected;
  1355. else if (IS_TMDS(intel_sdvo_connector))
  1356. ret = intel_sdvo_tmds_sink_detect(connector);
  1357. else {
  1358. struct edid *edid;
  1359. /* if we have an edid check it matches the connection */
  1360. edid = intel_sdvo_get_edid(connector);
  1361. if (edid == NULL)
  1362. edid = intel_sdvo_get_analog_edid(connector);
  1363. if (edid != NULL) {
  1364. if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
  1365. edid))
  1366. ret = connector_status_connected;
  1367. else
  1368. ret = connector_status_disconnected;
  1369. kfree(edid);
  1370. } else
  1371. ret = connector_status_connected;
  1372. }
  1373. /* May update encoder flag for like clock for SDVO TV, etc.*/
  1374. if (ret == connector_status_connected) {
  1375. intel_sdvo->is_tv = false;
  1376. intel_sdvo->is_lvds = false;
  1377. intel_sdvo->base.needs_tv_clock = false;
  1378. if (response & SDVO_TV_MASK) {
  1379. intel_sdvo->is_tv = true;
  1380. intel_sdvo->base.needs_tv_clock = true;
  1381. }
  1382. if (response & SDVO_LVDS_MASK)
  1383. intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
  1384. }
  1385. return ret;
  1386. }
  1387. static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
  1388. {
  1389. struct edid *edid;
  1390. /* set the bus switch and get the modes */
  1391. edid = intel_sdvo_get_edid(connector);
  1392. /*
  1393. * Mac mini hack. On this device, the DVI-I connector shares one DDC
  1394. * link between analog and digital outputs. So, if the regular SDVO
  1395. * DDC fails, check to see if the analog output is disconnected, in
  1396. * which case we'll look there for the digital DDC data.
  1397. */
  1398. if (edid == NULL)
  1399. edid = intel_sdvo_get_analog_edid(connector);
  1400. if (edid != NULL) {
  1401. if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
  1402. edid)) {
  1403. drm_mode_connector_update_edid_property(connector, edid);
  1404. drm_add_edid_modes(connector, edid);
  1405. }
  1406. kfree(edid);
  1407. }
  1408. }
  1409. /*
  1410. * Set of SDVO TV modes.
  1411. * Note! This is in reply order (see loop in get_tv_modes).
  1412. * XXX: all 60Hz refresh?
  1413. */
  1414. static const struct drm_display_mode sdvo_tv_modes[] = {
  1415. { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
  1416. 416, 0, 200, 201, 232, 233, 0,
  1417. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1418. { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
  1419. 416, 0, 240, 241, 272, 273, 0,
  1420. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1421. { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
  1422. 496, 0, 300, 301, 332, 333, 0,
  1423. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1424. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
  1425. 736, 0, 350, 351, 382, 383, 0,
  1426. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1427. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
  1428. 736, 0, 400, 401, 432, 433, 0,
  1429. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1430. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
  1431. 736, 0, 480, 481, 512, 513, 0,
  1432. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1433. { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
  1434. 800, 0, 480, 481, 512, 513, 0,
  1435. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1436. { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
  1437. 800, 0, 576, 577, 608, 609, 0,
  1438. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1439. { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
  1440. 816, 0, 350, 351, 382, 383, 0,
  1441. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1442. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
  1443. 816, 0, 400, 401, 432, 433, 0,
  1444. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1445. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
  1446. 816, 0, 480, 481, 512, 513, 0,
  1447. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1448. { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
  1449. 816, 0, 540, 541, 572, 573, 0,
  1450. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1451. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
  1452. 816, 0, 576, 577, 608, 609, 0,
  1453. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1454. { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
  1455. 864, 0, 576, 577, 608, 609, 0,
  1456. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1457. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
  1458. 896, 0, 600, 601, 632, 633, 0,
  1459. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1460. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
  1461. 928, 0, 624, 625, 656, 657, 0,
  1462. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1463. { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
  1464. 1016, 0, 766, 767, 798, 799, 0,
  1465. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1466. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
  1467. 1120, 0, 768, 769, 800, 801, 0,
  1468. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1469. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
  1470. 1376, 0, 1024, 1025, 1056, 1057, 0,
  1471. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1472. };
  1473. static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
  1474. {
  1475. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1476. struct intel_sdvo_sdtv_resolution_request tv_res;
  1477. uint32_t reply = 0, format_map = 0;
  1478. int i;
  1479. /* Read the list of supported input resolutions for the selected TV
  1480. * format.
  1481. */
  1482. format_map = 1 << intel_sdvo->tv_format_index;
  1483. memcpy(&tv_res, &format_map,
  1484. min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
  1485. if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
  1486. return;
  1487. BUILD_BUG_ON(sizeof(tv_res) != 3);
  1488. if (!intel_sdvo_write_cmd(intel_sdvo,
  1489. SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
  1490. &tv_res, sizeof(tv_res)))
  1491. return;
  1492. if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
  1493. return;
  1494. for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
  1495. if (reply & (1 << i)) {
  1496. struct drm_display_mode *nmode;
  1497. nmode = drm_mode_duplicate(connector->dev,
  1498. &sdvo_tv_modes[i]);
  1499. if (nmode)
  1500. drm_mode_probed_add(connector, nmode);
  1501. }
  1502. }
  1503. static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
  1504. {
  1505. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1506. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1507. struct drm_display_mode *newmode;
  1508. /*
  1509. * Attempt to get the mode list from DDC.
  1510. * Assume that the preferred modes are
  1511. * arranged in priority order.
  1512. */
  1513. intel_ddc_get_modes(connector, intel_sdvo->i2c);
  1514. if (list_empty(&connector->probed_modes) == false)
  1515. goto end;
  1516. /* Fetch modes from VBT */
  1517. if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
  1518. newmode = drm_mode_duplicate(connector->dev,
  1519. dev_priv->sdvo_lvds_vbt_mode);
  1520. if (newmode != NULL) {
  1521. /* Guarantee the mode is preferred */
  1522. newmode->type = (DRM_MODE_TYPE_PREFERRED |
  1523. DRM_MODE_TYPE_DRIVER);
  1524. drm_mode_probed_add(connector, newmode);
  1525. }
  1526. }
  1527. end:
  1528. list_for_each_entry(newmode, &connector->probed_modes, head) {
  1529. if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
  1530. intel_sdvo->sdvo_lvds_fixed_mode =
  1531. drm_mode_duplicate(connector->dev, newmode);
  1532. intel_sdvo->is_lvds = true;
  1533. break;
  1534. }
  1535. }
  1536. }
  1537. static int intel_sdvo_get_modes(struct drm_connector *connector)
  1538. {
  1539. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1540. if (IS_TV(intel_sdvo_connector))
  1541. intel_sdvo_get_tv_modes(connector);
  1542. else if (IS_LVDS(intel_sdvo_connector))
  1543. intel_sdvo_get_lvds_modes(connector);
  1544. else
  1545. intel_sdvo_get_ddc_modes(connector);
  1546. return !list_empty(&connector->probed_modes);
  1547. }
  1548. static void
  1549. intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
  1550. {
  1551. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1552. struct drm_device *dev = connector->dev;
  1553. if (intel_sdvo_connector->left)
  1554. drm_property_destroy(dev, intel_sdvo_connector->left);
  1555. if (intel_sdvo_connector->right)
  1556. drm_property_destroy(dev, intel_sdvo_connector->right);
  1557. if (intel_sdvo_connector->top)
  1558. drm_property_destroy(dev, intel_sdvo_connector->top);
  1559. if (intel_sdvo_connector->bottom)
  1560. drm_property_destroy(dev, intel_sdvo_connector->bottom);
  1561. if (intel_sdvo_connector->hpos)
  1562. drm_property_destroy(dev, intel_sdvo_connector->hpos);
  1563. if (intel_sdvo_connector->vpos)
  1564. drm_property_destroy(dev, intel_sdvo_connector->vpos);
  1565. if (intel_sdvo_connector->saturation)
  1566. drm_property_destroy(dev, intel_sdvo_connector->saturation);
  1567. if (intel_sdvo_connector->contrast)
  1568. drm_property_destroy(dev, intel_sdvo_connector->contrast);
  1569. if (intel_sdvo_connector->hue)
  1570. drm_property_destroy(dev, intel_sdvo_connector->hue);
  1571. if (intel_sdvo_connector->sharpness)
  1572. drm_property_destroy(dev, intel_sdvo_connector->sharpness);
  1573. if (intel_sdvo_connector->flicker_filter)
  1574. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
  1575. if (intel_sdvo_connector->flicker_filter_2d)
  1576. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
  1577. if (intel_sdvo_connector->flicker_filter_adaptive)
  1578. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
  1579. if (intel_sdvo_connector->tv_luma_filter)
  1580. drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
  1581. if (intel_sdvo_connector->tv_chroma_filter)
  1582. drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
  1583. if (intel_sdvo_connector->dot_crawl)
  1584. drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
  1585. if (intel_sdvo_connector->brightness)
  1586. drm_property_destroy(dev, intel_sdvo_connector->brightness);
  1587. }
  1588. static void intel_sdvo_destroy(struct drm_connector *connector)
  1589. {
  1590. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1591. if (intel_sdvo_connector->tv_format)
  1592. drm_property_destroy(connector->dev,
  1593. intel_sdvo_connector->tv_format);
  1594. intel_sdvo_destroy_enhance_property(connector);
  1595. drm_sysfs_connector_remove(connector);
  1596. drm_connector_cleanup(connector);
  1597. kfree(intel_sdvo_connector);
  1598. }
  1599. static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
  1600. {
  1601. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1602. struct edid *edid;
  1603. bool has_audio = false;
  1604. if (!intel_sdvo->is_hdmi)
  1605. return false;
  1606. edid = intel_sdvo_get_edid(connector);
  1607. if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
  1608. has_audio = drm_detect_monitor_audio(edid);
  1609. kfree(edid);
  1610. return has_audio;
  1611. }
  1612. static int
  1613. intel_sdvo_set_property(struct drm_connector *connector,
  1614. struct drm_property *property,
  1615. uint64_t val)
  1616. {
  1617. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1618. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1619. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1620. uint16_t temp_value;
  1621. uint8_t cmd;
  1622. int ret;
  1623. ret = drm_object_property_set_value(&connector->base, property, val);
  1624. if (ret)
  1625. return ret;
  1626. if (property == dev_priv->force_audio_property) {
  1627. int i = val;
  1628. bool has_audio;
  1629. if (i == intel_sdvo_connector->force_audio)
  1630. return 0;
  1631. intel_sdvo_connector->force_audio = i;
  1632. if (i == HDMI_AUDIO_AUTO)
  1633. has_audio = intel_sdvo_detect_hdmi_audio(connector);
  1634. else
  1635. has_audio = (i == HDMI_AUDIO_ON);
  1636. if (has_audio == intel_sdvo->has_hdmi_audio)
  1637. return 0;
  1638. intel_sdvo->has_hdmi_audio = has_audio;
  1639. goto done;
  1640. }
  1641. if (property == dev_priv->broadcast_rgb_property) {
  1642. switch (val) {
  1643. case INTEL_BROADCAST_RGB_AUTO:
  1644. intel_sdvo->color_range_auto = true;
  1645. break;
  1646. case INTEL_BROADCAST_RGB_FULL:
  1647. intel_sdvo->color_range_auto = false;
  1648. intel_sdvo->color_range = 0;
  1649. break;
  1650. case INTEL_BROADCAST_RGB_LIMITED:
  1651. intel_sdvo->color_range_auto = false;
  1652. /* FIXME: this bit is only valid when using TMDS
  1653. * encoding and 8 bit per color mode. */
  1654. intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
  1655. break;
  1656. default:
  1657. return -EINVAL;
  1658. }
  1659. goto done;
  1660. }
  1661. #define CHECK_PROPERTY(name, NAME) \
  1662. if (intel_sdvo_connector->name == property) { \
  1663. if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
  1664. if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
  1665. cmd = SDVO_CMD_SET_##NAME; \
  1666. intel_sdvo_connector->cur_##name = temp_value; \
  1667. goto set_value; \
  1668. }
  1669. if (property == intel_sdvo_connector->tv_format) {
  1670. if (val >= TV_FORMAT_NUM)
  1671. return -EINVAL;
  1672. if (intel_sdvo->tv_format_index ==
  1673. intel_sdvo_connector->tv_format_supported[val])
  1674. return 0;
  1675. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
  1676. goto done;
  1677. } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
  1678. temp_value = val;
  1679. if (intel_sdvo_connector->left == property) {
  1680. drm_object_property_set_value(&connector->base,
  1681. intel_sdvo_connector->right, val);
  1682. if (intel_sdvo_connector->left_margin == temp_value)
  1683. return 0;
  1684. intel_sdvo_connector->left_margin = temp_value;
  1685. intel_sdvo_connector->right_margin = temp_value;
  1686. temp_value = intel_sdvo_connector->max_hscan -
  1687. intel_sdvo_connector->left_margin;
  1688. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1689. goto set_value;
  1690. } else if (intel_sdvo_connector->right == property) {
  1691. drm_object_property_set_value(&connector->base,
  1692. intel_sdvo_connector->left, val);
  1693. if (intel_sdvo_connector->right_margin == temp_value)
  1694. return 0;
  1695. intel_sdvo_connector->left_margin = temp_value;
  1696. intel_sdvo_connector->right_margin = temp_value;
  1697. temp_value = intel_sdvo_connector->max_hscan -
  1698. intel_sdvo_connector->left_margin;
  1699. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1700. goto set_value;
  1701. } else if (intel_sdvo_connector->top == property) {
  1702. drm_object_property_set_value(&connector->base,
  1703. intel_sdvo_connector->bottom, val);
  1704. if (intel_sdvo_connector->top_margin == temp_value)
  1705. return 0;
  1706. intel_sdvo_connector->top_margin = temp_value;
  1707. intel_sdvo_connector->bottom_margin = temp_value;
  1708. temp_value = intel_sdvo_connector->max_vscan -
  1709. intel_sdvo_connector->top_margin;
  1710. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1711. goto set_value;
  1712. } else if (intel_sdvo_connector->bottom == property) {
  1713. drm_object_property_set_value(&connector->base,
  1714. intel_sdvo_connector->top, val);
  1715. if (intel_sdvo_connector->bottom_margin == temp_value)
  1716. return 0;
  1717. intel_sdvo_connector->top_margin = temp_value;
  1718. intel_sdvo_connector->bottom_margin = temp_value;
  1719. temp_value = intel_sdvo_connector->max_vscan -
  1720. intel_sdvo_connector->top_margin;
  1721. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1722. goto set_value;
  1723. }
  1724. CHECK_PROPERTY(hpos, HPOS)
  1725. CHECK_PROPERTY(vpos, VPOS)
  1726. CHECK_PROPERTY(saturation, SATURATION)
  1727. CHECK_PROPERTY(contrast, CONTRAST)
  1728. CHECK_PROPERTY(hue, HUE)
  1729. CHECK_PROPERTY(brightness, BRIGHTNESS)
  1730. CHECK_PROPERTY(sharpness, SHARPNESS)
  1731. CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
  1732. CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
  1733. CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
  1734. CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
  1735. CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
  1736. CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
  1737. }
  1738. return -EINVAL; /* unknown property */
  1739. set_value:
  1740. if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
  1741. return -EIO;
  1742. done:
  1743. if (intel_sdvo->base.base.crtc)
  1744. intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
  1745. return 0;
  1746. #undef CHECK_PROPERTY
  1747. }
  1748. static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
  1749. .mode_fixup = intel_sdvo_mode_fixup,
  1750. .mode_set = intel_sdvo_mode_set,
  1751. .disable = intel_encoder_noop,
  1752. };
  1753. static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
  1754. .dpms = intel_sdvo_dpms,
  1755. .detect = intel_sdvo_detect,
  1756. .fill_modes = drm_helper_probe_single_connector_modes,
  1757. .set_property = intel_sdvo_set_property,
  1758. .destroy = intel_sdvo_destroy,
  1759. };
  1760. static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
  1761. .get_modes = intel_sdvo_get_modes,
  1762. .mode_valid = intel_sdvo_mode_valid,
  1763. .best_encoder = intel_best_encoder,
  1764. };
  1765. static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
  1766. {
  1767. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  1768. if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
  1769. drm_mode_destroy(encoder->dev,
  1770. intel_sdvo->sdvo_lvds_fixed_mode);
  1771. i2c_del_adapter(&intel_sdvo->ddc);
  1772. intel_encoder_destroy(encoder);
  1773. }
  1774. static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
  1775. .destroy = intel_sdvo_enc_destroy,
  1776. };
  1777. static void
  1778. intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
  1779. {
  1780. uint16_t mask = 0;
  1781. unsigned int num_bits;
  1782. /* Make a mask of outputs less than or equal to our own priority in the
  1783. * list.
  1784. */
  1785. switch (sdvo->controlled_output) {
  1786. case SDVO_OUTPUT_LVDS1:
  1787. mask |= SDVO_OUTPUT_LVDS1;
  1788. case SDVO_OUTPUT_LVDS0:
  1789. mask |= SDVO_OUTPUT_LVDS0;
  1790. case SDVO_OUTPUT_TMDS1:
  1791. mask |= SDVO_OUTPUT_TMDS1;
  1792. case SDVO_OUTPUT_TMDS0:
  1793. mask |= SDVO_OUTPUT_TMDS0;
  1794. case SDVO_OUTPUT_RGB1:
  1795. mask |= SDVO_OUTPUT_RGB1;
  1796. case SDVO_OUTPUT_RGB0:
  1797. mask |= SDVO_OUTPUT_RGB0;
  1798. break;
  1799. }
  1800. /* Count bits to find what number we are in the priority list. */
  1801. mask &= sdvo->caps.output_flags;
  1802. num_bits = hweight16(mask);
  1803. /* If more than 3 outputs, default to DDC bus 3 for now. */
  1804. if (num_bits > 3)
  1805. num_bits = 3;
  1806. /* Corresponds to SDVO_CONTROL_BUS_DDCx */
  1807. sdvo->ddc_bus = 1 << num_bits;
  1808. }
  1809. /**
  1810. * Choose the appropriate DDC bus for control bus switch command for this
  1811. * SDVO output based on the controlled output.
  1812. *
  1813. * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
  1814. * outputs, then LVDS outputs.
  1815. */
  1816. static void
  1817. intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
  1818. struct intel_sdvo *sdvo, u32 reg)
  1819. {
  1820. struct sdvo_device_mapping *mapping;
  1821. if (sdvo->is_sdvob)
  1822. mapping = &(dev_priv->sdvo_mappings[0]);
  1823. else
  1824. mapping = &(dev_priv->sdvo_mappings[1]);
  1825. if (mapping->initialized)
  1826. sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
  1827. else
  1828. intel_sdvo_guess_ddc_bus(sdvo);
  1829. }
  1830. static void
  1831. intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
  1832. struct intel_sdvo *sdvo, u32 reg)
  1833. {
  1834. struct sdvo_device_mapping *mapping;
  1835. u8 pin;
  1836. if (sdvo->is_sdvob)
  1837. mapping = &dev_priv->sdvo_mappings[0];
  1838. else
  1839. mapping = &dev_priv->sdvo_mappings[1];
  1840. if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
  1841. pin = mapping->i2c_pin;
  1842. else
  1843. pin = GMBUS_PORT_DPB;
  1844. sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
  1845. /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
  1846. * our code totally fails once we start using gmbus. Hence fall back to
  1847. * bit banging for now. */
  1848. intel_gmbus_force_bit(sdvo->i2c, true);
  1849. }
  1850. /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
  1851. static void
  1852. intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
  1853. {
  1854. intel_gmbus_force_bit(sdvo->i2c, false);
  1855. }
  1856. static bool
  1857. intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
  1858. {
  1859. return intel_sdvo_check_supp_encode(intel_sdvo);
  1860. }
  1861. static u8
  1862. intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
  1863. {
  1864. struct drm_i915_private *dev_priv = dev->dev_private;
  1865. struct sdvo_device_mapping *my_mapping, *other_mapping;
  1866. if (sdvo->is_sdvob) {
  1867. my_mapping = &dev_priv->sdvo_mappings[0];
  1868. other_mapping = &dev_priv->sdvo_mappings[1];
  1869. } else {
  1870. my_mapping = &dev_priv->sdvo_mappings[1];
  1871. other_mapping = &dev_priv->sdvo_mappings[0];
  1872. }
  1873. /* If the BIOS described our SDVO device, take advantage of it. */
  1874. if (my_mapping->slave_addr)
  1875. return my_mapping->slave_addr;
  1876. /* If the BIOS only described a different SDVO device, use the
  1877. * address that it isn't using.
  1878. */
  1879. if (other_mapping->slave_addr) {
  1880. if (other_mapping->slave_addr == 0x70)
  1881. return 0x72;
  1882. else
  1883. return 0x70;
  1884. }
  1885. /* No SDVO device info is found for another DVO port,
  1886. * so use mapping assumption we had before BIOS parsing.
  1887. */
  1888. if (sdvo->is_sdvob)
  1889. return 0x70;
  1890. else
  1891. return 0x72;
  1892. }
  1893. static void
  1894. intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
  1895. struct intel_sdvo *encoder)
  1896. {
  1897. drm_connector_init(encoder->base.base.dev,
  1898. &connector->base.base,
  1899. &intel_sdvo_connector_funcs,
  1900. connector->base.base.connector_type);
  1901. drm_connector_helper_add(&connector->base.base,
  1902. &intel_sdvo_connector_helper_funcs);
  1903. connector->base.base.interlace_allowed = 1;
  1904. connector->base.base.doublescan_allowed = 0;
  1905. connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
  1906. connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
  1907. intel_connector_attach_encoder(&connector->base, &encoder->base);
  1908. drm_sysfs_connector_add(&connector->base.base);
  1909. }
  1910. static void
  1911. intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
  1912. struct intel_sdvo_connector *connector)
  1913. {
  1914. struct drm_device *dev = connector->base.base.dev;
  1915. intel_attach_force_audio_property(&connector->base.base);
  1916. if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
  1917. intel_attach_broadcast_rgb_property(&connector->base.base);
  1918. intel_sdvo->color_range_auto = true;
  1919. }
  1920. }
  1921. static bool
  1922. intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
  1923. {
  1924. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1925. struct drm_connector *connector;
  1926. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  1927. struct intel_connector *intel_connector;
  1928. struct intel_sdvo_connector *intel_sdvo_connector;
  1929. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1930. if (!intel_sdvo_connector)
  1931. return false;
  1932. if (device == 0) {
  1933. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
  1934. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
  1935. } else if (device == 1) {
  1936. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
  1937. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
  1938. }
  1939. intel_connector = &intel_sdvo_connector->base;
  1940. connector = &intel_connector->base;
  1941. if (intel_sdvo_get_hotplug_support(intel_sdvo) &
  1942. intel_sdvo_connector->output_flag) {
  1943. connector->polled = DRM_CONNECTOR_POLL_HPD;
  1944. intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
  1945. /* Some SDVO devices have one-shot hotplug interrupts.
  1946. * Ensure that they get re-enabled when an interrupt happens.
  1947. */
  1948. intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
  1949. intel_sdvo_enable_hotplug(intel_encoder);
  1950. } else {
  1951. connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
  1952. }
  1953. encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
  1954. connector->connector_type = DRM_MODE_CONNECTOR_DVID;
  1955. if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
  1956. connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
  1957. intel_sdvo->is_hdmi = true;
  1958. }
  1959. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1960. if (intel_sdvo->is_hdmi)
  1961. intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
  1962. return true;
  1963. }
  1964. static bool
  1965. intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
  1966. {
  1967. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1968. struct drm_connector *connector;
  1969. struct intel_connector *intel_connector;
  1970. struct intel_sdvo_connector *intel_sdvo_connector;
  1971. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1972. if (!intel_sdvo_connector)
  1973. return false;
  1974. intel_connector = &intel_sdvo_connector->base;
  1975. connector = &intel_connector->base;
  1976. encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
  1977. connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
  1978. intel_sdvo->controlled_output |= type;
  1979. intel_sdvo_connector->output_flag = type;
  1980. intel_sdvo->is_tv = true;
  1981. intel_sdvo->base.needs_tv_clock = true;
  1982. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1983. if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
  1984. goto err;
  1985. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  1986. goto err;
  1987. return true;
  1988. err:
  1989. intel_sdvo_destroy(connector);
  1990. return false;
  1991. }
  1992. static bool
  1993. intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
  1994. {
  1995. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1996. struct drm_connector *connector;
  1997. struct intel_connector *intel_connector;
  1998. struct intel_sdvo_connector *intel_sdvo_connector;
  1999. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  2000. if (!intel_sdvo_connector)
  2001. return false;
  2002. intel_connector = &intel_sdvo_connector->base;
  2003. connector = &intel_connector->base;
  2004. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  2005. encoder->encoder_type = DRM_MODE_ENCODER_DAC;
  2006. connector->connector_type = DRM_MODE_CONNECTOR_VGA;
  2007. if (device == 0) {
  2008. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
  2009. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
  2010. } else if (device == 1) {
  2011. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
  2012. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
  2013. }
  2014. intel_sdvo_connector_init(intel_sdvo_connector,
  2015. intel_sdvo);
  2016. return true;
  2017. }
  2018. static bool
  2019. intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
  2020. {
  2021. struct drm_encoder *encoder = &intel_sdvo->base.base;
  2022. struct drm_connector *connector;
  2023. struct intel_connector *intel_connector;
  2024. struct intel_sdvo_connector *intel_sdvo_connector;
  2025. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  2026. if (!intel_sdvo_connector)
  2027. return false;
  2028. intel_connector = &intel_sdvo_connector->base;
  2029. connector = &intel_connector->base;
  2030. encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
  2031. connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
  2032. if (device == 0) {
  2033. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
  2034. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
  2035. } else if (device == 1) {
  2036. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
  2037. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
  2038. }
  2039. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  2040. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  2041. goto err;
  2042. return true;
  2043. err:
  2044. intel_sdvo_destroy(connector);
  2045. return false;
  2046. }
  2047. static bool
  2048. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
  2049. {
  2050. intel_sdvo->is_tv = false;
  2051. intel_sdvo->base.needs_tv_clock = false;
  2052. intel_sdvo->is_lvds = false;
  2053. /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
  2054. if (flags & SDVO_OUTPUT_TMDS0)
  2055. if (!intel_sdvo_dvi_init(intel_sdvo, 0))
  2056. return false;
  2057. if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
  2058. if (!intel_sdvo_dvi_init(intel_sdvo, 1))
  2059. return false;
  2060. /* TV has no XXX1 function block */
  2061. if (flags & SDVO_OUTPUT_SVID0)
  2062. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
  2063. return false;
  2064. if (flags & SDVO_OUTPUT_CVBS0)
  2065. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
  2066. return false;
  2067. if (flags & SDVO_OUTPUT_YPRPB0)
  2068. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
  2069. return false;
  2070. if (flags & SDVO_OUTPUT_RGB0)
  2071. if (!intel_sdvo_analog_init(intel_sdvo, 0))
  2072. return false;
  2073. if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
  2074. if (!intel_sdvo_analog_init(intel_sdvo, 1))
  2075. return false;
  2076. if (flags & SDVO_OUTPUT_LVDS0)
  2077. if (!intel_sdvo_lvds_init(intel_sdvo, 0))
  2078. return false;
  2079. if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
  2080. if (!intel_sdvo_lvds_init(intel_sdvo, 1))
  2081. return false;
  2082. if ((flags & SDVO_OUTPUT_MASK) == 0) {
  2083. unsigned char bytes[2];
  2084. intel_sdvo->controlled_output = 0;
  2085. memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
  2086. DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
  2087. SDVO_NAME(intel_sdvo),
  2088. bytes[0], bytes[1]);
  2089. return false;
  2090. }
  2091. intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  2092. return true;
  2093. }
  2094. static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
  2095. {
  2096. struct drm_device *dev = intel_sdvo->base.base.dev;
  2097. struct drm_connector *connector, *tmp;
  2098. list_for_each_entry_safe(connector, tmp,
  2099. &dev->mode_config.connector_list, head) {
  2100. if (intel_attached_encoder(connector) == &intel_sdvo->base)
  2101. intel_sdvo_destroy(connector);
  2102. }
  2103. }
  2104. static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  2105. struct intel_sdvo_connector *intel_sdvo_connector,
  2106. int type)
  2107. {
  2108. struct drm_device *dev = intel_sdvo->base.base.dev;
  2109. struct intel_sdvo_tv_format format;
  2110. uint32_t format_map, i;
  2111. if (!intel_sdvo_set_target_output(intel_sdvo, type))
  2112. return false;
  2113. BUILD_BUG_ON(sizeof(format) != 6);
  2114. if (!intel_sdvo_get_value(intel_sdvo,
  2115. SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
  2116. &format, sizeof(format)))
  2117. return false;
  2118. memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
  2119. if (format_map == 0)
  2120. return false;
  2121. intel_sdvo_connector->format_supported_num = 0;
  2122. for (i = 0 ; i < TV_FORMAT_NUM; i++)
  2123. if (format_map & (1 << i))
  2124. intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
  2125. intel_sdvo_connector->tv_format =
  2126. drm_property_create(dev, DRM_MODE_PROP_ENUM,
  2127. "mode", intel_sdvo_connector->format_supported_num);
  2128. if (!intel_sdvo_connector->tv_format)
  2129. return false;
  2130. for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
  2131. drm_property_add_enum(
  2132. intel_sdvo_connector->tv_format, i,
  2133. i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
  2134. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
  2135. drm_object_attach_property(&intel_sdvo_connector->base.base.base,
  2136. intel_sdvo_connector->tv_format, 0);
  2137. return true;
  2138. }
  2139. #define ENHANCEMENT(name, NAME) do { \
  2140. if (enhancements.name) { \
  2141. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
  2142. !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
  2143. return false; \
  2144. intel_sdvo_connector->max_##name = data_value[0]; \
  2145. intel_sdvo_connector->cur_##name = response; \
  2146. intel_sdvo_connector->name = \
  2147. drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
  2148. if (!intel_sdvo_connector->name) return false; \
  2149. drm_object_attach_property(&connector->base, \
  2150. intel_sdvo_connector->name, \
  2151. intel_sdvo_connector->cur_##name); \
  2152. DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
  2153. data_value[0], data_value[1], response); \
  2154. } \
  2155. } while (0)
  2156. static bool
  2157. intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
  2158. struct intel_sdvo_connector *intel_sdvo_connector,
  2159. struct intel_sdvo_enhancements_reply enhancements)
  2160. {
  2161. struct drm_device *dev = intel_sdvo->base.base.dev;
  2162. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  2163. uint16_t response, data_value[2];
  2164. /* when horizontal overscan is supported, Add the left/right property */
  2165. if (enhancements.overscan_h) {
  2166. if (!intel_sdvo_get_value(intel_sdvo,
  2167. SDVO_CMD_GET_MAX_OVERSCAN_H,
  2168. &data_value, 4))
  2169. return false;
  2170. if (!intel_sdvo_get_value(intel_sdvo,
  2171. SDVO_CMD_GET_OVERSCAN_H,
  2172. &response, 2))
  2173. return false;
  2174. intel_sdvo_connector->max_hscan = data_value[0];
  2175. intel_sdvo_connector->left_margin = data_value[0] - response;
  2176. intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
  2177. intel_sdvo_connector->left =
  2178. drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
  2179. if (!intel_sdvo_connector->left)
  2180. return false;
  2181. drm_object_attach_property(&connector->base,
  2182. intel_sdvo_connector->left,
  2183. intel_sdvo_connector->left_margin);
  2184. intel_sdvo_connector->right =
  2185. drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
  2186. if (!intel_sdvo_connector->right)
  2187. return false;
  2188. drm_object_attach_property(&connector->base,
  2189. intel_sdvo_connector->right,
  2190. intel_sdvo_connector->right_margin);
  2191. DRM_DEBUG_KMS("h_overscan: max %d, "
  2192. "default %d, current %d\n",
  2193. data_value[0], data_value[1], response);
  2194. }
  2195. if (enhancements.overscan_v) {
  2196. if (!intel_sdvo_get_value(intel_sdvo,
  2197. SDVO_CMD_GET_MAX_OVERSCAN_V,
  2198. &data_value, 4))
  2199. return false;
  2200. if (!intel_sdvo_get_value(intel_sdvo,
  2201. SDVO_CMD_GET_OVERSCAN_V,
  2202. &response, 2))
  2203. return false;
  2204. intel_sdvo_connector->max_vscan = data_value[0];
  2205. intel_sdvo_connector->top_margin = data_value[0] - response;
  2206. intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
  2207. intel_sdvo_connector->top =
  2208. drm_property_create_range(dev, 0,
  2209. "top_margin", 0, data_value[0]);
  2210. if (!intel_sdvo_connector->top)
  2211. return false;
  2212. drm_object_attach_property(&connector->base,
  2213. intel_sdvo_connector->top,
  2214. intel_sdvo_connector->top_margin);
  2215. intel_sdvo_connector->bottom =
  2216. drm_property_create_range(dev, 0,
  2217. "bottom_margin", 0, data_value[0]);
  2218. if (!intel_sdvo_connector->bottom)
  2219. return false;
  2220. drm_object_attach_property(&connector->base,
  2221. intel_sdvo_connector->bottom,
  2222. intel_sdvo_connector->bottom_margin);
  2223. DRM_DEBUG_KMS("v_overscan: max %d, "
  2224. "default %d, current %d\n",
  2225. data_value[0], data_value[1], response);
  2226. }
  2227. ENHANCEMENT(hpos, HPOS);
  2228. ENHANCEMENT(vpos, VPOS);
  2229. ENHANCEMENT(saturation, SATURATION);
  2230. ENHANCEMENT(contrast, CONTRAST);
  2231. ENHANCEMENT(hue, HUE);
  2232. ENHANCEMENT(sharpness, SHARPNESS);
  2233. ENHANCEMENT(brightness, BRIGHTNESS);
  2234. ENHANCEMENT(flicker_filter, FLICKER_FILTER);
  2235. ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
  2236. ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
  2237. ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
  2238. ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
  2239. if (enhancements.dot_crawl) {
  2240. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
  2241. return false;
  2242. intel_sdvo_connector->max_dot_crawl = 1;
  2243. intel_sdvo_connector->cur_dot_crawl = response & 0x1;
  2244. intel_sdvo_connector->dot_crawl =
  2245. drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
  2246. if (!intel_sdvo_connector->dot_crawl)
  2247. return false;
  2248. drm_object_attach_property(&connector->base,
  2249. intel_sdvo_connector->dot_crawl,
  2250. intel_sdvo_connector->cur_dot_crawl);
  2251. DRM_DEBUG_KMS("dot crawl: current %d\n", response);
  2252. }
  2253. return true;
  2254. }
  2255. static bool
  2256. intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
  2257. struct intel_sdvo_connector *intel_sdvo_connector,
  2258. struct intel_sdvo_enhancements_reply enhancements)
  2259. {
  2260. struct drm_device *dev = intel_sdvo->base.base.dev;
  2261. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  2262. uint16_t response, data_value[2];
  2263. ENHANCEMENT(brightness, BRIGHTNESS);
  2264. return true;
  2265. }
  2266. #undef ENHANCEMENT
  2267. static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  2268. struct intel_sdvo_connector *intel_sdvo_connector)
  2269. {
  2270. union {
  2271. struct intel_sdvo_enhancements_reply reply;
  2272. uint16_t response;
  2273. } enhancements;
  2274. BUILD_BUG_ON(sizeof(enhancements) != 2);
  2275. enhancements.response = 0;
  2276. intel_sdvo_get_value(intel_sdvo,
  2277. SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
  2278. &enhancements, sizeof(enhancements));
  2279. if (enhancements.response == 0) {
  2280. DRM_DEBUG_KMS("No enhancement is supported\n");
  2281. return true;
  2282. }
  2283. if (IS_TV(intel_sdvo_connector))
  2284. return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2285. else if (IS_LVDS(intel_sdvo_connector))
  2286. return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2287. else
  2288. return true;
  2289. }
  2290. static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
  2291. struct i2c_msg *msgs,
  2292. int num)
  2293. {
  2294. struct intel_sdvo *sdvo = adapter->algo_data;
  2295. if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
  2296. return -EIO;
  2297. return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
  2298. }
  2299. static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
  2300. {
  2301. struct intel_sdvo *sdvo = adapter->algo_data;
  2302. return sdvo->i2c->algo->functionality(sdvo->i2c);
  2303. }
  2304. static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
  2305. .master_xfer = intel_sdvo_ddc_proxy_xfer,
  2306. .functionality = intel_sdvo_ddc_proxy_func
  2307. };
  2308. static bool
  2309. intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
  2310. struct drm_device *dev)
  2311. {
  2312. sdvo->ddc.owner = THIS_MODULE;
  2313. sdvo->ddc.class = I2C_CLASS_DDC;
  2314. snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
  2315. sdvo->ddc.dev.parent = &dev->pdev->dev;
  2316. sdvo->ddc.algo_data = sdvo;
  2317. sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
  2318. return i2c_add_adapter(&sdvo->ddc) == 0;
  2319. }
  2320. bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
  2321. {
  2322. struct drm_i915_private *dev_priv = dev->dev_private;
  2323. struct intel_encoder *intel_encoder;
  2324. struct intel_sdvo *intel_sdvo;
  2325. u32 hotplug_mask;
  2326. int i;
  2327. intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
  2328. if (!intel_sdvo)
  2329. return false;
  2330. intel_sdvo->sdvo_reg = sdvo_reg;
  2331. intel_sdvo->is_sdvob = is_sdvob;
  2332. intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
  2333. intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
  2334. if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
  2335. goto err_i2c_bus;
  2336. /* encoder type will be decided later */
  2337. intel_encoder = &intel_sdvo->base;
  2338. intel_encoder->type = INTEL_OUTPUT_SDVO;
  2339. drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
  2340. /* Read the regs to test if we can talk to the device */
  2341. for (i = 0; i < 0x40; i++) {
  2342. u8 byte;
  2343. if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
  2344. DRM_DEBUG_KMS("No SDVO device found on %s\n",
  2345. SDVO_NAME(intel_sdvo));
  2346. goto err;
  2347. }
  2348. }
  2349. hotplug_mask = 0;
  2350. if (IS_G4X(dev)) {
  2351. hotplug_mask = intel_sdvo->is_sdvob ?
  2352. SDVOB_HOTPLUG_INT_STATUS_G4X : SDVOC_HOTPLUG_INT_STATUS_G4X;
  2353. } else if (IS_GEN4(dev)) {
  2354. hotplug_mask = intel_sdvo->is_sdvob ?
  2355. SDVOB_HOTPLUG_INT_STATUS_I965 : SDVOC_HOTPLUG_INT_STATUS_I965;
  2356. } else {
  2357. hotplug_mask = intel_sdvo->is_sdvob ?
  2358. SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915;
  2359. }
  2360. drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
  2361. intel_encoder->disable = intel_disable_sdvo;
  2362. intel_encoder->enable = intel_enable_sdvo;
  2363. intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
  2364. /* In default case sdvo lvds is false */
  2365. if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
  2366. goto err;
  2367. if (intel_sdvo_output_setup(intel_sdvo,
  2368. intel_sdvo->caps.output_flags) != true) {
  2369. DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
  2370. SDVO_NAME(intel_sdvo));
  2371. /* Output_setup can leave behind connectors! */
  2372. goto err_output;
  2373. }
  2374. /*
  2375. * Cloning SDVO with anything is often impossible, since the SDVO
  2376. * encoder can request a special input timing mode. And even if that's
  2377. * not the case we have evidence that cloning a plain unscaled mode with
  2378. * VGA doesn't really work. Furthermore the cloning flags are way too
  2379. * simplistic anyway to express such constraints, so just give up on
  2380. * cloning for SDVO encoders.
  2381. */
  2382. intel_sdvo->base.cloneable = false;
  2383. /* Only enable the hotplug irq if we need it, to work around noisy
  2384. * hotplug lines.
  2385. */
  2386. if (intel_sdvo->hotplug_active)
  2387. dev_priv->hotplug_supported_mask |= hotplug_mask;
  2388. intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
  2389. /* Set the input timing to the screen. Assume always input 0. */
  2390. if (!intel_sdvo_set_target_input(intel_sdvo))
  2391. goto err_output;
  2392. if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
  2393. &intel_sdvo->pixel_clock_min,
  2394. &intel_sdvo->pixel_clock_max))
  2395. goto err_output;
  2396. DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
  2397. "clock range %dMHz - %dMHz, "
  2398. "input 1: %c, input 2: %c, "
  2399. "output 1: %c, output 2: %c\n",
  2400. SDVO_NAME(intel_sdvo),
  2401. intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
  2402. intel_sdvo->caps.device_rev_id,
  2403. intel_sdvo->pixel_clock_min / 1000,
  2404. intel_sdvo->pixel_clock_max / 1000,
  2405. (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
  2406. (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
  2407. /* check currently supported outputs */
  2408. intel_sdvo->caps.output_flags &
  2409. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
  2410. intel_sdvo->caps.output_flags &
  2411. (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
  2412. return true;
  2413. err_output:
  2414. intel_sdvo_output_cleanup(intel_sdvo);
  2415. err:
  2416. drm_encoder_cleanup(&intel_encoder->base);
  2417. i2c_del_adapter(&intel_sdvo->ddc);
  2418. err_i2c_bus:
  2419. intel_sdvo_unselect_i2c_bus(intel_sdvo);
  2420. kfree(intel_sdvo);
  2421. return false;
  2422. }