tx.c 32 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2005-2009 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/pci.h>
  11. #include <linux/tcp.h>
  12. #include <linux/ip.h>
  13. #include <linux/in.h>
  14. #include <linux/ipv6.h>
  15. #include <linux/slab.h>
  16. #include <net/ipv6.h>
  17. #include <linux/if_ether.h>
  18. #include <linux/highmem.h>
  19. #include "net_driver.h"
  20. #include "efx.h"
  21. #include "nic.h"
  22. #include "workarounds.h"
  23. /*
  24. * TX descriptor ring full threshold
  25. *
  26. * The tx_queue descriptor ring fill-level must fall below this value
  27. * before we restart the netif queue
  28. */
  29. #define EFX_TXQ_THRESHOLD(_efx) ((_efx)->txq_entries / 2u)
  30. /* We need to be able to nest calls to netif_tx_stop_queue(), partly
  31. * because of the 2 hardware queues associated with each core queue,
  32. * but also so that we can inhibit TX for reasons other than a full
  33. * hardware queue. */
  34. void efx_stop_queue(struct efx_channel *channel)
  35. {
  36. struct efx_nic *efx = channel->efx;
  37. struct efx_tx_queue *tx_queue = efx_channel_get_tx_queue(channel, 0);
  38. if (!tx_queue)
  39. return;
  40. spin_lock_bh(&channel->tx_stop_lock);
  41. netif_vdbg(efx, tx_queued, efx->net_dev, "stop TX queue\n");
  42. atomic_inc(&channel->tx_stop_count);
  43. netif_tx_stop_queue(
  44. netdev_get_tx_queue(efx->net_dev,
  45. tx_queue->queue / EFX_TXQ_TYPES));
  46. spin_unlock_bh(&channel->tx_stop_lock);
  47. }
  48. /* Decrement core TX queue stop count and wake it if the count is 0 */
  49. void efx_wake_queue(struct efx_channel *channel)
  50. {
  51. struct efx_nic *efx = channel->efx;
  52. struct efx_tx_queue *tx_queue = efx_channel_get_tx_queue(channel, 0);
  53. if (!tx_queue)
  54. return;
  55. local_bh_disable();
  56. if (atomic_dec_and_lock(&channel->tx_stop_count,
  57. &channel->tx_stop_lock)) {
  58. netif_vdbg(efx, tx_queued, efx->net_dev, "waking TX queue\n");
  59. netif_tx_wake_queue(
  60. netdev_get_tx_queue(efx->net_dev,
  61. tx_queue->queue / EFX_TXQ_TYPES));
  62. spin_unlock(&channel->tx_stop_lock);
  63. }
  64. local_bh_enable();
  65. }
  66. static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
  67. struct efx_tx_buffer *buffer)
  68. {
  69. if (buffer->unmap_len) {
  70. struct pci_dev *pci_dev = tx_queue->efx->pci_dev;
  71. dma_addr_t unmap_addr = (buffer->dma_addr + buffer->len -
  72. buffer->unmap_len);
  73. if (buffer->unmap_single)
  74. pci_unmap_single(pci_dev, unmap_addr, buffer->unmap_len,
  75. PCI_DMA_TODEVICE);
  76. else
  77. pci_unmap_page(pci_dev, unmap_addr, buffer->unmap_len,
  78. PCI_DMA_TODEVICE);
  79. buffer->unmap_len = 0;
  80. buffer->unmap_single = false;
  81. }
  82. if (buffer->skb) {
  83. dev_kfree_skb_any((struct sk_buff *) buffer->skb);
  84. buffer->skb = NULL;
  85. netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev,
  86. "TX queue %d transmission id %x complete\n",
  87. tx_queue->queue, tx_queue->read_count);
  88. }
  89. }
  90. /**
  91. * struct efx_tso_header - a DMA mapped buffer for packet headers
  92. * @next: Linked list of free ones.
  93. * The list is protected by the TX queue lock.
  94. * @dma_unmap_len: Length to unmap for an oversize buffer, or 0.
  95. * @dma_addr: The DMA address of the header below.
  96. *
  97. * This controls the memory used for a TSO header. Use TSOH_DATA()
  98. * to find the packet header data. Use TSOH_SIZE() to calculate the
  99. * total size required for a given packet header length. TSO headers
  100. * in the free list are exactly %TSOH_STD_SIZE bytes in size.
  101. */
  102. struct efx_tso_header {
  103. union {
  104. struct efx_tso_header *next;
  105. size_t unmap_len;
  106. };
  107. dma_addr_t dma_addr;
  108. };
  109. static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
  110. struct sk_buff *skb);
  111. static void efx_fini_tso(struct efx_tx_queue *tx_queue);
  112. static void efx_tsoh_heap_free(struct efx_tx_queue *tx_queue,
  113. struct efx_tso_header *tsoh);
  114. static void efx_tsoh_free(struct efx_tx_queue *tx_queue,
  115. struct efx_tx_buffer *buffer)
  116. {
  117. if (buffer->tsoh) {
  118. if (likely(!buffer->tsoh->unmap_len)) {
  119. buffer->tsoh->next = tx_queue->tso_headers_free;
  120. tx_queue->tso_headers_free = buffer->tsoh;
  121. } else {
  122. efx_tsoh_heap_free(tx_queue, buffer->tsoh);
  123. }
  124. buffer->tsoh = NULL;
  125. }
  126. }
  127. static inline unsigned
  128. efx_max_tx_len(struct efx_nic *efx, dma_addr_t dma_addr)
  129. {
  130. /* Depending on the NIC revision, we can use descriptor
  131. * lengths up to 8K or 8K-1. However, since PCI Express
  132. * devices must split read requests at 4K boundaries, there is
  133. * little benefit from using descriptors that cross those
  134. * boundaries and we keep things simple by not doing so.
  135. */
  136. unsigned len = (~dma_addr & 0xfff) + 1;
  137. /* Work around hardware bug for unaligned buffers. */
  138. if (EFX_WORKAROUND_5391(efx) && (dma_addr & 0xf))
  139. len = min_t(unsigned, len, 512 - (dma_addr & 0xf));
  140. return len;
  141. }
  142. /*
  143. * Add a socket buffer to a TX queue
  144. *
  145. * This maps all fragments of a socket buffer for DMA and adds them to
  146. * the TX queue. The queue's insert pointer will be incremented by
  147. * the number of fragments in the socket buffer.
  148. *
  149. * If any DMA mapping fails, any mapped fragments will be unmapped,
  150. * the queue's insert pointer will be restored to its original value.
  151. *
  152. * This function is split out from efx_hard_start_xmit to allow the
  153. * loopback test to direct packets via specific TX queues.
  154. *
  155. * Returns NETDEV_TX_OK or NETDEV_TX_BUSY
  156. * You must hold netif_tx_lock() to call this function.
  157. */
  158. netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
  159. {
  160. struct efx_nic *efx = tx_queue->efx;
  161. struct pci_dev *pci_dev = efx->pci_dev;
  162. struct efx_tx_buffer *buffer;
  163. skb_frag_t *fragment;
  164. struct page *page;
  165. int page_offset;
  166. unsigned int len, unmap_len = 0, fill_level, insert_ptr;
  167. dma_addr_t dma_addr, unmap_addr = 0;
  168. unsigned int dma_len;
  169. bool unmap_single;
  170. int q_space, i = 0;
  171. netdev_tx_t rc = NETDEV_TX_OK;
  172. EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
  173. if (skb_shinfo(skb)->gso_size)
  174. return efx_enqueue_skb_tso(tx_queue, skb);
  175. /* Get size of the initial fragment */
  176. len = skb_headlen(skb);
  177. /* Pad if necessary */
  178. if (EFX_WORKAROUND_15592(efx) && skb->len <= 32) {
  179. EFX_BUG_ON_PARANOID(skb->data_len);
  180. len = 32 + 1;
  181. if (skb_pad(skb, len - skb->len))
  182. return NETDEV_TX_OK;
  183. }
  184. fill_level = tx_queue->insert_count - tx_queue->old_read_count;
  185. q_space = efx->txq_entries - 1 - fill_level;
  186. /* Map for DMA. Use pci_map_single rather than pci_map_page
  187. * since this is more efficient on machines with sparse
  188. * memory.
  189. */
  190. unmap_single = true;
  191. dma_addr = pci_map_single(pci_dev, skb->data, len, PCI_DMA_TODEVICE);
  192. /* Process all fragments */
  193. while (1) {
  194. if (unlikely(pci_dma_mapping_error(pci_dev, dma_addr)))
  195. goto pci_err;
  196. /* Store fields for marking in the per-fragment final
  197. * descriptor */
  198. unmap_len = len;
  199. unmap_addr = dma_addr;
  200. /* Add to TX queue, splitting across DMA boundaries */
  201. do {
  202. if (unlikely(q_space-- <= 0)) {
  203. /* It might be that completions have
  204. * happened since the xmit path last
  205. * checked. Update the xmit path's
  206. * copy of read_count.
  207. */
  208. ++tx_queue->stopped;
  209. /* This memory barrier protects the
  210. * change of stopped from the access
  211. * of read_count. */
  212. smp_mb();
  213. tx_queue->old_read_count =
  214. *(volatile unsigned *)
  215. &tx_queue->read_count;
  216. fill_level = (tx_queue->insert_count
  217. - tx_queue->old_read_count);
  218. q_space = efx->txq_entries - 1 - fill_level;
  219. if (unlikely(q_space-- <= 0))
  220. goto stop;
  221. smp_mb();
  222. --tx_queue->stopped;
  223. }
  224. insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask;
  225. buffer = &tx_queue->buffer[insert_ptr];
  226. efx_tsoh_free(tx_queue, buffer);
  227. EFX_BUG_ON_PARANOID(buffer->tsoh);
  228. EFX_BUG_ON_PARANOID(buffer->skb);
  229. EFX_BUG_ON_PARANOID(buffer->len);
  230. EFX_BUG_ON_PARANOID(!buffer->continuation);
  231. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  232. dma_len = efx_max_tx_len(efx, dma_addr);
  233. if (likely(dma_len >= len))
  234. dma_len = len;
  235. /* Fill out per descriptor fields */
  236. buffer->len = dma_len;
  237. buffer->dma_addr = dma_addr;
  238. len -= dma_len;
  239. dma_addr += dma_len;
  240. ++tx_queue->insert_count;
  241. } while (len);
  242. /* Transfer ownership of the unmapping to the final buffer */
  243. buffer->unmap_single = unmap_single;
  244. buffer->unmap_len = unmap_len;
  245. unmap_len = 0;
  246. /* Get address and size of next fragment */
  247. if (i >= skb_shinfo(skb)->nr_frags)
  248. break;
  249. fragment = &skb_shinfo(skb)->frags[i];
  250. len = fragment->size;
  251. page = fragment->page;
  252. page_offset = fragment->page_offset;
  253. i++;
  254. /* Map for DMA */
  255. unmap_single = false;
  256. dma_addr = pci_map_page(pci_dev, page, page_offset, len,
  257. PCI_DMA_TODEVICE);
  258. }
  259. /* Transfer ownership of the skb to the final buffer */
  260. buffer->skb = skb;
  261. buffer->continuation = false;
  262. /* Pass off to hardware */
  263. efx_nic_push_buffers(tx_queue);
  264. return NETDEV_TX_OK;
  265. pci_err:
  266. netif_err(efx, tx_err, efx->net_dev,
  267. " TX queue %d could not map skb with %d bytes %d "
  268. "fragments for DMA\n", tx_queue->queue, skb->len,
  269. skb_shinfo(skb)->nr_frags + 1);
  270. /* Mark the packet as transmitted, and free the SKB ourselves */
  271. dev_kfree_skb_any(skb);
  272. goto unwind;
  273. stop:
  274. rc = NETDEV_TX_BUSY;
  275. if (tx_queue->stopped == 1)
  276. efx_stop_queue(tx_queue->channel);
  277. unwind:
  278. /* Work backwards until we hit the original insert pointer value */
  279. while (tx_queue->insert_count != tx_queue->write_count) {
  280. --tx_queue->insert_count;
  281. insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask;
  282. buffer = &tx_queue->buffer[insert_ptr];
  283. efx_dequeue_buffer(tx_queue, buffer);
  284. buffer->len = 0;
  285. }
  286. /* Free the fragment we were mid-way through pushing */
  287. if (unmap_len) {
  288. if (unmap_single)
  289. pci_unmap_single(pci_dev, unmap_addr, unmap_len,
  290. PCI_DMA_TODEVICE);
  291. else
  292. pci_unmap_page(pci_dev, unmap_addr, unmap_len,
  293. PCI_DMA_TODEVICE);
  294. }
  295. return rc;
  296. }
  297. /* Remove packets from the TX queue
  298. *
  299. * This removes packets from the TX queue, up to and including the
  300. * specified index.
  301. */
  302. static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue,
  303. unsigned int index)
  304. {
  305. struct efx_nic *efx = tx_queue->efx;
  306. unsigned int stop_index, read_ptr;
  307. stop_index = (index + 1) & tx_queue->ptr_mask;
  308. read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
  309. while (read_ptr != stop_index) {
  310. struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
  311. if (unlikely(buffer->len == 0)) {
  312. netif_err(efx, tx_err, efx->net_dev,
  313. "TX queue %d spurious TX completion id %x\n",
  314. tx_queue->queue, read_ptr);
  315. efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
  316. return;
  317. }
  318. efx_dequeue_buffer(tx_queue, buffer);
  319. buffer->continuation = true;
  320. buffer->len = 0;
  321. ++tx_queue->read_count;
  322. read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
  323. }
  324. }
  325. /* Initiate a packet transmission. We use one channel per CPU
  326. * (sharing when we have more CPUs than channels). On Falcon, the TX
  327. * completion events will be directed back to the CPU that transmitted
  328. * the packet, which should be cache-efficient.
  329. *
  330. * Context: non-blocking.
  331. * Note that returning anything other than NETDEV_TX_OK will cause the
  332. * OS to free the skb.
  333. */
  334. netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb,
  335. struct net_device *net_dev)
  336. {
  337. struct efx_nic *efx = netdev_priv(net_dev);
  338. struct efx_tx_queue *tx_queue;
  339. if (unlikely(efx->port_inhibited))
  340. return NETDEV_TX_BUSY;
  341. tx_queue = efx_get_tx_queue(efx, skb_get_queue_mapping(skb),
  342. skb->ip_summed == CHECKSUM_PARTIAL ?
  343. EFX_TXQ_TYPE_OFFLOAD : 0);
  344. return efx_enqueue_skb(tx_queue, skb);
  345. }
  346. void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
  347. {
  348. unsigned fill_level;
  349. struct efx_nic *efx = tx_queue->efx;
  350. struct netdev_queue *queue;
  351. EFX_BUG_ON_PARANOID(index > tx_queue->ptr_mask);
  352. efx_dequeue_buffers(tx_queue, index);
  353. /* See if we need to restart the netif queue. This barrier
  354. * separates the update of read_count from the test of
  355. * stopped. */
  356. smp_mb();
  357. if (unlikely(tx_queue->stopped) && likely(efx->port_enabled)) {
  358. fill_level = tx_queue->insert_count - tx_queue->read_count;
  359. if (fill_level < EFX_TXQ_THRESHOLD(efx)) {
  360. EFX_BUG_ON_PARANOID(!efx_dev_registered(efx));
  361. /* Do this under netif_tx_lock(), to avoid racing
  362. * with efx_xmit(). */
  363. queue = netdev_get_tx_queue(
  364. efx->net_dev,
  365. tx_queue->queue / EFX_TXQ_TYPES);
  366. __netif_tx_lock(queue, smp_processor_id());
  367. if (tx_queue->stopped) {
  368. tx_queue->stopped = 0;
  369. efx_wake_queue(tx_queue->channel);
  370. }
  371. __netif_tx_unlock(queue);
  372. }
  373. }
  374. }
  375. int efx_probe_tx_queue(struct efx_tx_queue *tx_queue)
  376. {
  377. struct efx_nic *efx = tx_queue->efx;
  378. unsigned int entries;
  379. int i, rc;
  380. /* Create the smallest power-of-two aligned ring */
  381. entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE);
  382. EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
  383. tx_queue->ptr_mask = entries - 1;
  384. netif_dbg(efx, probe, efx->net_dev,
  385. "creating TX queue %d size %#x mask %#x\n",
  386. tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask);
  387. /* Allocate software ring */
  388. tx_queue->buffer = kzalloc(entries * sizeof(*tx_queue->buffer),
  389. GFP_KERNEL);
  390. if (!tx_queue->buffer)
  391. return -ENOMEM;
  392. for (i = 0; i <= tx_queue->ptr_mask; ++i)
  393. tx_queue->buffer[i].continuation = true;
  394. /* Allocate hardware ring */
  395. rc = efx_nic_probe_tx(tx_queue);
  396. if (rc)
  397. goto fail;
  398. return 0;
  399. fail:
  400. kfree(tx_queue->buffer);
  401. tx_queue->buffer = NULL;
  402. return rc;
  403. }
  404. void efx_init_tx_queue(struct efx_tx_queue *tx_queue)
  405. {
  406. netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
  407. "initialising TX queue %d\n", tx_queue->queue);
  408. tx_queue->insert_count = 0;
  409. tx_queue->write_count = 0;
  410. tx_queue->read_count = 0;
  411. tx_queue->old_read_count = 0;
  412. BUG_ON(tx_queue->stopped);
  413. /* Set up TX descriptor ring */
  414. efx_nic_init_tx(tx_queue);
  415. }
  416. void efx_release_tx_buffers(struct efx_tx_queue *tx_queue)
  417. {
  418. struct efx_tx_buffer *buffer;
  419. if (!tx_queue->buffer)
  420. return;
  421. /* Free any buffers left in the ring */
  422. while (tx_queue->read_count != tx_queue->write_count) {
  423. buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask];
  424. efx_dequeue_buffer(tx_queue, buffer);
  425. buffer->continuation = true;
  426. buffer->len = 0;
  427. ++tx_queue->read_count;
  428. }
  429. }
  430. void efx_fini_tx_queue(struct efx_tx_queue *tx_queue)
  431. {
  432. netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
  433. "shutting down TX queue %d\n", tx_queue->queue);
  434. /* Flush TX queue, remove descriptor ring */
  435. efx_nic_fini_tx(tx_queue);
  436. efx_release_tx_buffers(tx_queue);
  437. /* Free up TSO header cache */
  438. efx_fini_tso(tx_queue);
  439. /* Release queue's stop on port, if any */
  440. if (tx_queue->stopped) {
  441. tx_queue->stopped = 0;
  442. efx_wake_queue(tx_queue->channel);
  443. }
  444. }
  445. void efx_remove_tx_queue(struct efx_tx_queue *tx_queue)
  446. {
  447. netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
  448. "destroying TX queue %d\n", tx_queue->queue);
  449. efx_nic_remove_tx(tx_queue);
  450. kfree(tx_queue->buffer);
  451. tx_queue->buffer = NULL;
  452. }
  453. /* Efx TCP segmentation acceleration.
  454. *
  455. * Why? Because by doing it here in the driver we can go significantly
  456. * faster than the GSO.
  457. *
  458. * Requires TX checksum offload support.
  459. */
  460. /* Number of bytes inserted at the start of a TSO header buffer,
  461. * similar to NET_IP_ALIGN.
  462. */
  463. #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  464. #define TSOH_OFFSET 0
  465. #else
  466. #define TSOH_OFFSET NET_IP_ALIGN
  467. #endif
  468. #define TSOH_BUFFER(tsoh) ((u8 *)(tsoh + 1) + TSOH_OFFSET)
  469. /* Total size of struct efx_tso_header, buffer and padding */
  470. #define TSOH_SIZE(hdr_len) \
  471. (sizeof(struct efx_tso_header) + TSOH_OFFSET + hdr_len)
  472. /* Size of blocks on free list. Larger blocks must be allocated from
  473. * the heap.
  474. */
  475. #define TSOH_STD_SIZE 128
  476. #define PTR_DIFF(p1, p2) ((u8 *)(p1) - (u8 *)(p2))
  477. #define ETH_HDR_LEN(skb) (skb_network_header(skb) - (skb)->data)
  478. #define SKB_TCP_OFF(skb) PTR_DIFF(tcp_hdr(skb), (skb)->data)
  479. #define SKB_IPV4_OFF(skb) PTR_DIFF(ip_hdr(skb), (skb)->data)
  480. #define SKB_IPV6_OFF(skb) PTR_DIFF(ipv6_hdr(skb), (skb)->data)
  481. /**
  482. * struct tso_state - TSO state for an SKB
  483. * @out_len: Remaining length in current segment
  484. * @seqnum: Current sequence number
  485. * @ipv4_id: Current IPv4 ID, host endian
  486. * @packet_space: Remaining space in current packet
  487. * @dma_addr: DMA address of current position
  488. * @in_len: Remaining length in current SKB fragment
  489. * @unmap_len: Length of SKB fragment
  490. * @unmap_addr: DMA address of SKB fragment
  491. * @unmap_single: DMA single vs page mapping flag
  492. * @protocol: Network protocol (after any VLAN header)
  493. * @header_len: Number of bytes of header
  494. * @full_packet_size: Number of bytes to put in each outgoing segment
  495. *
  496. * The state used during segmentation. It is put into this data structure
  497. * just to make it easy to pass into inline functions.
  498. */
  499. struct tso_state {
  500. /* Output position */
  501. unsigned out_len;
  502. unsigned seqnum;
  503. unsigned ipv4_id;
  504. unsigned packet_space;
  505. /* Input position */
  506. dma_addr_t dma_addr;
  507. unsigned in_len;
  508. unsigned unmap_len;
  509. dma_addr_t unmap_addr;
  510. bool unmap_single;
  511. __be16 protocol;
  512. unsigned header_len;
  513. int full_packet_size;
  514. };
  515. /*
  516. * Verify that our various assumptions about sk_buffs and the conditions
  517. * under which TSO will be attempted hold true. Return the protocol number.
  518. */
  519. static __be16 efx_tso_check_protocol(struct sk_buff *skb)
  520. {
  521. __be16 protocol = skb->protocol;
  522. EFX_BUG_ON_PARANOID(((struct ethhdr *)skb->data)->h_proto !=
  523. protocol);
  524. if (protocol == htons(ETH_P_8021Q)) {
  525. /* Find the encapsulated protocol; reset network header
  526. * and transport header based on that. */
  527. struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data;
  528. protocol = veh->h_vlan_encapsulated_proto;
  529. skb_set_network_header(skb, sizeof(*veh));
  530. if (protocol == htons(ETH_P_IP))
  531. skb_set_transport_header(skb, sizeof(*veh) +
  532. 4 * ip_hdr(skb)->ihl);
  533. else if (protocol == htons(ETH_P_IPV6))
  534. skb_set_transport_header(skb, sizeof(*veh) +
  535. sizeof(struct ipv6hdr));
  536. }
  537. if (protocol == htons(ETH_P_IP)) {
  538. EFX_BUG_ON_PARANOID(ip_hdr(skb)->protocol != IPPROTO_TCP);
  539. } else {
  540. EFX_BUG_ON_PARANOID(protocol != htons(ETH_P_IPV6));
  541. EFX_BUG_ON_PARANOID(ipv6_hdr(skb)->nexthdr != NEXTHDR_TCP);
  542. }
  543. EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb), skb->data)
  544. + (tcp_hdr(skb)->doff << 2u)) >
  545. skb_headlen(skb));
  546. return protocol;
  547. }
  548. /*
  549. * Allocate a page worth of efx_tso_header structures, and string them
  550. * into the tx_queue->tso_headers_free linked list. Return 0 or -ENOMEM.
  551. */
  552. static int efx_tsoh_block_alloc(struct efx_tx_queue *tx_queue)
  553. {
  554. struct pci_dev *pci_dev = tx_queue->efx->pci_dev;
  555. struct efx_tso_header *tsoh;
  556. dma_addr_t dma_addr;
  557. u8 *base_kva, *kva;
  558. base_kva = pci_alloc_consistent(pci_dev, PAGE_SIZE, &dma_addr);
  559. if (base_kva == NULL) {
  560. netif_err(tx_queue->efx, tx_err, tx_queue->efx->net_dev,
  561. "Unable to allocate page for TSO headers\n");
  562. return -ENOMEM;
  563. }
  564. /* pci_alloc_consistent() allocates pages. */
  565. EFX_BUG_ON_PARANOID(dma_addr & (PAGE_SIZE - 1u));
  566. for (kva = base_kva; kva < base_kva + PAGE_SIZE; kva += TSOH_STD_SIZE) {
  567. tsoh = (struct efx_tso_header *)kva;
  568. tsoh->dma_addr = dma_addr + (TSOH_BUFFER(tsoh) - base_kva);
  569. tsoh->next = tx_queue->tso_headers_free;
  570. tx_queue->tso_headers_free = tsoh;
  571. }
  572. return 0;
  573. }
  574. /* Free up a TSO header, and all others in the same page. */
  575. static void efx_tsoh_block_free(struct efx_tx_queue *tx_queue,
  576. struct efx_tso_header *tsoh,
  577. struct pci_dev *pci_dev)
  578. {
  579. struct efx_tso_header **p;
  580. unsigned long base_kva;
  581. dma_addr_t base_dma;
  582. base_kva = (unsigned long)tsoh & PAGE_MASK;
  583. base_dma = tsoh->dma_addr & PAGE_MASK;
  584. p = &tx_queue->tso_headers_free;
  585. while (*p != NULL) {
  586. if (((unsigned long)*p & PAGE_MASK) == base_kva)
  587. *p = (*p)->next;
  588. else
  589. p = &(*p)->next;
  590. }
  591. pci_free_consistent(pci_dev, PAGE_SIZE, (void *)base_kva, base_dma);
  592. }
  593. static struct efx_tso_header *
  594. efx_tsoh_heap_alloc(struct efx_tx_queue *tx_queue, size_t header_len)
  595. {
  596. struct efx_tso_header *tsoh;
  597. tsoh = kmalloc(TSOH_SIZE(header_len), GFP_ATOMIC | GFP_DMA);
  598. if (unlikely(!tsoh))
  599. return NULL;
  600. tsoh->dma_addr = pci_map_single(tx_queue->efx->pci_dev,
  601. TSOH_BUFFER(tsoh), header_len,
  602. PCI_DMA_TODEVICE);
  603. if (unlikely(pci_dma_mapping_error(tx_queue->efx->pci_dev,
  604. tsoh->dma_addr))) {
  605. kfree(tsoh);
  606. return NULL;
  607. }
  608. tsoh->unmap_len = header_len;
  609. return tsoh;
  610. }
  611. static void
  612. efx_tsoh_heap_free(struct efx_tx_queue *tx_queue, struct efx_tso_header *tsoh)
  613. {
  614. pci_unmap_single(tx_queue->efx->pci_dev,
  615. tsoh->dma_addr, tsoh->unmap_len,
  616. PCI_DMA_TODEVICE);
  617. kfree(tsoh);
  618. }
  619. /**
  620. * efx_tx_queue_insert - push descriptors onto the TX queue
  621. * @tx_queue: Efx TX queue
  622. * @dma_addr: DMA address of fragment
  623. * @len: Length of fragment
  624. * @final_buffer: The final buffer inserted into the queue
  625. *
  626. * Push descriptors onto the TX queue. Return 0 on success or 1 if
  627. * @tx_queue full.
  628. */
  629. static int efx_tx_queue_insert(struct efx_tx_queue *tx_queue,
  630. dma_addr_t dma_addr, unsigned len,
  631. struct efx_tx_buffer **final_buffer)
  632. {
  633. struct efx_tx_buffer *buffer;
  634. struct efx_nic *efx = tx_queue->efx;
  635. unsigned dma_len, fill_level, insert_ptr;
  636. int q_space;
  637. EFX_BUG_ON_PARANOID(len <= 0);
  638. fill_level = tx_queue->insert_count - tx_queue->old_read_count;
  639. /* -1 as there is no way to represent all descriptors used */
  640. q_space = efx->txq_entries - 1 - fill_level;
  641. while (1) {
  642. if (unlikely(q_space-- <= 0)) {
  643. /* It might be that completions have happened
  644. * since the xmit path last checked. Update
  645. * the xmit path's copy of read_count.
  646. */
  647. ++tx_queue->stopped;
  648. /* This memory barrier protects the change of
  649. * stopped from the access of read_count. */
  650. smp_mb();
  651. tx_queue->old_read_count =
  652. *(volatile unsigned *)&tx_queue->read_count;
  653. fill_level = (tx_queue->insert_count
  654. - tx_queue->old_read_count);
  655. q_space = efx->txq_entries - 1 - fill_level;
  656. if (unlikely(q_space-- <= 0)) {
  657. *final_buffer = NULL;
  658. return 1;
  659. }
  660. smp_mb();
  661. --tx_queue->stopped;
  662. }
  663. insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask;
  664. buffer = &tx_queue->buffer[insert_ptr];
  665. ++tx_queue->insert_count;
  666. EFX_BUG_ON_PARANOID(tx_queue->insert_count -
  667. tx_queue->read_count >=
  668. efx->txq_entries);
  669. efx_tsoh_free(tx_queue, buffer);
  670. EFX_BUG_ON_PARANOID(buffer->len);
  671. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  672. EFX_BUG_ON_PARANOID(buffer->skb);
  673. EFX_BUG_ON_PARANOID(!buffer->continuation);
  674. EFX_BUG_ON_PARANOID(buffer->tsoh);
  675. buffer->dma_addr = dma_addr;
  676. dma_len = efx_max_tx_len(efx, dma_addr);
  677. /* If there is enough space to send then do so */
  678. if (dma_len >= len)
  679. break;
  680. buffer->len = dma_len; /* Don't set the other members */
  681. dma_addr += dma_len;
  682. len -= dma_len;
  683. }
  684. EFX_BUG_ON_PARANOID(!len);
  685. buffer->len = len;
  686. *final_buffer = buffer;
  687. return 0;
  688. }
  689. /*
  690. * Put a TSO header into the TX queue.
  691. *
  692. * This is special-cased because we know that it is small enough to fit in
  693. * a single fragment, and we know it doesn't cross a page boundary. It
  694. * also allows us to not worry about end-of-packet etc.
  695. */
  696. static void efx_tso_put_header(struct efx_tx_queue *tx_queue,
  697. struct efx_tso_header *tsoh, unsigned len)
  698. {
  699. struct efx_tx_buffer *buffer;
  700. buffer = &tx_queue->buffer[tx_queue->insert_count & tx_queue->ptr_mask];
  701. efx_tsoh_free(tx_queue, buffer);
  702. EFX_BUG_ON_PARANOID(buffer->len);
  703. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  704. EFX_BUG_ON_PARANOID(buffer->skb);
  705. EFX_BUG_ON_PARANOID(!buffer->continuation);
  706. EFX_BUG_ON_PARANOID(buffer->tsoh);
  707. buffer->len = len;
  708. buffer->dma_addr = tsoh->dma_addr;
  709. buffer->tsoh = tsoh;
  710. ++tx_queue->insert_count;
  711. }
  712. /* Remove descriptors put into a tx_queue. */
  713. static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue)
  714. {
  715. struct efx_tx_buffer *buffer;
  716. dma_addr_t unmap_addr;
  717. /* Work backwards until we hit the original insert pointer value */
  718. while (tx_queue->insert_count != tx_queue->write_count) {
  719. --tx_queue->insert_count;
  720. buffer = &tx_queue->buffer[tx_queue->insert_count &
  721. tx_queue->ptr_mask];
  722. efx_tsoh_free(tx_queue, buffer);
  723. EFX_BUG_ON_PARANOID(buffer->skb);
  724. if (buffer->unmap_len) {
  725. unmap_addr = (buffer->dma_addr + buffer->len -
  726. buffer->unmap_len);
  727. if (buffer->unmap_single)
  728. pci_unmap_single(tx_queue->efx->pci_dev,
  729. unmap_addr, buffer->unmap_len,
  730. PCI_DMA_TODEVICE);
  731. else
  732. pci_unmap_page(tx_queue->efx->pci_dev,
  733. unmap_addr, buffer->unmap_len,
  734. PCI_DMA_TODEVICE);
  735. buffer->unmap_len = 0;
  736. }
  737. buffer->len = 0;
  738. buffer->continuation = true;
  739. }
  740. }
  741. /* Parse the SKB header and initialise state. */
  742. static void tso_start(struct tso_state *st, const struct sk_buff *skb)
  743. {
  744. /* All ethernet/IP/TCP headers combined size is TCP header size
  745. * plus offset of TCP header relative to start of packet.
  746. */
  747. st->header_len = ((tcp_hdr(skb)->doff << 2u)
  748. + PTR_DIFF(tcp_hdr(skb), skb->data));
  749. st->full_packet_size = st->header_len + skb_shinfo(skb)->gso_size;
  750. if (st->protocol == htons(ETH_P_IP))
  751. st->ipv4_id = ntohs(ip_hdr(skb)->id);
  752. else
  753. st->ipv4_id = 0;
  754. st->seqnum = ntohl(tcp_hdr(skb)->seq);
  755. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->urg);
  756. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->syn);
  757. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->rst);
  758. st->packet_space = st->full_packet_size;
  759. st->out_len = skb->len - st->header_len;
  760. st->unmap_len = 0;
  761. st->unmap_single = false;
  762. }
  763. static int tso_get_fragment(struct tso_state *st, struct efx_nic *efx,
  764. skb_frag_t *frag)
  765. {
  766. st->unmap_addr = pci_map_page(efx->pci_dev, frag->page,
  767. frag->page_offset, frag->size,
  768. PCI_DMA_TODEVICE);
  769. if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) {
  770. st->unmap_single = false;
  771. st->unmap_len = frag->size;
  772. st->in_len = frag->size;
  773. st->dma_addr = st->unmap_addr;
  774. return 0;
  775. }
  776. return -ENOMEM;
  777. }
  778. static int tso_get_head_fragment(struct tso_state *st, struct efx_nic *efx,
  779. const struct sk_buff *skb)
  780. {
  781. int hl = st->header_len;
  782. int len = skb_headlen(skb) - hl;
  783. st->unmap_addr = pci_map_single(efx->pci_dev, skb->data + hl,
  784. len, PCI_DMA_TODEVICE);
  785. if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) {
  786. st->unmap_single = true;
  787. st->unmap_len = len;
  788. st->in_len = len;
  789. st->dma_addr = st->unmap_addr;
  790. return 0;
  791. }
  792. return -ENOMEM;
  793. }
  794. /**
  795. * tso_fill_packet_with_fragment - form descriptors for the current fragment
  796. * @tx_queue: Efx TX queue
  797. * @skb: Socket buffer
  798. * @st: TSO state
  799. *
  800. * Form descriptors for the current fragment, until we reach the end
  801. * of fragment or end-of-packet. Return 0 on success, 1 if not enough
  802. * space in @tx_queue.
  803. */
  804. static int tso_fill_packet_with_fragment(struct efx_tx_queue *tx_queue,
  805. const struct sk_buff *skb,
  806. struct tso_state *st)
  807. {
  808. struct efx_tx_buffer *buffer;
  809. int n, end_of_packet, rc;
  810. if (st->in_len == 0)
  811. return 0;
  812. if (st->packet_space == 0)
  813. return 0;
  814. EFX_BUG_ON_PARANOID(st->in_len <= 0);
  815. EFX_BUG_ON_PARANOID(st->packet_space <= 0);
  816. n = min(st->in_len, st->packet_space);
  817. st->packet_space -= n;
  818. st->out_len -= n;
  819. st->in_len -= n;
  820. rc = efx_tx_queue_insert(tx_queue, st->dma_addr, n, &buffer);
  821. if (likely(rc == 0)) {
  822. if (st->out_len == 0)
  823. /* Transfer ownership of the skb */
  824. buffer->skb = skb;
  825. end_of_packet = st->out_len == 0 || st->packet_space == 0;
  826. buffer->continuation = !end_of_packet;
  827. if (st->in_len == 0) {
  828. /* Transfer ownership of the pci mapping */
  829. buffer->unmap_len = st->unmap_len;
  830. buffer->unmap_single = st->unmap_single;
  831. st->unmap_len = 0;
  832. }
  833. }
  834. st->dma_addr += n;
  835. return rc;
  836. }
  837. /**
  838. * tso_start_new_packet - generate a new header and prepare for the new packet
  839. * @tx_queue: Efx TX queue
  840. * @skb: Socket buffer
  841. * @st: TSO state
  842. *
  843. * Generate a new header and prepare for the new packet. Return 0 on
  844. * success, or -1 if failed to alloc header.
  845. */
  846. static int tso_start_new_packet(struct efx_tx_queue *tx_queue,
  847. const struct sk_buff *skb,
  848. struct tso_state *st)
  849. {
  850. struct efx_tso_header *tsoh;
  851. struct tcphdr *tsoh_th;
  852. unsigned ip_length;
  853. u8 *header;
  854. /* Allocate a DMA-mapped header buffer. */
  855. if (likely(TSOH_SIZE(st->header_len) <= TSOH_STD_SIZE)) {
  856. if (tx_queue->tso_headers_free == NULL) {
  857. if (efx_tsoh_block_alloc(tx_queue))
  858. return -1;
  859. }
  860. EFX_BUG_ON_PARANOID(!tx_queue->tso_headers_free);
  861. tsoh = tx_queue->tso_headers_free;
  862. tx_queue->tso_headers_free = tsoh->next;
  863. tsoh->unmap_len = 0;
  864. } else {
  865. tx_queue->tso_long_headers++;
  866. tsoh = efx_tsoh_heap_alloc(tx_queue, st->header_len);
  867. if (unlikely(!tsoh))
  868. return -1;
  869. }
  870. header = TSOH_BUFFER(tsoh);
  871. tsoh_th = (struct tcphdr *)(header + SKB_TCP_OFF(skb));
  872. /* Copy and update the headers. */
  873. memcpy(header, skb->data, st->header_len);
  874. tsoh_th->seq = htonl(st->seqnum);
  875. st->seqnum += skb_shinfo(skb)->gso_size;
  876. if (st->out_len > skb_shinfo(skb)->gso_size) {
  877. /* This packet will not finish the TSO burst. */
  878. ip_length = st->full_packet_size - ETH_HDR_LEN(skb);
  879. tsoh_th->fin = 0;
  880. tsoh_th->psh = 0;
  881. } else {
  882. /* This packet will be the last in the TSO burst. */
  883. ip_length = st->header_len - ETH_HDR_LEN(skb) + st->out_len;
  884. tsoh_th->fin = tcp_hdr(skb)->fin;
  885. tsoh_th->psh = tcp_hdr(skb)->psh;
  886. }
  887. if (st->protocol == htons(ETH_P_IP)) {
  888. struct iphdr *tsoh_iph =
  889. (struct iphdr *)(header + SKB_IPV4_OFF(skb));
  890. tsoh_iph->tot_len = htons(ip_length);
  891. /* Linux leaves suitable gaps in the IP ID space for us to fill. */
  892. tsoh_iph->id = htons(st->ipv4_id);
  893. st->ipv4_id++;
  894. } else {
  895. struct ipv6hdr *tsoh_iph =
  896. (struct ipv6hdr *)(header + SKB_IPV6_OFF(skb));
  897. tsoh_iph->payload_len = htons(ip_length - sizeof(*tsoh_iph));
  898. }
  899. st->packet_space = skb_shinfo(skb)->gso_size;
  900. ++tx_queue->tso_packets;
  901. /* Form a descriptor for this header. */
  902. efx_tso_put_header(tx_queue, tsoh, st->header_len);
  903. return 0;
  904. }
  905. /**
  906. * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer
  907. * @tx_queue: Efx TX queue
  908. * @skb: Socket buffer
  909. *
  910. * Context: You must hold netif_tx_lock() to call this function.
  911. *
  912. * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if
  913. * @skb was not enqueued. In all cases @skb is consumed. Return
  914. * %NETDEV_TX_OK or %NETDEV_TX_BUSY.
  915. */
  916. static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
  917. struct sk_buff *skb)
  918. {
  919. struct efx_nic *efx = tx_queue->efx;
  920. int frag_i, rc, rc2 = NETDEV_TX_OK;
  921. struct tso_state state;
  922. /* Find the packet protocol and sanity-check it */
  923. state.protocol = efx_tso_check_protocol(skb);
  924. EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
  925. tso_start(&state, skb);
  926. /* Assume that skb header area contains exactly the headers, and
  927. * all payload is in the frag list.
  928. */
  929. if (skb_headlen(skb) == state.header_len) {
  930. /* Grab the first payload fragment. */
  931. EFX_BUG_ON_PARANOID(skb_shinfo(skb)->nr_frags < 1);
  932. frag_i = 0;
  933. rc = tso_get_fragment(&state, efx,
  934. skb_shinfo(skb)->frags + frag_i);
  935. if (rc)
  936. goto mem_err;
  937. } else {
  938. rc = tso_get_head_fragment(&state, efx, skb);
  939. if (rc)
  940. goto mem_err;
  941. frag_i = -1;
  942. }
  943. if (tso_start_new_packet(tx_queue, skb, &state) < 0)
  944. goto mem_err;
  945. while (1) {
  946. rc = tso_fill_packet_with_fragment(tx_queue, skb, &state);
  947. if (unlikely(rc))
  948. goto stop;
  949. /* Move onto the next fragment? */
  950. if (state.in_len == 0) {
  951. if (++frag_i >= skb_shinfo(skb)->nr_frags)
  952. /* End of payload reached. */
  953. break;
  954. rc = tso_get_fragment(&state, efx,
  955. skb_shinfo(skb)->frags + frag_i);
  956. if (rc)
  957. goto mem_err;
  958. }
  959. /* Start at new packet? */
  960. if (state.packet_space == 0 &&
  961. tso_start_new_packet(tx_queue, skb, &state) < 0)
  962. goto mem_err;
  963. }
  964. /* Pass off to hardware */
  965. efx_nic_push_buffers(tx_queue);
  966. tx_queue->tso_bursts++;
  967. return NETDEV_TX_OK;
  968. mem_err:
  969. netif_err(efx, tx_err, efx->net_dev,
  970. "Out of memory for TSO headers, or PCI mapping error\n");
  971. dev_kfree_skb_any(skb);
  972. goto unwind;
  973. stop:
  974. rc2 = NETDEV_TX_BUSY;
  975. /* Stop the queue if it wasn't stopped before. */
  976. if (tx_queue->stopped == 1)
  977. efx_stop_queue(tx_queue->channel);
  978. unwind:
  979. /* Free the DMA mapping we were in the process of writing out */
  980. if (state.unmap_len) {
  981. if (state.unmap_single)
  982. pci_unmap_single(efx->pci_dev, state.unmap_addr,
  983. state.unmap_len, PCI_DMA_TODEVICE);
  984. else
  985. pci_unmap_page(efx->pci_dev, state.unmap_addr,
  986. state.unmap_len, PCI_DMA_TODEVICE);
  987. }
  988. efx_enqueue_unwind(tx_queue);
  989. return rc2;
  990. }
  991. /*
  992. * Free up all TSO datastructures associated with tx_queue. This
  993. * routine should be called only once the tx_queue is both empty and
  994. * will no longer be used.
  995. */
  996. static void efx_fini_tso(struct efx_tx_queue *tx_queue)
  997. {
  998. unsigned i;
  999. if (tx_queue->buffer) {
  1000. for (i = 0; i <= tx_queue->ptr_mask; ++i)
  1001. efx_tsoh_free(tx_queue, &tx_queue->buffer[i]);
  1002. }
  1003. while (tx_queue->tso_headers_free != NULL)
  1004. efx_tsoh_block_free(tx_queue, tx_queue->tso_headers_free,
  1005. tx_queue->efx->pci_dev);
  1006. }