exynos_thermal.c 28 KB

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  1. /*
  2. * exynos_thermal.c - Samsung EXYNOS TMU (Thermal Management Unit)
  3. *
  4. * Copyright (C) 2011 Samsung Electronics
  5. * Donggeun Kim <dg77.kim@samsung.com>
  6. * Amit Daniel Kachhap <amit.kachhap@linaro.org>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. *
  22. */
  23. #include <linux/module.h>
  24. #include <linux/err.h>
  25. #include <linux/kernel.h>
  26. #include <linux/slab.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/clk.h>
  30. #include <linux/workqueue.h>
  31. #include <linux/sysfs.h>
  32. #include <linux/kobject.h>
  33. #include <linux/io.h>
  34. #include <linux/mutex.h>
  35. #include <linux/platform_data/exynos_thermal.h>
  36. #include <linux/thermal.h>
  37. #include <linux/cpufreq.h>
  38. #include <linux/cpu_cooling.h>
  39. #include <linux/of.h>
  40. #include <plat/cpu.h>
  41. /* Exynos generic registers */
  42. #define EXYNOS_TMU_REG_TRIMINFO 0x0
  43. #define EXYNOS_TMU_REG_CONTROL 0x20
  44. #define EXYNOS_TMU_REG_STATUS 0x28
  45. #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
  46. #define EXYNOS_TMU_REG_INTEN 0x70
  47. #define EXYNOS_TMU_REG_INTSTAT 0x74
  48. #define EXYNOS_TMU_REG_INTCLEAR 0x78
  49. #define EXYNOS_TMU_TRIM_TEMP_MASK 0xff
  50. #define EXYNOS_TMU_GAIN_SHIFT 8
  51. #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
  52. #define EXYNOS_TMU_CORE_ON 3
  53. #define EXYNOS_TMU_CORE_OFF 2
  54. #define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET 50
  55. /* Exynos4210 specific registers */
  56. #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
  57. #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
  58. #define EXYNOS4210_TMU_REG_TRIG_LEVEL1 0x54
  59. #define EXYNOS4210_TMU_REG_TRIG_LEVEL2 0x58
  60. #define EXYNOS4210_TMU_REG_TRIG_LEVEL3 0x5C
  61. #define EXYNOS4210_TMU_REG_PAST_TEMP0 0x60
  62. #define EXYNOS4210_TMU_REG_PAST_TEMP1 0x64
  63. #define EXYNOS4210_TMU_REG_PAST_TEMP2 0x68
  64. #define EXYNOS4210_TMU_REG_PAST_TEMP3 0x6C
  65. #define EXYNOS4210_TMU_TRIG_LEVEL0_MASK 0x1
  66. #define EXYNOS4210_TMU_TRIG_LEVEL1_MASK 0x10
  67. #define EXYNOS4210_TMU_TRIG_LEVEL2_MASK 0x100
  68. #define EXYNOS4210_TMU_TRIG_LEVEL3_MASK 0x1000
  69. #define EXYNOS4210_TMU_INTCLEAR_VAL 0x1111
  70. /* Exynos5250 and Exynos4412 specific registers */
  71. #define EXYNOS_TMU_TRIMINFO_CON 0x14
  72. #define EXYNOS_THD_TEMP_RISE 0x50
  73. #define EXYNOS_THD_TEMP_FALL 0x54
  74. #define EXYNOS_EMUL_CON 0x80
  75. #define EXYNOS_TRIMINFO_RELOAD 0x1
  76. #define EXYNOS_TMU_CLEAR_RISE_INT 0x111
  77. #define EXYNOS_TMU_CLEAR_FALL_INT (0x111 << 12)
  78. #define EXYNOS_MUX_ADDR_VALUE 6
  79. #define EXYNOS_MUX_ADDR_SHIFT 20
  80. #define EXYNOS_TMU_TRIP_MODE_SHIFT 13
  81. #define EFUSE_MIN_VALUE 40
  82. #define EFUSE_MAX_VALUE 100
  83. /* In-kernel thermal framework related macros & definations */
  84. #define SENSOR_NAME_LEN 16
  85. #define MAX_TRIP_COUNT 8
  86. #define MAX_COOLING_DEVICE 4
  87. #define MAX_THRESHOLD_LEVS 4
  88. #define ACTIVE_INTERVAL 500
  89. #define IDLE_INTERVAL 10000
  90. #define MCELSIUS 1000
  91. #ifdef CONFIG_EXYNOS_THERMAL_EMUL
  92. #define EXYNOS_EMUL_TIME 0x57F0
  93. #define EXYNOS_EMUL_TIME_SHIFT 16
  94. #define EXYNOS_EMUL_DATA_SHIFT 8
  95. #define EXYNOS_EMUL_DATA_MASK 0xFF
  96. #define EXYNOS_EMUL_ENABLE 0x1
  97. #endif /* CONFIG_EXYNOS_THERMAL_EMUL */
  98. /* CPU Zone information */
  99. #define PANIC_ZONE 4
  100. #define WARN_ZONE 3
  101. #define MONITOR_ZONE 2
  102. #define SAFE_ZONE 1
  103. #define GET_ZONE(trip) (trip + 2)
  104. #define GET_TRIP(zone) (zone - 2)
  105. #define EXYNOS_ZONE_COUNT 3
  106. struct exynos_tmu_data {
  107. struct exynos_tmu_platform_data *pdata;
  108. struct resource *mem;
  109. void __iomem *base;
  110. int irq;
  111. enum soc_type soc;
  112. struct work_struct irq_work;
  113. struct mutex lock;
  114. struct clk *clk;
  115. u8 temp_error1, temp_error2;
  116. };
  117. struct thermal_trip_point_conf {
  118. int trip_val[MAX_TRIP_COUNT];
  119. int trip_count;
  120. u8 trigger_falling;
  121. };
  122. struct thermal_cooling_conf {
  123. struct freq_clip_table freq_data[MAX_TRIP_COUNT];
  124. int freq_clip_count;
  125. };
  126. struct thermal_sensor_conf {
  127. char name[SENSOR_NAME_LEN];
  128. int (*read_temperature)(void *data);
  129. struct thermal_trip_point_conf trip_data;
  130. struct thermal_cooling_conf cooling_data;
  131. void *private_data;
  132. };
  133. struct exynos_thermal_zone {
  134. enum thermal_device_mode mode;
  135. struct thermal_zone_device *therm_dev;
  136. struct thermal_cooling_device *cool_dev[MAX_COOLING_DEVICE];
  137. unsigned int cool_dev_size;
  138. struct platform_device *exynos4_dev;
  139. struct thermal_sensor_conf *sensor_conf;
  140. bool bind;
  141. };
  142. static struct exynos_thermal_zone *th_zone;
  143. static void exynos_unregister_thermal(void);
  144. static int exynos_register_thermal(struct thermal_sensor_conf *sensor_conf);
  145. /* Get mode callback functions for thermal zone */
  146. static int exynos_get_mode(struct thermal_zone_device *thermal,
  147. enum thermal_device_mode *mode)
  148. {
  149. if (th_zone)
  150. *mode = th_zone->mode;
  151. return 0;
  152. }
  153. /* Set mode callback functions for thermal zone */
  154. static int exynos_set_mode(struct thermal_zone_device *thermal,
  155. enum thermal_device_mode mode)
  156. {
  157. if (!th_zone->therm_dev) {
  158. pr_notice("thermal zone not registered\n");
  159. return 0;
  160. }
  161. mutex_lock(&th_zone->therm_dev->lock);
  162. if (mode == THERMAL_DEVICE_ENABLED &&
  163. !th_zone->sensor_conf->trip_data.trigger_falling)
  164. th_zone->therm_dev->polling_delay = IDLE_INTERVAL;
  165. else
  166. th_zone->therm_dev->polling_delay = 0;
  167. mutex_unlock(&th_zone->therm_dev->lock);
  168. th_zone->mode = mode;
  169. thermal_zone_device_update(th_zone->therm_dev);
  170. pr_info("thermal polling set for duration=%d msec\n",
  171. th_zone->therm_dev->polling_delay);
  172. return 0;
  173. }
  174. /* Get trip type callback functions for thermal zone */
  175. static int exynos_get_trip_type(struct thermal_zone_device *thermal, int trip,
  176. enum thermal_trip_type *type)
  177. {
  178. switch (GET_ZONE(trip)) {
  179. case MONITOR_ZONE:
  180. case WARN_ZONE:
  181. *type = THERMAL_TRIP_ACTIVE;
  182. break;
  183. case PANIC_ZONE:
  184. *type = THERMAL_TRIP_CRITICAL;
  185. break;
  186. default:
  187. return -EINVAL;
  188. }
  189. return 0;
  190. }
  191. /* Get trip temperature callback functions for thermal zone */
  192. static int exynos_get_trip_temp(struct thermal_zone_device *thermal, int trip,
  193. unsigned long *temp)
  194. {
  195. if (trip < GET_TRIP(MONITOR_ZONE) || trip > GET_TRIP(PANIC_ZONE))
  196. return -EINVAL;
  197. *temp = th_zone->sensor_conf->trip_data.trip_val[trip];
  198. /* convert the temperature into millicelsius */
  199. *temp = *temp * MCELSIUS;
  200. return 0;
  201. }
  202. /* Get critical temperature callback functions for thermal zone */
  203. static int exynos_get_crit_temp(struct thermal_zone_device *thermal,
  204. unsigned long *temp)
  205. {
  206. int ret;
  207. /* Panic zone */
  208. ret = exynos_get_trip_temp(thermal, GET_TRIP(PANIC_ZONE), temp);
  209. return ret;
  210. }
  211. static int exynos_get_frequency_level(unsigned int cpu, unsigned int freq)
  212. {
  213. int i = 0, ret = -EINVAL;
  214. struct cpufreq_frequency_table *table = NULL;
  215. #ifdef CONFIG_CPU_FREQ
  216. table = cpufreq_frequency_get_table(cpu);
  217. #endif
  218. if (!table)
  219. return ret;
  220. while (table[i].frequency != CPUFREQ_TABLE_END) {
  221. if (table[i].frequency == CPUFREQ_ENTRY_INVALID)
  222. continue;
  223. if (table[i].frequency == freq)
  224. return i;
  225. i++;
  226. }
  227. return ret;
  228. }
  229. /* Bind callback functions for thermal zone */
  230. static int exynos_bind(struct thermal_zone_device *thermal,
  231. struct thermal_cooling_device *cdev)
  232. {
  233. int ret = 0, i, tab_size, level;
  234. struct freq_clip_table *tab_ptr, *clip_data;
  235. struct thermal_sensor_conf *data = th_zone->sensor_conf;
  236. tab_ptr = (struct freq_clip_table *)data->cooling_data.freq_data;
  237. tab_size = data->cooling_data.freq_clip_count;
  238. if (tab_ptr == NULL || tab_size == 0)
  239. return -EINVAL;
  240. /* find the cooling device registered*/
  241. for (i = 0; i < th_zone->cool_dev_size; i++)
  242. if (cdev == th_zone->cool_dev[i])
  243. break;
  244. /* No matching cooling device */
  245. if (i == th_zone->cool_dev_size)
  246. return 0;
  247. /* Bind the thermal zone to the cpufreq cooling device */
  248. for (i = 0; i < tab_size; i++) {
  249. clip_data = (struct freq_clip_table *)&(tab_ptr[i]);
  250. level = exynos_get_frequency_level(0, clip_data->freq_clip_max);
  251. if (level < 0)
  252. return 0;
  253. switch (GET_ZONE(i)) {
  254. case MONITOR_ZONE:
  255. case WARN_ZONE:
  256. if (thermal_zone_bind_cooling_device(thermal, i, cdev,
  257. level, level)) {
  258. pr_err("error binding cdev inst %d\n", i);
  259. ret = -EINVAL;
  260. }
  261. th_zone->bind = true;
  262. break;
  263. default:
  264. ret = -EINVAL;
  265. }
  266. }
  267. return ret;
  268. }
  269. /* Unbind callback functions for thermal zone */
  270. static int exynos_unbind(struct thermal_zone_device *thermal,
  271. struct thermal_cooling_device *cdev)
  272. {
  273. int ret = 0, i, tab_size;
  274. struct thermal_sensor_conf *data = th_zone->sensor_conf;
  275. if (th_zone->bind == false)
  276. return 0;
  277. tab_size = data->cooling_data.freq_clip_count;
  278. if (tab_size == 0)
  279. return -EINVAL;
  280. /* find the cooling device registered*/
  281. for (i = 0; i < th_zone->cool_dev_size; i++)
  282. if (cdev == th_zone->cool_dev[i])
  283. break;
  284. /* No matching cooling device */
  285. if (i == th_zone->cool_dev_size)
  286. return 0;
  287. /* Bind the thermal zone to the cpufreq cooling device */
  288. for (i = 0; i < tab_size; i++) {
  289. switch (GET_ZONE(i)) {
  290. case MONITOR_ZONE:
  291. case WARN_ZONE:
  292. if (thermal_zone_unbind_cooling_device(thermal, i,
  293. cdev)) {
  294. pr_err("error unbinding cdev inst=%d\n", i);
  295. ret = -EINVAL;
  296. }
  297. th_zone->bind = false;
  298. break;
  299. default:
  300. ret = -EINVAL;
  301. }
  302. }
  303. return ret;
  304. }
  305. /* Get temperature callback functions for thermal zone */
  306. static int exynos_get_temp(struct thermal_zone_device *thermal,
  307. unsigned long *temp)
  308. {
  309. void *data;
  310. if (!th_zone->sensor_conf) {
  311. pr_info("Temperature sensor not initialised\n");
  312. return -EINVAL;
  313. }
  314. data = th_zone->sensor_conf->private_data;
  315. *temp = th_zone->sensor_conf->read_temperature(data);
  316. /* convert the temperature into millicelsius */
  317. *temp = *temp * MCELSIUS;
  318. return 0;
  319. }
  320. /* Get the temperature trend */
  321. static int exynos_get_trend(struct thermal_zone_device *thermal,
  322. int trip, enum thermal_trend *trend)
  323. {
  324. int ret;
  325. unsigned long trip_temp;
  326. ret = exynos_get_trip_temp(thermal, trip, &trip_temp);
  327. if (ret < 0)
  328. return ret;
  329. if (thermal->temperature >= trip_temp)
  330. *trend = THERMAL_TREND_RAISING;
  331. else
  332. *trend = THERMAL_TREND_DROPPING;
  333. return 0;
  334. }
  335. /* Operation callback functions for thermal zone */
  336. static struct thermal_zone_device_ops const exynos_dev_ops = {
  337. .bind = exynos_bind,
  338. .unbind = exynos_unbind,
  339. .get_temp = exynos_get_temp,
  340. .get_trend = exynos_get_trend,
  341. .get_mode = exynos_get_mode,
  342. .set_mode = exynos_set_mode,
  343. .get_trip_type = exynos_get_trip_type,
  344. .get_trip_temp = exynos_get_trip_temp,
  345. .get_crit_temp = exynos_get_crit_temp,
  346. };
  347. /*
  348. * This function may be called from interrupt based temperature sensor
  349. * when threshold is changed.
  350. */
  351. static void exynos_report_trigger(void)
  352. {
  353. unsigned int i;
  354. char data[10];
  355. char *envp[] = { data, NULL };
  356. if (!th_zone || !th_zone->therm_dev)
  357. return;
  358. if (th_zone->bind == false) {
  359. for (i = 0; i < th_zone->cool_dev_size; i++) {
  360. if (!th_zone->cool_dev[i])
  361. continue;
  362. exynos_bind(th_zone->therm_dev,
  363. th_zone->cool_dev[i]);
  364. }
  365. }
  366. thermal_zone_device_update(th_zone->therm_dev);
  367. mutex_lock(&th_zone->therm_dev->lock);
  368. /* Find the level for which trip happened */
  369. for (i = 0; i < th_zone->sensor_conf->trip_data.trip_count; i++) {
  370. if (th_zone->therm_dev->last_temperature <
  371. th_zone->sensor_conf->trip_data.trip_val[i] * MCELSIUS)
  372. break;
  373. }
  374. if (th_zone->mode == THERMAL_DEVICE_ENABLED &&
  375. !th_zone->sensor_conf->trip_data.trigger_falling) {
  376. if (i > 0)
  377. th_zone->therm_dev->polling_delay = ACTIVE_INTERVAL;
  378. else
  379. th_zone->therm_dev->polling_delay = IDLE_INTERVAL;
  380. }
  381. snprintf(data, sizeof(data), "%u", i);
  382. kobject_uevent_env(&th_zone->therm_dev->device.kobj, KOBJ_CHANGE, envp);
  383. mutex_unlock(&th_zone->therm_dev->lock);
  384. }
  385. /* Register with the in-kernel thermal management */
  386. static int exynos_register_thermal(struct thermal_sensor_conf *sensor_conf)
  387. {
  388. int ret;
  389. struct cpumask mask_val;
  390. if (!sensor_conf || !sensor_conf->read_temperature) {
  391. pr_err("Temperature sensor not initialised\n");
  392. return -EINVAL;
  393. }
  394. th_zone = kzalloc(sizeof(struct exynos_thermal_zone), GFP_KERNEL);
  395. if (!th_zone)
  396. return -ENOMEM;
  397. th_zone->sensor_conf = sensor_conf;
  398. cpumask_set_cpu(0, &mask_val);
  399. th_zone->cool_dev[0] = cpufreq_cooling_register(&mask_val);
  400. if (IS_ERR(th_zone->cool_dev[0])) {
  401. pr_err("Failed to register cpufreq cooling device\n");
  402. ret = -EINVAL;
  403. goto err_unregister;
  404. }
  405. th_zone->cool_dev_size++;
  406. th_zone->therm_dev = thermal_zone_device_register(sensor_conf->name,
  407. EXYNOS_ZONE_COUNT, 0, NULL, &exynos_dev_ops, NULL, 0,
  408. sensor_conf->trip_data.trigger_falling ?
  409. 0 : IDLE_INTERVAL);
  410. if (IS_ERR(th_zone->therm_dev)) {
  411. pr_err("Failed to register thermal zone device\n");
  412. ret = -EINVAL;
  413. goto err_unregister;
  414. }
  415. th_zone->mode = THERMAL_DEVICE_ENABLED;
  416. pr_info("Exynos: Kernel Thermal management registered\n");
  417. return 0;
  418. err_unregister:
  419. exynos_unregister_thermal();
  420. return ret;
  421. }
  422. /* Un-Register with the in-kernel thermal management */
  423. static void exynos_unregister_thermal(void)
  424. {
  425. int i;
  426. if (!th_zone)
  427. return;
  428. if (th_zone->therm_dev)
  429. thermal_zone_device_unregister(th_zone->therm_dev);
  430. for (i = 0; i < th_zone->cool_dev_size; i++) {
  431. if (th_zone->cool_dev[i])
  432. cpufreq_cooling_unregister(th_zone->cool_dev[i]);
  433. }
  434. kfree(th_zone);
  435. pr_info("Exynos: Kernel Thermal management unregistered\n");
  436. }
  437. /*
  438. * TMU treats temperature as a mapped temperature code.
  439. * The temperature is converted differently depending on the calibration type.
  440. */
  441. static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
  442. {
  443. struct exynos_tmu_platform_data *pdata = data->pdata;
  444. int temp_code;
  445. if (data->soc == SOC_ARCH_EXYNOS4210)
  446. /* temp should range between 25 and 125 */
  447. if (temp < 25 || temp > 125) {
  448. temp_code = -EINVAL;
  449. goto out;
  450. }
  451. switch (pdata->cal_type) {
  452. case TYPE_TWO_POINT_TRIMMING:
  453. temp_code = (temp - 25) *
  454. (data->temp_error2 - data->temp_error1) /
  455. (85 - 25) + data->temp_error1;
  456. break;
  457. case TYPE_ONE_POINT_TRIMMING:
  458. temp_code = temp + data->temp_error1 - 25;
  459. break;
  460. default:
  461. temp_code = temp + EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET;
  462. break;
  463. }
  464. out:
  465. return temp_code;
  466. }
  467. /*
  468. * Calculate a temperature value from a temperature code.
  469. * The unit of the temperature is degree Celsius.
  470. */
  471. static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
  472. {
  473. struct exynos_tmu_platform_data *pdata = data->pdata;
  474. int temp;
  475. if (data->soc == SOC_ARCH_EXYNOS4210)
  476. /* temp_code should range between 75 and 175 */
  477. if (temp_code < 75 || temp_code > 175) {
  478. temp = -ENODATA;
  479. goto out;
  480. }
  481. switch (pdata->cal_type) {
  482. case TYPE_TWO_POINT_TRIMMING:
  483. temp = (temp_code - data->temp_error1) * (85 - 25) /
  484. (data->temp_error2 - data->temp_error1) + 25;
  485. break;
  486. case TYPE_ONE_POINT_TRIMMING:
  487. temp = temp_code - data->temp_error1 + 25;
  488. break;
  489. default:
  490. temp = temp_code - EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET;
  491. break;
  492. }
  493. out:
  494. return temp;
  495. }
  496. static int exynos_tmu_initialize(struct platform_device *pdev)
  497. {
  498. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  499. struct exynos_tmu_platform_data *pdata = data->pdata;
  500. unsigned int status, trim_info;
  501. unsigned int rising_threshold = 0, falling_threshold = 0;
  502. int ret = 0, threshold_code, i, trigger_levs = 0;
  503. mutex_lock(&data->lock);
  504. clk_enable(data->clk);
  505. status = readb(data->base + EXYNOS_TMU_REG_STATUS);
  506. if (!status) {
  507. ret = -EBUSY;
  508. goto out;
  509. }
  510. if (data->soc == SOC_ARCH_EXYNOS) {
  511. __raw_writel(EXYNOS_TRIMINFO_RELOAD,
  512. data->base + EXYNOS_TMU_TRIMINFO_CON);
  513. }
  514. /* Save trimming info in order to perform calibration */
  515. trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
  516. data->temp_error1 = trim_info & EXYNOS_TMU_TRIM_TEMP_MASK;
  517. data->temp_error2 = ((trim_info >> 8) & EXYNOS_TMU_TRIM_TEMP_MASK);
  518. if ((EFUSE_MIN_VALUE > data->temp_error1) ||
  519. (data->temp_error1 > EFUSE_MAX_VALUE) ||
  520. (data->temp_error2 != 0))
  521. data->temp_error1 = pdata->efuse_value;
  522. /* Count trigger levels to be enabled */
  523. for (i = 0; i < MAX_THRESHOLD_LEVS; i++)
  524. if (pdata->trigger_levels[i])
  525. trigger_levs++;
  526. if (data->soc == SOC_ARCH_EXYNOS4210) {
  527. /* Write temperature code for threshold */
  528. threshold_code = temp_to_code(data, pdata->threshold);
  529. if (threshold_code < 0) {
  530. ret = threshold_code;
  531. goto out;
  532. }
  533. writeb(threshold_code,
  534. data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
  535. for (i = 0; i < trigger_levs; i++)
  536. writeb(pdata->trigger_levels[i],
  537. data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4);
  538. writel(EXYNOS4210_TMU_INTCLEAR_VAL,
  539. data->base + EXYNOS_TMU_REG_INTCLEAR);
  540. } else if (data->soc == SOC_ARCH_EXYNOS) {
  541. /* Write temperature code for rising and falling threshold */
  542. for (i = 0; i < trigger_levs; i++) {
  543. threshold_code = temp_to_code(data,
  544. pdata->trigger_levels[i]);
  545. if (threshold_code < 0) {
  546. ret = threshold_code;
  547. goto out;
  548. }
  549. rising_threshold |= threshold_code << 8 * i;
  550. if (pdata->threshold_falling) {
  551. threshold_code = temp_to_code(data,
  552. pdata->trigger_levels[i] -
  553. pdata->threshold_falling);
  554. if (threshold_code > 0)
  555. falling_threshold |=
  556. threshold_code << 8 * i;
  557. }
  558. }
  559. writel(rising_threshold,
  560. data->base + EXYNOS_THD_TEMP_RISE);
  561. writel(falling_threshold,
  562. data->base + EXYNOS_THD_TEMP_FALL);
  563. writel(EXYNOS_TMU_CLEAR_RISE_INT | EXYNOS_TMU_CLEAR_FALL_INT,
  564. data->base + EXYNOS_TMU_REG_INTCLEAR);
  565. }
  566. out:
  567. clk_disable(data->clk);
  568. mutex_unlock(&data->lock);
  569. return ret;
  570. }
  571. static void exynos_tmu_control(struct platform_device *pdev, bool on)
  572. {
  573. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  574. struct exynos_tmu_platform_data *pdata = data->pdata;
  575. unsigned int con, interrupt_en;
  576. mutex_lock(&data->lock);
  577. clk_enable(data->clk);
  578. con = pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT |
  579. pdata->gain << EXYNOS_TMU_GAIN_SHIFT;
  580. if (data->soc == SOC_ARCH_EXYNOS) {
  581. con |= pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT;
  582. con |= (EXYNOS_MUX_ADDR_VALUE << EXYNOS_MUX_ADDR_SHIFT);
  583. }
  584. if (on) {
  585. con |= EXYNOS_TMU_CORE_ON;
  586. interrupt_en = pdata->trigger_level3_en << 12 |
  587. pdata->trigger_level2_en << 8 |
  588. pdata->trigger_level1_en << 4 |
  589. pdata->trigger_level0_en;
  590. if (pdata->threshold_falling)
  591. interrupt_en |= interrupt_en << 16;
  592. } else {
  593. con |= EXYNOS_TMU_CORE_OFF;
  594. interrupt_en = 0; /* Disable all interrupts */
  595. }
  596. writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
  597. writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
  598. clk_disable(data->clk);
  599. mutex_unlock(&data->lock);
  600. }
  601. static int exynos_tmu_read(struct exynos_tmu_data *data)
  602. {
  603. u8 temp_code;
  604. int temp;
  605. mutex_lock(&data->lock);
  606. clk_enable(data->clk);
  607. temp_code = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
  608. temp = code_to_temp(data, temp_code);
  609. clk_disable(data->clk);
  610. mutex_unlock(&data->lock);
  611. return temp;
  612. }
  613. static void exynos_tmu_work(struct work_struct *work)
  614. {
  615. struct exynos_tmu_data *data = container_of(work,
  616. struct exynos_tmu_data, irq_work);
  617. exynos_report_trigger();
  618. mutex_lock(&data->lock);
  619. clk_enable(data->clk);
  620. if (data->soc == SOC_ARCH_EXYNOS)
  621. writel(EXYNOS_TMU_CLEAR_RISE_INT |
  622. EXYNOS_TMU_CLEAR_FALL_INT,
  623. data->base + EXYNOS_TMU_REG_INTCLEAR);
  624. else
  625. writel(EXYNOS4210_TMU_INTCLEAR_VAL,
  626. data->base + EXYNOS_TMU_REG_INTCLEAR);
  627. clk_disable(data->clk);
  628. mutex_unlock(&data->lock);
  629. enable_irq(data->irq);
  630. }
  631. static irqreturn_t exynos_tmu_irq(int irq, void *id)
  632. {
  633. struct exynos_tmu_data *data = id;
  634. disable_irq_nosync(irq);
  635. schedule_work(&data->irq_work);
  636. return IRQ_HANDLED;
  637. }
  638. static struct thermal_sensor_conf exynos_sensor_conf = {
  639. .name = "exynos-therm",
  640. .read_temperature = (int (*)(void *))exynos_tmu_read,
  641. };
  642. #if defined(CONFIG_CPU_EXYNOS4210)
  643. static struct exynos_tmu_platform_data const exynos4210_default_tmu_data = {
  644. .threshold = 80,
  645. .trigger_levels[0] = 5,
  646. .trigger_levels[1] = 20,
  647. .trigger_levels[2] = 30,
  648. .trigger_level0_en = 1,
  649. .trigger_level1_en = 1,
  650. .trigger_level2_en = 1,
  651. .trigger_level3_en = 0,
  652. .gain = 15,
  653. .reference_voltage = 7,
  654. .cal_type = TYPE_ONE_POINT_TRIMMING,
  655. .freq_tab[0] = {
  656. .freq_clip_max = 800 * 1000,
  657. .temp_level = 85,
  658. },
  659. .freq_tab[1] = {
  660. .freq_clip_max = 200 * 1000,
  661. .temp_level = 100,
  662. },
  663. .freq_tab_count = 2,
  664. .type = SOC_ARCH_EXYNOS4210,
  665. };
  666. #define EXYNOS4210_TMU_DRV_DATA (&exynos4210_default_tmu_data)
  667. #else
  668. #define EXYNOS4210_TMU_DRV_DATA (NULL)
  669. #endif
  670. #if defined(CONFIG_SOC_EXYNOS5250) || defined(CONFIG_SOC_EXYNOS4412)
  671. static struct exynos_tmu_platform_data const exynos_default_tmu_data = {
  672. .threshold_falling = 10,
  673. .trigger_levels[0] = 85,
  674. .trigger_levels[1] = 103,
  675. .trigger_levels[2] = 110,
  676. .trigger_level0_en = 1,
  677. .trigger_level1_en = 1,
  678. .trigger_level2_en = 1,
  679. .trigger_level3_en = 0,
  680. .gain = 8,
  681. .reference_voltage = 16,
  682. .noise_cancel_mode = 4,
  683. .cal_type = TYPE_ONE_POINT_TRIMMING,
  684. .efuse_value = 55,
  685. .freq_tab[0] = {
  686. .freq_clip_max = 800 * 1000,
  687. .temp_level = 85,
  688. },
  689. .freq_tab[1] = {
  690. .freq_clip_max = 200 * 1000,
  691. .temp_level = 103,
  692. },
  693. .freq_tab_count = 2,
  694. .type = SOC_ARCH_EXYNOS,
  695. };
  696. #define EXYNOS_TMU_DRV_DATA (&exynos_default_tmu_data)
  697. #else
  698. #define EXYNOS_TMU_DRV_DATA (NULL)
  699. #endif
  700. #ifdef CONFIG_OF
  701. static const struct of_device_id exynos_tmu_match[] = {
  702. {
  703. .compatible = "samsung,exynos4210-tmu",
  704. .data = (void *)EXYNOS4210_TMU_DRV_DATA,
  705. },
  706. {
  707. .compatible = "samsung,exynos5250-tmu",
  708. .data = (void *)EXYNOS_TMU_DRV_DATA,
  709. },
  710. {},
  711. };
  712. MODULE_DEVICE_TABLE(of, exynos_tmu_match);
  713. #endif
  714. static struct platform_device_id exynos_tmu_driver_ids[] = {
  715. {
  716. .name = "exynos4210-tmu",
  717. .driver_data = (kernel_ulong_t)EXYNOS4210_TMU_DRV_DATA,
  718. },
  719. {
  720. .name = "exynos5250-tmu",
  721. .driver_data = (kernel_ulong_t)EXYNOS_TMU_DRV_DATA,
  722. },
  723. { },
  724. };
  725. MODULE_DEVICE_TABLE(platform, exynos_tmu_driver_ids);
  726. static inline struct exynos_tmu_platform_data *exynos_get_driver_data(
  727. struct platform_device *pdev)
  728. {
  729. #ifdef CONFIG_OF
  730. if (pdev->dev.of_node) {
  731. const struct of_device_id *match;
  732. match = of_match_node(exynos_tmu_match, pdev->dev.of_node);
  733. if (!match)
  734. return NULL;
  735. return (struct exynos_tmu_platform_data *) match->data;
  736. }
  737. #endif
  738. return (struct exynos_tmu_platform_data *)
  739. platform_get_device_id(pdev)->driver_data;
  740. }
  741. #ifdef CONFIG_EXYNOS_THERMAL_EMUL
  742. static ssize_t exynos_tmu_emulation_show(struct device *dev,
  743. struct device_attribute *attr,
  744. char *buf)
  745. {
  746. struct platform_device *pdev = container_of(dev,
  747. struct platform_device, dev);
  748. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  749. unsigned int reg;
  750. u8 temp_code;
  751. int temp = 0;
  752. if (data->soc == SOC_ARCH_EXYNOS4210)
  753. goto out;
  754. mutex_lock(&data->lock);
  755. clk_enable(data->clk);
  756. reg = readl(data->base + EXYNOS_EMUL_CON);
  757. clk_disable(data->clk);
  758. mutex_unlock(&data->lock);
  759. if (reg & EXYNOS_EMUL_ENABLE) {
  760. reg >>= EXYNOS_EMUL_DATA_SHIFT;
  761. temp_code = reg & EXYNOS_EMUL_DATA_MASK;
  762. temp = code_to_temp(data, temp_code);
  763. }
  764. out:
  765. return sprintf(buf, "%d\n", temp * MCELSIUS);
  766. }
  767. static ssize_t exynos_tmu_emulation_store(struct device *dev,
  768. struct device_attribute *attr,
  769. const char *buf, size_t count)
  770. {
  771. struct platform_device *pdev = container_of(dev,
  772. struct platform_device, dev);
  773. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  774. unsigned int reg;
  775. int temp;
  776. if (data->soc == SOC_ARCH_EXYNOS4210)
  777. goto out;
  778. if (!sscanf(buf, "%d\n", &temp) || temp < 0)
  779. return -EINVAL;
  780. mutex_lock(&data->lock);
  781. clk_enable(data->clk);
  782. reg = readl(data->base + EXYNOS_EMUL_CON);
  783. if (temp) {
  784. /* Both CELSIUS and MCELSIUS type are available for input */
  785. if (temp > MCELSIUS)
  786. temp /= MCELSIUS;
  787. reg = (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT) |
  788. (temp_to_code(data, (temp / MCELSIUS))
  789. << EXYNOS_EMUL_DATA_SHIFT) | EXYNOS_EMUL_ENABLE;
  790. } else {
  791. reg &= ~EXYNOS_EMUL_ENABLE;
  792. }
  793. writel(reg, data->base + EXYNOS_EMUL_CON);
  794. clk_disable(data->clk);
  795. mutex_unlock(&data->lock);
  796. out:
  797. return count;
  798. }
  799. static DEVICE_ATTR(emulation, 0644, exynos_tmu_emulation_show,
  800. exynos_tmu_emulation_store);
  801. static int create_emulation_sysfs(struct device *dev)
  802. {
  803. return device_create_file(dev, &dev_attr_emulation);
  804. }
  805. static void remove_emulation_sysfs(struct device *dev)
  806. {
  807. device_remove_file(dev, &dev_attr_emulation);
  808. }
  809. #else
  810. static inline int create_emulation_sysfs(struct device *dev) { return 0; }
  811. static inline void remove_emulation_sysfs(struct device *dev) {}
  812. #endif
  813. static int __devinit exynos_tmu_probe(struct platform_device *pdev)
  814. {
  815. struct exynos_tmu_data *data;
  816. struct exynos_tmu_platform_data *pdata = pdev->dev.platform_data;
  817. int ret, i;
  818. if (!pdata)
  819. pdata = exynos_get_driver_data(pdev);
  820. if (!pdata) {
  821. dev_err(&pdev->dev, "No platform init data supplied.\n");
  822. return -ENODEV;
  823. }
  824. data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
  825. GFP_KERNEL);
  826. if (!data) {
  827. dev_err(&pdev->dev, "Failed to allocate driver structure\n");
  828. return -ENOMEM;
  829. }
  830. data->irq = platform_get_irq(pdev, 0);
  831. if (data->irq < 0) {
  832. dev_err(&pdev->dev, "Failed to get platform irq\n");
  833. return data->irq;
  834. }
  835. INIT_WORK(&data->irq_work, exynos_tmu_work);
  836. data->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  837. if (!data->mem) {
  838. dev_err(&pdev->dev, "Failed to get platform resource\n");
  839. return -ENOENT;
  840. }
  841. data->base = devm_request_and_ioremap(&pdev->dev, data->mem);
  842. if (!data->base) {
  843. dev_err(&pdev->dev, "Failed to ioremap memory\n");
  844. return -ENODEV;
  845. }
  846. ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
  847. IRQF_TRIGGER_RISING, "exynos-tmu", data);
  848. if (ret) {
  849. dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
  850. return ret;
  851. }
  852. data->clk = clk_get(NULL, "tmu_apbif");
  853. if (IS_ERR(data->clk)) {
  854. dev_err(&pdev->dev, "Failed to get clock\n");
  855. return PTR_ERR(data->clk);
  856. }
  857. if (pdata->type == SOC_ARCH_EXYNOS ||
  858. pdata->type == SOC_ARCH_EXYNOS4210)
  859. data->soc = pdata->type;
  860. else {
  861. ret = -EINVAL;
  862. dev_err(&pdev->dev, "Platform not supported\n");
  863. goto err_clk;
  864. }
  865. data->pdata = pdata;
  866. platform_set_drvdata(pdev, data);
  867. mutex_init(&data->lock);
  868. ret = exynos_tmu_initialize(pdev);
  869. if (ret) {
  870. dev_err(&pdev->dev, "Failed to initialize TMU\n");
  871. goto err_clk;
  872. }
  873. exynos_tmu_control(pdev, true);
  874. /* Register the sensor with thermal management interface */
  875. (&exynos_sensor_conf)->private_data = data;
  876. exynos_sensor_conf.trip_data.trip_count = pdata->trigger_level0_en +
  877. pdata->trigger_level1_en + pdata->trigger_level2_en +
  878. pdata->trigger_level3_en;
  879. for (i = 0; i < exynos_sensor_conf.trip_data.trip_count; i++)
  880. exynos_sensor_conf.trip_data.trip_val[i] =
  881. pdata->threshold + pdata->trigger_levels[i];
  882. exynos_sensor_conf.trip_data.trigger_falling = pdata->threshold_falling;
  883. exynos_sensor_conf.cooling_data.freq_clip_count =
  884. pdata->freq_tab_count;
  885. for (i = 0; i < pdata->freq_tab_count; i++) {
  886. exynos_sensor_conf.cooling_data.freq_data[i].freq_clip_max =
  887. pdata->freq_tab[i].freq_clip_max;
  888. exynos_sensor_conf.cooling_data.freq_data[i].temp_level =
  889. pdata->freq_tab[i].temp_level;
  890. }
  891. ret = exynos_register_thermal(&exynos_sensor_conf);
  892. if (ret) {
  893. dev_err(&pdev->dev, "Failed to register thermal interface\n");
  894. goto err_clk;
  895. }
  896. ret = create_emulation_sysfs(&pdev->dev);
  897. if (ret)
  898. dev_err(&pdev->dev, "Failed to create emulation mode sysfs node\n");
  899. return 0;
  900. err_clk:
  901. platform_set_drvdata(pdev, NULL);
  902. clk_put(data->clk);
  903. return ret;
  904. }
  905. static int __devexit exynos_tmu_remove(struct platform_device *pdev)
  906. {
  907. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  908. remove_emulation_sysfs(&pdev->dev);
  909. exynos_tmu_control(pdev, false);
  910. exynos_unregister_thermal();
  911. clk_put(data->clk);
  912. platform_set_drvdata(pdev, NULL);
  913. return 0;
  914. }
  915. #ifdef CONFIG_PM_SLEEP
  916. static int exynos_tmu_suspend(struct device *dev)
  917. {
  918. exynos_tmu_control(to_platform_device(dev), false);
  919. return 0;
  920. }
  921. static int exynos_tmu_resume(struct device *dev)
  922. {
  923. struct platform_device *pdev = to_platform_device(dev);
  924. exynos_tmu_initialize(pdev);
  925. exynos_tmu_control(pdev, true);
  926. return 0;
  927. }
  928. static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
  929. exynos_tmu_suspend, exynos_tmu_resume);
  930. #define EXYNOS_TMU_PM (&exynos_tmu_pm)
  931. #else
  932. #define EXYNOS_TMU_PM NULL
  933. #endif
  934. static struct platform_driver exynos_tmu_driver = {
  935. .driver = {
  936. .name = "exynos-tmu",
  937. .owner = THIS_MODULE,
  938. .pm = EXYNOS_TMU_PM,
  939. .of_match_table = of_match_ptr(exynos_tmu_match),
  940. },
  941. .probe = exynos_tmu_probe,
  942. .remove = __devexit_p(exynos_tmu_remove),
  943. .id_table = exynos_tmu_driver_ids,
  944. };
  945. module_platform_driver(exynos_tmu_driver);
  946. MODULE_DESCRIPTION("EXYNOS TMU Driver");
  947. MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
  948. MODULE_LICENSE("GPL");
  949. MODULE_ALIAS("platform:exynos-tmu");