dice.c 29 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232
  1. /*
  2. * TC Applied Technologies Digital Interface Communications Engine driver
  3. *
  4. * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
  5. * Licensed under the terms of the GNU General Public License, version 2.
  6. */
  7. #include <linux/compat.h>
  8. #include <linux/completion.h>
  9. #include <linux/delay.h>
  10. #include <linux/device.h>
  11. #include <linux/firewire.h>
  12. #include <linux/firewire-constants.h>
  13. #include <linux/jiffies.h>
  14. #include <linux/module.h>
  15. #include <linux/mod_devicetable.h>
  16. #include <linux/mutex.h>
  17. #include <linux/slab.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/wait.h>
  20. #include <sound/control.h>
  21. #include <sound/core.h>
  22. #include <sound/firewire.h>
  23. #include <sound/hwdep.h>
  24. #include <sound/initval.h>
  25. #include <sound/pcm.h>
  26. #include <sound/pcm_params.h>
  27. #include "amdtp.h"
  28. #include "iso-resources.h"
  29. #include "lib.h"
  30. #include "dice-interface.h"
  31. struct dice {
  32. struct snd_card *card;
  33. struct fw_unit *unit;
  34. spinlock_t lock;
  35. struct mutex mutex;
  36. unsigned int global_offset;
  37. unsigned int rx_offset;
  38. unsigned int clock_caps;
  39. unsigned int rx_channels[3];
  40. unsigned int rx_midi_ports[3];
  41. struct fw_address_handler notification_handler;
  42. int owner_generation;
  43. int dev_lock_count; /* > 0 driver, < 0 userspace */
  44. bool dev_lock_changed;
  45. bool global_enabled;
  46. struct completion clock_accepted;
  47. wait_queue_head_t hwdep_wait;
  48. u32 notification_bits;
  49. struct fw_iso_resources resources;
  50. struct amdtp_out_stream stream;
  51. };
  52. MODULE_DESCRIPTION("DICE driver");
  53. MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
  54. MODULE_LICENSE("GPL v2");
  55. static const unsigned int dice_rates[] = {
  56. /* mode 0 */
  57. [0] = 32000,
  58. [1] = 44100,
  59. [2] = 48000,
  60. /* mode 1 */
  61. [3] = 88200,
  62. [4] = 96000,
  63. /* mode 2 */
  64. [5] = 176400,
  65. [6] = 192000,
  66. };
  67. static unsigned int rate_to_index(unsigned int rate)
  68. {
  69. unsigned int i;
  70. for (i = 0; i < ARRAY_SIZE(dice_rates); ++i)
  71. if (dice_rates[i] == rate)
  72. return i;
  73. return 0;
  74. }
  75. static unsigned int rate_index_to_mode(unsigned int rate_index)
  76. {
  77. return ((int)rate_index - 1) / 2;
  78. }
  79. static void dice_lock_changed(struct dice *dice)
  80. {
  81. dice->dev_lock_changed = true;
  82. wake_up(&dice->hwdep_wait);
  83. }
  84. static int dice_try_lock(struct dice *dice)
  85. {
  86. int err;
  87. spin_lock_irq(&dice->lock);
  88. if (dice->dev_lock_count < 0) {
  89. err = -EBUSY;
  90. goto out;
  91. }
  92. if (dice->dev_lock_count++ == 0)
  93. dice_lock_changed(dice);
  94. err = 0;
  95. out:
  96. spin_unlock_irq(&dice->lock);
  97. return err;
  98. }
  99. static void dice_unlock(struct dice *dice)
  100. {
  101. spin_lock_irq(&dice->lock);
  102. if (WARN_ON(dice->dev_lock_count <= 0))
  103. goto out;
  104. if (--dice->dev_lock_count == 0)
  105. dice_lock_changed(dice);
  106. out:
  107. spin_unlock_irq(&dice->lock);
  108. }
  109. static inline u64 global_address(struct dice *dice, unsigned int offset)
  110. {
  111. return DICE_PRIVATE_SPACE + dice->global_offset + offset;
  112. }
  113. // TODO: rx index
  114. static inline u64 rx_address(struct dice *dice, unsigned int offset)
  115. {
  116. return DICE_PRIVATE_SPACE + dice->rx_offset + offset;
  117. }
  118. static int dice_owner_set(struct dice *dice)
  119. {
  120. struct fw_device *device = fw_parent_device(dice->unit);
  121. __be64 *buffer;
  122. int err, errors = 0;
  123. buffer = kmalloc(2 * 8, GFP_KERNEL);
  124. if (!buffer)
  125. return -ENOMEM;
  126. for (;;) {
  127. buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
  128. buffer[1] = cpu_to_be64(
  129. ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
  130. dice->notification_handler.offset);
  131. dice->owner_generation = device->generation;
  132. smp_rmb(); /* node_id vs. generation */
  133. err = snd_fw_transaction(dice->unit,
  134. TCODE_LOCK_COMPARE_SWAP,
  135. global_address(dice, GLOBAL_OWNER),
  136. buffer, 2 * 8,
  137. FW_FIXED_GENERATION |
  138. dice->owner_generation);
  139. if (err == 0) {
  140. if (buffer[0] != cpu_to_be64(OWNER_NO_OWNER)) {
  141. dev_err(&dice->unit->device,
  142. "device is already in use\n");
  143. err = -EBUSY;
  144. }
  145. break;
  146. }
  147. if (err != -EAGAIN || ++errors >= 3)
  148. break;
  149. msleep(20);
  150. }
  151. kfree(buffer);
  152. return err;
  153. }
  154. static int dice_owner_update(struct dice *dice)
  155. {
  156. struct fw_device *device = fw_parent_device(dice->unit);
  157. __be64 *buffer;
  158. int err;
  159. if (dice->owner_generation == -1)
  160. return 0;
  161. buffer = kmalloc(2 * 8, GFP_KERNEL);
  162. if (!buffer)
  163. return -ENOMEM;
  164. buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
  165. buffer[1] = cpu_to_be64(
  166. ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
  167. dice->notification_handler.offset);
  168. dice->owner_generation = device->generation;
  169. smp_rmb(); /* node_id vs. generation */
  170. err = snd_fw_transaction(dice->unit, TCODE_LOCK_COMPARE_SWAP,
  171. global_address(dice, GLOBAL_OWNER),
  172. buffer, 2 * 8,
  173. FW_FIXED_GENERATION | dice->owner_generation);
  174. if (err == 0) {
  175. if (buffer[0] != cpu_to_be64(OWNER_NO_OWNER)) {
  176. dev_err(&dice->unit->device,
  177. "device is already in use\n");
  178. err = -EBUSY;
  179. }
  180. } else if (err == -EAGAIN) {
  181. err = 0; /* try again later */
  182. }
  183. kfree(buffer);
  184. if (err < 0)
  185. dice->owner_generation = -1;
  186. return err;
  187. }
  188. static void dice_owner_clear(struct dice *dice)
  189. {
  190. struct fw_device *device = fw_parent_device(dice->unit);
  191. __be64 *buffer;
  192. buffer = kmalloc(2 * 8, GFP_KERNEL);
  193. if (!buffer)
  194. return;
  195. buffer[0] = cpu_to_be64(
  196. ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
  197. dice->notification_handler.offset);
  198. buffer[1] = cpu_to_be64(OWNER_NO_OWNER);
  199. snd_fw_transaction(dice->unit, TCODE_LOCK_COMPARE_SWAP,
  200. global_address(dice, GLOBAL_OWNER),
  201. buffer, 2 * 8, FW_QUIET |
  202. FW_FIXED_GENERATION | dice->owner_generation);
  203. kfree(buffer);
  204. dice->owner_generation = -1;
  205. }
  206. static int dice_enable_set(struct dice *dice)
  207. {
  208. __be32 value;
  209. int err;
  210. value = cpu_to_be32(1);
  211. err = snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
  212. global_address(dice, GLOBAL_ENABLE),
  213. &value, 4,
  214. FW_FIXED_GENERATION | dice->owner_generation);
  215. if (err < 0)
  216. return err;
  217. dice->global_enabled = true;
  218. return 0;
  219. }
  220. static void dice_enable_clear(struct dice *dice)
  221. {
  222. __be32 value;
  223. if (!dice->global_enabled)
  224. return;
  225. value = 0;
  226. snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
  227. global_address(dice, GLOBAL_ENABLE),
  228. &value, 4, FW_QUIET |
  229. FW_FIXED_GENERATION | dice->owner_generation);
  230. dice->global_enabled = false;
  231. }
  232. static void dice_notification(struct fw_card *card, struct fw_request *request,
  233. int tcode, int destination, int source,
  234. int generation, unsigned long long offset,
  235. void *data, size_t length, void *callback_data)
  236. {
  237. struct dice *dice = callback_data;
  238. u32 bits;
  239. unsigned long flags;
  240. if (tcode != TCODE_WRITE_QUADLET_REQUEST) {
  241. fw_send_response(card, request, RCODE_TYPE_ERROR);
  242. return;
  243. }
  244. if ((offset & 3) != 0) {
  245. fw_send_response(card, request, RCODE_ADDRESS_ERROR);
  246. return;
  247. }
  248. bits = be32_to_cpup(data);
  249. spin_lock_irqsave(&dice->lock, flags);
  250. dice->notification_bits |= bits;
  251. spin_unlock_irqrestore(&dice->lock, flags);
  252. fw_send_response(card, request, RCODE_COMPLETE);
  253. if (bits & NOTIFY_CLOCK_ACCEPTED)
  254. complete(&dice->clock_accepted);
  255. wake_up(&dice->hwdep_wait);
  256. }
  257. static int dice_rate_constraint(struct snd_pcm_hw_params *params,
  258. struct snd_pcm_hw_rule *rule)
  259. {
  260. struct dice *dice = rule->private;
  261. const struct snd_interval *channels =
  262. hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_CHANNELS);
  263. struct snd_interval *rate =
  264. hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
  265. struct snd_interval allowed_rates = {
  266. .min = UINT_MAX, .max = 0, .integer = 1
  267. };
  268. unsigned int i, mode;
  269. for (i = 0; i < ARRAY_SIZE(dice_rates); ++i) {
  270. mode = rate_index_to_mode(i);
  271. if ((dice->clock_caps & (1 << i)) &&
  272. snd_interval_test(channels, dice->rx_channels[mode])) {
  273. allowed_rates.min = min(allowed_rates.min,
  274. dice_rates[i]);
  275. allowed_rates.max = max(allowed_rates.max,
  276. dice_rates[i]);
  277. }
  278. }
  279. return snd_interval_refine(rate, &allowed_rates);
  280. }
  281. static int dice_channels_constraint(struct snd_pcm_hw_params *params,
  282. struct snd_pcm_hw_rule *rule)
  283. {
  284. struct dice *dice = rule->private;
  285. const struct snd_interval *rate =
  286. hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_RATE);
  287. struct snd_interval *channels =
  288. hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
  289. struct snd_interval allowed_channels = {
  290. .min = UINT_MAX, .max = 0, .integer = 1
  291. };
  292. unsigned int i, mode;
  293. for (i = 0; i < ARRAY_SIZE(dice_rates); ++i)
  294. if ((dice->clock_caps & (1 << i)) &&
  295. snd_interval_test(rate, dice_rates[i])) {
  296. mode = rate_index_to_mode(i);
  297. allowed_channels.min = min(allowed_channels.min,
  298. dice->rx_channels[mode]);
  299. allowed_channels.max = max(allowed_channels.max,
  300. dice->rx_channels[mode]);
  301. }
  302. return snd_interval_refine(channels, &allowed_channels);
  303. }
  304. static int dice_open(struct snd_pcm_substream *substream)
  305. {
  306. static const struct snd_pcm_hardware hardware = {
  307. .info = SNDRV_PCM_INFO_MMAP |
  308. SNDRV_PCM_INFO_MMAP_VALID |
  309. SNDRV_PCM_INFO_BATCH |
  310. SNDRV_PCM_INFO_INTERLEAVED |
  311. SNDRV_PCM_INFO_BLOCK_TRANSFER,
  312. .formats = AMDTP_OUT_PCM_FORMAT_BITS,
  313. .channels_min = UINT_MAX,
  314. .channels_max = 0,
  315. .buffer_bytes_max = 16 * 1024 * 1024,
  316. .period_bytes_min = 1,
  317. .period_bytes_max = UINT_MAX,
  318. .periods_min = 1,
  319. .periods_max = UINT_MAX,
  320. };
  321. struct dice *dice = substream->private_data;
  322. struct snd_pcm_runtime *runtime = substream->runtime;
  323. unsigned int i;
  324. int err;
  325. err = dice_try_lock(dice);
  326. if (err < 0)
  327. goto error;
  328. runtime->hw = hardware;
  329. for (i = 0; i < ARRAY_SIZE(dice_rates); ++i)
  330. if (dice->clock_caps & (1 << i))
  331. runtime->hw.rates |=
  332. snd_pcm_rate_to_rate_bit(dice_rates[i]);
  333. snd_pcm_limit_hw_rates(runtime);
  334. for (i = 0; i < 3; ++i)
  335. if (dice->rx_channels[i]) {
  336. runtime->hw.channels_min = min(runtime->hw.channels_min,
  337. dice->rx_channels[i]);
  338. runtime->hw.channels_max = max(runtime->hw.channels_max,
  339. dice->rx_channels[i]);
  340. }
  341. err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  342. dice_rate_constraint, dice,
  343. SNDRV_PCM_HW_PARAM_CHANNELS, -1);
  344. if (err < 0)
  345. goto err_lock;
  346. err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
  347. dice_channels_constraint, dice,
  348. SNDRV_PCM_HW_PARAM_RATE, -1);
  349. if (err < 0)
  350. goto err_lock;
  351. err = snd_pcm_hw_constraint_step(runtime, 0,
  352. SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 32);
  353. if (err < 0)
  354. goto err_lock;
  355. err = snd_pcm_hw_constraint_step(runtime, 0,
  356. SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 32);
  357. if (err < 0)
  358. goto err_lock;
  359. err = snd_pcm_hw_constraint_minmax(runtime,
  360. SNDRV_PCM_HW_PARAM_PERIOD_TIME,
  361. 5000, UINT_MAX);
  362. if (err < 0)
  363. goto err_lock;
  364. err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  365. if (err < 0)
  366. goto err_lock;
  367. return 0;
  368. err_lock:
  369. dice_unlock(dice);
  370. error:
  371. return err;
  372. }
  373. static int dice_close(struct snd_pcm_substream *substream)
  374. {
  375. struct dice *dice = substream->private_data;
  376. dice_unlock(dice);
  377. return 0;
  378. }
  379. static int dice_stream_start_packets(struct dice *dice)
  380. {
  381. int err;
  382. if (amdtp_out_stream_running(&dice->stream))
  383. return 0;
  384. err = amdtp_out_stream_start(&dice->stream, dice->resources.channel,
  385. fw_parent_device(dice->unit)->max_speed);
  386. if (err < 0)
  387. return err;
  388. err = dice_enable_set(dice);
  389. if (err < 0) {
  390. amdtp_out_stream_stop(&dice->stream);
  391. return err;
  392. }
  393. return 0;
  394. }
  395. static int dice_stream_start(struct dice *dice)
  396. {
  397. __be32 channel;
  398. int err;
  399. if (!dice->resources.allocated) {
  400. err = fw_iso_resources_allocate(&dice->resources,
  401. amdtp_out_stream_get_max_payload(&dice->stream),
  402. fw_parent_device(dice->unit)->max_speed);
  403. if (err < 0)
  404. goto error;
  405. channel = cpu_to_be32(dice->resources.channel);
  406. err = snd_fw_transaction(dice->unit,
  407. TCODE_WRITE_QUADLET_REQUEST,
  408. rx_address(dice, RX_ISOCHRONOUS),
  409. &channel, 4, 0);
  410. if (err < 0)
  411. goto err_resources;
  412. }
  413. err = dice_stream_start_packets(dice);
  414. if (err < 0)
  415. goto err_rx_channel;
  416. return 0;
  417. err_rx_channel:
  418. channel = cpu_to_be32((u32)-1);
  419. snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
  420. rx_address(dice, RX_ISOCHRONOUS), &channel, 4, 0);
  421. err_resources:
  422. fw_iso_resources_free(&dice->resources);
  423. error:
  424. return err;
  425. }
  426. static void dice_stream_stop_packets(struct dice *dice)
  427. {
  428. if (amdtp_out_stream_running(&dice->stream)) {
  429. dice_enable_clear(dice);
  430. amdtp_out_stream_stop(&dice->stream);
  431. }
  432. }
  433. static void dice_stream_stop(struct dice *dice)
  434. {
  435. __be32 channel;
  436. dice_stream_stop_packets(dice);
  437. if (!dice->resources.allocated)
  438. return;
  439. channel = cpu_to_be32((u32)-1);
  440. snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
  441. rx_address(dice, RX_ISOCHRONOUS), &channel, 4, 0);
  442. fw_iso_resources_free(&dice->resources);
  443. }
  444. static int dice_change_rate(struct dice *dice, unsigned int clock_rate)
  445. {
  446. __be32 value;
  447. int err;
  448. INIT_COMPLETION(dice->clock_accepted);
  449. value = cpu_to_be32(clock_rate | CLOCK_SOURCE_ARX1);
  450. err = snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
  451. global_address(dice, GLOBAL_CLOCK_SELECT),
  452. &value, 4, 0);
  453. if (err < 0)
  454. return err;
  455. wait_for_completion_timeout(&dice->clock_accepted,
  456. msecs_to_jiffies(100));
  457. return 0;
  458. }
  459. static int dice_hw_params(struct snd_pcm_substream *substream,
  460. struct snd_pcm_hw_params *hw_params)
  461. {
  462. struct dice *dice = substream->private_data;
  463. unsigned int rate_index, mode;
  464. int err;
  465. mutex_lock(&dice->mutex);
  466. dice_stream_stop(dice);
  467. mutex_unlock(&dice->mutex);
  468. err = snd_pcm_lib_alloc_vmalloc_buffer(substream,
  469. params_buffer_bytes(hw_params));
  470. if (err < 0)
  471. return err;
  472. rate_index = rate_to_index(params_rate(hw_params));
  473. err = dice_change_rate(dice, rate_index << CLOCK_RATE_SHIFT);
  474. if (err < 0)
  475. return err;
  476. mode = rate_index_to_mode(rate_index);
  477. amdtp_out_stream_set_parameters(&dice->stream,
  478. params_rate(hw_params),
  479. params_channels(hw_params),
  480. dice->rx_midi_ports[mode]);
  481. amdtp_out_stream_set_pcm_format(&dice->stream,
  482. params_format(hw_params));
  483. return 0;
  484. }
  485. static int dice_hw_free(struct snd_pcm_substream *substream)
  486. {
  487. struct dice *dice = substream->private_data;
  488. mutex_lock(&dice->mutex);
  489. dice_stream_stop(dice);
  490. mutex_unlock(&dice->mutex);
  491. return snd_pcm_lib_free_vmalloc_buffer(substream);
  492. }
  493. static int dice_prepare(struct snd_pcm_substream *substream)
  494. {
  495. struct dice *dice = substream->private_data;
  496. int err;
  497. mutex_lock(&dice->mutex);
  498. if (amdtp_out_streaming_error(&dice->stream))
  499. dice_stream_stop_packets(dice);
  500. err = dice_stream_start(dice);
  501. if (err < 0) {
  502. mutex_unlock(&dice->mutex);
  503. return err;
  504. }
  505. mutex_unlock(&dice->mutex);
  506. amdtp_out_stream_pcm_prepare(&dice->stream);
  507. return 0;
  508. }
  509. static int dice_trigger(struct snd_pcm_substream *substream, int cmd)
  510. {
  511. struct dice *dice = substream->private_data;
  512. struct snd_pcm_substream *pcm;
  513. switch (cmd) {
  514. case SNDRV_PCM_TRIGGER_START:
  515. pcm = substream;
  516. break;
  517. case SNDRV_PCM_TRIGGER_STOP:
  518. pcm = NULL;
  519. break;
  520. default:
  521. return -EINVAL;
  522. }
  523. amdtp_out_stream_pcm_trigger(&dice->stream, pcm);
  524. return 0;
  525. }
  526. static snd_pcm_uframes_t dice_pointer(struct snd_pcm_substream *substream)
  527. {
  528. struct dice *dice = substream->private_data;
  529. return amdtp_out_stream_pcm_pointer(&dice->stream);
  530. }
  531. static int dice_create_pcm(struct dice *dice)
  532. {
  533. static struct snd_pcm_ops ops = {
  534. .open = dice_open,
  535. .close = dice_close,
  536. .ioctl = snd_pcm_lib_ioctl,
  537. .hw_params = dice_hw_params,
  538. .hw_free = dice_hw_free,
  539. .prepare = dice_prepare,
  540. .trigger = dice_trigger,
  541. .pointer = dice_pointer,
  542. .page = snd_pcm_lib_get_vmalloc_page,
  543. .mmap = snd_pcm_lib_mmap_vmalloc,
  544. };
  545. struct snd_pcm *pcm;
  546. int err;
  547. err = snd_pcm_new(dice->card, "DICE", 0, 1, 0, &pcm);
  548. if (err < 0)
  549. return err;
  550. pcm->private_data = dice;
  551. strcpy(pcm->name, dice->card->shortname);
  552. pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->ops = &ops;
  553. return 0;
  554. }
  555. static long dice_hwdep_read(struct snd_hwdep *hwdep, char __user *buf,
  556. long count, loff_t *offset)
  557. {
  558. struct dice *dice = hwdep->private_data;
  559. DEFINE_WAIT(wait);
  560. union snd_firewire_event event;
  561. spin_lock_irq(&dice->lock);
  562. while (!dice->dev_lock_changed && dice->notification_bits == 0) {
  563. prepare_to_wait(&dice->hwdep_wait, &wait, TASK_INTERRUPTIBLE);
  564. spin_unlock_irq(&dice->lock);
  565. schedule();
  566. finish_wait(&dice->hwdep_wait, &wait);
  567. if (signal_pending(current))
  568. return -ERESTARTSYS;
  569. spin_lock_irq(&dice->lock);
  570. }
  571. memset(&event, 0, sizeof(event));
  572. if (dice->dev_lock_changed) {
  573. event.lock_status.type = SNDRV_FIREWIRE_EVENT_LOCK_STATUS;
  574. event.lock_status.status = dice->dev_lock_count > 0;
  575. dice->dev_lock_changed = false;
  576. count = min(count, (long)sizeof(event.lock_status));
  577. } else {
  578. event.dice_notification.type = SNDRV_FIREWIRE_EVENT_DICE_NOTIFICATION;
  579. event.dice_notification.notification = dice->notification_bits;
  580. dice->notification_bits = 0;
  581. count = min(count, (long)sizeof(event.dice_notification));
  582. }
  583. spin_unlock_irq(&dice->lock);
  584. if (copy_to_user(buf, &event, count))
  585. return -EFAULT;
  586. return count;
  587. }
  588. static unsigned int dice_hwdep_poll(struct snd_hwdep *hwdep, struct file *file,
  589. poll_table *wait)
  590. {
  591. struct dice *dice = hwdep->private_data;
  592. unsigned int events;
  593. poll_wait(file, &dice->hwdep_wait, wait);
  594. spin_lock_irq(&dice->lock);
  595. if (dice->dev_lock_changed || dice->notification_bits != 0)
  596. events = POLLIN | POLLRDNORM;
  597. else
  598. events = 0;
  599. spin_unlock_irq(&dice->lock);
  600. return events;
  601. }
  602. static int dice_hwdep_get_info(struct dice *dice, void __user *arg)
  603. {
  604. struct fw_device *dev = fw_parent_device(dice->unit);
  605. struct snd_firewire_get_info info;
  606. memset(&info, 0, sizeof(info));
  607. info.type = SNDRV_FIREWIRE_TYPE_DICE;
  608. info.card = dev->card->index;
  609. *(__be32 *)&info.guid[0] = cpu_to_be32(dev->config_rom[3]);
  610. *(__be32 *)&info.guid[4] = cpu_to_be32(dev->config_rom[4]);
  611. strlcpy(info.device_name, dev_name(&dev->device),
  612. sizeof(info.device_name));
  613. if (copy_to_user(arg, &info, sizeof(info)))
  614. return -EFAULT;
  615. return 0;
  616. }
  617. static int dice_hwdep_lock(struct dice *dice)
  618. {
  619. int err;
  620. spin_lock_irq(&dice->lock);
  621. if (dice->dev_lock_count == 0) {
  622. dice->dev_lock_count = -1;
  623. err = 0;
  624. } else {
  625. err = -EBUSY;
  626. }
  627. spin_unlock_irq(&dice->lock);
  628. return err;
  629. }
  630. static int dice_hwdep_unlock(struct dice *dice)
  631. {
  632. int err;
  633. spin_lock_irq(&dice->lock);
  634. if (dice->dev_lock_count == -1) {
  635. dice->dev_lock_count = 0;
  636. err = 0;
  637. } else {
  638. err = -EBADFD;
  639. }
  640. spin_unlock_irq(&dice->lock);
  641. return err;
  642. }
  643. static int dice_hwdep_release(struct snd_hwdep *hwdep, struct file *file)
  644. {
  645. struct dice *dice = hwdep->private_data;
  646. spin_lock_irq(&dice->lock);
  647. if (dice->dev_lock_count == -1)
  648. dice->dev_lock_count = 0;
  649. spin_unlock_irq(&dice->lock);
  650. return 0;
  651. }
  652. static int dice_hwdep_ioctl(struct snd_hwdep *hwdep, struct file *file,
  653. unsigned int cmd, unsigned long arg)
  654. {
  655. struct dice *dice = hwdep->private_data;
  656. switch (cmd) {
  657. case SNDRV_FIREWIRE_IOCTL_GET_INFO:
  658. return dice_hwdep_get_info(dice, (void __user *)arg);
  659. case SNDRV_FIREWIRE_IOCTL_LOCK:
  660. return dice_hwdep_lock(dice);
  661. case SNDRV_FIREWIRE_IOCTL_UNLOCK:
  662. return dice_hwdep_unlock(dice);
  663. default:
  664. return -ENOIOCTLCMD;
  665. }
  666. }
  667. #ifdef CONFIG_COMPAT
  668. static int dice_hwdep_compat_ioctl(struct snd_hwdep *hwdep, struct file *file,
  669. unsigned int cmd, unsigned long arg)
  670. {
  671. return dice_hwdep_ioctl(hwdep, file, cmd,
  672. (unsigned long)compat_ptr(arg));
  673. }
  674. #else
  675. #define dice_hwdep_compat_ioctl NULL
  676. #endif
  677. static int dice_create_hwdep(struct dice *dice)
  678. {
  679. static const struct snd_hwdep_ops ops = {
  680. .read = dice_hwdep_read,
  681. .release = dice_hwdep_release,
  682. .poll = dice_hwdep_poll,
  683. .ioctl = dice_hwdep_ioctl,
  684. .ioctl_compat = dice_hwdep_compat_ioctl,
  685. };
  686. struct snd_hwdep *hwdep;
  687. int err;
  688. err = snd_hwdep_new(dice->card, "DICE", 0, &hwdep);
  689. if (err < 0)
  690. return err;
  691. strcpy(hwdep->name, "DICE");
  692. hwdep->iface = SNDRV_HWDEP_IFACE_FW_DICE;
  693. hwdep->ops = ops;
  694. hwdep->private_data = dice;
  695. hwdep->exclusive = true;
  696. return 0;
  697. }
  698. static void dice_card_free(struct snd_card *card)
  699. {
  700. struct dice *dice = card->private_data;
  701. amdtp_out_stream_destroy(&dice->stream);
  702. fw_core_remove_address_handler(&dice->notification_handler);
  703. mutex_destroy(&dice->mutex);
  704. }
  705. #define DICE_CATEGORY_ID 0x04
  706. static int dice_interface_check(struct fw_unit *unit)
  707. {
  708. static const int min_values[10] = {
  709. 10, 0x64 / 4,
  710. 10, 0x18 / 4,
  711. 10, 0x18 / 4,
  712. 0, 0,
  713. 0, 0,
  714. };
  715. struct fw_device *device = fw_parent_device(unit);
  716. struct fw_csr_iterator it;
  717. int key, value, vendor = -1, model = -1, err;
  718. unsigned int i;
  719. __be32 pointers[ARRAY_SIZE(min_values)];
  720. __be32 version;
  721. /*
  722. * Check that GUID and unit directory are constructed according to DICE
  723. * rules, i.e., that the specifier ID is the GUID's OUI, and that the
  724. * GUID chip ID consists of the 8-bit DICE category ID, the 10-bit
  725. * product ID, and a 22-bit serial number.
  726. */
  727. fw_csr_iterator_init(&it, unit->directory);
  728. while (fw_csr_iterator_next(&it, &key, &value)) {
  729. switch (key) {
  730. case CSR_SPECIFIER_ID:
  731. vendor = value;
  732. break;
  733. case CSR_MODEL:
  734. model = value;
  735. break;
  736. }
  737. }
  738. if (device->config_rom[3] != ((vendor << 8) | DICE_CATEGORY_ID) ||
  739. device->config_rom[4] >> 22 != model)
  740. return -ENODEV;
  741. /*
  742. * Check that the sub address spaces exist and are located inside the
  743. * private address space. The minimum values are chosen so that all
  744. * minimally required registers are included.
  745. */
  746. err = snd_fw_transaction(unit, TCODE_READ_BLOCK_REQUEST,
  747. DICE_PRIVATE_SPACE,
  748. pointers, sizeof(pointers), 0);
  749. if (err < 0)
  750. return -ENODEV;
  751. for (i = 0; i < ARRAY_SIZE(pointers); ++i) {
  752. value = be32_to_cpu(pointers[i]);
  753. if (value < min_values[i] || value >= 0x40000)
  754. return -ENODEV;
  755. }
  756. /*
  757. * Check that the implemented DICE driver specification major version
  758. * number matches.
  759. */
  760. err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
  761. DICE_PRIVATE_SPACE +
  762. be32_to_cpu(pointers[0]) * 4 + GLOBAL_VERSION,
  763. &version, 4, 0);
  764. if (err < 0)
  765. return -ENODEV;
  766. if ((version & cpu_to_be32(0xff000000)) != cpu_to_be32(0x01000000)) {
  767. dev_err(&unit->device,
  768. "unknown DICE version: 0x%08x\n", be32_to_cpu(version));
  769. return -ENODEV;
  770. }
  771. return 0;
  772. }
  773. static int highest_supported_mode_rate(struct dice *dice, unsigned int mode)
  774. {
  775. int i;
  776. for (i = ARRAY_SIZE(dice_rates) - 1; i >= 0; --i)
  777. if ((dice->clock_caps & (1 << i)) &&
  778. rate_index_to_mode(i) == mode)
  779. return i;
  780. return -1;
  781. }
  782. static int dice_read_mode_params(struct dice *dice, unsigned int mode)
  783. {
  784. __be32 values[2];
  785. int rate_index, err;
  786. rate_index = highest_supported_mode_rate(dice, mode);
  787. if (rate_index < 0) {
  788. dice->rx_channels[mode] = 0;
  789. dice->rx_midi_ports[mode] = 0;
  790. return 0;
  791. }
  792. err = dice_change_rate(dice, rate_index << CLOCK_RATE_SHIFT);
  793. if (err < 0)
  794. return err;
  795. err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
  796. rx_address(dice, RX_NUMBER_AUDIO),
  797. values, 2 * 4, 0);
  798. if (err < 0)
  799. return err;
  800. dice->rx_channels[mode] = be32_to_cpu(values[0]);
  801. dice->rx_midi_ports[mode] = be32_to_cpu(values[1]);
  802. return 0;
  803. }
  804. static int dice_read_params(struct dice *dice)
  805. {
  806. __be32 pointers[6];
  807. __be32 value;
  808. int mode, err;
  809. err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
  810. DICE_PRIVATE_SPACE,
  811. pointers, sizeof(pointers), 0);
  812. if (err < 0)
  813. return err;
  814. dice->global_offset = be32_to_cpu(pointers[0]) * 4;
  815. dice->rx_offset = be32_to_cpu(pointers[4]) * 4;
  816. /* some very old firmwares don't tell about their clock support */
  817. if (be32_to_cpu(pointers[1]) * 4 >= GLOBAL_CLOCK_CAPABILITIES + 4) {
  818. err = snd_fw_transaction(
  819. dice->unit, TCODE_READ_QUADLET_REQUEST,
  820. global_address(dice, GLOBAL_CLOCK_CAPABILITIES),
  821. &value, 4, 0);
  822. if (err < 0)
  823. return err;
  824. dice->clock_caps = be32_to_cpu(value);
  825. } else {
  826. /* this should be supported by any device */
  827. dice->clock_caps = CLOCK_CAP_RATE_44100 |
  828. CLOCK_CAP_RATE_48000 |
  829. CLOCK_CAP_SOURCE_ARX1 |
  830. CLOCK_CAP_SOURCE_INTERNAL;
  831. }
  832. for (mode = 2; mode >= 0; --mode) {
  833. err = dice_read_mode_params(dice, mode);
  834. if (err < 0)
  835. return err;
  836. }
  837. return 0;
  838. }
  839. static void dice_card_strings(struct dice *dice)
  840. {
  841. struct snd_card *card = dice->card;
  842. struct fw_device *dev = fw_parent_device(dice->unit);
  843. char vendor[32], model[32];
  844. unsigned int i;
  845. int err;
  846. strcpy(card->driver, "DICE");
  847. strcpy(card->shortname, "DICE");
  848. BUILD_BUG_ON(NICK_NAME_SIZE < sizeof(card->shortname));
  849. err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
  850. global_address(dice, GLOBAL_NICK_NAME),
  851. card->shortname, sizeof(card->shortname), 0);
  852. if (err >= 0) {
  853. /* DICE strings are returned in "always-wrong" endianness */
  854. BUILD_BUG_ON(sizeof(card->shortname) % 4 != 0);
  855. for (i = 0; i < sizeof(card->shortname); i += 4)
  856. swab32s((u32 *)&card->shortname[i]);
  857. card->shortname[sizeof(card->shortname) - 1] = '\0';
  858. }
  859. strcpy(vendor, "?");
  860. fw_csr_string(dev->config_rom + 5, CSR_VENDOR, vendor, sizeof(vendor));
  861. strcpy(model, "?");
  862. fw_csr_string(dice->unit->directory, CSR_MODEL, model, sizeof(model));
  863. snprintf(card->longname, sizeof(card->longname),
  864. "%s %s (serial %u) at %s, S%d",
  865. vendor, model, dev->config_rom[4] & 0x3fffff,
  866. dev_name(&dice->unit->device), 100 << dev->max_speed);
  867. strcpy(card->mixername, "DICE");
  868. }
  869. static int dice_probe(struct fw_unit *unit, const struct ieee1394_device_id *id)
  870. {
  871. struct snd_card *card;
  872. struct dice *dice;
  873. __be32 clock_sel;
  874. int err;
  875. err = dice_interface_check(unit);
  876. if (err < 0)
  877. return err;
  878. err = snd_card_create(-1, NULL, THIS_MODULE, sizeof(*dice), &card);
  879. if (err < 0)
  880. return err;
  881. snd_card_set_dev(card, &unit->device);
  882. dice = card->private_data;
  883. dice->card = card;
  884. spin_lock_init(&dice->lock);
  885. mutex_init(&dice->mutex);
  886. dice->unit = unit;
  887. init_completion(&dice->clock_accepted);
  888. init_waitqueue_head(&dice->hwdep_wait);
  889. dice->notification_handler.length = 4;
  890. dice->notification_handler.address_callback = dice_notification;
  891. dice->notification_handler.callback_data = dice;
  892. err = fw_core_add_address_handler(&dice->notification_handler,
  893. &fw_high_memory_region);
  894. if (err < 0)
  895. goto err_mutex;
  896. err = dice_owner_set(dice);
  897. if (err < 0)
  898. goto err_notification_handler;
  899. err = dice_read_params(dice);
  900. if (err < 0)
  901. goto err_owner;
  902. err = fw_iso_resources_init(&dice->resources, unit);
  903. if (err < 0)
  904. goto err_owner;
  905. dice->resources.channels_mask = 0x00000000ffffffffuLL;
  906. err = amdtp_out_stream_init(&dice->stream, unit,
  907. CIP_BLOCKING | CIP_HI_DUALWIRE);
  908. if (err < 0)
  909. goto err_resources;
  910. card->private_free = dice_card_free;
  911. dice_card_strings(dice);
  912. err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
  913. global_address(dice, GLOBAL_CLOCK_SELECT),
  914. &clock_sel, 4, 0);
  915. if (err < 0)
  916. goto error;
  917. clock_sel &= cpu_to_be32(~CLOCK_SOURCE_MASK);
  918. clock_sel |= cpu_to_be32(CLOCK_SOURCE_ARX1);
  919. err = snd_fw_transaction(unit, TCODE_WRITE_QUADLET_REQUEST,
  920. global_address(dice, GLOBAL_CLOCK_SELECT),
  921. &clock_sel, 4, 0);
  922. if (err < 0)
  923. goto error;
  924. err = dice_create_pcm(dice);
  925. if (err < 0)
  926. goto error;
  927. err = dice_create_hwdep(dice);
  928. if (err < 0)
  929. goto error;
  930. err = snd_card_register(card);
  931. if (err < 0)
  932. goto error;
  933. dev_set_drvdata(&unit->device, dice);
  934. return 0;
  935. err_resources:
  936. fw_iso_resources_destroy(&dice->resources);
  937. err_owner:
  938. dice_owner_clear(dice);
  939. err_notification_handler:
  940. fw_core_remove_address_handler(&dice->notification_handler);
  941. err_mutex:
  942. mutex_destroy(&dice->mutex);
  943. error:
  944. snd_card_free(card);
  945. return err;
  946. }
  947. static void dice_remove(struct fw_unit *unit)
  948. {
  949. struct dice *dice = dev_get_drvdata(&unit->device);
  950. amdtp_out_stream_pcm_abort(&dice->stream);
  951. snd_card_disconnect(dice->card);
  952. mutex_lock(&dice->mutex);
  953. dice_stream_stop(dice);
  954. dice_owner_clear(dice);
  955. mutex_unlock(&dice->mutex);
  956. snd_card_free_when_closed(dice->card);
  957. }
  958. static void dice_bus_reset(struct fw_unit *unit)
  959. {
  960. struct dice *dice = dev_get_drvdata(&unit->device);
  961. /*
  962. * On a bus reset, the DICE firmware disables streaming and then goes
  963. * off contemplating its own navel for hundreds of milliseconds before
  964. * it can react to any of our attempts to reenable streaming. This
  965. * means that we lose synchronization anyway, so we force our streams
  966. * to stop so that the application can restart them in an orderly
  967. * manner.
  968. */
  969. amdtp_out_stream_pcm_abort(&dice->stream);
  970. mutex_lock(&dice->mutex);
  971. dice->global_enabled = false;
  972. dice_stream_stop_packets(dice);
  973. dice_owner_update(dice);
  974. fw_iso_resources_update(&dice->resources);
  975. mutex_unlock(&dice->mutex);
  976. }
  977. #define DICE_INTERFACE 0x000001
  978. static const struct ieee1394_device_id dice_id_table[] = {
  979. {
  980. .match_flags = IEEE1394_MATCH_VERSION,
  981. .version = DICE_INTERFACE,
  982. },
  983. { }
  984. };
  985. MODULE_DEVICE_TABLE(ieee1394, dice_id_table);
  986. static struct fw_driver dice_driver = {
  987. .driver = {
  988. .owner = THIS_MODULE,
  989. .name = KBUILD_MODNAME,
  990. .bus = &fw_bus_type,
  991. },
  992. .probe = dice_probe,
  993. .update = dice_bus_reset,
  994. .remove = dice_remove,
  995. .id_table = dice_id_table,
  996. };
  997. static int __init alsa_dice_init(void)
  998. {
  999. return driver_register(&dice_driver.driver);
  1000. }
  1001. static void __exit alsa_dice_exit(void)
  1002. {
  1003. driver_unregister(&dice_driver.driver);
  1004. }
  1005. module_init(alsa_dice_init);
  1006. module_exit(alsa_dice_exit);