entry-macro.S 2.3 KB

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  1. /* arch/arm/mach-exynos4/include/mach/entry-macro.S
  2. *
  3. * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S
  4. *
  5. * Low-level IRQ helper macros for EXYNOS4 platforms
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <mach/hardware.h>
  12. #include <mach/map.h>
  13. #include <asm/hardware/gic.h>
  14. .macro disable_fiq
  15. .endm
  16. .macro get_irqnr_preamble, base, tmp
  17. mov \tmp, #0
  18. mrc p15, 0, \base, c0, c0, 5
  19. and \base, \base, #3
  20. cmp \base, #0
  21. beq 1f
  22. ldr \tmp, =gic_bank_offset
  23. ldr \tmp, [\tmp]
  24. cmp \base, #1
  25. beq 1f
  26. cmp \base, #2
  27. addeq \tmp, \tmp, \tmp
  28. addne \tmp, \tmp, \tmp, LSL #1
  29. 1: ldr \base, =gic_cpu_base_addr
  30. ldr \base, [\base]
  31. add \base, \base, \tmp
  32. .endm
  33. .macro arch_ret_to_user, tmp1, tmp2
  34. .endm
  35. /*
  36. * The interrupt numbering scheme is defined in the
  37. * interrupt controller spec. To wit:
  38. *
  39. * Interrupts 0-15 are IPI
  40. * 16-28 are reserved
  41. * 29-31 are local. We allow 30 to be used for the watchdog.
  42. * 32-1020 are global
  43. * 1021-1022 are reserved
  44. * 1023 is "spurious" (no interrupt)
  45. *
  46. * For now, we ignore all local interrupts so only return an interrupt if it's
  47. * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
  48. *
  49. * A simple read from the controller will tell us the number of the highest
  50. * priority enabled interrupt. We then just need to check whether it is in the
  51. * valid range for an IRQ (30-1020 inclusive).
  52. */
  53. .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
  54. ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
  55. ldr \tmp, =1021
  56. bic \irqnr, \irqstat, #0x1c00
  57. cmp \irqnr, #15
  58. cmpcc \irqnr, \irqnr
  59. cmpne \irqnr, \tmp
  60. cmpcs \irqnr, \irqnr
  61. .endm
  62. /* We assume that irqstat (the raw value of the IRQ acknowledge
  63. * register) is preserved from the macro above.
  64. * If there is an IPI, we immediately signal end of interrupt on the
  65. * controller, since this requires the original irqstat value which
  66. * we won't easily be able to recreate later.
  67. */
  68. .macro test_for_ipi, irqnr, irqstat, base, tmp
  69. bic \irqnr, \irqstat, #0x1c00
  70. cmp \irqnr, #16
  71. strcc \irqstat, [\base, #GIC_CPU_EOI]
  72. cmpcs \irqnr, \irqnr
  73. .endm