devices.c 22 KB

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  1. #include <linux/module.h>
  2. #include <linux/kernel.h>
  3. #include <linux/init.h>
  4. #include <linux/platform_device.h>
  5. #include <linux/dma-mapping.h>
  6. #include <linux/spi/pxa2xx_spi.h>
  7. #include <linux/i2c/pxa-i2c.h>
  8. #include <asm/pmu.h>
  9. #include <mach/udc.h>
  10. #include <mach/pxa3xx-u2d.h>
  11. #include <mach/pxafb.h>
  12. #include <mach/mmc.h>
  13. #include <mach/irda.h>
  14. #include <mach/irqs.h>
  15. #include <mach/ohci.h>
  16. #include <plat/pxa27x_keypad.h>
  17. #include <mach/camera.h>
  18. #include <mach/audio.h>
  19. #include <mach/hardware.h>
  20. #include <plat/pxa3xx_nand.h>
  21. #include "devices.h"
  22. #include "generic.h"
  23. void __init pxa_register_device(struct platform_device *dev, void *data)
  24. {
  25. int ret;
  26. dev->dev.platform_data = data;
  27. ret = platform_device_register(dev);
  28. if (ret)
  29. dev_err(&dev->dev, "unable to register device: %d\n", ret);
  30. }
  31. static struct resource pxa_resource_pmu = {
  32. .start = IRQ_PMU,
  33. .end = IRQ_PMU,
  34. .flags = IORESOURCE_IRQ,
  35. };
  36. struct platform_device pxa_device_pmu = {
  37. .name = "arm-pmu",
  38. .id = ARM_PMU_DEVICE_CPU,
  39. .resource = &pxa_resource_pmu,
  40. .num_resources = 1,
  41. };
  42. static struct resource pxamci_resources[] = {
  43. [0] = {
  44. .start = 0x41100000,
  45. .end = 0x41100fff,
  46. .flags = IORESOURCE_MEM,
  47. },
  48. [1] = {
  49. .start = IRQ_MMC,
  50. .end = IRQ_MMC,
  51. .flags = IORESOURCE_IRQ,
  52. },
  53. [2] = {
  54. .start = 21,
  55. .end = 21,
  56. .flags = IORESOURCE_DMA,
  57. },
  58. [3] = {
  59. .start = 22,
  60. .end = 22,
  61. .flags = IORESOURCE_DMA,
  62. },
  63. };
  64. static u64 pxamci_dmamask = 0xffffffffUL;
  65. struct platform_device pxa_device_mci = {
  66. .name = "pxa2xx-mci",
  67. .id = 0,
  68. .dev = {
  69. .dma_mask = &pxamci_dmamask,
  70. .coherent_dma_mask = 0xffffffff,
  71. },
  72. .num_resources = ARRAY_SIZE(pxamci_resources),
  73. .resource = pxamci_resources,
  74. };
  75. void __init pxa_set_mci_info(struct pxamci_platform_data *info)
  76. {
  77. pxa_register_device(&pxa_device_mci, info);
  78. }
  79. static struct pxa2xx_udc_mach_info pxa_udc_info = {
  80. .gpio_pullup = -1,
  81. };
  82. void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
  83. {
  84. memcpy(&pxa_udc_info, info, sizeof *info);
  85. }
  86. static struct resource pxa2xx_udc_resources[] = {
  87. [0] = {
  88. .start = 0x40600000,
  89. .end = 0x4060ffff,
  90. .flags = IORESOURCE_MEM,
  91. },
  92. [1] = {
  93. .start = IRQ_USB,
  94. .end = IRQ_USB,
  95. .flags = IORESOURCE_IRQ,
  96. },
  97. };
  98. static u64 udc_dma_mask = ~(u32)0;
  99. struct platform_device pxa25x_device_udc = {
  100. .name = "pxa25x-udc",
  101. .id = -1,
  102. .resource = pxa2xx_udc_resources,
  103. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  104. .dev = {
  105. .platform_data = &pxa_udc_info,
  106. .dma_mask = &udc_dma_mask,
  107. }
  108. };
  109. struct platform_device pxa27x_device_udc = {
  110. .name = "pxa27x-udc",
  111. .id = -1,
  112. .resource = pxa2xx_udc_resources,
  113. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  114. .dev = {
  115. .platform_data = &pxa_udc_info,
  116. .dma_mask = &udc_dma_mask,
  117. }
  118. };
  119. #ifdef CONFIG_PXA3xx
  120. static struct resource pxa3xx_u2d_resources[] = {
  121. [0] = {
  122. .start = 0x54100000,
  123. .end = 0x54100fff,
  124. .flags = IORESOURCE_MEM,
  125. },
  126. [1] = {
  127. .start = IRQ_USB2,
  128. .end = IRQ_USB2,
  129. .flags = IORESOURCE_IRQ,
  130. },
  131. };
  132. struct platform_device pxa3xx_device_u2d = {
  133. .name = "pxa3xx-u2d",
  134. .id = -1,
  135. .resource = pxa3xx_u2d_resources,
  136. .num_resources = ARRAY_SIZE(pxa3xx_u2d_resources),
  137. };
  138. void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
  139. {
  140. pxa_register_device(&pxa3xx_device_u2d, info);
  141. }
  142. #endif /* CONFIG_PXA3xx */
  143. static struct resource pxafb_resources[] = {
  144. [0] = {
  145. .start = 0x44000000,
  146. .end = 0x4400ffff,
  147. .flags = IORESOURCE_MEM,
  148. },
  149. [1] = {
  150. .start = IRQ_LCD,
  151. .end = IRQ_LCD,
  152. .flags = IORESOURCE_IRQ,
  153. },
  154. };
  155. static u64 fb_dma_mask = ~(u64)0;
  156. struct platform_device pxa_device_fb = {
  157. .name = "pxa2xx-fb",
  158. .id = -1,
  159. .dev = {
  160. .dma_mask = &fb_dma_mask,
  161. .coherent_dma_mask = 0xffffffff,
  162. },
  163. .num_resources = ARRAY_SIZE(pxafb_resources),
  164. .resource = pxafb_resources,
  165. };
  166. void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info)
  167. {
  168. pxa_device_fb.dev.parent = parent;
  169. pxa_register_device(&pxa_device_fb, info);
  170. }
  171. static struct resource pxa_resource_ffuart[] = {
  172. {
  173. .start = 0x40100000,
  174. .end = 0x40100023,
  175. .flags = IORESOURCE_MEM,
  176. }, {
  177. .start = IRQ_FFUART,
  178. .end = IRQ_FFUART,
  179. .flags = IORESOURCE_IRQ,
  180. }
  181. };
  182. struct platform_device pxa_device_ffuart = {
  183. .name = "pxa2xx-uart",
  184. .id = 0,
  185. .resource = pxa_resource_ffuart,
  186. .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
  187. };
  188. void __init pxa_set_ffuart_info(void *info)
  189. {
  190. pxa_register_device(&pxa_device_ffuart, info);
  191. }
  192. static struct resource pxa_resource_btuart[] = {
  193. {
  194. .start = 0x40200000,
  195. .end = 0x40200023,
  196. .flags = IORESOURCE_MEM,
  197. }, {
  198. .start = IRQ_BTUART,
  199. .end = IRQ_BTUART,
  200. .flags = IORESOURCE_IRQ,
  201. }
  202. };
  203. struct platform_device pxa_device_btuart = {
  204. .name = "pxa2xx-uart",
  205. .id = 1,
  206. .resource = pxa_resource_btuart,
  207. .num_resources = ARRAY_SIZE(pxa_resource_btuart),
  208. };
  209. void __init pxa_set_btuart_info(void *info)
  210. {
  211. pxa_register_device(&pxa_device_btuart, info);
  212. }
  213. static struct resource pxa_resource_stuart[] = {
  214. {
  215. .start = 0x40700000,
  216. .end = 0x40700023,
  217. .flags = IORESOURCE_MEM,
  218. }, {
  219. .start = IRQ_STUART,
  220. .end = IRQ_STUART,
  221. .flags = IORESOURCE_IRQ,
  222. }
  223. };
  224. struct platform_device pxa_device_stuart = {
  225. .name = "pxa2xx-uart",
  226. .id = 2,
  227. .resource = pxa_resource_stuart,
  228. .num_resources = ARRAY_SIZE(pxa_resource_stuart),
  229. };
  230. void __init pxa_set_stuart_info(void *info)
  231. {
  232. pxa_register_device(&pxa_device_stuart, info);
  233. }
  234. static struct resource pxa_resource_hwuart[] = {
  235. {
  236. .start = 0x41600000,
  237. .end = 0x4160002F,
  238. .flags = IORESOURCE_MEM,
  239. }, {
  240. .start = IRQ_HWUART,
  241. .end = IRQ_HWUART,
  242. .flags = IORESOURCE_IRQ,
  243. }
  244. };
  245. struct platform_device pxa_device_hwuart = {
  246. .name = "pxa2xx-uart",
  247. .id = 3,
  248. .resource = pxa_resource_hwuart,
  249. .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
  250. };
  251. void __init pxa_set_hwuart_info(void *info)
  252. {
  253. if (cpu_is_pxa255())
  254. pxa_register_device(&pxa_device_hwuart, info);
  255. else
  256. pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
  257. }
  258. static struct resource pxai2c_resources[] = {
  259. {
  260. .start = 0x40301680,
  261. .end = 0x403016a3,
  262. .flags = IORESOURCE_MEM,
  263. }, {
  264. .start = IRQ_I2C,
  265. .end = IRQ_I2C,
  266. .flags = IORESOURCE_IRQ,
  267. },
  268. };
  269. struct platform_device pxa_device_i2c = {
  270. .name = "pxa2xx-i2c",
  271. .id = 0,
  272. .resource = pxai2c_resources,
  273. .num_resources = ARRAY_SIZE(pxai2c_resources),
  274. };
  275. void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
  276. {
  277. pxa_register_device(&pxa_device_i2c, info);
  278. }
  279. #ifdef CONFIG_PXA27x
  280. static struct resource pxa27x_resources_i2c_power[] = {
  281. {
  282. .start = 0x40f00180,
  283. .end = 0x40f001a3,
  284. .flags = IORESOURCE_MEM,
  285. }, {
  286. .start = IRQ_PWRI2C,
  287. .end = IRQ_PWRI2C,
  288. .flags = IORESOURCE_IRQ,
  289. },
  290. };
  291. struct platform_device pxa27x_device_i2c_power = {
  292. .name = "pxa2xx-i2c",
  293. .id = 1,
  294. .resource = pxa27x_resources_i2c_power,
  295. .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
  296. };
  297. #endif
  298. static struct resource pxai2s_resources[] = {
  299. {
  300. .start = 0x40400000,
  301. .end = 0x40400083,
  302. .flags = IORESOURCE_MEM,
  303. }, {
  304. .start = IRQ_I2S,
  305. .end = IRQ_I2S,
  306. .flags = IORESOURCE_IRQ,
  307. },
  308. };
  309. struct platform_device pxa_device_i2s = {
  310. .name = "pxa2xx-i2s",
  311. .id = -1,
  312. .resource = pxai2s_resources,
  313. .num_resources = ARRAY_SIZE(pxai2s_resources),
  314. };
  315. struct platform_device pxa_device_asoc_ssp1 = {
  316. .name = "pxa-ssp-dai",
  317. .id = 0,
  318. };
  319. struct platform_device pxa_device_asoc_ssp2= {
  320. .name = "pxa-ssp-dai",
  321. .id = 1,
  322. };
  323. struct platform_device pxa_device_asoc_ssp3 = {
  324. .name = "pxa-ssp-dai",
  325. .id = 2,
  326. };
  327. struct platform_device pxa_device_asoc_ssp4 = {
  328. .name = "pxa-ssp-dai",
  329. .id = 3,
  330. };
  331. struct platform_device pxa_device_asoc_platform = {
  332. .name = "pxa-pcm-audio",
  333. .id = -1,
  334. };
  335. static u64 pxaficp_dmamask = ~(u32)0;
  336. struct platform_device pxa_device_ficp = {
  337. .name = "pxa2xx-ir",
  338. .id = -1,
  339. .dev = {
  340. .dma_mask = &pxaficp_dmamask,
  341. .coherent_dma_mask = 0xffffffff,
  342. },
  343. };
  344. void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
  345. {
  346. pxa_register_device(&pxa_device_ficp, info);
  347. }
  348. static struct resource pxa_rtc_resources[] = {
  349. [0] = {
  350. .start = 0x40900000,
  351. .end = 0x40900000 + 0x3b,
  352. .flags = IORESOURCE_MEM,
  353. },
  354. [1] = {
  355. .start = IRQ_RTC1Hz,
  356. .end = IRQ_RTC1Hz,
  357. .flags = IORESOURCE_IRQ,
  358. },
  359. [2] = {
  360. .start = IRQ_RTCAlrm,
  361. .end = IRQ_RTCAlrm,
  362. .flags = IORESOURCE_IRQ,
  363. },
  364. };
  365. static struct resource sa1100_rtc_resources[] = {
  366. [0] = {
  367. .start = 0x40900000,
  368. .end = 0x409000ff,
  369. .flags = IORESOURCE_MEM,
  370. },
  371. [1] = {
  372. .start = IRQ_RTC1Hz,
  373. .end = IRQ_RTC1Hz,
  374. .flags = IORESOURCE_IRQ,
  375. },
  376. [2] = {
  377. .start = IRQ_RTCAlrm,
  378. .end = IRQ_RTCAlrm,
  379. .flags = IORESOURCE_IRQ,
  380. },
  381. };
  382. struct platform_device sa1100_device_rtc = {
  383. .name = "sa1100-rtc",
  384. .id = -1,
  385. .num_resources = ARRAY_SIZE(sa1100_rtc_resources),
  386. .resource = sa1100_rtc_resources,
  387. };
  388. struct platform_device pxa_device_rtc = {
  389. .name = "pxa-rtc",
  390. .id = -1,
  391. .num_resources = ARRAY_SIZE(pxa_rtc_resources),
  392. .resource = pxa_rtc_resources,
  393. };
  394. static struct resource pxa_ac97_resources[] = {
  395. [0] = {
  396. .start = 0x40500000,
  397. .end = 0x40500000 + 0xfff,
  398. .flags = IORESOURCE_MEM,
  399. },
  400. [1] = {
  401. .start = IRQ_AC97,
  402. .end = IRQ_AC97,
  403. .flags = IORESOURCE_IRQ,
  404. },
  405. };
  406. static u64 pxa_ac97_dmamask = 0xffffffffUL;
  407. struct platform_device pxa_device_ac97 = {
  408. .name = "pxa2xx-ac97",
  409. .id = -1,
  410. .dev = {
  411. .dma_mask = &pxa_ac97_dmamask,
  412. .coherent_dma_mask = 0xffffffff,
  413. },
  414. .num_resources = ARRAY_SIZE(pxa_ac97_resources),
  415. .resource = pxa_ac97_resources,
  416. };
  417. void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
  418. {
  419. pxa_register_device(&pxa_device_ac97, ops);
  420. }
  421. #ifdef CONFIG_PXA25x
  422. static struct resource pxa25x_resource_pwm0[] = {
  423. [0] = {
  424. .start = 0x40b00000,
  425. .end = 0x40b0000f,
  426. .flags = IORESOURCE_MEM,
  427. },
  428. };
  429. struct platform_device pxa25x_device_pwm0 = {
  430. .name = "pxa25x-pwm",
  431. .id = 0,
  432. .resource = pxa25x_resource_pwm0,
  433. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
  434. };
  435. static struct resource pxa25x_resource_pwm1[] = {
  436. [0] = {
  437. .start = 0x40c00000,
  438. .end = 0x40c0000f,
  439. .flags = IORESOURCE_MEM,
  440. },
  441. };
  442. struct platform_device pxa25x_device_pwm1 = {
  443. .name = "pxa25x-pwm",
  444. .id = 1,
  445. .resource = pxa25x_resource_pwm1,
  446. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
  447. };
  448. static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
  449. static struct resource pxa25x_resource_ssp[] = {
  450. [0] = {
  451. .start = 0x41000000,
  452. .end = 0x4100001f,
  453. .flags = IORESOURCE_MEM,
  454. },
  455. [1] = {
  456. .start = IRQ_SSP,
  457. .end = IRQ_SSP,
  458. .flags = IORESOURCE_IRQ,
  459. },
  460. [2] = {
  461. /* DRCMR for RX */
  462. .start = 13,
  463. .end = 13,
  464. .flags = IORESOURCE_DMA,
  465. },
  466. [3] = {
  467. /* DRCMR for TX */
  468. .start = 14,
  469. .end = 14,
  470. .flags = IORESOURCE_DMA,
  471. },
  472. };
  473. struct platform_device pxa25x_device_ssp = {
  474. .name = "pxa25x-ssp",
  475. .id = 0,
  476. .dev = {
  477. .dma_mask = &pxa25x_ssp_dma_mask,
  478. .coherent_dma_mask = DMA_BIT_MASK(32),
  479. },
  480. .resource = pxa25x_resource_ssp,
  481. .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
  482. };
  483. static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
  484. static struct resource pxa25x_resource_nssp[] = {
  485. [0] = {
  486. .start = 0x41400000,
  487. .end = 0x4140002f,
  488. .flags = IORESOURCE_MEM,
  489. },
  490. [1] = {
  491. .start = IRQ_NSSP,
  492. .end = IRQ_NSSP,
  493. .flags = IORESOURCE_IRQ,
  494. },
  495. [2] = {
  496. /* DRCMR for RX */
  497. .start = 15,
  498. .end = 15,
  499. .flags = IORESOURCE_DMA,
  500. },
  501. [3] = {
  502. /* DRCMR for TX */
  503. .start = 16,
  504. .end = 16,
  505. .flags = IORESOURCE_DMA,
  506. },
  507. };
  508. struct platform_device pxa25x_device_nssp = {
  509. .name = "pxa25x-nssp",
  510. .id = 1,
  511. .dev = {
  512. .dma_mask = &pxa25x_nssp_dma_mask,
  513. .coherent_dma_mask = DMA_BIT_MASK(32),
  514. },
  515. .resource = pxa25x_resource_nssp,
  516. .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
  517. };
  518. static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
  519. static struct resource pxa25x_resource_assp[] = {
  520. [0] = {
  521. .start = 0x41500000,
  522. .end = 0x4150002f,
  523. .flags = IORESOURCE_MEM,
  524. },
  525. [1] = {
  526. .start = IRQ_ASSP,
  527. .end = IRQ_ASSP,
  528. .flags = IORESOURCE_IRQ,
  529. },
  530. [2] = {
  531. /* DRCMR for RX */
  532. .start = 23,
  533. .end = 23,
  534. .flags = IORESOURCE_DMA,
  535. },
  536. [3] = {
  537. /* DRCMR for TX */
  538. .start = 24,
  539. .end = 24,
  540. .flags = IORESOURCE_DMA,
  541. },
  542. };
  543. struct platform_device pxa25x_device_assp = {
  544. /* ASSP is basically equivalent to NSSP */
  545. .name = "pxa25x-nssp",
  546. .id = 2,
  547. .dev = {
  548. .dma_mask = &pxa25x_assp_dma_mask,
  549. .coherent_dma_mask = DMA_BIT_MASK(32),
  550. },
  551. .resource = pxa25x_resource_assp,
  552. .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
  553. };
  554. #endif /* CONFIG_PXA25x */
  555. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  556. static struct resource pxa27x_resource_camera[] = {
  557. [0] = {
  558. .start = 0x50000000,
  559. .end = 0x50000fff,
  560. .flags = IORESOURCE_MEM,
  561. },
  562. [1] = {
  563. .start = IRQ_CAMERA,
  564. .end = IRQ_CAMERA,
  565. .flags = IORESOURCE_IRQ,
  566. },
  567. };
  568. static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
  569. static struct platform_device pxa27x_device_camera = {
  570. .name = "pxa27x-camera",
  571. .id = 0, /* This is used to put cameras on this interface */
  572. .dev = {
  573. .dma_mask = &pxa27x_dma_mask_camera,
  574. .coherent_dma_mask = 0xffffffff,
  575. },
  576. .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
  577. .resource = pxa27x_resource_camera,
  578. };
  579. void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
  580. {
  581. pxa_register_device(&pxa27x_device_camera, info);
  582. }
  583. static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
  584. static struct resource pxa27x_resource_ohci[] = {
  585. [0] = {
  586. .start = 0x4C000000,
  587. .end = 0x4C00ff6f,
  588. .flags = IORESOURCE_MEM,
  589. },
  590. [1] = {
  591. .start = IRQ_USBH1,
  592. .end = IRQ_USBH1,
  593. .flags = IORESOURCE_IRQ,
  594. },
  595. };
  596. struct platform_device pxa27x_device_ohci = {
  597. .name = "pxa27x-ohci",
  598. .id = -1,
  599. .dev = {
  600. .dma_mask = &pxa27x_ohci_dma_mask,
  601. .coherent_dma_mask = DMA_BIT_MASK(32),
  602. },
  603. .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
  604. .resource = pxa27x_resource_ohci,
  605. };
  606. void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
  607. {
  608. pxa_register_device(&pxa27x_device_ohci, info);
  609. }
  610. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  611. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
  612. static struct resource pxa27x_resource_keypad[] = {
  613. [0] = {
  614. .start = 0x41500000,
  615. .end = 0x4150004c,
  616. .flags = IORESOURCE_MEM,
  617. },
  618. [1] = {
  619. .start = IRQ_KEYPAD,
  620. .end = IRQ_KEYPAD,
  621. .flags = IORESOURCE_IRQ,
  622. },
  623. };
  624. struct platform_device pxa27x_device_keypad = {
  625. .name = "pxa27x-keypad",
  626. .id = -1,
  627. .resource = pxa27x_resource_keypad,
  628. .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
  629. };
  630. void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
  631. {
  632. pxa_register_device(&pxa27x_device_keypad, info);
  633. }
  634. static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
  635. static struct resource pxa27x_resource_ssp1[] = {
  636. [0] = {
  637. .start = 0x41000000,
  638. .end = 0x4100003f,
  639. .flags = IORESOURCE_MEM,
  640. },
  641. [1] = {
  642. .start = IRQ_SSP,
  643. .end = IRQ_SSP,
  644. .flags = IORESOURCE_IRQ,
  645. },
  646. [2] = {
  647. /* DRCMR for RX */
  648. .start = 13,
  649. .end = 13,
  650. .flags = IORESOURCE_DMA,
  651. },
  652. [3] = {
  653. /* DRCMR for TX */
  654. .start = 14,
  655. .end = 14,
  656. .flags = IORESOURCE_DMA,
  657. },
  658. };
  659. struct platform_device pxa27x_device_ssp1 = {
  660. .name = "pxa27x-ssp",
  661. .id = 0,
  662. .dev = {
  663. .dma_mask = &pxa27x_ssp1_dma_mask,
  664. .coherent_dma_mask = DMA_BIT_MASK(32),
  665. },
  666. .resource = pxa27x_resource_ssp1,
  667. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  668. };
  669. static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
  670. static struct resource pxa27x_resource_ssp2[] = {
  671. [0] = {
  672. .start = 0x41700000,
  673. .end = 0x4170003f,
  674. .flags = IORESOURCE_MEM,
  675. },
  676. [1] = {
  677. .start = IRQ_SSP2,
  678. .end = IRQ_SSP2,
  679. .flags = IORESOURCE_IRQ,
  680. },
  681. [2] = {
  682. /* DRCMR for RX */
  683. .start = 15,
  684. .end = 15,
  685. .flags = IORESOURCE_DMA,
  686. },
  687. [3] = {
  688. /* DRCMR for TX */
  689. .start = 16,
  690. .end = 16,
  691. .flags = IORESOURCE_DMA,
  692. },
  693. };
  694. struct platform_device pxa27x_device_ssp2 = {
  695. .name = "pxa27x-ssp",
  696. .id = 1,
  697. .dev = {
  698. .dma_mask = &pxa27x_ssp2_dma_mask,
  699. .coherent_dma_mask = DMA_BIT_MASK(32),
  700. },
  701. .resource = pxa27x_resource_ssp2,
  702. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  703. };
  704. static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
  705. static struct resource pxa27x_resource_ssp3[] = {
  706. [0] = {
  707. .start = 0x41900000,
  708. .end = 0x4190003f,
  709. .flags = IORESOURCE_MEM,
  710. },
  711. [1] = {
  712. .start = IRQ_SSP3,
  713. .end = IRQ_SSP3,
  714. .flags = IORESOURCE_IRQ,
  715. },
  716. [2] = {
  717. /* DRCMR for RX */
  718. .start = 66,
  719. .end = 66,
  720. .flags = IORESOURCE_DMA,
  721. },
  722. [3] = {
  723. /* DRCMR for TX */
  724. .start = 67,
  725. .end = 67,
  726. .flags = IORESOURCE_DMA,
  727. },
  728. };
  729. struct platform_device pxa27x_device_ssp3 = {
  730. .name = "pxa27x-ssp",
  731. .id = 2,
  732. .dev = {
  733. .dma_mask = &pxa27x_ssp3_dma_mask,
  734. .coherent_dma_mask = DMA_BIT_MASK(32),
  735. },
  736. .resource = pxa27x_resource_ssp3,
  737. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  738. };
  739. static struct resource pxa27x_resource_pwm0[] = {
  740. [0] = {
  741. .start = 0x40b00000,
  742. .end = 0x40b0001f,
  743. .flags = IORESOURCE_MEM,
  744. },
  745. };
  746. struct platform_device pxa27x_device_pwm0 = {
  747. .name = "pxa27x-pwm",
  748. .id = 0,
  749. .resource = pxa27x_resource_pwm0,
  750. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
  751. };
  752. static struct resource pxa27x_resource_pwm1[] = {
  753. [0] = {
  754. .start = 0x40c00000,
  755. .end = 0x40c0001f,
  756. .flags = IORESOURCE_MEM,
  757. },
  758. };
  759. struct platform_device pxa27x_device_pwm1 = {
  760. .name = "pxa27x-pwm",
  761. .id = 1,
  762. .resource = pxa27x_resource_pwm1,
  763. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
  764. };
  765. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx || CONFIG_PXA95x*/
  766. #ifdef CONFIG_PXA3xx
  767. static struct resource pxa3xx_resources_mci2[] = {
  768. [0] = {
  769. .start = 0x42000000,
  770. .end = 0x42000fff,
  771. .flags = IORESOURCE_MEM,
  772. },
  773. [1] = {
  774. .start = IRQ_MMC2,
  775. .end = IRQ_MMC2,
  776. .flags = IORESOURCE_IRQ,
  777. },
  778. [2] = {
  779. .start = 93,
  780. .end = 93,
  781. .flags = IORESOURCE_DMA,
  782. },
  783. [3] = {
  784. .start = 94,
  785. .end = 94,
  786. .flags = IORESOURCE_DMA,
  787. },
  788. };
  789. struct platform_device pxa3xx_device_mci2 = {
  790. .name = "pxa2xx-mci",
  791. .id = 1,
  792. .dev = {
  793. .dma_mask = &pxamci_dmamask,
  794. .coherent_dma_mask = 0xffffffff,
  795. },
  796. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
  797. .resource = pxa3xx_resources_mci2,
  798. };
  799. void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
  800. {
  801. pxa_register_device(&pxa3xx_device_mci2, info);
  802. }
  803. static struct resource pxa3xx_resources_mci3[] = {
  804. [0] = {
  805. .start = 0x42500000,
  806. .end = 0x42500fff,
  807. .flags = IORESOURCE_MEM,
  808. },
  809. [1] = {
  810. .start = IRQ_MMC3,
  811. .end = IRQ_MMC3,
  812. .flags = IORESOURCE_IRQ,
  813. },
  814. [2] = {
  815. .start = 100,
  816. .end = 100,
  817. .flags = IORESOURCE_DMA,
  818. },
  819. [3] = {
  820. .start = 101,
  821. .end = 101,
  822. .flags = IORESOURCE_DMA,
  823. },
  824. };
  825. struct platform_device pxa3xx_device_mci3 = {
  826. .name = "pxa2xx-mci",
  827. .id = 2,
  828. .dev = {
  829. .dma_mask = &pxamci_dmamask,
  830. .coherent_dma_mask = 0xffffffff,
  831. },
  832. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
  833. .resource = pxa3xx_resources_mci3,
  834. };
  835. void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
  836. {
  837. pxa_register_device(&pxa3xx_device_mci3, info);
  838. }
  839. static struct resource pxa3xx_resources_gcu[] = {
  840. {
  841. .start = 0x54000000,
  842. .end = 0x54000fff,
  843. .flags = IORESOURCE_MEM,
  844. },
  845. {
  846. .start = IRQ_GCU,
  847. .end = IRQ_GCU,
  848. .flags = IORESOURCE_IRQ,
  849. },
  850. };
  851. static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
  852. struct platform_device pxa3xx_device_gcu = {
  853. .name = "pxa3xx-gcu",
  854. .id = -1,
  855. .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
  856. .resource = pxa3xx_resources_gcu,
  857. .dev = {
  858. .dma_mask = &pxa3xx_gcu_dmamask,
  859. .coherent_dma_mask = 0xffffffff,
  860. },
  861. };
  862. #endif /* CONFIG_PXA3xx */
  863. #if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
  864. static struct resource pxa3xx_resources_i2c_power[] = {
  865. {
  866. .start = 0x40f500c0,
  867. .end = 0x40f500d3,
  868. .flags = IORESOURCE_MEM,
  869. }, {
  870. .start = IRQ_PWRI2C,
  871. .end = IRQ_PWRI2C,
  872. .flags = IORESOURCE_IRQ,
  873. },
  874. };
  875. struct platform_device pxa3xx_device_i2c_power = {
  876. .name = "pxa3xx-pwri2c",
  877. .id = 1,
  878. .resource = pxa3xx_resources_i2c_power,
  879. .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
  880. };
  881. static struct resource pxa3xx_resources_nand[] = {
  882. [0] = {
  883. .start = 0x43100000,
  884. .end = 0x43100053,
  885. .flags = IORESOURCE_MEM,
  886. },
  887. [1] = {
  888. .start = IRQ_NAND,
  889. .end = IRQ_NAND,
  890. .flags = IORESOURCE_IRQ,
  891. },
  892. [2] = {
  893. /* DRCMR for Data DMA */
  894. .start = 97,
  895. .end = 97,
  896. .flags = IORESOURCE_DMA,
  897. },
  898. [3] = {
  899. /* DRCMR for Command DMA */
  900. .start = 99,
  901. .end = 99,
  902. .flags = IORESOURCE_DMA,
  903. },
  904. };
  905. static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
  906. struct platform_device pxa3xx_device_nand = {
  907. .name = "pxa3xx-nand",
  908. .id = -1,
  909. .dev = {
  910. .dma_mask = &pxa3xx_nand_dma_mask,
  911. .coherent_dma_mask = DMA_BIT_MASK(32),
  912. },
  913. .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
  914. .resource = pxa3xx_resources_nand,
  915. };
  916. void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
  917. {
  918. pxa_register_device(&pxa3xx_device_nand, info);
  919. }
  920. static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
  921. static struct resource pxa3xx_resource_ssp4[] = {
  922. [0] = {
  923. .start = 0x41a00000,
  924. .end = 0x41a0003f,
  925. .flags = IORESOURCE_MEM,
  926. },
  927. [1] = {
  928. .start = IRQ_SSP4,
  929. .end = IRQ_SSP4,
  930. .flags = IORESOURCE_IRQ,
  931. },
  932. [2] = {
  933. /* DRCMR for RX */
  934. .start = 2,
  935. .end = 2,
  936. .flags = IORESOURCE_DMA,
  937. },
  938. [3] = {
  939. /* DRCMR for TX */
  940. .start = 3,
  941. .end = 3,
  942. .flags = IORESOURCE_DMA,
  943. },
  944. };
  945. struct platform_device pxa3xx_device_ssp4 = {
  946. /* PXA3xx SSP is basically equivalent to PXA27x */
  947. .name = "pxa27x-ssp",
  948. .id = 3,
  949. .dev = {
  950. .dma_mask = &pxa3xx_ssp4_dma_mask,
  951. .coherent_dma_mask = DMA_BIT_MASK(32),
  952. },
  953. .resource = pxa3xx_resource_ssp4,
  954. .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
  955. };
  956. #endif /* CONFIG_PXA3xx || CONFIG_PXA95x */
  957. struct resource pxa_resource_gpio[] = {
  958. {
  959. .start = 0x40e00000,
  960. .end = 0x40e0ffff,
  961. .flags = IORESOURCE_MEM,
  962. }, {
  963. .start = IRQ_GPIO0,
  964. .end = IRQ_GPIO0,
  965. .name = "gpio0",
  966. .flags = IORESOURCE_IRQ,
  967. }, {
  968. .start = IRQ_GPIO1,
  969. .end = IRQ_GPIO1,
  970. .name = "gpio1",
  971. .flags = IORESOURCE_IRQ,
  972. }, {
  973. .start = IRQ_GPIO_2_x,
  974. .end = IRQ_GPIO_2_x,
  975. .name = "gpio_mux",
  976. .flags = IORESOURCE_IRQ,
  977. },
  978. };
  979. struct platform_device pxa_device_gpio = {
  980. .name = "pxa-gpio",
  981. .id = -1,
  982. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  983. .resource = pxa_resource_gpio,
  984. };
  985. /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
  986. * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
  987. void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
  988. {
  989. struct platform_device *pd;
  990. pd = platform_device_alloc("pxa2xx-spi", id);
  991. if (pd == NULL) {
  992. printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
  993. id);
  994. return;
  995. }
  996. pd->dev.platform_data = info;
  997. platform_device_add(pd);
  998. }