rt61pci.c 86 KB

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  1. /*
  2. Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
  3. <http://rt2x00.serialmonkey.com>
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the
  14. Free Software Foundation, Inc.,
  15. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16. */
  17. /*
  18. Module: rt61pci
  19. Abstract: rt61pci device specific routines.
  20. Supported chipsets: RT2561, RT2561s, RT2661.
  21. */
  22. #include <linux/crc-itu-t.h>
  23. #include <linux/delay.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/init.h>
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/pci.h>
  29. #include <linux/eeprom_93cx6.h>
  30. #include "rt2x00.h"
  31. #include "rt2x00pci.h"
  32. #include "rt61pci.h"
  33. /*
  34. * Allow hardware encryption to be disabled.
  35. */
  36. static int modparam_nohwcrypt = 0;
  37. module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  38. MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  39. /*
  40. * Register access.
  41. * BBP and RF register require indirect register access,
  42. * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
  43. * These indirect registers work with busy bits,
  44. * and we will try maximal REGISTER_BUSY_COUNT times to access
  45. * the register while taking a REGISTER_BUSY_DELAY us delay
  46. * between each attampt. When the busy bit is still set at that time,
  47. * the access attempt is considered to have failed,
  48. * and we will print an error.
  49. */
  50. #define WAIT_FOR_BBP(__dev, __reg) \
  51. rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
  52. #define WAIT_FOR_RF(__dev, __reg) \
  53. rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
  54. #define WAIT_FOR_MCU(__dev, __reg) \
  55. rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  56. H2M_MAILBOX_CSR_OWNER, (__reg))
  57. static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  58. const unsigned int word, const u8 value)
  59. {
  60. u32 reg;
  61. mutex_lock(&rt2x00dev->csr_mutex);
  62. /*
  63. * Wait until the BBP becomes available, afterwards we
  64. * can safely write the new data into the register.
  65. */
  66. if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  67. reg = 0;
  68. rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
  69. rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  70. rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  71. rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
  72. rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
  73. }
  74. mutex_unlock(&rt2x00dev->csr_mutex);
  75. }
  76. static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  77. const unsigned int word, u8 *value)
  78. {
  79. u32 reg;
  80. mutex_lock(&rt2x00dev->csr_mutex);
  81. /*
  82. * Wait until the BBP becomes available, afterwards we
  83. * can safely write the read request into the register.
  84. * After the data has been written, we wait until hardware
  85. * returns the correct value, if at any time the register
  86. * doesn't become available in time, reg will be 0xffffffff
  87. * which means we return 0xff to the caller.
  88. */
  89. if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  90. reg = 0;
  91. rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  92. rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  93. rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
  94. rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
  95. WAIT_FOR_BBP(rt2x00dev, &reg);
  96. }
  97. *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
  98. mutex_unlock(&rt2x00dev->csr_mutex);
  99. }
  100. static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
  101. const unsigned int word, const u32 value)
  102. {
  103. u32 reg;
  104. if (!word)
  105. return;
  106. mutex_lock(&rt2x00dev->csr_mutex);
  107. /*
  108. * Wait until the RF becomes available, afterwards we
  109. * can safely write the new data into the register.
  110. */
  111. if (WAIT_FOR_RF(rt2x00dev, &reg)) {
  112. reg = 0;
  113. rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
  114. rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
  115. rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
  116. rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
  117. rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
  118. rt2x00_rf_write(rt2x00dev, word, value);
  119. }
  120. mutex_unlock(&rt2x00dev->csr_mutex);
  121. }
  122. static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
  123. const u8 command, const u8 token,
  124. const u8 arg0, const u8 arg1)
  125. {
  126. u32 reg;
  127. mutex_lock(&rt2x00dev->csr_mutex);
  128. /*
  129. * Wait until the MCU becomes available, afterwards we
  130. * can safely write the new data into the register.
  131. */
  132. if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
  133. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
  134. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
  135. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
  136. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
  137. rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
  138. rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
  139. rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
  140. rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
  141. rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
  142. }
  143. mutex_unlock(&rt2x00dev->csr_mutex);
  144. }
  145. static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
  146. {
  147. struct rt2x00_dev *rt2x00dev = eeprom->data;
  148. u32 reg;
  149. rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
  150. eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
  151. eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
  152. eeprom->reg_data_clock =
  153. !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
  154. eeprom->reg_chip_select =
  155. !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
  156. }
  157. static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
  158. {
  159. struct rt2x00_dev *rt2x00dev = eeprom->data;
  160. u32 reg = 0;
  161. rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
  162. rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
  163. rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
  164. !!eeprom->reg_data_clock);
  165. rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
  166. !!eeprom->reg_chip_select);
  167. rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
  168. }
  169. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  170. static const struct rt2x00debug rt61pci_rt2x00debug = {
  171. .owner = THIS_MODULE,
  172. .csr = {
  173. .read = rt2x00pci_register_read,
  174. .write = rt2x00pci_register_write,
  175. .flags = RT2X00DEBUGFS_OFFSET,
  176. .word_base = CSR_REG_BASE,
  177. .word_size = sizeof(u32),
  178. .word_count = CSR_REG_SIZE / sizeof(u32),
  179. },
  180. .eeprom = {
  181. .read = rt2x00_eeprom_read,
  182. .write = rt2x00_eeprom_write,
  183. .word_base = EEPROM_BASE,
  184. .word_size = sizeof(u16),
  185. .word_count = EEPROM_SIZE / sizeof(u16),
  186. },
  187. .bbp = {
  188. .read = rt61pci_bbp_read,
  189. .write = rt61pci_bbp_write,
  190. .word_base = BBP_BASE,
  191. .word_size = sizeof(u8),
  192. .word_count = BBP_SIZE / sizeof(u8),
  193. },
  194. .rf = {
  195. .read = rt2x00_rf_read,
  196. .write = rt61pci_rf_write,
  197. .word_base = RF_BASE,
  198. .word_size = sizeof(u32),
  199. .word_count = RF_SIZE / sizeof(u32),
  200. },
  201. };
  202. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  203. #ifdef CONFIG_RT2X00_LIB_RFKILL
  204. static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
  205. {
  206. u32 reg;
  207. rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
  208. return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
  209. }
  210. #else
  211. #define rt61pci_rfkill_poll NULL
  212. #endif /* CONFIG_RT2X00_LIB_RFKILL */
  213. #ifdef CONFIG_RT2X00_LIB_LEDS
  214. static void rt61pci_brightness_set(struct led_classdev *led_cdev,
  215. enum led_brightness brightness)
  216. {
  217. struct rt2x00_led *led =
  218. container_of(led_cdev, struct rt2x00_led, led_dev);
  219. unsigned int enabled = brightness != LED_OFF;
  220. unsigned int a_mode =
  221. (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
  222. unsigned int bg_mode =
  223. (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
  224. if (led->type == LED_TYPE_RADIO) {
  225. rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
  226. MCU_LEDCS_RADIO_STATUS, enabled);
  227. rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
  228. (led->rt2x00dev->led_mcu_reg & 0xff),
  229. ((led->rt2x00dev->led_mcu_reg >> 8)));
  230. } else if (led->type == LED_TYPE_ASSOC) {
  231. rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
  232. MCU_LEDCS_LINK_BG_STATUS, bg_mode);
  233. rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
  234. MCU_LEDCS_LINK_A_STATUS, a_mode);
  235. rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
  236. (led->rt2x00dev->led_mcu_reg & 0xff),
  237. ((led->rt2x00dev->led_mcu_reg >> 8)));
  238. } else if (led->type == LED_TYPE_QUALITY) {
  239. /*
  240. * The brightness is divided into 6 levels (0 - 5),
  241. * this means we need to convert the brightness
  242. * argument into the matching level within that range.
  243. */
  244. rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
  245. brightness / (LED_FULL / 6), 0);
  246. }
  247. }
  248. static int rt61pci_blink_set(struct led_classdev *led_cdev,
  249. unsigned long *delay_on,
  250. unsigned long *delay_off)
  251. {
  252. struct rt2x00_led *led =
  253. container_of(led_cdev, struct rt2x00_led, led_dev);
  254. u32 reg;
  255. rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
  256. rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
  257. rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
  258. rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
  259. return 0;
  260. }
  261. static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
  262. struct rt2x00_led *led,
  263. enum led_type type)
  264. {
  265. led->rt2x00dev = rt2x00dev;
  266. led->type = type;
  267. led->led_dev.brightness_set = rt61pci_brightness_set;
  268. led->led_dev.blink_set = rt61pci_blink_set;
  269. led->flags = LED_INITIALIZED;
  270. }
  271. #endif /* CONFIG_RT2X00_LIB_LEDS */
  272. /*
  273. * Configuration handlers.
  274. */
  275. static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
  276. struct rt2x00lib_crypto *crypto,
  277. struct ieee80211_key_conf *key)
  278. {
  279. struct hw_key_entry key_entry;
  280. struct rt2x00_field32 field;
  281. u32 mask;
  282. u32 reg;
  283. if (crypto->cmd == SET_KEY) {
  284. /*
  285. * rt2x00lib can't determine the correct free
  286. * key_idx for shared keys. We have 1 register
  287. * with key valid bits. The goal is simple, read
  288. * the register, if that is full we have no slots
  289. * left.
  290. * Note that each BSS is allowed to have up to 4
  291. * shared keys, so put a mask over the allowed
  292. * entries.
  293. */
  294. mask = (0xf << crypto->bssidx);
  295. rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
  296. reg &= mask;
  297. if (reg && reg == mask)
  298. return -ENOSPC;
  299. key->hw_key_idx += reg ? ffz(reg) : 0;
  300. /*
  301. * Upload key to hardware
  302. */
  303. memcpy(key_entry.key, crypto->key,
  304. sizeof(key_entry.key));
  305. memcpy(key_entry.tx_mic, crypto->tx_mic,
  306. sizeof(key_entry.tx_mic));
  307. memcpy(key_entry.rx_mic, crypto->rx_mic,
  308. sizeof(key_entry.rx_mic));
  309. reg = SHARED_KEY_ENTRY(key->hw_key_idx);
  310. rt2x00pci_register_multiwrite(rt2x00dev, reg,
  311. &key_entry, sizeof(key_entry));
  312. /*
  313. * The cipher types are stored over 2 registers.
  314. * bssidx 0 and 1 keys are stored in SEC_CSR1 and
  315. * bssidx 1 and 2 keys are stored in SEC_CSR5.
  316. * Using the correct defines correctly will cause overhead,
  317. * so just calculate the correct offset.
  318. */
  319. if (key->hw_key_idx < 8) {
  320. field.bit_offset = (3 * key->hw_key_idx);
  321. field.bit_mask = 0x7 << field.bit_offset;
  322. rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg);
  323. rt2x00_set_field32(&reg, field, crypto->cipher);
  324. rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
  325. } else {
  326. field.bit_offset = (3 * (key->hw_key_idx - 8));
  327. field.bit_mask = 0x7 << field.bit_offset;
  328. rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg);
  329. rt2x00_set_field32(&reg, field, crypto->cipher);
  330. rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
  331. }
  332. /*
  333. * The driver does not support the IV/EIV generation
  334. * in hardware. However it doesn't support the IV/EIV
  335. * inside the ieee80211 frame either, but requires it
  336. * to be provided seperately for the descriptor.
  337. * rt2x00lib will cut the IV/EIV data out of all frames
  338. * given to us by mac80211, but we must tell mac80211
  339. * to generate the IV/EIV data.
  340. */
  341. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  342. }
  343. /*
  344. * SEC_CSR0 contains only single-bit fields to indicate
  345. * a particular key is valid. Because using the FIELD32()
  346. * defines directly will cause a lot of overhead we use
  347. * a calculation to determine the correct bit directly.
  348. */
  349. mask = 1 << key->hw_key_idx;
  350. rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
  351. if (crypto->cmd == SET_KEY)
  352. reg |= mask;
  353. else if (crypto->cmd == DISABLE_KEY)
  354. reg &= ~mask;
  355. rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
  356. return 0;
  357. }
  358. static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
  359. struct rt2x00lib_crypto *crypto,
  360. struct ieee80211_key_conf *key)
  361. {
  362. struct hw_pairwise_ta_entry addr_entry;
  363. struct hw_key_entry key_entry;
  364. u32 mask;
  365. u32 reg;
  366. if (crypto->cmd == SET_KEY) {
  367. /*
  368. * rt2x00lib can't determine the correct free
  369. * key_idx for pairwise keys. We have 2 registers
  370. * with key valid bits. The goal is simple, read
  371. * the first register, if that is full move to
  372. * the next register.
  373. * When both registers are full, we drop the key,
  374. * otherwise we use the first invalid entry.
  375. */
  376. rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
  377. if (reg && reg == ~0) {
  378. key->hw_key_idx = 32;
  379. rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
  380. if (reg && reg == ~0)
  381. return -ENOSPC;
  382. }
  383. key->hw_key_idx += reg ? ffz(reg) : 0;
  384. /*
  385. * Upload key to hardware
  386. */
  387. memcpy(key_entry.key, crypto->key,
  388. sizeof(key_entry.key));
  389. memcpy(key_entry.tx_mic, crypto->tx_mic,
  390. sizeof(key_entry.tx_mic));
  391. memcpy(key_entry.rx_mic, crypto->rx_mic,
  392. sizeof(key_entry.rx_mic));
  393. memset(&addr_entry, 0, sizeof(addr_entry));
  394. memcpy(&addr_entry, crypto->address, ETH_ALEN);
  395. addr_entry.cipher = crypto->cipher;
  396. reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
  397. rt2x00pci_register_multiwrite(rt2x00dev, reg,
  398. &key_entry, sizeof(key_entry));
  399. reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
  400. rt2x00pci_register_multiwrite(rt2x00dev, reg,
  401. &addr_entry, sizeof(addr_entry));
  402. /*
  403. * Enable pairwise lookup table for given BSS idx,
  404. * without this received frames will not be decrypted
  405. * by the hardware.
  406. */
  407. rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
  408. reg |= (1 << crypto->bssidx);
  409. rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
  410. /*
  411. * The driver does not support the IV/EIV generation
  412. * in hardware. However it doesn't support the IV/EIV
  413. * inside the ieee80211 frame either, but requires it
  414. * to be provided seperately for the descriptor.
  415. * rt2x00lib will cut the IV/EIV data out of all frames
  416. * given to us by mac80211, but we must tell mac80211
  417. * to generate the IV/EIV data.
  418. */
  419. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  420. }
  421. /*
  422. * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
  423. * a particular key is valid. Because using the FIELD32()
  424. * defines directly will cause a lot of overhead we use
  425. * a calculation to determine the correct bit directly.
  426. */
  427. if (key->hw_key_idx < 32) {
  428. mask = 1 << key->hw_key_idx;
  429. rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
  430. if (crypto->cmd == SET_KEY)
  431. reg |= mask;
  432. else if (crypto->cmd == DISABLE_KEY)
  433. reg &= ~mask;
  434. rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
  435. } else {
  436. mask = 1 << (key->hw_key_idx - 32);
  437. rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
  438. if (crypto->cmd == SET_KEY)
  439. reg |= mask;
  440. else if (crypto->cmd == DISABLE_KEY)
  441. reg &= ~mask;
  442. rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
  443. }
  444. return 0;
  445. }
  446. static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
  447. const unsigned int filter_flags)
  448. {
  449. u32 reg;
  450. /*
  451. * Start configuration steps.
  452. * Note that the version error will always be dropped
  453. * and broadcast frames will always be accepted since
  454. * there is no filter for it at this time.
  455. */
  456. rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
  457. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
  458. !(filter_flags & FIF_FCSFAIL));
  459. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
  460. !(filter_flags & FIF_PLCPFAIL));
  461. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
  462. !(filter_flags & FIF_CONTROL));
  463. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
  464. !(filter_flags & FIF_PROMISC_IN_BSS));
  465. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
  466. !(filter_flags & FIF_PROMISC_IN_BSS) &&
  467. !rt2x00dev->intf_ap_count);
  468. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
  469. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
  470. !(filter_flags & FIF_ALLMULTI));
  471. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
  472. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
  473. !(filter_flags & FIF_CONTROL));
  474. rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
  475. }
  476. static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
  477. struct rt2x00_intf *intf,
  478. struct rt2x00intf_conf *conf,
  479. const unsigned int flags)
  480. {
  481. unsigned int beacon_base;
  482. u32 reg;
  483. if (flags & CONFIG_UPDATE_TYPE) {
  484. /*
  485. * Clear current synchronisation setup.
  486. * For the Beacon base registers we only need to clear
  487. * the first byte since that byte contains the VALID and OWNER
  488. * bits which (when set to 0) will invalidate the entire beacon.
  489. */
  490. beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
  491. rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
  492. /*
  493. * Enable synchronisation.
  494. */
  495. rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
  496. rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
  497. rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
  498. rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
  499. rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
  500. }
  501. if (flags & CONFIG_UPDATE_MAC) {
  502. reg = le32_to_cpu(conf->mac[1]);
  503. rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
  504. conf->mac[1] = cpu_to_le32(reg);
  505. rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
  506. conf->mac, sizeof(conf->mac));
  507. }
  508. if (flags & CONFIG_UPDATE_BSSID) {
  509. reg = le32_to_cpu(conf->bssid[1]);
  510. rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
  511. conf->bssid[1] = cpu_to_le32(reg);
  512. rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
  513. conf->bssid, sizeof(conf->bssid));
  514. }
  515. }
  516. static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
  517. struct rt2x00lib_erp *erp)
  518. {
  519. u32 reg;
  520. rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
  521. rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
  522. rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
  523. rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
  524. rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
  525. !!erp->short_preamble);
  526. rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
  527. rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
  528. rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
  529. rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
  530. rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
  531. rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
  532. rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
  533. rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
  534. rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
  535. rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
  536. }
  537. static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
  538. struct antenna_setup *ant)
  539. {
  540. u8 r3;
  541. u8 r4;
  542. u8 r77;
  543. rt61pci_bbp_read(rt2x00dev, 3, &r3);
  544. rt61pci_bbp_read(rt2x00dev, 4, &r4);
  545. rt61pci_bbp_read(rt2x00dev, 77, &r77);
  546. rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
  547. rt2x00_rf(&rt2x00dev->chip, RF5325));
  548. /*
  549. * Configure the RX antenna.
  550. */
  551. switch (ant->rx) {
  552. case ANTENNA_HW_DIVERSITY:
  553. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
  554. rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
  555. (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
  556. break;
  557. case ANTENNA_A:
  558. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
  559. rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
  560. if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
  561. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
  562. else
  563. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
  564. break;
  565. case ANTENNA_B:
  566. default:
  567. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
  568. rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
  569. if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
  570. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
  571. else
  572. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
  573. break;
  574. }
  575. rt61pci_bbp_write(rt2x00dev, 77, r77);
  576. rt61pci_bbp_write(rt2x00dev, 3, r3);
  577. rt61pci_bbp_write(rt2x00dev, 4, r4);
  578. }
  579. static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
  580. struct antenna_setup *ant)
  581. {
  582. u8 r3;
  583. u8 r4;
  584. u8 r77;
  585. rt61pci_bbp_read(rt2x00dev, 3, &r3);
  586. rt61pci_bbp_read(rt2x00dev, 4, &r4);
  587. rt61pci_bbp_read(rt2x00dev, 77, &r77);
  588. rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
  589. rt2x00_rf(&rt2x00dev->chip, RF2529));
  590. rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
  591. !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
  592. /*
  593. * Configure the RX antenna.
  594. */
  595. switch (ant->rx) {
  596. case ANTENNA_HW_DIVERSITY:
  597. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
  598. break;
  599. case ANTENNA_A:
  600. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
  601. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
  602. break;
  603. case ANTENNA_B:
  604. default:
  605. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
  606. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
  607. break;
  608. }
  609. rt61pci_bbp_write(rt2x00dev, 77, r77);
  610. rt61pci_bbp_write(rt2x00dev, 3, r3);
  611. rt61pci_bbp_write(rt2x00dev, 4, r4);
  612. }
  613. static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
  614. const int p1, const int p2)
  615. {
  616. u32 reg;
  617. rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
  618. rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
  619. rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
  620. rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
  621. rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
  622. rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
  623. }
  624. static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
  625. struct antenna_setup *ant)
  626. {
  627. u8 r3;
  628. u8 r4;
  629. u8 r77;
  630. rt61pci_bbp_read(rt2x00dev, 3, &r3);
  631. rt61pci_bbp_read(rt2x00dev, 4, &r4);
  632. rt61pci_bbp_read(rt2x00dev, 77, &r77);
  633. /*
  634. * Configure the RX antenna.
  635. */
  636. switch (ant->rx) {
  637. case ANTENNA_A:
  638. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
  639. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
  640. rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
  641. break;
  642. case ANTENNA_HW_DIVERSITY:
  643. /*
  644. * FIXME: Antenna selection for the rf 2529 is very confusing
  645. * in the legacy driver. Just default to antenna B until the
  646. * legacy code can be properly translated into rt2x00 code.
  647. */
  648. case ANTENNA_B:
  649. default:
  650. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
  651. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
  652. rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
  653. break;
  654. }
  655. rt61pci_bbp_write(rt2x00dev, 77, r77);
  656. rt61pci_bbp_write(rt2x00dev, 3, r3);
  657. rt61pci_bbp_write(rt2x00dev, 4, r4);
  658. }
  659. struct antenna_sel {
  660. u8 word;
  661. /*
  662. * value[0] -> non-LNA
  663. * value[1] -> LNA
  664. */
  665. u8 value[2];
  666. };
  667. static const struct antenna_sel antenna_sel_a[] = {
  668. { 96, { 0x58, 0x78 } },
  669. { 104, { 0x38, 0x48 } },
  670. { 75, { 0xfe, 0x80 } },
  671. { 86, { 0xfe, 0x80 } },
  672. { 88, { 0xfe, 0x80 } },
  673. { 35, { 0x60, 0x60 } },
  674. { 97, { 0x58, 0x58 } },
  675. { 98, { 0x58, 0x58 } },
  676. };
  677. static const struct antenna_sel antenna_sel_bg[] = {
  678. { 96, { 0x48, 0x68 } },
  679. { 104, { 0x2c, 0x3c } },
  680. { 75, { 0xfe, 0x80 } },
  681. { 86, { 0xfe, 0x80 } },
  682. { 88, { 0xfe, 0x80 } },
  683. { 35, { 0x50, 0x50 } },
  684. { 97, { 0x48, 0x48 } },
  685. { 98, { 0x48, 0x48 } },
  686. };
  687. static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
  688. struct antenna_setup *ant)
  689. {
  690. const struct antenna_sel *sel;
  691. unsigned int lna;
  692. unsigned int i;
  693. u32 reg;
  694. /*
  695. * We should never come here because rt2x00lib is supposed
  696. * to catch this and send us the correct antenna explicitely.
  697. */
  698. BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
  699. ant->tx == ANTENNA_SW_DIVERSITY);
  700. if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
  701. sel = antenna_sel_a;
  702. lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
  703. } else {
  704. sel = antenna_sel_bg;
  705. lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
  706. }
  707. for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
  708. rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
  709. rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
  710. rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
  711. rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
  712. rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
  713. rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
  714. rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
  715. if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
  716. rt2x00_rf(&rt2x00dev->chip, RF5325))
  717. rt61pci_config_antenna_5x(rt2x00dev, ant);
  718. else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
  719. rt61pci_config_antenna_2x(rt2x00dev, ant);
  720. else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
  721. if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
  722. rt61pci_config_antenna_2x(rt2x00dev, ant);
  723. else
  724. rt61pci_config_antenna_2529(rt2x00dev, ant);
  725. }
  726. }
  727. static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
  728. struct rt2x00lib_conf *libconf)
  729. {
  730. u16 eeprom;
  731. short lna_gain = 0;
  732. if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
  733. if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
  734. lna_gain += 14;
  735. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
  736. lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
  737. } else {
  738. if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
  739. lna_gain += 14;
  740. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
  741. lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
  742. }
  743. rt2x00dev->lna_gain = lna_gain;
  744. }
  745. static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
  746. struct rf_channel *rf, const int txpower)
  747. {
  748. u8 r3;
  749. u8 r94;
  750. u8 smart;
  751. rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
  752. rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
  753. smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
  754. rt2x00_rf(&rt2x00dev->chip, RF2527));
  755. rt61pci_bbp_read(rt2x00dev, 3, &r3);
  756. rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
  757. rt61pci_bbp_write(rt2x00dev, 3, r3);
  758. r94 = 6;
  759. if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
  760. r94 += txpower - MAX_TXPOWER;
  761. else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
  762. r94 += txpower;
  763. rt61pci_bbp_write(rt2x00dev, 94, r94);
  764. rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
  765. rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
  766. rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
  767. rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
  768. udelay(200);
  769. rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
  770. rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
  771. rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
  772. rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
  773. udelay(200);
  774. rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
  775. rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
  776. rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
  777. rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
  778. msleep(1);
  779. }
  780. static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
  781. const int txpower)
  782. {
  783. struct rf_channel rf;
  784. rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
  785. rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
  786. rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
  787. rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
  788. rt61pci_config_channel(rt2x00dev, &rf, txpower);
  789. }
  790. static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
  791. struct rt2x00lib_conf *libconf)
  792. {
  793. u32 reg;
  794. rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
  795. rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
  796. libconf->conf->long_frame_max_tx_count);
  797. rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
  798. libconf->conf->short_frame_max_tx_count);
  799. rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
  800. }
  801. static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
  802. struct rt2x00lib_conf *libconf)
  803. {
  804. u32 reg;
  805. rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
  806. rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
  807. rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
  808. rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
  809. rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
  810. rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
  811. rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
  812. rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
  813. libconf->conf->beacon_int * 16);
  814. rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
  815. }
  816. static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
  817. struct rt2x00lib_conf *libconf)
  818. {
  819. enum dev_state state =
  820. (libconf->conf->flags & IEEE80211_CONF_PS) ?
  821. STATE_SLEEP : STATE_AWAKE;
  822. u32 reg;
  823. if (state == STATE_SLEEP) {
  824. rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
  825. rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
  826. libconf->conf->beacon_int - 10);
  827. rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
  828. libconf->conf->listen_interval - 1);
  829. rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
  830. /* We must first disable autowake before it can be enabled */
  831. rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
  832. rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
  833. rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
  834. rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
  835. rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005);
  836. rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
  837. rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
  838. rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
  839. } else {
  840. rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
  841. rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
  842. rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
  843. rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
  844. rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
  845. rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
  846. rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
  847. rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
  848. rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
  849. rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
  850. }
  851. }
  852. static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
  853. struct rt2x00lib_conf *libconf,
  854. const unsigned int flags)
  855. {
  856. /* Always recalculate LNA gain before changing configuration */
  857. rt61pci_config_lna_gain(rt2x00dev, libconf);
  858. if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
  859. rt61pci_config_channel(rt2x00dev, &libconf->rf,
  860. libconf->conf->power_level);
  861. if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
  862. !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
  863. rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
  864. if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
  865. rt61pci_config_retry_limit(rt2x00dev, libconf);
  866. if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
  867. rt61pci_config_duration(rt2x00dev, libconf);
  868. if (flags & IEEE80211_CONF_CHANGE_PS)
  869. rt61pci_config_ps(rt2x00dev, libconf);
  870. }
  871. /*
  872. * Link tuning
  873. */
  874. static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
  875. struct link_qual *qual)
  876. {
  877. u32 reg;
  878. /*
  879. * Update FCS error count from register.
  880. */
  881. rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
  882. qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
  883. /*
  884. * Update False CCA count from register.
  885. */
  886. rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
  887. qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
  888. }
  889. static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
  890. struct link_qual *qual, u8 vgc_level)
  891. {
  892. if (qual->vgc_level != vgc_level) {
  893. rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
  894. qual->vgc_level = vgc_level;
  895. qual->vgc_level_reg = vgc_level;
  896. }
  897. }
  898. static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
  899. struct link_qual *qual)
  900. {
  901. rt61pci_set_vgc(rt2x00dev, qual, 0x20);
  902. }
  903. static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
  904. struct link_qual *qual, const u32 count)
  905. {
  906. u8 up_bound;
  907. u8 low_bound;
  908. /*
  909. * Determine r17 bounds.
  910. */
  911. if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
  912. low_bound = 0x28;
  913. up_bound = 0x48;
  914. if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
  915. low_bound += 0x10;
  916. up_bound += 0x10;
  917. }
  918. } else {
  919. low_bound = 0x20;
  920. up_bound = 0x40;
  921. if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
  922. low_bound += 0x10;
  923. up_bound += 0x10;
  924. }
  925. }
  926. /*
  927. * If we are not associated, we should go straight to the
  928. * dynamic CCA tuning.
  929. */
  930. if (!rt2x00dev->intf_associated)
  931. goto dynamic_cca_tune;
  932. /*
  933. * Special big-R17 for very short distance
  934. */
  935. if (qual->rssi >= -35) {
  936. rt61pci_set_vgc(rt2x00dev, qual, 0x60);
  937. return;
  938. }
  939. /*
  940. * Special big-R17 for short distance
  941. */
  942. if (qual->rssi >= -58) {
  943. rt61pci_set_vgc(rt2x00dev, qual, up_bound);
  944. return;
  945. }
  946. /*
  947. * Special big-R17 for middle-short distance
  948. */
  949. if (qual->rssi >= -66) {
  950. rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
  951. return;
  952. }
  953. /*
  954. * Special mid-R17 for middle distance
  955. */
  956. if (qual->rssi >= -74) {
  957. rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
  958. return;
  959. }
  960. /*
  961. * Special case: Change up_bound based on the rssi.
  962. * Lower up_bound when rssi is weaker then -74 dBm.
  963. */
  964. up_bound -= 2 * (-74 - qual->rssi);
  965. if (low_bound > up_bound)
  966. up_bound = low_bound;
  967. if (qual->vgc_level > up_bound) {
  968. rt61pci_set_vgc(rt2x00dev, qual, up_bound);
  969. return;
  970. }
  971. dynamic_cca_tune:
  972. /*
  973. * r17 does not yet exceed upper limit, continue and base
  974. * the r17 tuning on the false CCA count.
  975. */
  976. if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
  977. rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
  978. else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
  979. rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
  980. }
  981. /*
  982. * Firmware functions
  983. */
  984. static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
  985. {
  986. char *fw_name;
  987. switch (rt2x00dev->chip.rt) {
  988. case RT2561:
  989. fw_name = FIRMWARE_RT2561;
  990. break;
  991. case RT2561s:
  992. fw_name = FIRMWARE_RT2561s;
  993. break;
  994. case RT2661:
  995. fw_name = FIRMWARE_RT2661;
  996. break;
  997. default:
  998. fw_name = NULL;
  999. break;
  1000. }
  1001. return fw_name;
  1002. }
  1003. static u16 rt61pci_get_firmware_crc(const void *data, const size_t len)
  1004. {
  1005. u16 crc;
  1006. /*
  1007. * Use the crc itu-t algorithm.
  1008. * The last 2 bytes in the firmware array are the crc checksum itself,
  1009. * this means that we should never pass those 2 bytes to the crc
  1010. * algorithm.
  1011. */
  1012. crc = crc_itu_t(0, data, len - 2);
  1013. crc = crc_itu_t_byte(crc, 0);
  1014. crc = crc_itu_t_byte(crc, 0);
  1015. return crc;
  1016. }
  1017. static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
  1018. const size_t len)
  1019. {
  1020. int i;
  1021. u32 reg;
  1022. /*
  1023. * Wait for stable hardware.
  1024. */
  1025. for (i = 0; i < 100; i++) {
  1026. rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
  1027. if (reg)
  1028. break;
  1029. msleep(1);
  1030. }
  1031. if (!reg) {
  1032. ERROR(rt2x00dev, "Unstable hardware.\n");
  1033. return -EBUSY;
  1034. }
  1035. /*
  1036. * Prepare MCU and mailbox for firmware loading.
  1037. */
  1038. reg = 0;
  1039. rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
  1040. rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
  1041. rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
  1042. rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
  1043. rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
  1044. /*
  1045. * Write firmware to device.
  1046. */
  1047. reg = 0;
  1048. rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
  1049. rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
  1050. rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
  1051. rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
  1052. data, len);
  1053. rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
  1054. rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
  1055. rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
  1056. rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
  1057. for (i = 0; i < 100; i++) {
  1058. rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
  1059. if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
  1060. break;
  1061. msleep(1);
  1062. }
  1063. if (i == 100) {
  1064. ERROR(rt2x00dev, "MCU Control register not ready.\n");
  1065. return -EBUSY;
  1066. }
  1067. /*
  1068. * Hardware needs another millisecond before it is ready.
  1069. */
  1070. msleep(1);
  1071. /*
  1072. * Reset MAC and BBP registers.
  1073. */
  1074. reg = 0;
  1075. rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
  1076. rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
  1077. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  1078. rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
  1079. rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
  1080. rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
  1081. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  1082. rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
  1083. rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
  1084. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  1085. return 0;
  1086. }
  1087. /*
  1088. * Initialization functions.
  1089. */
  1090. static bool rt61pci_get_entry_state(struct queue_entry *entry)
  1091. {
  1092. struct queue_entry_priv_pci *entry_priv = entry->priv_data;
  1093. u32 word;
  1094. if (entry->queue->qid == QID_RX) {
  1095. rt2x00_desc_read(entry_priv->desc, 0, &word);
  1096. return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
  1097. } else {
  1098. rt2x00_desc_read(entry_priv->desc, 0, &word);
  1099. return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
  1100. rt2x00_get_field32(word, TXD_W0_VALID));
  1101. }
  1102. }
  1103. static void rt61pci_clear_entry(struct queue_entry *entry)
  1104. {
  1105. struct queue_entry_priv_pci *entry_priv = entry->priv_data;
  1106. struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
  1107. u32 word;
  1108. if (entry->queue->qid == QID_RX) {
  1109. rt2x00_desc_read(entry_priv->desc, 5, &word);
  1110. rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
  1111. skbdesc->skb_dma);
  1112. rt2x00_desc_write(entry_priv->desc, 5, word);
  1113. rt2x00_desc_read(entry_priv->desc, 0, &word);
  1114. rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
  1115. rt2x00_desc_write(entry_priv->desc, 0, word);
  1116. } else {
  1117. rt2x00_desc_read(entry_priv->desc, 0, &word);
  1118. rt2x00_set_field32(&word, TXD_W0_VALID, 0);
  1119. rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
  1120. rt2x00_desc_write(entry_priv->desc, 0, word);
  1121. }
  1122. }
  1123. static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
  1124. {
  1125. struct queue_entry_priv_pci *entry_priv;
  1126. u32 reg;
  1127. /*
  1128. * Initialize registers.
  1129. */
  1130. rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
  1131. rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
  1132. rt2x00dev->tx[0].limit);
  1133. rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
  1134. rt2x00dev->tx[1].limit);
  1135. rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
  1136. rt2x00dev->tx[2].limit);
  1137. rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
  1138. rt2x00dev->tx[3].limit);
  1139. rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
  1140. rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
  1141. rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
  1142. rt2x00dev->tx[0].desc_size / 4);
  1143. rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
  1144. entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
  1145. rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
  1146. rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
  1147. entry_priv->desc_dma);
  1148. rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
  1149. entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
  1150. rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
  1151. rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
  1152. entry_priv->desc_dma);
  1153. rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
  1154. entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
  1155. rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
  1156. rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
  1157. entry_priv->desc_dma);
  1158. rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
  1159. entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
  1160. rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
  1161. rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
  1162. entry_priv->desc_dma);
  1163. rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
  1164. rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
  1165. rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
  1166. rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
  1167. rt2x00dev->rx->desc_size / 4);
  1168. rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
  1169. rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
  1170. entry_priv = rt2x00dev->rx->entries[0].priv_data;
  1171. rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
  1172. rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
  1173. entry_priv->desc_dma);
  1174. rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
  1175. rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
  1176. rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
  1177. rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
  1178. rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
  1179. rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
  1180. rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
  1181. rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
  1182. rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
  1183. rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
  1184. rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
  1185. rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
  1186. rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
  1187. rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
  1188. rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
  1189. rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
  1190. return 0;
  1191. }
  1192. static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
  1193. {
  1194. u32 reg;
  1195. rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
  1196. rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
  1197. rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
  1198. rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
  1199. rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
  1200. rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
  1201. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
  1202. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
  1203. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
  1204. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
  1205. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
  1206. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
  1207. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
  1208. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
  1209. rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
  1210. /*
  1211. * CCK TXD BBP registers
  1212. */
  1213. rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
  1214. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
  1215. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
  1216. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
  1217. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
  1218. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
  1219. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
  1220. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
  1221. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
  1222. rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
  1223. /*
  1224. * OFDM TXD BBP registers
  1225. */
  1226. rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
  1227. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
  1228. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
  1229. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
  1230. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
  1231. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
  1232. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
  1233. rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
  1234. rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
  1235. rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
  1236. rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
  1237. rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
  1238. rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
  1239. rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
  1240. rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
  1241. rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
  1242. rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
  1243. rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
  1244. rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
  1245. rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
  1246. rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
  1247. rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
  1248. rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
  1249. rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
  1250. rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
  1251. rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
  1252. rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
  1253. rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
  1254. rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
  1255. rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
  1256. rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
  1257. rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
  1258. rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
  1259. rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
  1260. if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
  1261. return -EBUSY;
  1262. rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
  1263. /*
  1264. * Invalidate all Shared Keys (SEC_CSR0),
  1265. * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
  1266. */
  1267. rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
  1268. rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
  1269. rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
  1270. rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
  1271. rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
  1272. rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
  1273. rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
  1274. rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
  1275. rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
  1276. rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
  1277. /*
  1278. * Clear all beacons
  1279. * For the Beacon base registers we only need to clear
  1280. * the first byte since that byte contains the VALID and OWNER
  1281. * bits which (when set to 0) will invalidate the entire beacon.
  1282. */
  1283. rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
  1284. rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
  1285. rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
  1286. rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
  1287. /*
  1288. * We must clear the error counters.
  1289. * These registers are cleared on read,
  1290. * so we may pass a useless variable to store the value.
  1291. */
  1292. rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
  1293. rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
  1294. rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
  1295. /*
  1296. * Reset MAC and BBP registers.
  1297. */
  1298. rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
  1299. rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
  1300. rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
  1301. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  1302. rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
  1303. rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
  1304. rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
  1305. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  1306. rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
  1307. rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
  1308. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  1309. return 0;
  1310. }
  1311. static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
  1312. {
  1313. unsigned int i;
  1314. u8 value;
  1315. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  1316. rt61pci_bbp_read(rt2x00dev, 0, &value);
  1317. if ((value != 0xff) && (value != 0x00))
  1318. return 0;
  1319. udelay(REGISTER_BUSY_DELAY);
  1320. }
  1321. ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
  1322. return -EACCES;
  1323. }
  1324. static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
  1325. {
  1326. unsigned int i;
  1327. u16 eeprom;
  1328. u8 reg_id;
  1329. u8 value;
  1330. if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
  1331. return -EACCES;
  1332. rt61pci_bbp_write(rt2x00dev, 3, 0x00);
  1333. rt61pci_bbp_write(rt2x00dev, 15, 0x30);
  1334. rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
  1335. rt61pci_bbp_write(rt2x00dev, 22, 0x38);
  1336. rt61pci_bbp_write(rt2x00dev, 23, 0x06);
  1337. rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
  1338. rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
  1339. rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
  1340. rt61pci_bbp_write(rt2x00dev, 34, 0x12);
  1341. rt61pci_bbp_write(rt2x00dev, 37, 0x07);
  1342. rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
  1343. rt61pci_bbp_write(rt2x00dev, 41, 0x60);
  1344. rt61pci_bbp_write(rt2x00dev, 53, 0x10);
  1345. rt61pci_bbp_write(rt2x00dev, 54, 0x18);
  1346. rt61pci_bbp_write(rt2x00dev, 60, 0x10);
  1347. rt61pci_bbp_write(rt2x00dev, 61, 0x04);
  1348. rt61pci_bbp_write(rt2x00dev, 62, 0x04);
  1349. rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
  1350. rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
  1351. rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
  1352. rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
  1353. rt61pci_bbp_write(rt2x00dev, 99, 0x00);
  1354. rt61pci_bbp_write(rt2x00dev, 102, 0x16);
  1355. rt61pci_bbp_write(rt2x00dev, 107, 0x04);
  1356. for (i = 0; i < EEPROM_BBP_SIZE; i++) {
  1357. rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
  1358. if (eeprom != 0xffff && eeprom != 0x0000) {
  1359. reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
  1360. value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
  1361. rt61pci_bbp_write(rt2x00dev, reg_id, value);
  1362. }
  1363. }
  1364. return 0;
  1365. }
  1366. /*
  1367. * Device state switch handlers.
  1368. */
  1369. static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
  1370. enum dev_state state)
  1371. {
  1372. u32 reg;
  1373. rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
  1374. rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
  1375. (state == STATE_RADIO_RX_OFF) ||
  1376. (state == STATE_RADIO_RX_OFF_LINK));
  1377. rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
  1378. }
  1379. static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
  1380. enum dev_state state)
  1381. {
  1382. int mask = (state == STATE_RADIO_IRQ_OFF);
  1383. u32 reg;
  1384. /*
  1385. * When interrupts are being enabled, the interrupt registers
  1386. * should clear the register to assure a clean state.
  1387. */
  1388. if (state == STATE_RADIO_IRQ_ON) {
  1389. rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
  1390. rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
  1391. rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
  1392. rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
  1393. }
  1394. /*
  1395. * Only toggle the interrupts bits we are going to use.
  1396. * Non-checked interrupt bits are disabled by default.
  1397. */
  1398. rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
  1399. rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
  1400. rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
  1401. rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
  1402. rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
  1403. rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
  1404. rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
  1405. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
  1406. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
  1407. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
  1408. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
  1409. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
  1410. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
  1411. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
  1412. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
  1413. rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
  1414. }
  1415. static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
  1416. {
  1417. u32 reg;
  1418. /*
  1419. * Initialize all registers.
  1420. */
  1421. if (unlikely(rt61pci_init_queues(rt2x00dev) ||
  1422. rt61pci_init_registers(rt2x00dev) ||
  1423. rt61pci_init_bbp(rt2x00dev)))
  1424. return -EIO;
  1425. /*
  1426. * Enable RX.
  1427. */
  1428. rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
  1429. rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
  1430. rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
  1431. return 0;
  1432. }
  1433. static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
  1434. {
  1435. u32 reg;
  1436. rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
  1437. /*
  1438. * Disable synchronisation.
  1439. */
  1440. rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
  1441. /*
  1442. * Cancel RX and TX.
  1443. */
  1444. rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
  1445. rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
  1446. rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
  1447. rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
  1448. rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
  1449. rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
  1450. }
  1451. static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
  1452. {
  1453. u32 reg;
  1454. unsigned int i;
  1455. char put_to_sleep;
  1456. put_to_sleep = (state != STATE_AWAKE);
  1457. rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
  1458. rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
  1459. rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
  1460. rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
  1461. /*
  1462. * Device is not guaranteed to be in the requested state yet.
  1463. * We must wait until the register indicates that the
  1464. * device has entered the correct state.
  1465. */
  1466. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  1467. rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
  1468. state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
  1469. if (state == !put_to_sleep)
  1470. return 0;
  1471. msleep(10);
  1472. }
  1473. return -EBUSY;
  1474. }
  1475. static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
  1476. enum dev_state state)
  1477. {
  1478. int retval = 0;
  1479. switch (state) {
  1480. case STATE_RADIO_ON:
  1481. retval = rt61pci_enable_radio(rt2x00dev);
  1482. break;
  1483. case STATE_RADIO_OFF:
  1484. rt61pci_disable_radio(rt2x00dev);
  1485. break;
  1486. case STATE_RADIO_RX_ON:
  1487. case STATE_RADIO_RX_ON_LINK:
  1488. case STATE_RADIO_RX_OFF:
  1489. case STATE_RADIO_RX_OFF_LINK:
  1490. rt61pci_toggle_rx(rt2x00dev, state);
  1491. break;
  1492. case STATE_RADIO_IRQ_ON:
  1493. case STATE_RADIO_IRQ_OFF:
  1494. rt61pci_toggle_irq(rt2x00dev, state);
  1495. break;
  1496. case STATE_DEEP_SLEEP:
  1497. case STATE_SLEEP:
  1498. case STATE_STANDBY:
  1499. case STATE_AWAKE:
  1500. retval = rt61pci_set_state(rt2x00dev, state);
  1501. break;
  1502. default:
  1503. retval = -ENOTSUPP;
  1504. break;
  1505. }
  1506. if (unlikely(retval))
  1507. ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
  1508. state, retval);
  1509. return retval;
  1510. }
  1511. /*
  1512. * TX descriptor initialization
  1513. */
  1514. static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
  1515. struct sk_buff *skb,
  1516. struct txentry_desc *txdesc)
  1517. {
  1518. struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
  1519. __le32 *txd = skbdesc->desc;
  1520. u32 word;
  1521. /*
  1522. * Start writing the descriptor words.
  1523. */
  1524. rt2x00_desc_read(txd, 1, &word);
  1525. rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
  1526. rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
  1527. rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
  1528. rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
  1529. rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
  1530. rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
  1531. test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
  1532. rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
  1533. rt2x00_desc_write(txd, 1, word);
  1534. rt2x00_desc_read(txd, 2, &word);
  1535. rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
  1536. rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
  1537. rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
  1538. rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
  1539. rt2x00_desc_write(txd, 2, word);
  1540. if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
  1541. _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
  1542. _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
  1543. }
  1544. rt2x00_desc_read(txd, 5, &word);
  1545. rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
  1546. rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
  1547. skbdesc->entry->entry_idx);
  1548. rt2x00_set_field32(&word, TXD_W5_TX_POWER,
  1549. TXPOWER_TO_DEV(rt2x00dev->tx_power));
  1550. rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
  1551. rt2x00_desc_write(txd, 5, word);
  1552. rt2x00_desc_read(txd, 6, &word);
  1553. rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
  1554. skbdesc->skb_dma);
  1555. rt2x00_desc_write(txd, 6, word);
  1556. if (skbdesc->desc_len > TXINFO_SIZE) {
  1557. rt2x00_desc_read(txd, 11, &word);
  1558. rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skb->len);
  1559. rt2x00_desc_write(txd, 11, word);
  1560. }
  1561. rt2x00_desc_read(txd, 0, &word);
  1562. rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
  1563. rt2x00_set_field32(&word, TXD_W0_VALID, 1);
  1564. rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
  1565. test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
  1566. rt2x00_set_field32(&word, TXD_W0_ACK,
  1567. test_bit(ENTRY_TXD_ACK, &txdesc->flags));
  1568. rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
  1569. test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
  1570. rt2x00_set_field32(&word, TXD_W0_OFDM,
  1571. (txdesc->rate_mode == RATE_MODE_OFDM));
  1572. rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
  1573. rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
  1574. test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
  1575. rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
  1576. test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
  1577. rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
  1578. test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
  1579. rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
  1580. rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
  1581. rt2x00_set_field32(&word, TXD_W0_BURST,
  1582. test_bit(ENTRY_TXD_BURST, &txdesc->flags));
  1583. rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
  1584. rt2x00_desc_write(txd, 0, word);
  1585. }
  1586. /*
  1587. * TX data initialization
  1588. */
  1589. static void rt61pci_write_beacon(struct queue_entry *entry)
  1590. {
  1591. struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
  1592. struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
  1593. unsigned int beacon_base;
  1594. u32 reg;
  1595. /*
  1596. * Disable beaconing while we are reloading the beacon data,
  1597. * otherwise we might be sending out invalid data.
  1598. */
  1599. rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
  1600. rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
  1601. rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
  1602. rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
  1603. rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
  1604. /*
  1605. * Write entire beacon with descriptor to register.
  1606. */
  1607. beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
  1608. rt2x00pci_register_multiwrite(rt2x00dev,
  1609. beacon_base,
  1610. skbdesc->desc, skbdesc->desc_len);
  1611. rt2x00pci_register_multiwrite(rt2x00dev,
  1612. beacon_base + skbdesc->desc_len,
  1613. entry->skb->data, entry->skb->len);
  1614. /*
  1615. * Clean up beacon skb.
  1616. */
  1617. dev_kfree_skb_any(entry->skb);
  1618. entry->skb = NULL;
  1619. }
  1620. static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
  1621. const enum data_queue_qid queue)
  1622. {
  1623. u32 reg;
  1624. if (queue == QID_BEACON) {
  1625. /*
  1626. * For Wi-Fi faily generated beacons between participating
  1627. * stations. Set TBTT phase adaptive adjustment step to 8us.
  1628. */
  1629. rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
  1630. rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
  1631. if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
  1632. rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
  1633. rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
  1634. rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
  1635. rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
  1636. }
  1637. return;
  1638. }
  1639. rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
  1640. rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
  1641. rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
  1642. rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
  1643. rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
  1644. rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
  1645. }
  1646. /*
  1647. * RX control handlers
  1648. */
  1649. static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
  1650. {
  1651. u8 offset = rt2x00dev->lna_gain;
  1652. u8 lna;
  1653. lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
  1654. switch (lna) {
  1655. case 3:
  1656. offset += 90;
  1657. break;
  1658. case 2:
  1659. offset += 74;
  1660. break;
  1661. case 1:
  1662. offset += 64;
  1663. break;
  1664. default:
  1665. return 0;
  1666. }
  1667. if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
  1668. if (lna == 3 || lna == 2)
  1669. offset += 10;
  1670. }
  1671. return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
  1672. }
  1673. static void rt61pci_fill_rxdone(struct queue_entry *entry,
  1674. struct rxdone_entry_desc *rxdesc)
  1675. {
  1676. struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
  1677. struct queue_entry_priv_pci *entry_priv = entry->priv_data;
  1678. u32 word0;
  1679. u32 word1;
  1680. rt2x00_desc_read(entry_priv->desc, 0, &word0);
  1681. rt2x00_desc_read(entry_priv->desc, 1, &word1);
  1682. if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
  1683. rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
  1684. if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
  1685. rxdesc->cipher =
  1686. rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
  1687. rxdesc->cipher_status =
  1688. rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
  1689. }
  1690. if (rxdesc->cipher != CIPHER_NONE) {
  1691. _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
  1692. _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
  1693. rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
  1694. _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
  1695. rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
  1696. /*
  1697. * Hardware has stripped IV/EIV data from 802.11 frame during
  1698. * decryption. It has provided the data seperately but rt2x00lib
  1699. * should decide if it should be reinserted.
  1700. */
  1701. rxdesc->flags |= RX_FLAG_IV_STRIPPED;
  1702. /*
  1703. * FIXME: Legacy driver indicates that the frame does
  1704. * contain the Michael Mic. Unfortunately, in rt2x00
  1705. * the MIC seems to be missing completely...
  1706. */
  1707. rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
  1708. if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
  1709. rxdesc->flags |= RX_FLAG_DECRYPTED;
  1710. else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
  1711. rxdesc->flags |= RX_FLAG_MMIC_ERROR;
  1712. }
  1713. /*
  1714. * Obtain the status about this packet.
  1715. * When frame was received with an OFDM bitrate,
  1716. * the signal is the PLCP value. If it was received with
  1717. * a CCK bitrate the signal is the rate in 100kbit/s.
  1718. */
  1719. rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
  1720. rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
  1721. rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
  1722. if (rt2x00_get_field32(word0, RXD_W0_OFDM))
  1723. rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
  1724. else
  1725. rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
  1726. if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
  1727. rxdesc->dev_flags |= RXDONE_MY_BSS;
  1728. }
  1729. /*
  1730. * Interrupt functions.
  1731. */
  1732. static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
  1733. {
  1734. struct data_queue *queue;
  1735. struct queue_entry *entry;
  1736. struct queue_entry *entry_done;
  1737. struct queue_entry_priv_pci *entry_priv;
  1738. struct txdone_entry_desc txdesc;
  1739. u32 word;
  1740. u32 reg;
  1741. u32 old_reg;
  1742. int type;
  1743. int index;
  1744. /*
  1745. * During each loop we will compare the freshly read
  1746. * STA_CSR4 register value with the value read from
  1747. * the previous loop. If the 2 values are equal then
  1748. * we should stop processing because the chance it
  1749. * quite big that the device has been unplugged and
  1750. * we risk going into an endless loop.
  1751. */
  1752. old_reg = 0;
  1753. while (1) {
  1754. rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
  1755. if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
  1756. break;
  1757. if (old_reg == reg)
  1758. break;
  1759. old_reg = reg;
  1760. /*
  1761. * Skip this entry when it contains an invalid
  1762. * queue identication number.
  1763. */
  1764. type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
  1765. queue = rt2x00queue_get_queue(rt2x00dev, type);
  1766. if (unlikely(!queue))
  1767. continue;
  1768. /*
  1769. * Skip this entry when it contains an invalid
  1770. * index number.
  1771. */
  1772. index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
  1773. if (unlikely(index >= queue->limit))
  1774. continue;
  1775. entry = &queue->entries[index];
  1776. entry_priv = entry->priv_data;
  1777. rt2x00_desc_read(entry_priv->desc, 0, &word);
  1778. if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
  1779. !rt2x00_get_field32(word, TXD_W0_VALID))
  1780. return;
  1781. entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
  1782. while (entry != entry_done) {
  1783. /* Catch up.
  1784. * Just report any entries we missed as failed.
  1785. */
  1786. WARNING(rt2x00dev,
  1787. "TX status report missed for entry %d\n",
  1788. entry_done->entry_idx);
  1789. txdesc.flags = 0;
  1790. __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
  1791. txdesc.retry = 0;
  1792. rt2x00lib_txdone(entry_done, &txdesc);
  1793. entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
  1794. }
  1795. /*
  1796. * Obtain the status about this packet.
  1797. */
  1798. txdesc.flags = 0;
  1799. switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
  1800. case 0: /* Success, maybe with retry */
  1801. __set_bit(TXDONE_SUCCESS, &txdesc.flags);
  1802. break;
  1803. case 6: /* Failure, excessive retries */
  1804. __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
  1805. /* Don't break, this is a failed frame! */
  1806. default: /* Failure */
  1807. __set_bit(TXDONE_FAILURE, &txdesc.flags);
  1808. }
  1809. txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
  1810. rt2x00lib_txdone(entry, &txdesc);
  1811. }
  1812. }
  1813. static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
  1814. {
  1815. struct rt2x00_dev *rt2x00dev = dev_instance;
  1816. u32 reg_mcu;
  1817. u32 reg;
  1818. /*
  1819. * Get the interrupt sources & saved to local variable.
  1820. * Write register value back to clear pending interrupts.
  1821. */
  1822. rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
  1823. rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
  1824. rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
  1825. rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
  1826. if (!reg && !reg_mcu)
  1827. return IRQ_NONE;
  1828. if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
  1829. return IRQ_HANDLED;
  1830. /*
  1831. * Handle interrupts, walk through all bits
  1832. * and run the tasks, the bits are checked in order of
  1833. * priority.
  1834. */
  1835. /*
  1836. * 1 - Rx ring done interrupt.
  1837. */
  1838. if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
  1839. rt2x00pci_rxdone(rt2x00dev);
  1840. /*
  1841. * 2 - Tx ring done interrupt.
  1842. */
  1843. if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
  1844. rt61pci_txdone(rt2x00dev);
  1845. /*
  1846. * 3 - Handle MCU command done.
  1847. */
  1848. if (reg_mcu)
  1849. rt2x00pci_register_write(rt2x00dev,
  1850. M2H_CMD_DONE_CSR, 0xffffffff);
  1851. return IRQ_HANDLED;
  1852. }
  1853. /*
  1854. * Device probe functions.
  1855. */
  1856. static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
  1857. {
  1858. struct eeprom_93cx6 eeprom;
  1859. u32 reg;
  1860. u16 word;
  1861. u8 *mac;
  1862. s8 value;
  1863. rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
  1864. eeprom.data = rt2x00dev;
  1865. eeprom.register_read = rt61pci_eepromregister_read;
  1866. eeprom.register_write = rt61pci_eepromregister_write;
  1867. eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
  1868. PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
  1869. eeprom.reg_data_in = 0;
  1870. eeprom.reg_data_out = 0;
  1871. eeprom.reg_data_clock = 0;
  1872. eeprom.reg_chip_select = 0;
  1873. eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
  1874. EEPROM_SIZE / sizeof(u16));
  1875. /*
  1876. * Start validation of the data that has been read.
  1877. */
  1878. mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
  1879. if (!is_valid_ether_addr(mac)) {
  1880. random_ether_addr(mac);
  1881. EEPROM(rt2x00dev, "MAC: %pM\n", mac);
  1882. }
  1883. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
  1884. if (word == 0xffff) {
  1885. rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
  1886. rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
  1887. ANTENNA_B);
  1888. rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
  1889. ANTENNA_B);
  1890. rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
  1891. rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
  1892. rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
  1893. rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
  1894. rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
  1895. EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
  1896. }
  1897. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
  1898. if (word == 0xffff) {
  1899. rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
  1900. rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
  1901. rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0);
  1902. rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0);
  1903. rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
  1904. rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
  1905. rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
  1906. rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
  1907. EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
  1908. }
  1909. rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
  1910. if (word == 0xffff) {
  1911. rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
  1912. LED_MODE_DEFAULT);
  1913. rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
  1914. EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
  1915. }
  1916. rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
  1917. if (word == 0xffff) {
  1918. rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
  1919. rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
  1920. rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
  1921. EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
  1922. }
  1923. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
  1924. if (word == 0xffff) {
  1925. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
  1926. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
  1927. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
  1928. EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
  1929. } else {
  1930. value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
  1931. if (value < -10 || value > 10)
  1932. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
  1933. value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
  1934. if (value < -10 || value > 10)
  1935. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
  1936. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
  1937. }
  1938. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
  1939. if (word == 0xffff) {
  1940. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
  1941. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
  1942. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
  1943. EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
  1944. } else {
  1945. value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
  1946. if (value < -10 || value > 10)
  1947. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
  1948. value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
  1949. if (value < -10 || value > 10)
  1950. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
  1951. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
  1952. }
  1953. return 0;
  1954. }
  1955. static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
  1956. {
  1957. u32 reg;
  1958. u16 value;
  1959. u16 eeprom;
  1960. u16 device;
  1961. /*
  1962. * Read EEPROM word for configuration.
  1963. */
  1964. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
  1965. /*
  1966. * Identify RF chipset.
  1967. * To determine the RT chip we have to read the
  1968. * PCI header of the device.
  1969. */
  1970. pci_read_config_word(to_pci_dev(rt2x00dev->dev),
  1971. PCI_CONFIG_HEADER_DEVICE, &device);
  1972. value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
  1973. rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
  1974. rt2x00_set_chip(rt2x00dev, device, value, reg);
  1975. if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
  1976. !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
  1977. !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
  1978. !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
  1979. ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
  1980. return -ENODEV;
  1981. }
  1982. /*
  1983. * Determine number of antenna's.
  1984. */
  1985. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
  1986. __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
  1987. /*
  1988. * Identify default antenna configuration.
  1989. */
  1990. rt2x00dev->default_ant.tx =
  1991. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
  1992. rt2x00dev->default_ant.rx =
  1993. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
  1994. /*
  1995. * Read the Frame type.
  1996. */
  1997. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
  1998. __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
  1999. /*
  2000. * Detect if this device has an hardware controlled radio.
  2001. */
  2002. #ifdef CONFIG_RT2X00_LIB_RFKILL
  2003. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
  2004. __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
  2005. #endif /* CONFIG_RT2X00_LIB_RFKILL */
  2006. /*
  2007. * Read frequency offset and RF programming sequence.
  2008. */
  2009. rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
  2010. if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
  2011. __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
  2012. rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
  2013. /*
  2014. * Read external LNA informations.
  2015. */
  2016. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
  2017. if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
  2018. __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
  2019. if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
  2020. __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
  2021. /*
  2022. * When working with a RF2529 chip without double antenna
  2023. * the antenna settings should be gathered from the NIC
  2024. * eeprom word.
  2025. */
  2026. if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
  2027. !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
  2028. rt2x00dev->default_ant.rx =
  2029. ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
  2030. rt2x00dev->default_ant.tx =
  2031. ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED);
  2032. if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
  2033. rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
  2034. if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
  2035. rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
  2036. }
  2037. /*
  2038. * Store led settings, for correct led behaviour.
  2039. * If the eeprom value is invalid,
  2040. * switch to default led mode.
  2041. */
  2042. #ifdef CONFIG_RT2X00_LIB_LEDS
  2043. rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
  2044. value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
  2045. rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
  2046. rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
  2047. if (value == LED_MODE_SIGNAL_STRENGTH)
  2048. rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
  2049. LED_TYPE_QUALITY);
  2050. rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
  2051. rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
  2052. rt2x00_get_field16(eeprom,
  2053. EEPROM_LED_POLARITY_GPIO_0));
  2054. rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
  2055. rt2x00_get_field16(eeprom,
  2056. EEPROM_LED_POLARITY_GPIO_1));
  2057. rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
  2058. rt2x00_get_field16(eeprom,
  2059. EEPROM_LED_POLARITY_GPIO_2));
  2060. rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
  2061. rt2x00_get_field16(eeprom,
  2062. EEPROM_LED_POLARITY_GPIO_3));
  2063. rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
  2064. rt2x00_get_field16(eeprom,
  2065. EEPROM_LED_POLARITY_GPIO_4));
  2066. rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
  2067. rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
  2068. rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
  2069. rt2x00_get_field16(eeprom,
  2070. EEPROM_LED_POLARITY_RDY_G));
  2071. rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
  2072. rt2x00_get_field16(eeprom,
  2073. EEPROM_LED_POLARITY_RDY_A));
  2074. #endif /* CONFIG_RT2X00_LIB_LEDS */
  2075. return 0;
  2076. }
  2077. /*
  2078. * RF value list for RF5225 & RF5325
  2079. * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
  2080. */
  2081. static const struct rf_channel rf_vals_noseq[] = {
  2082. { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
  2083. { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
  2084. { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
  2085. { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
  2086. { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
  2087. { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
  2088. { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
  2089. { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
  2090. { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
  2091. { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
  2092. { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
  2093. { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
  2094. { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
  2095. { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
  2096. /* 802.11 UNI / HyperLan 2 */
  2097. { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
  2098. { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
  2099. { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
  2100. { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
  2101. { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
  2102. { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
  2103. { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
  2104. { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
  2105. /* 802.11 HyperLan 2 */
  2106. { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
  2107. { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
  2108. { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
  2109. { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
  2110. { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
  2111. { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
  2112. { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
  2113. { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
  2114. { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
  2115. { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
  2116. /* 802.11 UNII */
  2117. { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
  2118. { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
  2119. { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
  2120. { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
  2121. { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
  2122. { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
  2123. /* MMAC(Japan)J52 ch 34,38,42,46 */
  2124. { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
  2125. { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
  2126. { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
  2127. { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
  2128. };
  2129. /*
  2130. * RF value list for RF5225 & RF5325
  2131. * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
  2132. */
  2133. static const struct rf_channel rf_vals_seq[] = {
  2134. { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
  2135. { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
  2136. { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
  2137. { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
  2138. { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
  2139. { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
  2140. { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
  2141. { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
  2142. { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
  2143. { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
  2144. { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
  2145. { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
  2146. { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
  2147. { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
  2148. /* 802.11 UNI / HyperLan 2 */
  2149. { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
  2150. { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
  2151. { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
  2152. { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
  2153. { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
  2154. { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
  2155. { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
  2156. { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
  2157. /* 802.11 HyperLan 2 */
  2158. { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
  2159. { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
  2160. { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
  2161. { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
  2162. { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
  2163. { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
  2164. { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
  2165. { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
  2166. { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
  2167. { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
  2168. /* 802.11 UNII */
  2169. { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
  2170. { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
  2171. { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
  2172. { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
  2173. { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
  2174. { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
  2175. /* MMAC(Japan)J52 ch 34,38,42,46 */
  2176. { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
  2177. { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
  2178. { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
  2179. { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
  2180. };
  2181. static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
  2182. {
  2183. struct hw_mode_spec *spec = &rt2x00dev->spec;
  2184. struct channel_info *info;
  2185. char *tx_power;
  2186. unsigned int i;
  2187. /*
  2188. * Initialize all hw fields.
  2189. */
  2190. rt2x00dev->hw->flags =
  2191. IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
  2192. IEEE80211_HW_SIGNAL_DBM |
  2193. IEEE80211_HW_SUPPORTS_PS |
  2194. IEEE80211_HW_PS_NULLFUNC_STACK;
  2195. rt2x00dev->hw->extra_tx_headroom = 0;
  2196. SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
  2197. SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
  2198. rt2x00_eeprom_addr(rt2x00dev,
  2199. EEPROM_MAC_ADDR_0));
  2200. /*
  2201. * Initialize hw_mode information.
  2202. */
  2203. spec->supported_bands = SUPPORT_BAND_2GHZ;
  2204. spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
  2205. if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
  2206. spec->num_channels = 14;
  2207. spec->channels = rf_vals_noseq;
  2208. } else {
  2209. spec->num_channels = 14;
  2210. spec->channels = rf_vals_seq;
  2211. }
  2212. if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
  2213. rt2x00_rf(&rt2x00dev->chip, RF5325)) {
  2214. spec->supported_bands |= SUPPORT_BAND_5GHZ;
  2215. spec->num_channels = ARRAY_SIZE(rf_vals_seq);
  2216. }
  2217. /*
  2218. * Create channel information array
  2219. */
  2220. info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
  2221. if (!info)
  2222. return -ENOMEM;
  2223. spec->channels_info = info;
  2224. tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
  2225. for (i = 0; i < 14; i++)
  2226. info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
  2227. if (spec->num_channels > 14) {
  2228. tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
  2229. for (i = 14; i < spec->num_channels; i++)
  2230. info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
  2231. }
  2232. return 0;
  2233. }
  2234. static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
  2235. {
  2236. int retval;
  2237. /*
  2238. * Allocate eeprom data.
  2239. */
  2240. retval = rt61pci_validate_eeprom(rt2x00dev);
  2241. if (retval)
  2242. return retval;
  2243. retval = rt61pci_init_eeprom(rt2x00dev);
  2244. if (retval)
  2245. return retval;
  2246. /*
  2247. * Initialize hw specifications.
  2248. */
  2249. retval = rt61pci_probe_hw_mode(rt2x00dev);
  2250. if (retval)
  2251. return retval;
  2252. /*
  2253. * This device requires firmware and DMA mapped skbs.
  2254. */
  2255. __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
  2256. __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
  2257. if (!modparam_nohwcrypt)
  2258. __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
  2259. /*
  2260. * Set the rssi offset.
  2261. */
  2262. rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
  2263. return 0;
  2264. }
  2265. /*
  2266. * IEEE80211 stack callback functions.
  2267. */
  2268. static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
  2269. const struct ieee80211_tx_queue_params *params)
  2270. {
  2271. struct rt2x00_dev *rt2x00dev = hw->priv;
  2272. struct data_queue *queue;
  2273. struct rt2x00_field32 field;
  2274. int retval;
  2275. u32 reg;
  2276. /*
  2277. * First pass the configuration through rt2x00lib, that will
  2278. * update the queue settings and validate the input. After that
  2279. * we are free to update the registers based on the value
  2280. * in the queue parameter.
  2281. */
  2282. retval = rt2x00mac_conf_tx(hw, queue_idx, params);
  2283. if (retval)
  2284. return retval;
  2285. queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
  2286. /* Update WMM TXOP register */
  2287. if (queue_idx < 2) {
  2288. field.bit_offset = queue_idx * 16;
  2289. field.bit_mask = 0xffff << field.bit_offset;
  2290. rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
  2291. rt2x00_set_field32(&reg, field, queue->txop);
  2292. rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
  2293. } else if (queue_idx < 4) {
  2294. field.bit_offset = (queue_idx - 2) * 16;
  2295. field.bit_mask = 0xffff << field.bit_offset;
  2296. rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
  2297. rt2x00_set_field32(&reg, field, queue->txop);
  2298. rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
  2299. }
  2300. /* Update WMM registers */
  2301. field.bit_offset = queue_idx * 4;
  2302. field.bit_mask = 0xf << field.bit_offset;
  2303. rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, &reg);
  2304. rt2x00_set_field32(&reg, field, queue->aifs);
  2305. rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
  2306. rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, &reg);
  2307. rt2x00_set_field32(&reg, field, queue->cw_min);
  2308. rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
  2309. rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, &reg);
  2310. rt2x00_set_field32(&reg, field, queue->cw_max);
  2311. rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
  2312. return 0;
  2313. }
  2314. static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
  2315. {
  2316. struct rt2x00_dev *rt2x00dev = hw->priv;
  2317. u64 tsf;
  2318. u32 reg;
  2319. rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
  2320. tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
  2321. rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
  2322. tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
  2323. return tsf;
  2324. }
  2325. static const struct ieee80211_ops rt61pci_mac80211_ops = {
  2326. .tx = rt2x00mac_tx,
  2327. .start = rt2x00mac_start,
  2328. .stop = rt2x00mac_stop,
  2329. .add_interface = rt2x00mac_add_interface,
  2330. .remove_interface = rt2x00mac_remove_interface,
  2331. .config = rt2x00mac_config,
  2332. .config_interface = rt2x00mac_config_interface,
  2333. .configure_filter = rt2x00mac_configure_filter,
  2334. .set_key = rt2x00mac_set_key,
  2335. .get_stats = rt2x00mac_get_stats,
  2336. .bss_info_changed = rt2x00mac_bss_info_changed,
  2337. .conf_tx = rt61pci_conf_tx,
  2338. .get_tx_stats = rt2x00mac_get_tx_stats,
  2339. .get_tsf = rt61pci_get_tsf,
  2340. };
  2341. static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
  2342. .irq_handler = rt61pci_interrupt,
  2343. .probe_hw = rt61pci_probe_hw,
  2344. .get_firmware_name = rt61pci_get_firmware_name,
  2345. .get_firmware_crc = rt61pci_get_firmware_crc,
  2346. .load_firmware = rt61pci_load_firmware,
  2347. .initialize = rt2x00pci_initialize,
  2348. .uninitialize = rt2x00pci_uninitialize,
  2349. .get_entry_state = rt61pci_get_entry_state,
  2350. .clear_entry = rt61pci_clear_entry,
  2351. .set_device_state = rt61pci_set_device_state,
  2352. .rfkill_poll = rt61pci_rfkill_poll,
  2353. .link_stats = rt61pci_link_stats,
  2354. .reset_tuner = rt61pci_reset_tuner,
  2355. .link_tuner = rt61pci_link_tuner,
  2356. .write_tx_desc = rt61pci_write_tx_desc,
  2357. .write_tx_data = rt2x00pci_write_tx_data,
  2358. .write_beacon = rt61pci_write_beacon,
  2359. .kick_tx_queue = rt61pci_kick_tx_queue,
  2360. .fill_rxdone = rt61pci_fill_rxdone,
  2361. .config_shared_key = rt61pci_config_shared_key,
  2362. .config_pairwise_key = rt61pci_config_pairwise_key,
  2363. .config_filter = rt61pci_config_filter,
  2364. .config_intf = rt61pci_config_intf,
  2365. .config_erp = rt61pci_config_erp,
  2366. .config_ant = rt61pci_config_ant,
  2367. .config = rt61pci_config,
  2368. };
  2369. static const struct data_queue_desc rt61pci_queue_rx = {
  2370. .entry_num = RX_ENTRIES,
  2371. .data_size = DATA_FRAME_SIZE,
  2372. .desc_size = RXD_DESC_SIZE,
  2373. .priv_size = sizeof(struct queue_entry_priv_pci),
  2374. };
  2375. static const struct data_queue_desc rt61pci_queue_tx = {
  2376. .entry_num = TX_ENTRIES,
  2377. .data_size = DATA_FRAME_SIZE,
  2378. .desc_size = TXD_DESC_SIZE,
  2379. .priv_size = sizeof(struct queue_entry_priv_pci),
  2380. };
  2381. static const struct data_queue_desc rt61pci_queue_bcn = {
  2382. .entry_num = 4 * BEACON_ENTRIES,
  2383. .data_size = 0, /* No DMA required for beacons */
  2384. .desc_size = TXINFO_SIZE,
  2385. .priv_size = sizeof(struct queue_entry_priv_pci),
  2386. };
  2387. static const struct rt2x00_ops rt61pci_ops = {
  2388. .name = KBUILD_MODNAME,
  2389. .max_sta_intf = 1,
  2390. .max_ap_intf = 4,
  2391. .eeprom_size = EEPROM_SIZE,
  2392. .rf_size = RF_SIZE,
  2393. .tx_queues = NUM_TX_QUEUES,
  2394. .rx = &rt61pci_queue_rx,
  2395. .tx = &rt61pci_queue_tx,
  2396. .bcn = &rt61pci_queue_bcn,
  2397. .lib = &rt61pci_rt2x00_ops,
  2398. .hw = &rt61pci_mac80211_ops,
  2399. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  2400. .debugfs = &rt61pci_rt2x00debug,
  2401. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  2402. };
  2403. /*
  2404. * RT61pci module information.
  2405. */
  2406. static struct pci_device_id rt61pci_device_table[] = {
  2407. /* RT2561s */
  2408. { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
  2409. /* RT2561 v2 */
  2410. { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
  2411. /* RT2661 */
  2412. { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
  2413. { 0, }
  2414. };
  2415. MODULE_AUTHOR(DRV_PROJECT);
  2416. MODULE_VERSION(DRV_VERSION);
  2417. MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
  2418. MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
  2419. "PCI & PCMCIA chipset based cards");
  2420. MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
  2421. MODULE_FIRMWARE(FIRMWARE_RT2561);
  2422. MODULE_FIRMWARE(FIRMWARE_RT2561s);
  2423. MODULE_FIRMWARE(FIRMWARE_RT2661);
  2424. MODULE_LICENSE("GPL");
  2425. static struct pci_driver rt61pci_driver = {
  2426. .name = KBUILD_MODNAME,
  2427. .id_table = rt61pci_device_table,
  2428. .probe = rt2x00pci_probe,
  2429. .remove = __devexit_p(rt2x00pci_remove),
  2430. .suspend = rt2x00pci_suspend,
  2431. .resume = rt2x00pci_resume,
  2432. };
  2433. static int __init rt61pci_init(void)
  2434. {
  2435. return pci_register_driver(&rt61pci_driver);
  2436. }
  2437. static void __exit rt61pci_exit(void)
  2438. {
  2439. pci_unregister_driver(&rt61pci_driver);
  2440. }
  2441. module_init(rt61pci_init);
  2442. module_exit(rt61pci_exit);