iwl-4965.c 101 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  23. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24. *
  25. *****************************************************************************/
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/version.h>
  29. #include <linux/init.h>
  30. #include <linux/pci.h>
  31. #include <linux/dma-mapping.h>
  32. #include <linux/delay.h>
  33. #include <linux/skbuff.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/wireless.h>
  36. #include <net/mac80211.h>
  37. #include <linux/etherdevice.h>
  38. #include <asm/unaligned.h>
  39. #include "iwl-eeprom.h"
  40. #include "iwl-dev.h"
  41. #include "iwl-core.h"
  42. #include "iwl-io.h"
  43. #include "iwl-helpers.h"
  44. #include "iwl-calib.h"
  45. #include "iwl-sta.h"
  46. /* module parameters */
  47. static struct iwl_mod_params iwl4965_mod_params = {
  48. .num_of_queues = IWL49_NUM_QUEUES,
  49. .enable_qos = 1,
  50. .amsdu_size_8K = 1,
  51. .restart_fw = 1,
  52. /* the rest are 0 by default */
  53. };
  54. /* check contents of special bootstrap uCode SRAM */
  55. static int iwl4965_verify_bsm(struct iwl_priv *priv)
  56. {
  57. __le32 *image = priv->ucode_boot.v_addr;
  58. u32 len = priv->ucode_boot.len;
  59. u32 reg;
  60. u32 val;
  61. IWL_DEBUG_INFO("Begin verify bsm\n");
  62. /* verify BSM SRAM contents */
  63. val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
  64. for (reg = BSM_SRAM_LOWER_BOUND;
  65. reg < BSM_SRAM_LOWER_BOUND + len;
  66. reg += sizeof(u32), image++) {
  67. val = iwl_read_prph(priv, reg);
  68. if (val != le32_to_cpu(*image)) {
  69. IWL_ERROR("BSM uCode verification failed at "
  70. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  71. BSM_SRAM_LOWER_BOUND,
  72. reg - BSM_SRAM_LOWER_BOUND, len,
  73. val, le32_to_cpu(*image));
  74. return -EIO;
  75. }
  76. }
  77. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  78. return 0;
  79. }
  80. /**
  81. * iwl4965_load_bsm - Load bootstrap instructions
  82. *
  83. * BSM operation:
  84. *
  85. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  86. * in special SRAM that does not power down during RFKILL. When powering back
  87. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  88. * the bootstrap program into the on-board processor, and starts it.
  89. *
  90. * The bootstrap program loads (via DMA) instructions and data for a new
  91. * program from host DRAM locations indicated by the host driver in the
  92. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  93. * automatically.
  94. *
  95. * When initializing the NIC, the host driver points the BSM to the
  96. * "initialize" uCode image. This uCode sets up some internal data, then
  97. * notifies host via "initialize alive" that it is complete.
  98. *
  99. * The host then replaces the BSM_DRAM_* pointer values to point to the
  100. * normal runtime uCode instructions and a backup uCode data cache buffer
  101. * (filled initially with starting data values for the on-board processor),
  102. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  103. * which begins normal operation.
  104. *
  105. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  106. * the backup data cache in DRAM before SRAM is powered down.
  107. *
  108. * When powering back up, the BSM loads the bootstrap program. This reloads
  109. * the runtime uCode instructions and the backup data cache into SRAM,
  110. * and re-launches the runtime uCode from where it left off.
  111. */
  112. static int iwl4965_load_bsm(struct iwl_priv *priv)
  113. {
  114. __le32 *image = priv->ucode_boot.v_addr;
  115. u32 len = priv->ucode_boot.len;
  116. dma_addr_t pinst;
  117. dma_addr_t pdata;
  118. u32 inst_len;
  119. u32 data_len;
  120. int i;
  121. u32 done;
  122. u32 reg_offset;
  123. int ret;
  124. IWL_DEBUG_INFO("Begin load bsm\n");
  125. priv->ucode_type = UCODE_RT;
  126. /* make sure bootstrap program is no larger than BSM's SRAM size */
  127. if (len > IWL_MAX_BSM_SIZE)
  128. return -EINVAL;
  129. /* Tell bootstrap uCode where to find the "Initialize" uCode
  130. * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
  131. * NOTE: iwl_init_alive_start() will replace these values,
  132. * after the "initialize" uCode has run, to point to
  133. * runtime/protocol instructions and backup data cache.
  134. */
  135. pinst = priv->ucode_init.p_addr >> 4;
  136. pdata = priv->ucode_init_data.p_addr >> 4;
  137. inst_len = priv->ucode_init.len;
  138. data_len = priv->ucode_init_data.len;
  139. ret = iwl_grab_nic_access(priv);
  140. if (ret)
  141. return ret;
  142. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  143. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  144. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  145. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  146. /* Fill BSM memory with bootstrap instructions */
  147. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  148. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  149. reg_offset += sizeof(u32), image++)
  150. _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
  151. ret = iwl4965_verify_bsm(priv);
  152. if (ret) {
  153. iwl_release_nic_access(priv);
  154. return ret;
  155. }
  156. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  157. iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  158. iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
  159. iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  160. /* Load bootstrap code into instruction SRAM now,
  161. * to prepare to load "initialize" uCode */
  162. iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
  163. /* Wait for load of bootstrap uCode to finish */
  164. for (i = 0; i < 100; i++) {
  165. done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
  166. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  167. break;
  168. udelay(10);
  169. }
  170. if (i < 100)
  171. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  172. else {
  173. IWL_ERROR("BSM write did not complete!\n");
  174. return -EIO;
  175. }
  176. /* Enable future boot loads whenever power management unit triggers it
  177. * (e.g. when powering back up after power-save shutdown) */
  178. iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
  179. iwl_release_nic_access(priv);
  180. return 0;
  181. }
  182. /**
  183. * iwl4965_set_ucode_ptrs - Set uCode address location
  184. *
  185. * Tell initialization uCode where to find runtime uCode.
  186. *
  187. * BSM registers initially contain pointers to initialization uCode.
  188. * We need to replace them to load runtime uCode inst and data,
  189. * and to save runtime data when powering down.
  190. */
  191. static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
  192. {
  193. dma_addr_t pinst;
  194. dma_addr_t pdata;
  195. unsigned long flags;
  196. int ret = 0;
  197. /* bits 35:4 for 4965 */
  198. pinst = priv->ucode_code.p_addr >> 4;
  199. pdata = priv->ucode_data_backup.p_addr >> 4;
  200. spin_lock_irqsave(&priv->lock, flags);
  201. ret = iwl_grab_nic_access(priv);
  202. if (ret) {
  203. spin_unlock_irqrestore(&priv->lock, flags);
  204. return ret;
  205. }
  206. /* Tell bootstrap uCode where to find image to load */
  207. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  208. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  209. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  210. priv->ucode_data.len);
  211. /* Inst bytecount must be last to set up, bit 31 signals uCode
  212. * that all new ptr/size info is in place */
  213. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  214. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  215. iwl_release_nic_access(priv);
  216. spin_unlock_irqrestore(&priv->lock, flags);
  217. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  218. return ret;
  219. }
  220. /**
  221. * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
  222. *
  223. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  224. *
  225. * The 4965 "initialize" ALIVE reply contains calibration data for:
  226. * Voltage, temperature, and MIMO tx gain correction, now stored in priv
  227. * (3945 does not contain this data).
  228. *
  229. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  230. */
  231. static void iwl4965_init_alive_start(struct iwl_priv *priv)
  232. {
  233. /* Check alive response for "valid" sign from uCode */
  234. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  235. /* We had an error bringing up the hardware, so take it
  236. * all the way back down so we can try again */
  237. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  238. goto restart;
  239. }
  240. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  241. * This is a paranoid check, because we would not have gotten the
  242. * "initialize" alive if code weren't properly loaded. */
  243. if (iwl_verify_ucode(priv)) {
  244. /* Runtime instruction load was bad;
  245. * take it all the way back down so we can try again */
  246. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  247. goto restart;
  248. }
  249. /* Calculate temperature */
  250. priv->temperature = iwl4965_get_temperature(priv);
  251. /* Send pointers to protocol/runtime uCode image ... init code will
  252. * load and launch runtime uCode, which will send us another "Alive"
  253. * notification. */
  254. IWL_DEBUG_INFO("Initialization Alive received.\n");
  255. if (iwl4965_set_ucode_ptrs(priv)) {
  256. /* Runtime instruction load won't happen;
  257. * take it all the way back down so we can try again */
  258. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  259. goto restart;
  260. }
  261. return;
  262. restart:
  263. queue_work(priv->workqueue, &priv->restart);
  264. }
  265. static int is_fat_channel(__le32 rxon_flags)
  266. {
  267. return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
  268. (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
  269. }
  270. int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
  271. {
  272. int idx = 0;
  273. /* 4965 HT rate format */
  274. if (rate_n_flags & RATE_MCS_HT_MSK) {
  275. idx = (rate_n_flags & 0xff);
  276. if (idx >= IWL_RATE_MIMO2_6M_PLCP)
  277. idx = idx - IWL_RATE_MIMO2_6M_PLCP;
  278. idx += IWL_FIRST_OFDM_RATE;
  279. /* skip 9M not supported in ht*/
  280. if (idx >= IWL_RATE_9M_INDEX)
  281. idx += 1;
  282. if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
  283. return idx;
  284. /* 4965 legacy rate format, search for match in table */
  285. } else {
  286. for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
  287. if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
  288. return idx;
  289. }
  290. return -1;
  291. }
  292. /**
  293. * translate ucode response to mac80211 tx status control values
  294. */
  295. void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
  296. struct ieee80211_tx_info *control)
  297. {
  298. int rate_index;
  299. control->antenna_sel_tx =
  300. ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
  301. if (rate_n_flags & RATE_MCS_HT_MSK)
  302. control->flags |= IEEE80211_TX_CTL_OFDM_HT;
  303. if (rate_n_flags & RATE_MCS_GF_MSK)
  304. control->flags |= IEEE80211_TX_CTL_GREEN_FIELD;
  305. if (rate_n_flags & RATE_MCS_FAT_MSK)
  306. control->flags |= IEEE80211_TX_CTL_40_MHZ_WIDTH;
  307. if (rate_n_flags & RATE_MCS_DUP_MSK)
  308. control->flags |= IEEE80211_TX_CTL_DUP_DATA;
  309. if (rate_n_flags & RATE_MCS_SGI_MSK)
  310. control->flags |= IEEE80211_TX_CTL_SHORT_GI;
  311. rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
  312. if (control->band == IEEE80211_BAND_5GHZ)
  313. rate_index -= IWL_FIRST_OFDM_RATE;
  314. control->tx_rate_idx = rate_index;
  315. }
  316. /*
  317. * EEPROM handlers
  318. */
  319. static int iwl4965_eeprom_check_version(struct iwl_priv *priv)
  320. {
  321. u16 eeprom_ver;
  322. u16 calib_ver;
  323. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  324. calib_ver = iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
  325. if (eeprom_ver < EEPROM_4965_EEPROM_VERSION ||
  326. calib_ver < EEPROM_4965_TX_POWER_VERSION)
  327. goto err;
  328. return 0;
  329. err:
  330. IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
  331. eeprom_ver, EEPROM_4965_EEPROM_VERSION,
  332. calib_ver, EEPROM_4965_TX_POWER_VERSION);
  333. return -EINVAL;
  334. }
  335. int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  336. {
  337. int ret;
  338. unsigned long flags;
  339. spin_lock_irqsave(&priv->lock, flags);
  340. ret = iwl_grab_nic_access(priv);
  341. if (ret) {
  342. spin_unlock_irqrestore(&priv->lock, flags);
  343. return ret;
  344. }
  345. if (src == IWL_PWR_SRC_VAUX) {
  346. u32 val;
  347. ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
  348. &val);
  349. if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
  350. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  351. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  352. ~APMG_PS_CTRL_MSK_PWR_SRC);
  353. }
  354. } else {
  355. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  356. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  357. ~APMG_PS_CTRL_MSK_PWR_SRC);
  358. }
  359. iwl_release_nic_access(priv);
  360. spin_unlock_irqrestore(&priv->lock, flags);
  361. return ret;
  362. }
  363. /*
  364. * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
  365. * must be called under priv->lock and mac access
  366. */
  367. static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
  368. {
  369. iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
  370. }
  371. static int iwl4965_apm_init(struct iwl_priv *priv)
  372. {
  373. int ret = 0;
  374. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  375. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  376. /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
  377. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  378. CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  379. /* set "initialization complete" bit to move adapter
  380. * D0U* --> D0A* state */
  381. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  382. /* wait for clock stabilization */
  383. ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
  384. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  385. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  386. if (ret < 0) {
  387. IWL_DEBUG_INFO("Failed to init the card\n");
  388. goto out;
  389. }
  390. ret = iwl_grab_nic_access(priv);
  391. if (ret)
  392. goto out;
  393. /* enable DMA */
  394. iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
  395. APMG_CLK_VAL_BSM_CLK_RQT);
  396. udelay(20);
  397. /* disable L1-Active */
  398. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  399. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  400. iwl_release_nic_access(priv);
  401. out:
  402. return ret;
  403. }
  404. static void iwl4965_nic_config(struct iwl_priv *priv)
  405. {
  406. unsigned long flags;
  407. u32 val;
  408. u16 radio_cfg;
  409. u8 val_link;
  410. spin_lock_irqsave(&priv->lock, flags);
  411. if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
  412. pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
  413. /* Enable No Snoop field */
  414. pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
  415. val & ~(1 << 11));
  416. }
  417. pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
  418. /* L1 is enabled by BIOS */
  419. if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN)
  420. /* diable L0S disabled L1A enabled */
  421. iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
  422. else
  423. /* L0S enabled L1A disabled */
  424. iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
  425. radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
  426. /* write radio config values to register */
  427. if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
  428. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  429. EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
  430. EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
  431. EEPROM_RF_CFG_DASH_MSK(radio_cfg));
  432. /* set CSR_HW_CONFIG_REG for uCode use */
  433. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  434. CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
  435. CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
  436. priv->calib_info = (struct iwl_eeprom_calib_info *)
  437. iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
  438. spin_unlock_irqrestore(&priv->lock, flags);
  439. }
  440. static int iwl4965_apm_stop_master(struct iwl_priv *priv)
  441. {
  442. int ret = 0;
  443. unsigned long flags;
  444. spin_lock_irqsave(&priv->lock, flags);
  445. /* set stop master bit */
  446. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  447. ret = iwl_poll_bit(priv, CSR_RESET,
  448. CSR_RESET_REG_FLAG_MASTER_DISABLED,
  449. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  450. if (ret < 0)
  451. goto out;
  452. out:
  453. spin_unlock_irqrestore(&priv->lock, flags);
  454. IWL_DEBUG_INFO("stop master\n");
  455. return ret;
  456. }
  457. static void iwl4965_apm_stop(struct iwl_priv *priv)
  458. {
  459. unsigned long flags;
  460. iwl4965_apm_stop_master(priv);
  461. spin_lock_irqsave(&priv->lock, flags);
  462. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  463. udelay(10);
  464. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  465. spin_unlock_irqrestore(&priv->lock, flags);
  466. }
  467. static int iwl4965_apm_reset(struct iwl_priv *priv)
  468. {
  469. int ret = 0;
  470. unsigned long flags;
  471. iwl4965_apm_stop_master(priv);
  472. spin_lock_irqsave(&priv->lock, flags);
  473. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  474. udelay(10);
  475. /* FIXME: put here L1A -L0S w/a */
  476. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  477. ret = iwl_poll_bit(priv, CSR_RESET,
  478. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  479. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
  480. if (ret)
  481. goto out;
  482. udelay(10);
  483. ret = iwl_grab_nic_access(priv);
  484. if (ret)
  485. goto out;
  486. /* Enable DMA and BSM Clock */
  487. iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT |
  488. APMG_CLK_VAL_BSM_CLK_RQT);
  489. udelay(10);
  490. /* disable L1A */
  491. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  492. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  493. iwl_release_nic_access(priv);
  494. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  495. wake_up_interruptible(&priv->wait_command_queue);
  496. out:
  497. spin_unlock_irqrestore(&priv->lock, flags);
  498. return ret;
  499. }
  500. #define REG_RECALIB_PERIOD (60)
  501. void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
  502. {
  503. struct iwl4965_ct_kill_config cmd;
  504. unsigned long flags;
  505. int ret = 0;
  506. spin_lock_irqsave(&priv->lock, flags);
  507. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  508. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  509. spin_unlock_irqrestore(&priv->lock, flags);
  510. cmd.critical_temperature_R =
  511. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  512. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  513. sizeof(cmd), &cmd);
  514. if (ret)
  515. IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
  516. else
  517. IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
  518. "critical temperature is %d\n",
  519. cmd.critical_temperature_R);
  520. }
  521. /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
  522. * Called after every association, but this runs only once!
  523. * ... once chain noise is calibrated the first time, it's good forever. */
  524. static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
  525. {
  526. struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
  527. if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
  528. struct iwl4965_calibration_cmd cmd;
  529. memset(&cmd, 0, sizeof(cmd));
  530. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  531. cmd.diff_gain_a = 0;
  532. cmd.diff_gain_b = 0;
  533. cmd.diff_gain_c = 0;
  534. if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  535. sizeof(cmd), &cmd))
  536. IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
  537. data->state = IWL_CHAIN_NOISE_ACCUMULATE;
  538. IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
  539. }
  540. }
  541. static void iwl4965_gain_computation(struct iwl_priv *priv,
  542. u32 *average_noise,
  543. u16 min_average_noise_antenna_i,
  544. u32 min_average_noise)
  545. {
  546. int i, ret;
  547. struct iwl_chain_noise_data *data = &priv->chain_noise_data;
  548. data->delta_gain_code[min_average_noise_antenna_i] = 0;
  549. for (i = 0; i < NUM_RX_CHAINS; i++) {
  550. s32 delta_g = 0;
  551. if (!(data->disconn_array[i]) &&
  552. (data->delta_gain_code[i] ==
  553. CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
  554. delta_g = average_noise[i] - min_average_noise;
  555. data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
  556. data->delta_gain_code[i] =
  557. min(data->delta_gain_code[i],
  558. (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
  559. data->delta_gain_code[i] =
  560. (data->delta_gain_code[i] | (1 << 2));
  561. } else {
  562. data->delta_gain_code[i] = 0;
  563. }
  564. }
  565. IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
  566. data->delta_gain_code[0],
  567. data->delta_gain_code[1],
  568. data->delta_gain_code[2]);
  569. /* Differential gain gets sent to uCode only once */
  570. if (!data->radio_write) {
  571. struct iwl4965_calibration_cmd cmd;
  572. data->radio_write = 1;
  573. memset(&cmd, 0, sizeof(cmd));
  574. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  575. cmd.diff_gain_a = data->delta_gain_code[0];
  576. cmd.diff_gain_b = data->delta_gain_code[1];
  577. cmd.diff_gain_c = data->delta_gain_code[2];
  578. ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  579. sizeof(cmd), &cmd);
  580. if (ret)
  581. IWL_DEBUG_CALIB("fail sending cmd "
  582. "REPLY_PHY_CALIBRATION_CMD \n");
  583. /* TODO we might want recalculate
  584. * rx_chain in rxon cmd */
  585. /* Mark so we run this algo only once! */
  586. data->state = IWL_CHAIN_NOISE_CALIBRATED;
  587. }
  588. data->chain_noise_a = 0;
  589. data->chain_noise_b = 0;
  590. data->chain_noise_c = 0;
  591. data->chain_signal_a = 0;
  592. data->chain_signal_b = 0;
  593. data->chain_signal_c = 0;
  594. data->beacon_count = 0;
  595. }
  596. static void iwl4965_bg_txpower_work(struct work_struct *work)
  597. {
  598. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  599. txpower_work);
  600. /* If a scan happened to start before we got here
  601. * then just return; the statistics notification will
  602. * kick off another scheduled work to compensate for
  603. * any temperature delta we missed here. */
  604. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  605. test_bit(STATUS_SCANNING, &priv->status))
  606. return;
  607. mutex_lock(&priv->mutex);
  608. /* Regardless of if we are assocaited, we must reconfigure the
  609. * TX power since frames can be sent on non-radar channels while
  610. * not associated */
  611. iwl4965_hw_reg_send_txpower(priv);
  612. /* Update last_temperature to keep is_calib_needed from running
  613. * when it isn't needed... */
  614. priv->last_temperature = priv->temperature;
  615. mutex_unlock(&priv->mutex);
  616. }
  617. /*
  618. * Acquire priv->lock before calling this function !
  619. */
  620. static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
  621. {
  622. iwl_write_direct32(priv, HBUS_TARG_WRPTR,
  623. (index & 0xff) | (txq_id << 8));
  624. iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
  625. }
  626. /**
  627. * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
  628. * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
  629. * @scd_retry: (1) Indicates queue will be used in aggregation mode
  630. *
  631. * NOTE: Acquire priv->lock before calling this function !
  632. */
  633. static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
  634. struct iwl_tx_queue *txq,
  635. int tx_fifo_id, int scd_retry)
  636. {
  637. int txq_id = txq->q.id;
  638. /* Find out whether to activate Tx queue */
  639. int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
  640. /* Set up and activate */
  641. iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
  642. (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
  643. (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
  644. (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
  645. (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
  646. IWL49_SCD_QUEUE_STTS_REG_MSK);
  647. txq->sched_retry = scd_retry;
  648. IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
  649. active ? "Activate" : "Deactivate",
  650. scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
  651. }
  652. static const u16 default_queue_to_tx_fifo[] = {
  653. IWL_TX_FIFO_AC3,
  654. IWL_TX_FIFO_AC2,
  655. IWL_TX_FIFO_AC1,
  656. IWL_TX_FIFO_AC0,
  657. IWL49_CMD_FIFO_NUM,
  658. IWL_TX_FIFO_HCCA_1,
  659. IWL_TX_FIFO_HCCA_2
  660. };
  661. int iwl4965_alive_notify(struct iwl_priv *priv)
  662. {
  663. u32 a;
  664. int i = 0;
  665. unsigned long flags;
  666. int ret;
  667. spin_lock_irqsave(&priv->lock, flags);
  668. ret = iwl_grab_nic_access(priv);
  669. if (ret) {
  670. spin_unlock_irqrestore(&priv->lock, flags);
  671. return ret;
  672. }
  673. /* Clear 4965's internal Tx Scheduler data base */
  674. priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
  675. a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
  676. for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
  677. iwl_write_targ_mem(priv, a, 0);
  678. for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
  679. iwl_write_targ_mem(priv, a, 0);
  680. for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
  681. iwl_write_targ_mem(priv, a, 0);
  682. /* Tel 4965 where to find Tx byte count tables */
  683. iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
  684. (priv->shared_phys +
  685. offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
  686. /* Disable chain mode for all queues */
  687. iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
  688. /* Initialize each Tx queue (including the command queue) */
  689. for (i = 0; i < priv->hw_params.max_txq_num; i++) {
  690. /* TFD circular buffer read/write indexes */
  691. iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
  692. iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
  693. /* Max Tx Window size for Scheduler-ACK mode */
  694. iwl_write_targ_mem(priv, priv->scd_base_addr +
  695. IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
  696. (SCD_WIN_SIZE <<
  697. IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  698. IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  699. /* Frame limit */
  700. iwl_write_targ_mem(priv, priv->scd_base_addr +
  701. IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
  702. sizeof(u32),
  703. (SCD_FRAME_LIMIT <<
  704. IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
  705. IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  706. }
  707. iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
  708. (1 << priv->hw_params.max_txq_num) - 1);
  709. /* Activate all Tx DMA/FIFO channels */
  710. priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
  711. iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
  712. /* Map each Tx/cmd queue to its corresponding fifo */
  713. for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
  714. int ac = default_queue_to_tx_fifo[i];
  715. iwl_txq_ctx_activate(priv, i);
  716. iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
  717. }
  718. iwl_release_nic_access(priv);
  719. spin_unlock_irqrestore(&priv->lock, flags);
  720. return ret;
  721. }
  722. static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
  723. .min_nrg_cck = 97,
  724. .max_nrg_cck = 0,
  725. .auto_corr_min_ofdm = 85,
  726. .auto_corr_min_ofdm_mrc = 170,
  727. .auto_corr_min_ofdm_x1 = 105,
  728. .auto_corr_min_ofdm_mrc_x1 = 220,
  729. .auto_corr_max_ofdm = 120,
  730. .auto_corr_max_ofdm_mrc = 210,
  731. .auto_corr_max_ofdm_x1 = 140,
  732. .auto_corr_max_ofdm_mrc_x1 = 270,
  733. .auto_corr_min_cck = 125,
  734. .auto_corr_max_cck = 200,
  735. .auto_corr_min_cck_mrc = 200,
  736. .auto_corr_max_cck_mrc = 400,
  737. .nrg_th_cck = 100,
  738. .nrg_th_ofdm = 100,
  739. };
  740. /**
  741. * iwl4965_hw_set_hw_params
  742. *
  743. * Called when initializing driver
  744. */
  745. int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
  746. {
  747. if ((priv->cfg->mod_params->num_of_queues > IWL49_NUM_QUEUES) ||
  748. (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
  749. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  750. IWL_MIN_NUM_QUEUES, IWL49_NUM_QUEUES);
  751. return -EINVAL;
  752. }
  753. priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
  754. priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
  755. priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
  756. priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
  757. if (priv->cfg->mod_params->amsdu_size_8K)
  758. priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
  759. else
  760. priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
  761. priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
  762. priv->hw_params.max_stations = IWL4965_STATION_COUNT;
  763. priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
  764. priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
  765. priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
  766. priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
  767. priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
  768. priv->hw_params.tx_chains_num = 2;
  769. priv->hw_params.rx_chains_num = 2;
  770. priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
  771. priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
  772. priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
  773. priv->hw_params.sens = &iwl4965_sensitivity;
  774. return 0;
  775. }
  776. /* set card power command */
  777. static int iwl4965_set_power(struct iwl_priv *priv,
  778. void *cmd)
  779. {
  780. int ret = 0;
  781. ret = iwl_send_cmd_pdu_async(priv, POWER_TABLE_CMD,
  782. sizeof(struct iwl4965_powertable_cmd),
  783. cmd, NULL);
  784. return ret;
  785. }
  786. int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
  787. {
  788. IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
  789. return -EINVAL;
  790. }
  791. static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
  792. {
  793. s32 sign = 1;
  794. if (num < 0) {
  795. sign = -sign;
  796. num = -num;
  797. }
  798. if (denom < 0) {
  799. sign = -sign;
  800. denom = -denom;
  801. }
  802. *res = 1;
  803. *res = ((num * 2 + denom) / (denom * 2)) * sign;
  804. return 1;
  805. }
  806. /**
  807. * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
  808. *
  809. * Determines power supply voltage compensation for txpower calculations.
  810. * Returns number of 1/2-dB steps to subtract from gain table index,
  811. * to compensate for difference between power supply voltage during
  812. * factory measurements, vs. current power supply voltage.
  813. *
  814. * Voltage indication is higher for lower voltage.
  815. * Lower voltage requires more gain (lower gain table index).
  816. */
  817. static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
  818. s32 current_voltage)
  819. {
  820. s32 comp = 0;
  821. if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
  822. (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
  823. return 0;
  824. iwl4965_math_div_round(current_voltage - eeprom_voltage,
  825. TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
  826. if (current_voltage > eeprom_voltage)
  827. comp *= 2;
  828. if ((comp < -2) || (comp > 2))
  829. comp = 0;
  830. return comp;
  831. }
  832. static const struct iwl_channel_info *
  833. iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
  834. enum ieee80211_band band, u16 channel)
  835. {
  836. const struct iwl_channel_info *ch_info;
  837. ch_info = iwl_get_channel_info(priv, band, channel);
  838. if (!is_channel_valid(ch_info))
  839. return NULL;
  840. return ch_info;
  841. }
  842. static s32 iwl4965_get_tx_atten_grp(u16 channel)
  843. {
  844. if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
  845. channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
  846. return CALIB_CH_GROUP_5;
  847. if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
  848. channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
  849. return CALIB_CH_GROUP_1;
  850. if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
  851. channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
  852. return CALIB_CH_GROUP_2;
  853. if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
  854. channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
  855. return CALIB_CH_GROUP_3;
  856. if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
  857. channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
  858. return CALIB_CH_GROUP_4;
  859. IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
  860. return -1;
  861. }
  862. static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
  863. {
  864. s32 b = -1;
  865. for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
  866. if (priv->calib_info->band_info[b].ch_from == 0)
  867. continue;
  868. if ((channel >= priv->calib_info->band_info[b].ch_from)
  869. && (channel <= priv->calib_info->band_info[b].ch_to))
  870. break;
  871. }
  872. return b;
  873. }
  874. static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
  875. {
  876. s32 val;
  877. if (x2 == x1)
  878. return y1;
  879. else {
  880. iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
  881. return val + y2;
  882. }
  883. }
  884. /**
  885. * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
  886. *
  887. * Interpolates factory measurements from the two sample channels within a
  888. * sub-band, to apply to channel of interest. Interpolation is proportional to
  889. * differences in channel frequencies, which is proportional to differences
  890. * in channel number.
  891. */
  892. static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
  893. struct iwl_eeprom_calib_ch_info *chan_info)
  894. {
  895. s32 s = -1;
  896. u32 c;
  897. u32 m;
  898. const struct iwl_eeprom_calib_measure *m1;
  899. const struct iwl_eeprom_calib_measure *m2;
  900. struct iwl_eeprom_calib_measure *omeas;
  901. u32 ch_i1;
  902. u32 ch_i2;
  903. s = iwl4965_get_sub_band(priv, channel);
  904. if (s >= EEPROM_TX_POWER_BANDS) {
  905. IWL_ERROR("Tx Power can not find channel %d ", channel);
  906. return -1;
  907. }
  908. ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
  909. ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
  910. chan_info->ch_num = (u8) channel;
  911. IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
  912. channel, s, ch_i1, ch_i2);
  913. for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
  914. for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
  915. m1 = &(priv->calib_info->band_info[s].ch1.
  916. measurements[c][m]);
  917. m2 = &(priv->calib_info->band_info[s].ch2.
  918. measurements[c][m]);
  919. omeas = &(chan_info->measurements[c][m]);
  920. omeas->actual_pow =
  921. (u8) iwl4965_interpolate_value(channel, ch_i1,
  922. m1->actual_pow,
  923. ch_i2,
  924. m2->actual_pow);
  925. omeas->gain_idx =
  926. (u8) iwl4965_interpolate_value(channel, ch_i1,
  927. m1->gain_idx, ch_i2,
  928. m2->gain_idx);
  929. omeas->temperature =
  930. (u8) iwl4965_interpolate_value(channel, ch_i1,
  931. m1->temperature,
  932. ch_i2,
  933. m2->temperature);
  934. omeas->pa_det =
  935. (s8) iwl4965_interpolate_value(channel, ch_i1,
  936. m1->pa_det, ch_i2,
  937. m2->pa_det);
  938. IWL_DEBUG_TXPOWER
  939. ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
  940. m1->actual_pow, m2->actual_pow, omeas->actual_pow);
  941. IWL_DEBUG_TXPOWER
  942. ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
  943. m1->gain_idx, m2->gain_idx, omeas->gain_idx);
  944. IWL_DEBUG_TXPOWER
  945. ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
  946. m1->pa_det, m2->pa_det, omeas->pa_det);
  947. IWL_DEBUG_TXPOWER
  948. ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
  949. m1->temperature, m2->temperature,
  950. omeas->temperature);
  951. }
  952. }
  953. return 0;
  954. }
  955. /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
  956. * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
  957. static s32 back_off_table[] = {
  958. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
  959. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
  960. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
  961. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
  962. 10 /* CCK */
  963. };
  964. /* Thermal compensation values for txpower for various frequency ranges ...
  965. * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
  966. static struct iwl4965_txpower_comp_entry {
  967. s32 degrees_per_05db_a;
  968. s32 degrees_per_05db_a_denom;
  969. } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
  970. {9, 2}, /* group 0 5.2, ch 34-43 */
  971. {4, 1}, /* group 1 5.2, ch 44-70 */
  972. {4, 1}, /* group 2 5.2, ch 71-124 */
  973. {4, 1}, /* group 3 5.2, ch 125-200 */
  974. {3, 1} /* group 4 2.4, ch all */
  975. };
  976. static s32 get_min_power_index(s32 rate_power_index, u32 band)
  977. {
  978. if (!band) {
  979. if ((rate_power_index & 7) <= 4)
  980. return MIN_TX_GAIN_INDEX_52GHZ_EXT;
  981. }
  982. return MIN_TX_GAIN_INDEX;
  983. }
  984. struct gain_entry {
  985. u8 dsp;
  986. u8 radio;
  987. };
  988. static const struct gain_entry gain_table[2][108] = {
  989. /* 5.2GHz power gain index table */
  990. {
  991. {123, 0x3F}, /* highest txpower */
  992. {117, 0x3F},
  993. {110, 0x3F},
  994. {104, 0x3F},
  995. {98, 0x3F},
  996. {110, 0x3E},
  997. {104, 0x3E},
  998. {98, 0x3E},
  999. {110, 0x3D},
  1000. {104, 0x3D},
  1001. {98, 0x3D},
  1002. {110, 0x3C},
  1003. {104, 0x3C},
  1004. {98, 0x3C},
  1005. {110, 0x3B},
  1006. {104, 0x3B},
  1007. {98, 0x3B},
  1008. {110, 0x3A},
  1009. {104, 0x3A},
  1010. {98, 0x3A},
  1011. {110, 0x39},
  1012. {104, 0x39},
  1013. {98, 0x39},
  1014. {110, 0x38},
  1015. {104, 0x38},
  1016. {98, 0x38},
  1017. {110, 0x37},
  1018. {104, 0x37},
  1019. {98, 0x37},
  1020. {110, 0x36},
  1021. {104, 0x36},
  1022. {98, 0x36},
  1023. {110, 0x35},
  1024. {104, 0x35},
  1025. {98, 0x35},
  1026. {110, 0x34},
  1027. {104, 0x34},
  1028. {98, 0x34},
  1029. {110, 0x33},
  1030. {104, 0x33},
  1031. {98, 0x33},
  1032. {110, 0x32},
  1033. {104, 0x32},
  1034. {98, 0x32},
  1035. {110, 0x31},
  1036. {104, 0x31},
  1037. {98, 0x31},
  1038. {110, 0x30},
  1039. {104, 0x30},
  1040. {98, 0x30},
  1041. {110, 0x25},
  1042. {104, 0x25},
  1043. {98, 0x25},
  1044. {110, 0x24},
  1045. {104, 0x24},
  1046. {98, 0x24},
  1047. {110, 0x23},
  1048. {104, 0x23},
  1049. {98, 0x23},
  1050. {110, 0x22},
  1051. {104, 0x18},
  1052. {98, 0x18},
  1053. {110, 0x17},
  1054. {104, 0x17},
  1055. {98, 0x17},
  1056. {110, 0x16},
  1057. {104, 0x16},
  1058. {98, 0x16},
  1059. {110, 0x15},
  1060. {104, 0x15},
  1061. {98, 0x15},
  1062. {110, 0x14},
  1063. {104, 0x14},
  1064. {98, 0x14},
  1065. {110, 0x13},
  1066. {104, 0x13},
  1067. {98, 0x13},
  1068. {110, 0x12},
  1069. {104, 0x08},
  1070. {98, 0x08},
  1071. {110, 0x07},
  1072. {104, 0x07},
  1073. {98, 0x07},
  1074. {110, 0x06},
  1075. {104, 0x06},
  1076. {98, 0x06},
  1077. {110, 0x05},
  1078. {104, 0x05},
  1079. {98, 0x05},
  1080. {110, 0x04},
  1081. {104, 0x04},
  1082. {98, 0x04},
  1083. {110, 0x03},
  1084. {104, 0x03},
  1085. {98, 0x03},
  1086. {110, 0x02},
  1087. {104, 0x02},
  1088. {98, 0x02},
  1089. {110, 0x01},
  1090. {104, 0x01},
  1091. {98, 0x01},
  1092. {110, 0x00},
  1093. {104, 0x00},
  1094. {98, 0x00},
  1095. {93, 0x00},
  1096. {88, 0x00},
  1097. {83, 0x00},
  1098. {78, 0x00},
  1099. },
  1100. /* 2.4GHz power gain index table */
  1101. {
  1102. {110, 0x3f}, /* highest txpower */
  1103. {104, 0x3f},
  1104. {98, 0x3f},
  1105. {110, 0x3e},
  1106. {104, 0x3e},
  1107. {98, 0x3e},
  1108. {110, 0x3d},
  1109. {104, 0x3d},
  1110. {98, 0x3d},
  1111. {110, 0x3c},
  1112. {104, 0x3c},
  1113. {98, 0x3c},
  1114. {110, 0x3b},
  1115. {104, 0x3b},
  1116. {98, 0x3b},
  1117. {110, 0x3a},
  1118. {104, 0x3a},
  1119. {98, 0x3a},
  1120. {110, 0x39},
  1121. {104, 0x39},
  1122. {98, 0x39},
  1123. {110, 0x38},
  1124. {104, 0x38},
  1125. {98, 0x38},
  1126. {110, 0x37},
  1127. {104, 0x37},
  1128. {98, 0x37},
  1129. {110, 0x36},
  1130. {104, 0x36},
  1131. {98, 0x36},
  1132. {110, 0x35},
  1133. {104, 0x35},
  1134. {98, 0x35},
  1135. {110, 0x34},
  1136. {104, 0x34},
  1137. {98, 0x34},
  1138. {110, 0x33},
  1139. {104, 0x33},
  1140. {98, 0x33},
  1141. {110, 0x32},
  1142. {104, 0x32},
  1143. {98, 0x32},
  1144. {110, 0x31},
  1145. {104, 0x31},
  1146. {98, 0x31},
  1147. {110, 0x30},
  1148. {104, 0x30},
  1149. {98, 0x30},
  1150. {110, 0x6},
  1151. {104, 0x6},
  1152. {98, 0x6},
  1153. {110, 0x5},
  1154. {104, 0x5},
  1155. {98, 0x5},
  1156. {110, 0x4},
  1157. {104, 0x4},
  1158. {98, 0x4},
  1159. {110, 0x3},
  1160. {104, 0x3},
  1161. {98, 0x3},
  1162. {110, 0x2},
  1163. {104, 0x2},
  1164. {98, 0x2},
  1165. {110, 0x1},
  1166. {104, 0x1},
  1167. {98, 0x1},
  1168. {110, 0x0},
  1169. {104, 0x0},
  1170. {98, 0x0},
  1171. {97, 0},
  1172. {96, 0},
  1173. {95, 0},
  1174. {94, 0},
  1175. {93, 0},
  1176. {92, 0},
  1177. {91, 0},
  1178. {90, 0},
  1179. {89, 0},
  1180. {88, 0},
  1181. {87, 0},
  1182. {86, 0},
  1183. {85, 0},
  1184. {84, 0},
  1185. {83, 0},
  1186. {82, 0},
  1187. {81, 0},
  1188. {80, 0},
  1189. {79, 0},
  1190. {78, 0},
  1191. {77, 0},
  1192. {76, 0},
  1193. {75, 0},
  1194. {74, 0},
  1195. {73, 0},
  1196. {72, 0},
  1197. {71, 0},
  1198. {70, 0},
  1199. {69, 0},
  1200. {68, 0},
  1201. {67, 0},
  1202. {66, 0},
  1203. {65, 0},
  1204. {64, 0},
  1205. {63, 0},
  1206. {62, 0},
  1207. {61, 0},
  1208. {60, 0},
  1209. {59, 0},
  1210. }
  1211. };
  1212. static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
  1213. u8 is_fat, u8 ctrl_chan_high,
  1214. struct iwl4965_tx_power_db *tx_power_tbl)
  1215. {
  1216. u8 saturation_power;
  1217. s32 target_power;
  1218. s32 user_target_power;
  1219. s32 power_limit;
  1220. s32 current_temp;
  1221. s32 reg_limit;
  1222. s32 current_regulatory;
  1223. s32 txatten_grp = CALIB_CH_GROUP_MAX;
  1224. int i;
  1225. int c;
  1226. const struct iwl_channel_info *ch_info = NULL;
  1227. struct iwl_eeprom_calib_ch_info ch_eeprom_info;
  1228. const struct iwl_eeprom_calib_measure *measurement;
  1229. s16 voltage;
  1230. s32 init_voltage;
  1231. s32 voltage_compensation;
  1232. s32 degrees_per_05db_num;
  1233. s32 degrees_per_05db_denom;
  1234. s32 factory_temp;
  1235. s32 temperature_comp[2];
  1236. s32 factory_gain_index[2];
  1237. s32 factory_actual_pwr[2];
  1238. s32 power_index;
  1239. /* Sanity check requested level (dBm) */
  1240. if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
  1241. IWL_WARNING("Requested user TXPOWER %d below limit.\n",
  1242. priv->user_txpower_limit);
  1243. return -EINVAL;
  1244. }
  1245. if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
  1246. IWL_WARNING("Requested user TXPOWER %d above limit.\n",
  1247. priv->user_txpower_limit);
  1248. return -EINVAL;
  1249. }
  1250. /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
  1251. * are used for indexing into txpower table) */
  1252. user_target_power = 2 * priv->user_txpower_limit;
  1253. /* Get current (RXON) channel, band, width */
  1254. ch_info =
  1255. iwl4965_get_channel_txpower_info(priv, priv->band, channel);
  1256. IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
  1257. is_fat);
  1258. if (!ch_info)
  1259. return -EINVAL;
  1260. /* get txatten group, used to select 1) thermal txpower adjustment
  1261. * and 2) mimo txpower balance between Tx chains. */
  1262. txatten_grp = iwl4965_get_tx_atten_grp(channel);
  1263. if (txatten_grp < 0)
  1264. return -EINVAL;
  1265. IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
  1266. channel, txatten_grp);
  1267. if (is_fat) {
  1268. if (ctrl_chan_high)
  1269. channel -= 2;
  1270. else
  1271. channel += 2;
  1272. }
  1273. /* hardware txpower limits ...
  1274. * saturation (clipping distortion) txpowers are in half-dBm */
  1275. if (band)
  1276. saturation_power = priv->calib_info->saturation_power24;
  1277. else
  1278. saturation_power = priv->calib_info->saturation_power52;
  1279. if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
  1280. saturation_power > IWL_TX_POWER_SATURATION_MAX) {
  1281. if (band)
  1282. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
  1283. else
  1284. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
  1285. }
  1286. /* regulatory txpower limits ... reg_limit values are in half-dBm,
  1287. * max_power_avg values are in dBm, convert * 2 */
  1288. if (is_fat)
  1289. reg_limit = ch_info->fat_max_power_avg * 2;
  1290. else
  1291. reg_limit = ch_info->max_power_avg * 2;
  1292. if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
  1293. (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
  1294. if (band)
  1295. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
  1296. else
  1297. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
  1298. }
  1299. /* Interpolate txpower calibration values for this channel,
  1300. * based on factory calibration tests on spaced channels. */
  1301. iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
  1302. /* calculate tx gain adjustment based on power supply voltage */
  1303. voltage = priv->calib_info->voltage;
  1304. init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
  1305. voltage_compensation =
  1306. iwl4965_get_voltage_compensation(voltage, init_voltage);
  1307. IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
  1308. init_voltage,
  1309. voltage, voltage_compensation);
  1310. /* get current temperature (Celsius) */
  1311. current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
  1312. current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
  1313. current_temp = KELVIN_TO_CELSIUS(current_temp);
  1314. /* select thermal txpower adjustment params, based on channel group
  1315. * (same frequency group used for mimo txatten adjustment) */
  1316. degrees_per_05db_num =
  1317. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
  1318. degrees_per_05db_denom =
  1319. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
  1320. /* get per-chain txpower values from factory measurements */
  1321. for (c = 0; c < 2; c++) {
  1322. measurement = &ch_eeprom_info.measurements[c][1];
  1323. /* txgain adjustment (in half-dB steps) based on difference
  1324. * between factory and current temperature */
  1325. factory_temp = measurement->temperature;
  1326. iwl4965_math_div_round((current_temp - factory_temp) *
  1327. degrees_per_05db_denom,
  1328. degrees_per_05db_num,
  1329. &temperature_comp[c]);
  1330. factory_gain_index[c] = measurement->gain_idx;
  1331. factory_actual_pwr[c] = measurement->actual_pow;
  1332. IWL_DEBUG_TXPOWER("chain = %d\n", c);
  1333. IWL_DEBUG_TXPOWER("fctry tmp %d, "
  1334. "curr tmp %d, comp %d steps\n",
  1335. factory_temp, current_temp,
  1336. temperature_comp[c]);
  1337. IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
  1338. factory_gain_index[c],
  1339. factory_actual_pwr[c]);
  1340. }
  1341. /* for each of 33 bit-rates (including 1 for CCK) */
  1342. for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
  1343. u8 is_mimo_rate;
  1344. union iwl4965_tx_power_dual_stream tx_power;
  1345. /* for mimo, reduce each chain's txpower by half
  1346. * (3dB, 6 steps), so total output power is regulatory
  1347. * compliant. */
  1348. if (i & 0x8) {
  1349. current_regulatory = reg_limit -
  1350. IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
  1351. is_mimo_rate = 1;
  1352. } else {
  1353. current_regulatory = reg_limit;
  1354. is_mimo_rate = 0;
  1355. }
  1356. /* find txpower limit, either hardware or regulatory */
  1357. power_limit = saturation_power - back_off_table[i];
  1358. if (power_limit > current_regulatory)
  1359. power_limit = current_regulatory;
  1360. /* reduce user's txpower request if necessary
  1361. * for this rate on this channel */
  1362. target_power = user_target_power;
  1363. if (target_power > power_limit)
  1364. target_power = power_limit;
  1365. IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
  1366. i, saturation_power - back_off_table[i],
  1367. current_regulatory, user_target_power,
  1368. target_power);
  1369. /* for each of 2 Tx chains (radio transmitters) */
  1370. for (c = 0; c < 2; c++) {
  1371. s32 atten_value;
  1372. if (is_mimo_rate)
  1373. atten_value =
  1374. (s32)le32_to_cpu(priv->card_alive_init.
  1375. tx_atten[txatten_grp][c]);
  1376. else
  1377. atten_value = 0;
  1378. /* calculate index; higher index means lower txpower */
  1379. power_index = (u8) (factory_gain_index[c] -
  1380. (target_power -
  1381. factory_actual_pwr[c]) -
  1382. temperature_comp[c] -
  1383. voltage_compensation +
  1384. atten_value);
  1385. /* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
  1386. power_index); */
  1387. if (power_index < get_min_power_index(i, band))
  1388. power_index = get_min_power_index(i, band);
  1389. /* adjust 5 GHz index to support negative indexes */
  1390. if (!band)
  1391. power_index += 9;
  1392. /* CCK, rate 32, reduce txpower for CCK */
  1393. if (i == POWER_TABLE_CCK_ENTRY)
  1394. power_index +=
  1395. IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
  1396. /* stay within the table! */
  1397. if (power_index > 107) {
  1398. IWL_WARNING("txpower index %d > 107\n",
  1399. power_index);
  1400. power_index = 107;
  1401. }
  1402. if (power_index < 0) {
  1403. IWL_WARNING("txpower index %d < 0\n",
  1404. power_index);
  1405. power_index = 0;
  1406. }
  1407. /* fill txpower command for this rate/chain */
  1408. tx_power.s.radio_tx_gain[c] =
  1409. gain_table[band][power_index].radio;
  1410. tx_power.s.dsp_predis_atten[c] =
  1411. gain_table[band][power_index].dsp;
  1412. IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
  1413. "gain 0x%02x dsp %d\n",
  1414. c, atten_value, power_index,
  1415. tx_power.s.radio_tx_gain[c],
  1416. tx_power.s.dsp_predis_atten[c]);
  1417. }/* for each chain */
  1418. tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
  1419. }/* for each rate */
  1420. return 0;
  1421. }
  1422. /**
  1423. * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
  1424. *
  1425. * Uses the active RXON for channel, band, and characteristics (fat, high)
  1426. * The power limit is taken from priv->user_txpower_limit.
  1427. */
  1428. int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
  1429. {
  1430. struct iwl4965_txpowertable_cmd cmd = { 0 };
  1431. int ret;
  1432. u8 band = 0;
  1433. u8 is_fat = 0;
  1434. u8 ctrl_chan_high = 0;
  1435. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1436. /* If this gets hit a lot, switch it to a BUG() and catch
  1437. * the stack trace to find out who is calling this during
  1438. * a scan. */
  1439. IWL_WARNING("TX Power requested while scanning!\n");
  1440. return -EAGAIN;
  1441. }
  1442. band = priv->band == IEEE80211_BAND_2GHZ;
  1443. is_fat = is_fat_channel(priv->active_rxon.flags);
  1444. if (is_fat &&
  1445. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  1446. ctrl_chan_high = 1;
  1447. cmd.band = band;
  1448. cmd.channel = priv->active_rxon.channel;
  1449. ret = iwl4965_fill_txpower_tbl(priv, band,
  1450. le16_to_cpu(priv->active_rxon.channel),
  1451. is_fat, ctrl_chan_high, &cmd.tx_power);
  1452. if (ret)
  1453. goto out;
  1454. ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
  1455. out:
  1456. return ret;
  1457. }
  1458. static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
  1459. {
  1460. int ret = 0;
  1461. struct iwl4965_rxon_assoc_cmd rxon_assoc;
  1462. const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
  1463. const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
  1464. if ((rxon1->flags == rxon2->flags) &&
  1465. (rxon1->filter_flags == rxon2->filter_flags) &&
  1466. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  1467. (rxon1->ofdm_ht_single_stream_basic_rates ==
  1468. rxon2->ofdm_ht_single_stream_basic_rates) &&
  1469. (rxon1->ofdm_ht_dual_stream_basic_rates ==
  1470. rxon2->ofdm_ht_dual_stream_basic_rates) &&
  1471. (rxon1->rx_chain == rxon2->rx_chain) &&
  1472. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  1473. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  1474. return 0;
  1475. }
  1476. rxon_assoc.flags = priv->staging_rxon.flags;
  1477. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  1478. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  1479. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  1480. rxon_assoc.reserved = 0;
  1481. rxon_assoc.ofdm_ht_single_stream_basic_rates =
  1482. priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
  1483. rxon_assoc.ofdm_ht_dual_stream_basic_rates =
  1484. priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
  1485. rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
  1486. ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
  1487. sizeof(rxon_assoc), &rxon_assoc, NULL);
  1488. if (ret)
  1489. return ret;
  1490. return ret;
  1491. }
  1492. int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
  1493. {
  1494. int rc;
  1495. u8 band = 0;
  1496. u8 is_fat = 0;
  1497. u8 ctrl_chan_high = 0;
  1498. struct iwl4965_channel_switch_cmd cmd = { 0 };
  1499. const struct iwl_channel_info *ch_info;
  1500. band = priv->band == IEEE80211_BAND_2GHZ;
  1501. ch_info = iwl_get_channel_info(priv, priv->band, channel);
  1502. is_fat = is_fat_channel(priv->staging_rxon.flags);
  1503. if (is_fat &&
  1504. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  1505. ctrl_chan_high = 1;
  1506. cmd.band = band;
  1507. cmd.expect_beacon = 0;
  1508. cmd.channel = cpu_to_le16(channel);
  1509. cmd.rxon_flags = priv->active_rxon.flags;
  1510. cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
  1511. cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
  1512. if (ch_info)
  1513. cmd.expect_beacon = is_channel_radar(ch_info);
  1514. else
  1515. cmd.expect_beacon = 1;
  1516. rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
  1517. ctrl_chan_high, &cmd.tx_power);
  1518. if (rc) {
  1519. IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
  1520. return rc;
  1521. }
  1522. rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
  1523. return rc;
  1524. }
  1525. static int iwl4965_shared_mem_rx_idx(struct iwl_priv *priv)
  1526. {
  1527. struct iwl4965_shared *s = priv->shared_virt;
  1528. return le32_to_cpu(s->rb_closed) & 0xFFF;
  1529. }
  1530. int iwl4965_hw_get_temperature(struct iwl_priv *priv)
  1531. {
  1532. return priv->temperature;
  1533. }
  1534. unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
  1535. struct iwl_frame *frame, u8 rate)
  1536. {
  1537. struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
  1538. unsigned int frame_size;
  1539. tx_beacon_cmd = &frame->u.beacon;
  1540. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  1541. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  1542. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  1543. frame_size = iwl4965_fill_beacon_frame(priv,
  1544. tx_beacon_cmd->frame,
  1545. iwl_bcast_addr,
  1546. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  1547. BUG_ON(frame_size > MAX_MPDU_SIZE);
  1548. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  1549. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  1550. tx_beacon_cmd->tx.rate_n_flags =
  1551. iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  1552. else
  1553. tx_beacon_cmd->tx.rate_n_flags =
  1554. iwl4965_hw_set_rate_n_flags(rate, 0);
  1555. tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
  1556. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
  1557. return (sizeof(*tx_beacon_cmd) + frame_size);
  1558. }
  1559. static int iwl4965_alloc_shared_mem(struct iwl_priv *priv)
  1560. {
  1561. priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
  1562. sizeof(struct iwl4965_shared),
  1563. &priv->shared_phys);
  1564. if (!priv->shared_virt)
  1565. return -ENOMEM;
  1566. memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
  1567. priv->rb_closed_offset = offsetof(struct iwl4965_shared, rb_closed);
  1568. return 0;
  1569. }
  1570. static void iwl4965_free_shared_mem(struct iwl_priv *priv)
  1571. {
  1572. if (priv->shared_virt)
  1573. pci_free_consistent(priv->pci_dev,
  1574. sizeof(struct iwl4965_shared),
  1575. priv->shared_virt,
  1576. priv->shared_phys);
  1577. }
  1578. /**
  1579. * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
  1580. */
  1581. static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
  1582. struct iwl_tx_queue *txq,
  1583. u16 byte_cnt)
  1584. {
  1585. int len;
  1586. int txq_id = txq->q.id;
  1587. struct iwl4965_shared *shared_data = priv->shared_virt;
  1588. len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
  1589. /* Set up byte count within first 256 entries */
  1590. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  1591. tfd_offset[txq->q.write_ptr], byte_cnt, len);
  1592. /* If within first 64 entries, duplicate at end */
  1593. if (txq->q.write_ptr < IWL49_MAX_WIN_SIZE)
  1594. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  1595. tfd_offset[IWL49_QUEUE_SIZE + txq->q.write_ptr],
  1596. byte_cnt, len);
  1597. }
  1598. /**
  1599. * sign_extend - Sign extend a value using specified bit as sign-bit
  1600. *
  1601. * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
  1602. * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
  1603. *
  1604. * @param oper value to sign extend
  1605. * @param index 0 based bit index (0<=index<32) to sign bit
  1606. */
  1607. static s32 sign_extend(u32 oper, int index)
  1608. {
  1609. u8 shift = 31 - index;
  1610. return (s32)(oper << shift) >> shift;
  1611. }
  1612. /**
  1613. * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
  1614. * @statistics: Provides the temperature reading from the uCode
  1615. *
  1616. * A return of <0 indicates bogus data in the statistics
  1617. */
  1618. int iwl4965_get_temperature(const struct iwl_priv *priv)
  1619. {
  1620. s32 temperature;
  1621. s32 vt;
  1622. s32 R1, R2, R3;
  1623. u32 R4;
  1624. if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
  1625. (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
  1626. IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
  1627. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
  1628. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
  1629. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
  1630. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
  1631. } else {
  1632. IWL_DEBUG_TEMP("Running temperature calibration\n");
  1633. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
  1634. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
  1635. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
  1636. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
  1637. }
  1638. /*
  1639. * Temperature is only 23 bits, so sign extend out to 32.
  1640. *
  1641. * NOTE If we haven't received a statistics notification yet
  1642. * with an updated temperature, use R4 provided to us in the
  1643. * "initialize" ALIVE response.
  1644. */
  1645. if (!test_bit(STATUS_TEMPERATURE, &priv->status))
  1646. vt = sign_extend(R4, 23);
  1647. else
  1648. vt = sign_extend(
  1649. le32_to_cpu(priv->statistics.general.temperature), 23);
  1650. IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
  1651. R1, R2, R3, vt);
  1652. if (R3 == R1) {
  1653. IWL_ERROR("Calibration conflict R1 == R3\n");
  1654. return -1;
  1655. }
  1656. /* Calculate temperature in degrees Kelvin, adjust by 97%.
  1657. * Add offset to center the adjustment around 0 degrees Centigrade. */
  1658. temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
  1659. temperature /= (R3 - R1);
  1660. temperature = (temperature * 97) / 100 +
  1661. TEMPERATURE_CALIB_KELVIN_OFFSET;
  1662. IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
  1663. KELVIN_TO_CELSIUS(temperature));
  1664. return temperature;
  1665. }
  1666. /* Adjust Txpower only if temperature variance is greater than threshold. */
  1667. #define IWL_TEMPERATURE_THRESHOLD 3
  1668. /**
  1669. * iwl4965_is_temp_calib_needed - determines if new calibration is needed
  1670. *
  1671. * If the temperature changed has changed sufficiently, then a recalibration
  1672. * is needed.
  1673. *
  1674. * Assumes caller will replace priv->last_temperature once calibration
  1675. * executed.
  1676. */
  1677. static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
  1678. {
  1679. int temp_diff;
  1680. if (!test_bit(STATUS_STATISTICS, &priv->status)) {
  1681. IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
  1682. return 0;
  1683. }
  1684. temp_diff = priv->temperature - priv->last_temperature;
  1685. /* get absolute value */
  1686. if (temp_diff < 0) {
  1687. IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
  1688. temp_diff = -temp_diff;
  1689. } else if (temp_diff == 0)
  1690. IWL_DEBUG_POWER("Same temp, \n");
  1691. else
  1692. IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
  1693. if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
  1694. IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
  1695. return 0;
  1696. }
  1697. IWL_DEBUG_POWER("Thermal txpower calib needed\n");
  1698. return 1;
  1699. }
  1700. /* Calculate noise level, based on measurements during network silence just
  1701. * before arriving beacon. This measurement can be done only if we know
  1702. * exactly when to expect beacons, therefore only when we're associated. */
  1703. static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
  1704. {
  1705. struct statistics_rx_non_phy *rx_info
  1706. = &(priv->statistics.rx.general);
  1707. int num_active_rx = 0;
  1708. int total_silence = 0;
  1709. int bcn_silence_a =
  1710. le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
  1711. int bcn_silence_b =
  1712. le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
  1713. int bcn_silence_c =
  1714. le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
  1715. if (bcn_silence_a) {
  1716. total_silence += bcn_silence_a;
  1717. num_active_rx++;
  1718. }
  1719. if (bcn_silence_b) {
  1720. total_silence += bcn_silence_b;
  1721. num_active_rx++;
  1722. }
  1723. if (bcn_silence_c) {
  1724. total_silence += bcn_silence_c;
  1725. num_active_rx++;
  1726. }
  1727. /* Average among active antennas */
  1728. if (num_active_rx)
  1729. priv->last_rx_noise = (total_silence / num_active_rx) - 107;
  1730. else
  1731. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  1732. IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
  1733. bcn_silence_a, bcn_silence_b, bcn_silence_c,
  1734. priv->last_rx_noise);
  1735. }
  1736. void iwl4965_hw_rx_statistics(struct iwl_priv *priv,
  1737. struct iwl_rx_mem_buffer *rxb)
  1738. {
  1739. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1740. int change;
  1741. s32 temp;
  1742. IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
  1743. (int)sizeof(priv->statistics), pkt->len);
  1744. change = ((priv->statistics.general.temperature !=
  1745. pkt->u.stats.general.temperature) ||
  1746. ((priv->statistics.flag &
  1747. STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
  1748. (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
  1749. memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
  1750. set_bit(STATUS_STATISTICS, &priv->status);
  1751. /* Reschedule the statistics timer to occur in
  1752. * REG_RECALIB_PERIOD seconds to ensure we get a
  1753. * thermal update even if the uCode doesn't give
  1754. * us one */
  1755. mod_timer(&priv->statistics_periodic, jiffies +
  1756. msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
  1757. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  1758. (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
  1759. iwl4965_rx_calc_noise(priv);
  1760. queue_work(priv->workqueue, &priv->run_time_calib_work);
  1761. }
  1762. iwl_leds_background(priv);
  1763. /* If the hardware hasn't reported a change in
  1764. * temperature then don't bother computing a
  1765. * calibrated temperature value */
  1766. if (!change)
  1767. return;
  1768. temp = iwl4965_get_temperature(priv);
  1769. if (temp < 0)
  1770. return;
  1771. if (priv->temperature != temp) {
  1772. if (priv->temperature)
  1773. IWL_DEBUG_TEMP("Temperature changed "
  1774. "from %dC to %dC\n",
  1775. KELVIN_TO_CELSIUS(priv->temperature),
  1776. KELVIN_TO_CELSIUS(temp));
  1777. else
  1778. IWL_DEBUG_TEMP("Temperature "
  1779. "initialized to %dC\n",
  1780. KELVIN_TO_CELSIUS(temp));
  1781. }
  1782. priv->temperature = temp;
  1783. set_bit(STATUS_TEMPERATURE, &priv->status);
  1784. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  1785. iwl4965_is_temp_calib_needed(priv))
  1786. queue_work(priv->workqueue, &priv->txpower_work);
  1787. }
  1788. static void iwl4965_add_radiotap(struct iwl_priv *priv,
  1789. struct sk_buff *skb,
  1790. struct iwl4965_rx_phy_res *rx_start,
  1791. struct ieee80211_rx_status *stats,
  1792. u32 ampdu_status)
  1793. {
  1794. s8 signal = stats->signal;
  1795. s8 noise = 0;
  1796. int rate = stats->rate_idx;
  1797. u64 tsf = stats->mactime;
  1798. __le16 antenna;
  1799. __le16 phy_flags_hw = rx_start->phy_flags;
  1800. struct iwl4965_rt_rx_hdr {
  1801. struct ieee80211_radiotap_header rt_hdr;
  1802. __le64 rt_tsf; /* TSF */
  1803. u8 rt_flags; /* radiotap packet flags */
  1804. u8 rt_rate; /* rate in 500kb/s */
  1805. __le16 rt_channelMHz; /* channel in MHz */
  1806. __le16 rt_chbitmask; /* channel bitfield */
  1807. s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
  1808. s8 rt_dbmnoise;
  1809. u8 rt_antenna; /* antenna number */
  1810. } __attribute__ ((packed)) *iwl4965_rt;
  1811. /* TODO: We won't have enough headroom for HT frames. Fix it later. */
  1812. if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
  1813. if (net_ratelimit())
  1814. printk(KERN_ERR "not enough headroom [%d] for "
  1815. "radiotap head [%zd]\n",
  1816. skb_headroom(skb), sizeof(*iwl4965_rt));
  1817. return;
  1818. }
  1819. /* put radiotap header in front of 802.11 header and data */
  1820. iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
  1821. /* initialise radiotap header */
  1822. iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
  1823. iwl4965_rt->rt_hdr.it_pad = 0;
  1824. /* total header + data */
  1825. put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
  1826. &iwl4965_rt->rt_hdr.it_len);
  1827. /* Indicate all the fields we add to the radiotap header */
  1828. put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
  1829. (1 << IEEE80211_RADIOTAP_FLAGS) |
  1830. (1 << IEEE80211_RADIOTAP_RATE) |
  1831. (1 << IEEE80211_RADIOTAP_CHANNEL) |
  1832. (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
  1833. (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
  1834. (1 << IEEE80211_RADIOTAP_ANTENNA)),
  1835. &iwl4965_rt->rt_hdr.it_present);
  1836. /* Zero the flags, we'll add to them as we go */
  1837. iwl4965_rt->rt_flags = 0;
  1838. put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
  1839. iwl4965_rt->rt_dbmsignal = signal;
  1840. iwl4965_rt->rt_dbmnoise = noise;
  1841. /* Convert the channel frequency and set the flags */
  1842. put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
  1843. if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
  1844. put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
  1845. IEEE80211_CHAN_5GHZ),
  1846. &iwl4965_rt->rt_chbitmask);
  1847. else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
  1848. put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
  1849. IEEE80211_CHAN_2GHZ),
  1850. &iwl4965_rt->rt_chbitmask);
  1851. else /* 802.11g */
  1852. put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
  1853. IEEE80211_CHAN_2GHZ),
  1854. &iwl4965_rt->rt_chbitmask);
  1855. if (rate == -1)
  1856. iwl4965_rt->rt_rate = 0;
  1857. else
  1858. iwl4965_rt->rt_rate = iwl_rates[rate].ieee;
  1859. /*
  1860. * "antenna number"
  1861. *
  1862. * It seems that the antenna field in the phy flags value
  1863. * is actually a bitfield. This is undefined by radiotap,
  1864. * it wants an actual antenna number but I always get "7"
  1865. * for most legacy frames I receive indicating that the
  1866. * same frame was received on all three RX chains.
  1867. *
  1868. * I think this field should be removed in favour of a
  1869. * new 802.11n radiotap field "RX chains" that is defined
  1870. * as a bitmask.
  1871. */
  1872. antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
  1873. iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
  1874. /* set the preamble flag if appropriate */
  1875. if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  1876. iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
  1877. stats->flag |= RX_FLAG_RADIOTAP;
  1878. }
  1879. static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
  1880. {
  1881. /* 0 - mgmt, 1 - cnt, 2 - data */
  1882. int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
  1883. priv->rx_stats[idx].cnt++;
  1884. priv->rx_stats[idx].bytes += len;
  1885. }
  1886. /*
  1887. * returns non-zero if packet should be dropped
  1888. */
  1889. static int iwl4965_set_decrypted_flag(struct iwl_priv *priv,
  1890. struct ieee80211_hdr *hdr,
  1891. u32 decrypt_res,
  1892. struct ieee80211_rx_status *stats)
  1893. {
  1894. u16 fc = le16_to_cpu(hdr->frame_control);
  1895. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  1896. return 0;
  1897. if (!(fc & IEEE80211_FCTL_PROTECTED))
  1898. return 0;
  1899. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  1900. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  1901. case RX_RES_STATUS_SEC_TYPE_TKIP:
  1902. /* The uCode has got a bad phase 1 Key, pushes the packet.
  1903. * Decryption will be done in SW. */
  1904. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  1905. RX_RES_STATUS_BAD_KEY_TTAK)
  1906. break;
  1907. case RX_RES_STATUS_SEC_TYPE_WEP:
  1908. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  1909. RX_RES_STATUS_BAD_ICV_MIC) {
  1910. /* bad ICV, the packet is destroyed since the
  1911. * decryption is inplace, drop it */
  1912. IWL_DEBUG_RX("Packet destroyed\n");
  1913. return -1;
  1914. }
  1915. case RX_RES_STATUS_SEC_TYPE_CCMP:
  1916. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  1917. RX_RES_STATUS_DECRYPT_OK) {
  1918. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  1919. stats->flag |= RX_FLAG_DECRYPTED;
  1920. }
  1921. break;
  1922. default:
  1923. break;
  1924. }
  1925. return 0;
  1926. }
  1927. static u32 iwl4965_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
  1928. {
  1929. u32 decrypt_out = 0;
  1930. if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
  1931. RX_RES_STATUS_STATION_FOUND)
  1932. decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
  1933. RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
  1934. decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
  1935. /* packet was not encrypted */
  1936. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  1937. RX_RES_STATUS_SEC_TYPE_NONE)
  1938. return decrypt_out;
  1939. /* packet was encrypted with unknown alg */
  1940. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  1941. RX_RES_STATUS_SEC_TYPE_ERR)
  1942. return decrypt_out;
  1943. /* decryption was not done in HW */
  1944. if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
  1945. RX_MPDU_RES_STATUS_DEC_DONE_MSK)
  1946. return decrypt_out;
  1947. switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
  1948. case RX_RES_STATUS_SEC_TYPE_CCMP:
  1949. /* alg is CCM: check MIC only */
  1950. if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
  1951. /* Bad MIC */
  1952. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  1953. else
  1954. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  1955. break;
  1956. case RX_RES_STATUS_SEC_TYPE_TKIP:
  1957. if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
  1958. /* Bad TTAK */
  1959. decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
  1960. break;
  1961. }
  1962. /* fall through if TTAK OK */
  1963. default:
  1964. if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
  1965. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  1966. else
  1967. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  1968. break;
  1969. };
  1970. IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
  1971. decrypt_in, decrypt_out);
  1972. return decrypt_out;
  1973. }
  1974. static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
  1975. int include_phy,
  1976. struct iwl_rx_mem_buffer *rxb,
  1977. struct ieee80211_rx_status *stats)
  1978. {
  1979. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1980. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  1981. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
  1982. struct ieee80211_hdr *hdr;
  1983. u16 len;
  1984. __le32 *rx_end;
  1985. unsigned int skblen;
  1986. u32 ampdu_status;
  1987. u32 ampdu_status_legacy;
  1988. if (!include_phy && priv->last_phy_res[0])
  1989. rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  1990. if (!rx_start) {
  1991. IWL_ERROR("MPDU frame without a PHY data\n");
  1992. return;
  1993. }
  1994. if (include_phy) {
  1995. hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
  1996. rx_start->cfg_phy_cnt);
  1997. len = le16_to_cpu(rx_start->byte_count);
  1998. rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
  1999. sizeof(struct iwl4965_rx_phy_res) +
  2000. rx_start->cfg_phy_cnt + len);
  2001. } else {
  2002. struct iwl4965_rx_mpdu_res_start *amsdu =
  2003. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  2004. hdr = (struct ieee80211_hdr *)(pkt->u.raw +
  2005. sizeof(struct iwl4965_rx_mpdu_res_start));
  2006. len = le16_to_cpu(amsdu->byte_count);
  2007. rx_start->byte_count = amsdu->byte_count;
  2008. rx_end = (__le32 *) (((u8 *) hdr) + len);
  2009. }
  2010. /* In monitor mode allow 802.11 ACk frames (10 bytes) */
  2011. if (len > priv->hw_params.max_pkt_size ||
  2012. len < ((priv->iw_mode == IEEE80211_IF_TYPE_MNTR) ? 10 : 16)) {
  2013. IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
  2014. return;
  2015. }
  2016. ampdu_status = le32_to_cpu(*rx_end);
  2017. skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
  2018. if (!include_phy) {
  2019. /* New status scheme, need to translate */
  2020. ampdu_status_legacy = ampdu_status;
  2021. ampdu_status = iwl4965_translate_rx_status(priv, ampdu_status);
  2022. }
  2023. /* start from MAC */
  2024. skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
  2025. skb_put(rxb->skb, len); /* end where data ends */
  2026. /* We only process data packets if the interface is open */
  2027. if (unlikely(!priv->is_open)) {
  2028. IWL_DEBUG_DROP_LIMIT
  2029. ("Dropping packet while interface is not open.\n");
  2030. return;
  2031. }
  2032. stats->flag = 0;
  2033. hdr = (struct ieee80211_hdr *)rxb->skb->data;
  2034. /* in case of HW accelerated crypto and bad decryption, drop */
  2035. if (!priv->hw_params.sw_crypto &&
  2036. iwl4965_set_decrypted_flag(priv, hdr, ampdu_status, stats))
  2037. return;
  2038. if (priv->add_radiotap)
  2039. iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
  2040. iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
  2041. ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
  2042. priv->alloc_rxb_skb--;
  2043. rxb->skb = NULL;
  2044. }
  2045. /* Calc max signal level (dBm) among 3 possible receivers */
  2046. static int iwl4965_calc_rssi(struct iwl_priv *priv,
  2047. struct iwl4965_rx_phy_res *rx_resp)
  2048. {
  2049. /* data from PHY/DSP regarding signal strength, etc.,
  2050. * contents are always there, not configurable by host. */
  2051. struct iwl4965_rx_non_cfg_phy *ncphy =
  2052. (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
  2053. u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
  2054. >> IWL_AGC_DB_POS;
  2055. u32 valid_antennae =
  2056. (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
  2057. >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
  2058. u8 max_rssi = 0;
  2059. u32 i;
  2060. /* Find max rssi among 3 possible receivers.
  2061. * These values are measured by the digital signal processor (DSP).
  2062. * They should stay fairly constant even as the signal strength varies,
  2063. * if the radio's automatic gain control (AGC) is working right.
  2064. * AGC value (see below) will provide the "interesting" info. */
  2065. for (i = 0; i < 3; i++)
  2066. if (valid_antennae & (1 << i))
  2067. max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
  2068. IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
  2069. ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
  2070. max_rssi, agc);
  2071. /* dBm = max_rssi dB - agc dB - constant.
  2072. * Higher AGC (higher radio gain) means lower signal. */
  2073. return (max_rssi - agc - IWL_RSSI_OFFSET);
  2074. }
  2075. static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
  2076. {
  2077. unsigned long flags;
  2078. spin_lock_irqsave(&priv->sta_lock, flags);
  2079. priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
  2080. priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
  2081. priv->stations[sta_id].sta.sta.modify_mask = 0;
  2082. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  2083. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2084. iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  2085. }
  2086. static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
  2087. {
  2088. /* FIXME: need locking over ps_status ??? */
  2089. u8 sta_id = iwl_find_station(priv, addr);
  2090. if (sta_id != IWL_INVALID_STATION) {
  2091. u8 sta_awake = priv->stations[sta_id].
  2092. ps_status == STA_PS_STATUS_WAKE;
  2093. if (sta_awake && ps_bit)
  2094. priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
  2095. else if (!sta_awake && !ps_bit) {
  2096. iwl4965_sta_modify_ps_wake(priv, sta_id);
  2097. priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
  2098. }
  2099. }
  2100. }
  2101. #ifdef CONFIG_IWLWIFI_DEBUG
  2102. /**
  2103. * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
  2104. *
  2105. * You may hack this function to show different aspects of received frames,
  2106. * including selective frame dumps.
  2107. * group100 parameter selects whether to show 1 out of 100 good frames.
  2108. *
  2109. * TODO: This was originally written for 3945, need to audit for
  2110. * proper operation with 4965.
  2111. */
  2112. static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
  2113. struct iwl_rx_packet *pkt,
  2114. struct ieee80211_hdr *header, int group100)
  2115. {
  2116. u32 to_us;
  2117. u32 print_summary = 0;
  2118. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  2119. u32 hundred = 0;
  2120. u32 dataframe = 0;
  2121. u16 fc;
  2122. u16 seq_ctl;
  2123. u16 channel;
  2124. u16 phy_flags;
  2125. int rate_sym;
  2126. u16 length;
  2127. u16 status;
  2128. u16 bcn_tmr;
  2129. u32 tsf_low;
  2130. u64 tsf;
  2131. u8 rssi;
  2132. u8 agc;
  2133. u16 sig_avg;
  2134. u16 noise_diff;
  2135. struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
  2136. struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
  2137. struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
  2138. u8 *data = IWL_RX_DATA(pkt);
  2139. if (likely(!(priv->debug_level & IWL_DL_RX)))
  2140. return;
  2141. /* MAC header */
  2142. fc = le16_to_cpu(header->frame_control);
  2143. seq_ctl = le16_to_cpu(header->seq_ctrl);
  2144. /* metadata */
  2145. channel = le16_to_cpu(rx_hdr->channel);
  2146. phy_flags = le16_to_cpu(rx_hdr->phy_flags);
  2147. rate_sym = rx_hdr->rate;
  2148. length = le16_to_cpu(rx_hdr->len);
  2149. /* end-of-frame status and timestamp */
  2150. status = le32_to_cpu(rx_end->status);
  2151. bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
  2152. tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
  2153. tsf = le64_to_cpu(rx_end->timestamp);
  2154. /* signal statistics */
  2155. rssi = rx_stats->rssi;
  2156. agc = rx_stats->agc;
  2157. sig_avg = le16_to_cpu(rx_stats->sig_avg);
  2158. noise_diff = le16_to_cpu(rx_stats->noise_diff);
  2159. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  2160. /* if data frame is to us and all is good,
  2161. * (optionally) print summary for only 1 out of every 100 */
  2162. if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
  2163. (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  2164. dataframe = 1;
  2165. if (!group100)
  2166. print_summary = 1; /* print each frame */
  2167. else if (priv->framecnt_to_us < 100) {
  2168. priv->framecnt_to_us++;
  2169. print_summary = 0;
  2170. } else {
  2171. priv->framecnt_to_us = 0;
  2172. print_summary = 1;
  2173. hundred = 1;
  2174. }
  2175. } else {
  2176. /* print summary for all other frames */
  2177. print_summary = 1;
  2178. }
  2179. if (print_summary) {
  2180. char *title;
  2181. int rate_idx;
  2182. u32 bitrate;
  2183. if (hundred)
  2184. title = "100Frames";
  2185. else if (fc & IEEE80211_FCTL_RETRY)
  2186. title = "Retry";
  2187. else if (ieee80211_is_assoc_response(fc))
  2188. title = "AscRsp";
  2189. else if (ieee80211_is_reassoc_response(fc))
  2190. title = "RasRsp";
  2191. else if (ieee80211_is_probe_response(fc)) {
  2192. title = "PrbRsp";
  2193. print_dump = 1; /* dump frame contents */
  2194. } else if (ieee80211_is_beacon(fc)) {
  2195. title = "Beacon";
  2196. print_dump = 1; /* dump frame contents */
  2197. } else if (ieee80211_is_atim(fc))
  2198. title = "ATIM";
  2199. else if (ieee80211_is_auth(fc))
  2200. title = "Auth";
  2201. else if (ieee80211_is_deauth(fc))
  2202. title = "DeAuth";
  2203. else if (ieee80211_is_disassoc(fc))
  2204. title = "DisAssoc";
  2205. else
  2206. title = "Frame";
  2207. rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
  2208. if (unlikely(rate_idx == -1))
  2209. bitrate = 0;
  2210. else
  2211. bitrate = iwl_rates[rate_idx].ieee / 2;
  2212. /* print frame summary.
  2213. * MAC addresses show just the last byte (for brevity),
  2214. * but you can hack it to show more, if you'd like to. */
  2215. if (dataframe)
  2216. IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
  2217. "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
  2218. title, fc, header->addr1[5],
  2219. length, rssi, channel, bitrate);
  2220. else {
  2221. /* src/dst addresses assume managed mode */
  2222. IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
  2223. "src=0x%02x, rssi=%u, tim=%lu usec, "
  2224. "phy=0x%02x, chnl=%d\n",
  2225. title, fc, header->addr1[5],
  2226. header->addr3[5], rssi,
  2227. tsf_low - priv->scan_start_tsf,
  2228. phy_flags, channel);
  2229. }
  2230. }
  2231. if (print_dump)
  2232. iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
  2233. }
  2234. #else
  2235. static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
  2236. struct iwl_rx_packet *pkt,
  2237. struct ieee80211_hdr *header,
  2238. int group100)
  2239. {
  2240. }
  2241. #endif
  2242. /* Called for REPLY_RX (legacy ABG frames), or
  2243. * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
  2244. void iwl4965_rx_reply_rx(struct iwl_priv *priv,
  2245. struct iwl_rx_mem_buffer *rxb)
  2246. {
  2247. struct ieee80211_hdr *header;
  2248. struct ieee80211_rx_status rx_status;
  2249. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2250. /* Use phy data (Rx signal strength, etc.) contained within
  2251. * this rx packet for legacy frames,
  2252. * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
  2253. int include_phy = (pkt->hdr.cmd == REPLY_RX);
  2254. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  2255. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
  2256. (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  2257. __le32 *rx_end;
  2258. unsigned int len = 0;
  2259. u16 fc;
  2260. u8 network_packet;
  2261. rx_status.mactime = le64_to_cpu(rx_start->timestamp);
  2262. rx_status.freq =
  2263. ieee80211_channel_to_frequency(le16_to_cpu(rx_start->channel));
  2264. rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  2265. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  2266. rx_status.rate_idx =
  2267. iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
  2268. if (rx_status.band == IEEE80211_BAND_5GHZ)
  2269. rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
  2270. rx_status.antenna = 0;
  2271. rx_status.flag = 0;
  2272. if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
  2273. IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
  2274. rx_start->cfg_phy_cnt);
  2275. return;
  2276. }
  2277. if (!include_phy) {
  2278. if (priv->last_phy_res[0])
  2279. rx_start = (struct iwl4965_rx_phy_res *)
  2280. &priv->last_phy_res[1];
  2281. else
  2282. rx_start = NULL;
  2283. }
  2284. if (!rx_start) {
  2285. IWL_ERROR("MPDU frame without a PHY data\n");
  2286. return;
  2287. }
  2288. if (include_phy) {
  2289. header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
  2290. + rx_start->cfg_phy_cnt);
  2291. len = le16_to_cpu(rx_start->byte_count);
  2292. rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
  2293. sizeof(struct iwl4965_rx_phy_res) + len);
  2294. } else {
  2295. struct iwl4965_rx_mpdu_res_start *amsdu =
  2296. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  2297. header = (void *)(pkt->u.raw +
  2298. sizeof(struct iwl4965_rx_mpdu_res_start));
  2299. len = le16_to_cpu(amsdu->byte_count);
  2300. rx_end = (__le32 *) (pkt->u.raw +
  2301. sizeof(struct iwl4965_rx_mpdu_res_start) + len);
  2302. }
  2303. if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
  2304. !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  2305. IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
  2306. le32_to_cpu(*rx_end));
  2307. return;
  2308. }
  2309. priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
  2310. /* Find max signal strength (dBm) among 3 antenna/receiver chains */
  2311. rx_status.signal = iwl4965_calc_rssi(priv, rx_start);
  2312. /* Meaningful noise values are available only from beacon statistics,
  2313. * which are gathered only when associated, and indicate noise
  2314. * only for the associated network channel ...
  2315. * Ignore these noise values while scanning (other channels) */
  2316. if (iwl_is_associated(priv) &&
  2317. !test_bit(STATUS_SCANNING, &priv->status)) {
  2318. rx_status.noise = priv->last_rx_noise;
  2319. rx_status.qual = iwl4965_calc_sig_qual(rx_status.signal,
  2320. rx_status.noise);
  2321. } else {
  2322. rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  2323. rx_status.qual = iwl4965_calc_sig_qual(rx_status.signal, 0);
  2324. }
  2325. /* Reset beacon noise level if not associated. */
  2326. if (!iwl_is_associated(priv))
  2327. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  2328. /* Set "1" to report good data frames in groups of 100 */
  2329. /* FIXME: need to optimze the call: */
  2330. iwl4965_dbg_report_frame(priv, pkt, header, 1);
  2331. IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
  2332. rx_status.signal, rx_status.noise, rx_status.signal,
  2333. (unsigned long long)rx_status.mactime);
  2334. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
  2335. iwl4965_handle_data_packet(priv, 1, include_phy,
  2336. rxb, &rx_status);
  2337. return;
  2338. }
  2339. network_packet = iwl4965_is_network_packet(priv, header);
  2340. if (network_packet) {
  2341. priv->last_rx_rssi = rx_status.signal;
  2342. priv->last_beacon_time = priv->ucode_beacon_time;
  2343. priv->last_tsf = le64_to_cpu(rx_start->timestamp);
  2344. }
  2345. fc = le16_to_cpu(header->frame_control);
  2346. switch (fc & IEEE80211_FCTL_FTYPE) {
  2347. case IEEE80211_FTYPE_MGMT:
  2348. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  2349. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  2350. header->addr2);
  2351. iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
  2352. break;
  2353. case IEEE80211_FTYPE_CTL:
  2354. switch (fc & IEEE80211_FCTL_STYPE) {
  2355. case IEEE80211_STYPE_BACK_REQ:
  2356. IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
  2357. iwl4965_handle_data_packet(priv, 0, include_phy,
  2358. rxb, &rx_status);
  2359. break;
  2360. default:
  2361. break;
  2362. }
  2363. break;
  2364. case IEEE80211_FTYPE_DATA: {
  2365. DECLARE_MAC_BUF(mac1);
  2366. DECLARE_MAC_BUF(mac2);
  2367. DECLARE_MAC_BUF(mac3);
  2368. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  2369. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  2370. header->addr2);
  2371. if (unlikely(!network_packet))
  2372. IWL_DEBUG_DROP("Dropping (non network): "
  2373. "%s, %s, %s\n",
  2374. print_mac(mac1, header->addr1),
  2375. print_mac(mac2, header->addr2),
  2376. print_mac(mac3, header->addr3));
  2377. else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
  2378. IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
  2379. print_mac(mac1, header->addr1),
  2380. print_mac(mac2, header->addr2),
  2381. print_mac(mac3, header->addr3));
  2382. else
  2383. iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
  2384. &rx_status);
  2385. break;
  2386. }
  2387. default:
  2388. break;
  2389. }
  2390. }
  2391. /**
  2392. * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
  2393. *
  2394. * Go through block-ack's bitmap of ACK'd frames, update driver's record of
  2395. * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
  2396. */
  2397. static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
  2398. struct iwl_ht_agg *agg,
  2399. struct iwl4965_compressed_ba_resp*
  2400. ba_resp)
  2401. {
  2402. int i, sh, ack;
  2403. u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
  2404. u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
  2405. u64 bitmap;
  2406. int successes = 0;
  2407. struct ieee80211_tx_info *info;
  2408. if (unlikely(!agg->wait_for_ba)) {
  2409. IWL_ERROR("Received BA when not expected\n");
  2410. return -EINVAL;
  2411. }
  2412. /* Mark that the expected block-ack response arrived */
  2413. agg->wait_for_ba = 0;
  2414. IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
  2415. /* Calculate shift to align block-ack bits with our Tx window bits */
  2416. sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
  2417. if (sh < 0) /* tbw something is wrong with indices */
  2418. sh += 0x100;
  2419. /* don't use 64-bit values for now */
  2420. bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
  2421. if (agg->frame_count > (64 - sh)) {
  2422. IWL_DEBUG_TX_REPLY("more frames than bitmap size");
  2423. return -1;
  2424. }
  2425. /* check for success or failure according to the
  2426. * transmitted bitmap and block-ack bitmap */
  2427. bitmap &= agg->bitmap;
  2428. /* For each frame attempted in aggregation,
  2429. * update driver's record of tx frame's status. */
  2430. for (i = 0; i < agg->frame_count ; i++) {
  2431. ack = bitmap & (1 << i);
  2432. successes += !!ack;
  2433. IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
  2434. ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
  2435. agg->start_idx + i);
  2436. }
  2437. info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
  2438. memset(&info->status, 0, sizeof(info->status));
  2439. info->flags = IEEE80211_TX_STAT_ACK;
  2440. info->flags |= IEEE80211_TX_STAT_AMPDU;
  2441. info->status.ampdu_ack_map = successes;
  2442. info->status.ampdu_ack_len = agg->frame_count;
  2443. iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
  2444. IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
  2445. return 0;
  2446. }
  2447. /**
  2448. * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
  2449. */
  2450. static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
  2451. u16 txq_id)
  2452. {
  2453. /* Simply stop the queue, but don't change any configuration;
  2454. * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
  2455. iwl_write_prph(priv,
  2456. IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
  2457. (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
  2458. (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
  2459. }
  2460. /**
  2461. * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
  2462. * priv->lock must be held by the caller
  2463. */
  2464. static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
  2465. u16 ssn_idx, u8 tx_fifo)
  2466. {
  2467. int ret = 0;
  2468. if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
  2469. IWL_WARNING("queue number too small: %d, must be > %d\n",
  2470. txq_id, IWL_BACK_QUEUE_FIRST_ID);
  2471. return -EINVAL;
  2472. }
  2473. ret = iwl_grab_nic_access(priv);
  2474. if (ret)
  2475. return ret;
  2476. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  2477. iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
  2478. priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
  2479. priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
  2480. /* supposes that ssn_idx is valid (!= 0xFFF) */
  2481. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  2482. iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
  2483. iwl_txq_ctx_deactivate(priv, txq_id);
  2484. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
  2485. iwl_release_nic_access(priv);
  2486. return 0;
  2487. }
  2488. /**
  2489. * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
  2490. *
  2491. * Handles block-acknowledge notification from device, which reports success
  2492. * of frames sent via aggregation.
  2493. */
  2494. static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
  2495. struct iwl_rx_mem_buffer *rxb)
  2496. {
  2497. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2498. struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
  2499. int index;
  2500. struct iwl_tx_queue *txq = NULL;
  2501. struct iwl_ht_agg *agg;
  2502. DECLARE_MAC_BUF(mac);
  2503. /* "flow" corresponds to Tx queue */
  2504. u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
  2505. /* "ssn" is start of block-ack Tx window, corresponds to index
  2506. * (in Tx queue's circular buffer) of first TFD/frame in window */
  2507. u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
  2508. if (scd_flow >= priv->hw_params.max_txq_num) {
  2509. IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
  2510. return;
  2511. }
  2512. txq = &priv->txq[scd_flow];
  2513. agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
  2514. /* Find index just before block-ack window */
  2515. index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
  2516. /* TODO: Need to get this copy more safely - now good for debug */
  2517. IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
  2518. "sta_id = %d\n",
  2519. agg->wait_for_ba,
  2520. print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
  2521. ba_resp->sta_id);
  2522. IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
  2523. "%d, scd_ssn = %d\n",
  2524. ba_resp->tid,
  2525. ba_resp->seq_ctl,
  2526. (unsigned long long)le64_to_cpu(ba_resp->bitmap),
  2527. ba_resp->scd_flow,
  2528. ba_resp->scd_ssn);
  2529. IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
  2530. agg->start_idx,
  2531. (unsigned long long)agg->bitmap);
  2532. /* Update driver's record of ACK vs. not for each frame in window */
  2533. iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
  2534. /* Release all TFDs before the SSN, i.e. all TFDs in front of
  2535. * block-ack window (we assume that they've been successfully
  2536. * transmitted ... if not, it's too late anyway). */
  2537. if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
  2538. /* calculate mac80211 ampdu sw queue to wake */
  2539. int ampdu_q =
  2540. scd_flow - IWL_BACK_QUEUE_FIRST_ID + priv->hw->queues;
  2541. int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
  2542. priv->stations[ba_resp->sta_id].
  2543. tid[ba_resp->tid].tfds_in_queue -= freed;
  2544. if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
  2545. priv->mac80211_registered &&
  2546. agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
  2547. ieee80211_wake_queue(priv->hw, ampdu_q);
  2548. iwl_txq_check_empty(priv, ba_resp->sta_id,
  2549. ba_resp->tid, scd_flow);
  2550. }
  2551. }
  2552. /**
  2553. * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
  2554. */
  2555. static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
  2556. u16 txq_id)
  2557. {
  2558. u32 tbl_dw_addr;
  2559. u32 tbl_dw;
  2560. u16 scd_q2ratid;
  2561. scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
  2562. tbl_dw_addr = priv->scd_base_addr +
  2563. IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
  2564. tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
  2565. if (txq_id & 0x1)
  2566. tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
  2567. else
  2568. tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
  2569. iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
  2570. return 0;
  2571. }
  2572. /**
  2573. * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
  2574. *
  2575. * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
  2576. * i.e. it must be one of the higher queues used for aggregation
  2577. */
  2578. static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
  2579. int tx_fifo, int sta_id, int tid, u16 ssn_idx)
  2580. {
  2581. unsigned long flags;
  2582. int ret;
  2583. u16 ra_tid;
  2584. if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
  2585. IWL_WARNING("queue number too small: %d, must be > %d\n",
  2586. txq_id, IWL_BACK_QUEUE_FIRST_ID);
  2587. ra_tid = BUILD_RAxTID(sta_id, tid);
  2588. /* Modify device's station table to Tx this TID */
  2589. iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
  2590. spin_lock_irqsave(&priv->lock, flags);
  2591. ret = iwl_grab_nic_access(priv);
  2592. if (ret) {
  2593. spin_unlock_irqrestore(&priv->lock, flags);
  2594. return ret;
  2595. }
  2596. /* Stop this Tx queue before configuring it */
  2597. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  2598. /* Map receiver-address / traffic-ID to this queue */
  2599. iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
  2600. /* Set this queue as a chain-building queue */
  2601. iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
  2602. /* Place first TFD at index corresponding to start sequence number.
  2603. * Assumes that ssn_idx is valid (!= 0xFFF) */
  2604. priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
  2605. priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
  2606. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  2607. /* Set up Tx window size and frame limit for this queue */
  2608. iwl_write_targ_mem(priv,
  2609. priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
  2610. (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  2611. IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  2612. iwl_write_targ_mem(priv, priv->scd_base_addr +
  2613. IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
  2614. (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
  2615. & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  2616. iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
  2617. /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
  2618. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
  2619. iwl_release_nic_access(priv);
  2620. spin_unlock_irqrestore(&priv->lock, flags);
  2621. return 0;
  2622. }
  2623. static int iwl4965_rx_agg_start(struct iwl_priv *priv,
  2624. const u8 *addr, int tid, u16 ssn)
  2625. {
  2626. unsigned long flags;
  2627. int sta_id;
  2628. sta_id = iwl_find_station(priv, addr);
  2629. if (sta_id == IWL_INVALID_STATION)
  2630. return -ENXIO;
  2631. spin_lock_irqsave(&priv->sta_lock, flags);
  2632. priv->stations[sta_id].sta.station_flags_msk = 0;
  2633. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
  2634. priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
  2635. priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
  2636. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  2637. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2638. return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
  2639. CMD_ASYNC);
  2640. }
  2641. static int iwl4965_rx_agg_stop(struct iwl_priv *priv,
  2642. const u8 *addr, int tid)
  2643. {
  2644. unsigned long flags;
  2645. int sta_id;
  2646. sta_id = iwl_find_station(priv, addr);
  2647. if (sta_id == IWL_INVALID_STATION)
  2648. return -ENXIO;
  2649. spin_lock_irqsave(&priv->sta_lock, flags);
  2650. priv->stations[sta_id].sta.station_flags_msk = 0;
  2651. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
  2652. priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
  2653. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  2654. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2655. return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
  2656. CMD_ASYNC);
  2657. }
  2658. int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
  2659. enum ieee80211_ampdu_mlme_action action,
  2660. const u8 *addr, u16 tid, u16 *ssn)
  2661. {
  2662. struct iwl_priv *priv = hw->priv;
  2663. DECLARE_MAC_BUF(mac);
  2664. IWL_DEBUG_HT("A-MPDU action on addr %s tid %d\n",
  2665. print_mac(mac, addr), tid);
  2666. switch (action) {
  2667. case IEEE80211_AMPDU_RX_START:
  2668. IWL_DEBUG_HT("start Rx\n");
  2669. return iwl4965_rx_agg_start(priv, addr, tid, *ssn);
  2670. case IEEE80211_AMPDU_RX_STOP:
  2671. IWL_DEBUG_HT("stop Rx\n");
  2672. return iwl4965_rx_agg_stop(priv, addr, tid);
  2673. case IEEE80211_AMPDU_TX_START:
  2674. IWL_DEBUG_HT("start Tx\n");
  2675. return iwl_tx_agg_start(priv, addr, tid, ssn);
  2676. case IEEE80211_AMPDU_TX_STOP:
  2677. IWL_DEBUG_HT("stop Tx\n");
  2678. return iwl_tx_agg_stop(priv, addr, tid);
  2679. default:
  2680. IWL_DEBUG_HT("unknown\n");
  2681. return -EINVAL;
  2682. break;
  2683. }
  2684. return 0;
  2685. }
  2686. static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len)
  2687. {
  2688. switch (cmd_id) {
  2689. case REPLY_RXON:
  2690. return (u16) sizeof(struct iwl4965_rxon_cmd);
  2691. default:
  2692. return len;
  2693. }
  2694. }
  2695. static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
  2696. {
  2697. struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
  2698. addsta->mode = cmd->mode;
  2699. memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
  2700. memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
  2701. addsta->station_flags = cmd->station_flags;
  2702. addsta->station_flags_msk = cmd->station_flags_msk;
  2703. addsta->tid_disable_tx = cmd->tid_disable_tx;
  2704. addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
  2705. addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
  2706. addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
  2707. addsta->reserved1 = __constant_cpu_to_le16(0);
  2708. addsta->reserved2 = __constant_cpu_to_le32(0);
  2709. return (u16)sizeof(struct iwl4965_addsta_cmd);
  2710. }
  2711. static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
  2712. {
  2713. __le32 *scd_ssn = (__le32 *)((u32 *)&tx_resp->status +
  2714. tx_resp->frame_count);
  2715. return le32_to_cpu(*scd_ssn) & MAX_SN;
  2716. }
  2717. /**
  2718. * iwl4965_tx_status_reply_tx - Handle Tx rspnse for frames in aggregation queue
  2719. */
  2720. static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv,
  2721. struct iwl_ht_agg *agg,
  2722. struct iwl4965_tx_resp_agg *tx_resp,
  2723. u16 start_idx)
  2724. {
  2725. u16 status;
  2726. struct agg_tx_status *frame_status = &tx_resp->status;
  2727. struct ieee80211_tx_info *info = NULL;
  2728. struct ieee80211_hdr *hdr = NULL;
  2729. int i, sh;
  2730. int txq_id, idx;
  2731. u16 seq;
  2732. if (agg->wait_for_ba)
  2733. IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
  2734. agg->frame_count = tx_resp->frame_count;
  2735. agg->start_idx = start_idx;
  2736. agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
  2737. agg->bitmap = 0;
  2738. /* # frames attempted by Tx command */
  2739. if (agg->frame_count == 1) {
  2740. /* Only one frame was attempted; no block-ack will arrive */
  2741. status = le16_to_cpu(frame_status[0].status);
  2742. seq = le16_to_cpu(frame_status[0].sequence);
  2743. idx = SEQ_TO_INDEX(seq);
  2744. txq_id = SEQ_TO_QUEUE(seq);
  2745. /* FIXME: code repetition */
  2746. IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
  2747. agg->frame_count, agg->start_idx, idx);
  2748. info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
  2749. info->status.retry_count = tx_resp->failure_frame;
  2750. info->flags &= ~IEEE80211_TX_CTL_AMPDU;
  2751. info->flags |= iwl_is_tx_success(status)?
  2752. IEEE80211_TX_STAT_ACK : 0;
  2753. iwl4965_hwrate_to_tx_control(priv,
  2754. le32_to_cpu(tx_resp->rate_n_flags),
  2755. info);
  2756. /* FIXME: code repetition end */
  2757. IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
  2758. status & 0xff, tx_resp->failure_frame);
  2759. IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n",
  2760. iwl4965_hw_get_rate_n_flags(tx_resp->rate_n_flags));
  2761. agg->wait_for_ba = 0;
  2762. } else {
  2763. /* Two or more frames were attempted; expect block-ack */
  2764. u64 bitmap = 0;
  2765. int start = agg->start_idx;
  2766. /* Construct bit-map of pending frames within Tx window */
  2767. for (i = 0; i < agg->frame_count; i++) {
  2768. u16 sc;
  2769. status = le16_to_cpu(frame_status[i].status);
  2770. seq = le16_to_cpu(frame_status[i].sequence);
  2771. idx = SEQ_TO_INDEX(seq);
  2772. txq_id = SEQ_TO_QUEUE(seq);
  2773. if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
  2774. AGG_TX_STATE_ABORT_MSK))
  2775. continue;
  2776. IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
  2777. agg->frame_count, txq_id, idx);
  2778. hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
  2779. sc = le16_to_cpu(hdr->seq_ctrl);
  2780. if (idx != (SEQ_TO_SN(sc) & 0xff)) {
  2781. IWL_ERROR("BUG_ON idx doesn't match seq control"
  2782. " idx=%d, seq_idx=%d, seq=%d\n",
  2783. idx, SEQ_TO_SN(sc),
  2784. hdr->seq_ctrl);
  2785. return -1;
  2786. }
  2787. IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
  2788. i, idx, SEQ_TO_SN(sc));
  2789. sh = idx - start;
  2790. if (sh > 64) {
  2791. sh = (start - idx) + 0xff;
  2792. bitmap = bitmap << sh;
  2793. sh = 0;
  2794. start = idx;
  2795. } else if (sh < -64)
  2796. sh = 0xff - (start - idx);
  2797. else if (sh < 0) {
  2798. sh = start - idx;
  2799. start = idx;
  2800. bitmap = bitmap << sh;
  2801. sh = 0;
  2802. }
  2803. bitmap |= (1 << sh);
  2804. IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n",
  2805. start, (u32)(bitmap & 0xFFFFFFFF));
  2806. }
  2807. agg->bitmap = bitmap;
  2808. agg->start_idx = start;
  2809. agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
  2810. IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
  2811. agg->frame_count, agg->start_idx,
  2812. (unsigned long long)agg->bitmap);
  2813. if (bitmap)
  2814. agg->wait_for_ba = 1;
  2815. }
  2816. return 0;
  2817. }
  2818. /**
  2819. * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
  2820. */
  2821. static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
  2822. struct iwl_rx_mem_buffer *rxb)
  2823. {
  2824. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2825. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2826. int txq_id = SEQ_TO_QUEUE(sequence);
  2827. int index = SEQ_TO_INDEX(sequence);
  2828. struct iwl_tx_queue *txq = &priv->txq[txq_id];
  2829. struct ieee80211_tx_info *info;
  2830. struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
  2831. u32 status = le32_to_cpu(tx_resp->status);
  2832. int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION;
  2833. u16 fc;
  2834. struct ieee80211_hdr *hdr;
  2835. u8 *qc = NULL;
  2836. if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
  2837. IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
  2838. "is out of range [0-%d] %d %d\n", txq_id,
  2839. index, txq->q.n_bd, txq->q.write_ptr,
  2840. txq->q.read_ptr);
  2841. return;
  2842. }
  2843. info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
  2844. memset(&info->status, 0, sizeof(info->status));
  2845. hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
  2846. fc = le16_to_cpu(hdr->frame_control);
  2847. if (ieee80211_is_qos_data(fc)) {
  2848. qc = ieee80211_get_qos_ctrl(hdr, ieee80211_get_hdrlen(fc));
  2849. tid = qc[0] & 0xf;
  2850. }
  2851. sta_id = iwl_get_ra_sta_id(priv, hdr);
  2852. if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
  2853. IWL_ERROR("Station not known\n");
  2854. return;
  2855. }
  2856. if (txq->sched_retry) {
  2857. const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
  2858. struct iwl_ht_agg *agg = NULL;
  2859. if (!qc)
  2860. return;
  2861. agg = &priv->stations[sta_id].tid[tid].agg;
  2862. iwl4965_tx_status_reply_tx(priv, agg,
  2863. (struct iwl4965_tx_resp_agg *)tx_resp, index);
  2864. if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) {
  2865. /* TODO: send BAR */
  2866. }
  2867. if (txq->q.read_ptr != (scd_ssn & 0xff)) {
  2868. int freed, ampdu_q;
  2869. index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
  2870. IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
  2871. "%d index %d\n", scd_ssn , index);
  2872. freed = iwl_tx_queue_reclaim(priv, txq_id, index);
  2873. priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
  2874. if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
  2875. txq_id >= 0 && priv->mac80211_registered &&
  2876. agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) {
  2877. /* calculate mac80211 ampdu sw queue to wake */
  2878. ampdu_q = txq_id - IWL_BACK_QUEUE_FIRST_ID +
  2879. priv->hw->queues;
  2880. if (agg->state == IWL_AGG_OFF)
  2881. ieee80211_wake_queue(priv->hw, txq_id);
  2882. else
  2883. ieee80211_wake_queue(priv->hw, ampdu_q);
  2884. }
  2885. iwl_txq_check_empty(priv, sta_id, tid, txq_id);
  2886. }
  2887. } else {
  2888. info->status.retry_count = tx_resp->failure_frame;
  2889. info->flags |=
  2890. iwl_is_tx_success(status) ? IEEE80211_TX_STAT_ACK : 0;
  2891. iwl4965_hwrate_to_tx_control(priv,
  2892. le32_to_cpu(tx_resp->rate_n_flags),
  2893. info);
  2894. IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags "
  2895. "0x%x retries %d\n", txq_id,
  2896. iwl_get_tx_fail_reason(status),
  2897. status, le32_to_cpu(tx_resp->rate_n_flags),
  2898. tx_resp->failure_frame);
  2899. IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
  2900. if (index != -1) {
  2901. int freed = iwl_tx_queue_reclaim(priv, txq_id, index);
  2902. if (tid != MAX_TID_COUNT)
  2903. priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
  2904. if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
  2905. (txq_id >= 0) && priv->mac80211_registered)
  2906. ieee80211_wake_queue(priv->hw, txq_id);
  2907. if (tid != MAX_TID_COUNT)
  2908. iwl_txq_check_empty(priv, sta_id, tid, txq_id);
  2909. }
  2910. }
  2911. if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
  2912. IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
  2913. }
  2914. /* Set up 4965-specific Rx frame reply handlers */
  2915. static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
  2916. {
  2917. /* Legacy Rx frames */
  2918. priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
  2919. /* Tx response */
  2920. priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
  2921. /* block ack */
  2922. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
  2923. }
  2924. static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
  2925. {
  2926. INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
  2927. }
  2928. static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
  2929. {
  2930. cancel_work_sync(&priv->txpower_work);
  2931. }
  2932. static struct iwl_hcmd_ops iwl4965_hcmd = {
  2933. .rxon_assoc = iwl4965_send_rxon_assoc,
  2934. };
  2935. static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
  2936. .get_hcmd_size = iwl4965_get_hcmd_size,
  2937. .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
  2938. .chain_noise_reset = iwl4965_chain_noise_reset,
  2939. .gain_computation = iwl4965_gain_computation,
  2940. };
  2941. static struct iwl_lib_ops iwl4965_lib = {
  2942. .set_hw_params = iwl4965_hw_set_hw_params,
  2943. .alloc_shared_mem = iwl4965_alloc_shared_mem,
  2944. .free_shared_mem = iwl4965_free_shared_mem,
  2945. .shared_mem_rx_idx = iwl4965_shared_mem_rx_idx,
  2946. .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
  2947. .txq_set_sched = iwl4965_txq_set_sched,
  2948. .txq_agg_enable = iwl4965_txq_agg_enable,
  2949. .txq_agg_disable = iwl4965_txq_agg_disable,
  2950. .rx_handler_setup = iwl4965_rx_handler_setup,
  2951. .setup_deferred_work = iwl4965_setup_deferred_work,
  2952. .cancel_deferred_work = iwl4965_cancel_deferred_work,
  2953. .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
  2954. .alive_notify = iwl4965_alive_notify,
  2955. .init_alive_start = iwl4965_init_alive_start,
  2956. .load_ucode = iwl4965_load_bsm,
  2957. .apm_ops = {
  2958. .init = iwl4965_apm_init,
  2959. .reset = iwl4965_apm_reset,
  2960. .stop = iwl4965_apm_stop,
  2961. .config = iwl4965_nic_config,
  2962. .set_pwr_src = iwl4965_set_pwr_src,
  2963. },
  2964. .eeprom_ops = {
  2965. .regulatory_bands = {
  2966. EEPROM_REGULATORY_BAND_1_CHANNELS,
  2967. EEPROM_REGULATORY_BAND_2_CHANNELS,
  2968. EEPROM_REGULATORY_BAND_3_CHANNELS,
  2969. EEPROM_REGULATORY_BAND_4_CHANNELS,
  2970. EEPROM_REGULATORY_BAND_5_CHANNELS,
  2971. EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
  2972. EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
  2973. },
  2974. .verify_signature = iwlcore_eeprom_verify_signature,
  2975. .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
  2976. .release_semaphore = iwlcore_eeprom_release_semaphore,
  2977. .check_version = iwl4965_eeprom_check_version,
  2978. .query_addr = iwlcore_eeprom_query_addr,
  2979. },
  2980. .radio_kill_sw = iwl4965_radio_kill_sw,
  2981. .set_power = iwl4965_set_power,
  2982. .update_chain_flags = iwl4965_update_chain_flags,
  2983. };
  2984. static struct iwl_ops iwl4965_ops = {
  2985. .lib = &iwl4965_lib,
  2986. .hcmd = &iwl4965_hcmd,
  2987. .utils = &iwl4965_hcmd_utils,
  2988. };
  2989. struct iwl_cfg iwl4965_agn_cfg = {
  2990. .name = "4965AGN",
  2991. .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
  2992. .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
  2993. .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
  2994. .ops = &iwl4965_ops,
  2995. .mod_params = &iwl4965_mod_params,
  2996. };
  2997. module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
  2998. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  2999. module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
  3000. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  3001. module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
  3002. MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])\n");
  3003. module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
  3004. MODULE_PARM_DESC(debug, "debug output mask");
  3005. module_param_named(
  3006. disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
  3007. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  3008. module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
  3009. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  3010. /* QoS */
  3011. module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
  3012. MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
  3013. module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
  3014. MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
  3015. module_param_named(fw_restart4965, iwl4965_mod_params.restart_fw, int, 0444);
  3016. MODULE_PARM_DESC(fw_restart4965, "restart firmware in case of error");