ab3550-core.c 30 KB

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  1. /*
  2. * Copyright (C) 2007-2010 ST-Ericsson
  3. * License terms: GNU General Public License (GPL) version 2
  4. * Low-level core for exclusive access to the AB3550 IC on the I2C bus
  5. * and some basic chip-configuration.
  6. * Author: Bengt Jonsson <bengt.g.jonsson@stericsson.com>
  7. * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
  8. * Author: Mattias Wallin <mattias.wallin@stericsson.com>
  9. * Author: Rickard Andersson <rickard.andersson@stericsson.com>
  10. */
  11. #include <linux/i2c.h>
  12. #include <linux/mutex.h>
  13. #include <linux/module.h>
  14. #include <linux/err.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/slab.h>
  17. #include <linux/device.h>
  18. #include <linux/irq.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/random.h>
  21. #include <linux/workqueue.h>
  22. #include <linux/debugfs.h>
  23. #include <linux/seq_file.h>
  24. #include <linux/uaccess.h>
  25. #include <linux/mfd/abx500.h>
  26. #include <linux/list.h>
  27. #include <linux/bitops.h>
  28. #include <linux/spinlock.h>
  29. #include <linux/mfd/core.h>
  30. #define AB3550_NAME_STRING "ab3550"
  31. #define AB3550_ID_FORMAT_STRING "AB3550 %s"
  32. #define AB3550_NUM_BANKS 2
  33. #define AB3550_NUM_EVENT_REG 5
  34. /* These are the only registers inside AB3550 used in this main file */
  35. /* Chip ID register */
  36. #define AB3550_CID_REG 0x20
  37. /* Interrupt event registers */
  38. #define AB3550_EVENT_BANK 0
  39. #define AB3550_EVENT_REG 0x22
  40. /* Read/write operation values. */
  41. #define AB3550_PERM_RD (0x01)
  42. #define AB3550_PERM_WR (0x02)
  43. /* Read/write permissions. */
  44. #define AB3550_PERM_RO (AB3550_PERM_RD)
  45. #define AB3550_PERM_RW (AB3550_PERM_RD | AB3550_PERM_WR)
  46. /**
  47. * struct ab3550
  48. * @access_mutex: lock out concurrent accesses to the AB registers
  49. * @i2c_client: I2C client for this chip
  50. * @chip_name: name of this chip variant
  51. * @chip_id: 8 bit chip ID for this chip variant
  52. * @mask_work: a worker for writing to mask registers
  53. * @event_lock: a lock to protect the event_mask
  54. * @event_mask: a local copy of the mask event registers
  55. * @startup_events: a copy of the first reading of the event registers
  56. * @startup_events_read: whether the first events have been read
  57. */
  58. struct ab3550 {
  59. struct mutex access_mutex;
  60. struct i2c_client *i2c_client[AB3550_NUM_BANKS];
  61. char chip_name[32];
  62. u8 chip_id;
  63. struct work_struct mask_work;
  64. spinlock_t event_lock;
  65. u8 event_mask[AB3550_NUM_EVENT_REG];
  66. u8 startup_events[AB3550_NUM_EVENT_REG];
  67. bool startup_events_read;
  68. #ifdef CONFIG_DEBUG_FS
  69. unsigned int debug_bank;
  70. unsigned int debug_address;
  71. #endif
  72. };
  73. /**
  74. * struct ab3550_reg_range
  75. * @first: the first address of the range
  76. * @last: the last address of the range
  77. * @perm: access permissions for the range
  78. */
  79. struct ab3550_reg_range {
  80. u8 first;
  81. u8 last;
  82. u8 perm;
  83. };
  84. /**
  85. * struct ab3550_reg_ranges
  86. * @count: the number of ranges in the list
  87. * @range: the list of register ranges
  88. */
  89. struct ab3550_reg_ranges {
  90. u8 count;
  91. const struct ab3550_reg_range *range;
  92. };
  93. /*
  94. * Permissible register ranges for reading and writing per device and bank.
  95. *
  96. * The ranges must be listed in increasing address order, and no overlaps are
  97. * allowed. It is assumed that write permission implies read permission
  98. * (i.e. only RO and RW permissions should be used). Ranges with write
  99. * permission must not be split up.
  100. */
  101. #define NO_RANGE {.count = 0, .range = NULL,}
  102. static struct
  103. ab3550_reg_ranges ab3550_reg_ranges[AB3550_NUM_DEVICES][AB3550_NUM_BANKS] = {
  104. [AB3550_DEVID_DAC] = {
  105. NO_RANGE,
  106. {
  107. .count = 2,
  108. .range = (struct ab3550_reg_range[]) {
  109. {
  110. .first = 0xb0,
  111. .last = 0xba,
  112. .perm = AB3550_PERM_RW,
  113. },
  114. {
  115. .first = 0xbc,
  116. .last = 0xc3,
  117. .perm = AB3550_PERM_RW,
  118. },
  119. },
  120. },
  121. },
  122. [AB3550_DEVID_LEDS] = {
  123. NO_RANGE,
  124. {
  125. .count = 2,
  126. .range = (struct ab3550_reg_range[]) {
  127. {
  128. .first = 0x5a,
  129. .last = 0x88,
  130. .perm = AB3550_PERM_RW,
  131. },
  132. {
  133. .first = 0x8a,
  134. .last = 0xad,
  135. .perm = AB3550_PERM_RW,
  136. },
  137. }
  138. },
  139. },
  140. [AB3550_DEVID_POWER] = {
  141. {
  142. .count = 1,
  143. .range = (struct ab3550_reg_range[]) {
  144. {
  145. .first = 0x21,
  146. .last = 0x21,
  147. .perm = AB3550_PERM_RO,
  148. },
  149. }
  150. },
  151. NO_RANGE,
  152. },
  153. [AB3550_DEVID_REGULATORS] = {
  154. {
  155. .count = 1,
  156. .range = (struct ab3550_reg_range[]) {
  157. {
  158. .first = 0x69,
  159. .last = 0xa3,
  160. .perm = AB3550_PERM_RW,
  161. },
  162. }
  163. },
  164. {
  165. .count = 1,
  166. .range = (struct ab3550_reg_range[]) {
  167. {
  168. .first = 0x14,
  169. .last = 0x16,
  170. .perm = AB3550_PERM_RW,
  171. },
  172. }
  173. },
  174. },
  175. [AB3550_DEVID_SIM] = {
  176. {
  177. .count = 1,
  178. .range = (struct ab3550_reg_range[]) {
  179. {
  180. .first = 0x21,
  181. .last = 0x21,
  182. .perm = AB3550_PERM_RO,
  183. },
  184. }
  185. },
  186. {
  187. .count = 1,
  188. .range = (struct ab3550_reg_range[]) {
  189. {
  190. .first = 0x14,
  191. .last = 0x17,
  192. .perm = AB3550_PERM_RW,
  193. },
  194. }
  195. },
  196. },
  197. [AB3550_DEVID_UART] = {
  198. NO_RANGE,
  199. NO_RANGE,
  200. },
  201. [AB3550_DEVID_RTC] = {
  202. {
  203. .count = 1,
  204. .range = (struct ab3550_reg_range[]) {
  205. {
  206. .first = 0x00,
  207. .last = 0x0c,
  208. .perm = AB3550_PERM_RW,
  209. },
  210. }
  211. },
  212. NO_RANGE,
  213. },
  214. [AB3550_DEVID_CHARGER] = {
  215. {
  216. .count = 2,
  217. .range = (struct ab3550_reg_range[]) {
  218. {
  219. .first = 0x10,
  220. .last = 0x1a,
  221. .perm = AB3550_PERM_RW,
  222. },
  223. {
  224. .first = 0x21,
  225. .last = 0x21,
  226. .perm = AB3550_PERM_RO,
  227. },
  228. }
  229. },
  230. NO_RANGE,
  231. },
  232. [AB3550_DEVID_ADC] = {
  233. NO_RANGE,
  234. {
  235. .count = 1,
  236. .range = (struct ab3550_reg_range[]) {
  237. {
  238. .first = 0x20,
  239. .last = 0x56,
  240. .perm = AB3550_PERM_RW,
  241. },
  242. }
  243. },
  244. },
  245. [AB3550_DEVID_FUELGAUGE] = {
  246. {
  247. .count = 1,
  248. .range = (struct ab3550_reg_range[]) {
  249. {
  250. .first = 0x21,
  251. .last = 0x21,
  252. .perm = AB3550_PERM_RO,
  253. },
  254. }
  255. },
  256. {
  257. .count = 1,
  258. .range = (struct ab3550_reg_range[]) {
  259. {
  260. .first = 0x00,
  261. .last = 0x0e,
  262. .perm = AB3550_PERM_RW,
  263. },
  264. }
  265. },
  266. },
  267. [AB3550_DEVID_VIBRATOR] = {
  268. NO_RANGE,
  269. {
  270. .count = 1,
  271. .range = (struct ab3550_reg_range[]) {
  272. {
  273. .first = 0x10,
  274. .last = 0x13,
  275. .perm = AB3550_PERM_RW,
  276. },
  277. }
  278. },
  279. },
  280. [AB3550_DEVID_CODEC] = {
  281. {
  282. .count = 2,
  283. .range = (struct ab3550_reg_range[]) {
  284. {
  285. .first = 0x31,
  286. .last = 0x63,
  287. .perm = AB3550_PERM_RW,
  288. },
  289. {
  290. .first = 0x65,
  291. .last = 0x68,
  292. .perm = AB3550_PERM_RW,
  293. },
  294. }
  295. },
  296. NO_RANGE,
  297. },
  298. };
  299. static struct mfd_cell ab3550_devs[AB3550_NUM_DEVICES] = {
  300. [AB3550_DEVID_DAC] = {
  301. .name = "ab3550-dac",
  302. .id = AB3550_DEVID_DAC,
  303. .num_resources = 0,
  304. },
  305. [AB3550_DEVID_LEDS] = {
  306. .name = "ab3550-leds",
  307. .id = AB3550_DEVID_LEDS,
  308. },
  309. [AB3550_DEVID_POWER] = {
  310. .name = "ab3550-power",
  311. .id = AB3550_DEVID_POWER,
  312. },
  313. [AB3550_DEVID_REGULATORS] = {
  314. .name = "ab3550-regulators",
  315. .id = AB3550_DEVID_REGULATORS,
  316. },
  317. [AB3550_DEVID_SIM] = {
  318. .name = "ab3550-sim",
  319. .id = AB3550_DEVID_SIM,
  320. },
  321. [AB3550_DEVID_UART] = {
  322. .name = "ab3550-uart",
  323. .id = AB3550_DEVID_UART,
  324. },
  325. [AB3550_DEVID_RTC] = {
  326. .name = "ab3550-rtc",
  327. .id = AB3550_DEVID_RTC,
  328. },
  329. [AB3550_DEVID_CHARGER] = {
  330. .name = "ab3550-charger",
  331. .id = AB3550_DEVID_CHARGER,
  332. },
  333. [AB3550_DEVID_ADC] = {
  334. .name = "ab3550-adc",
  335. .id = AB3550_DEVID_ADC,
  336. .num_resources = 10,
  337. .resources = (struct resource[]) {
  338. {
  339. .name = "TRIGGER-0",
  340. .flags = IORESOURCE_IRQ,
  341. .start = 16,
  342. .end = 16,
  343. },
  344. {
  345. .name = "TRIGGER-1",
  346. .flags = IORESOURCE_IRQ,
  347. .start = 17,
  348. .end = 17,
  349. },
  350. {
  351. .name = "TRIGGER-2",
  352. .flags = IORESOURCE_IRQ,
  353. .start = 18,
  354. .end = 18,
  355. },
  356. {
  357. .name = "TRIGGER-3",
  358. .flags = IORESOURCE_IRQ,
  359. .start = 19,
  360. .end = 19,
  361. },
  362. {
  363. .name = "TRIGGER-4",
  364. .flags = IORESOURCE_IRQ,
  365. .start = 20,
  366. .end = 20,
  367. },
  368. {
  369. .name = "TRIGGER-5",
  370. .flags = IORESOURCE_IRQ,
  371. .start = 21,
  372. .end = 21,
  373. },
  374. {
  375. .name = "TRIGGER-6",
  376. .flags = IORESOURCE_IRQ,
  377. .start = 22,
  378. .end = 22,
  379. },
  380. {
  381. .name = "TRIGGER-7",
  382. .flags = IORESOURCE_IRQ,
  383. .start = 23,
  384. .end = 23,
  385. },
  386. {
  387. .name = "TRIGGER-VBAT-TXON",
  388. .flags = IORESOURCE_IRQ,
  389. .start = 13,
  390. .end = 13,
  391. },
  392. {
  393. .name = "TRIGGER-VBAT",
  394. .flags = IORESOURCE_IRQ,
  395. .start = 12,
  396. .end = 12,
  397. },
  398. },
  399. },
  400. [AB3550_DEVID_FUELGAUGE] = {
  401. .name = "ab3550-fuelgauge",
  402. .id = AB3550_DEVID_FUELGAUGE,
  403. },
  404. [AB3550_DEVID_VIBRATOR] = {
  405. .name = "ab3550-vibrator",
  406. .id = AB3550_DEVID_VIBRATOR,
  407. },
  408. [AB3550_DEVID_CODEC] = {
  409. .name = "ab3550-codec",
  410. .id = AB3550_DEVID_CODEC,
  411. },
  412. };
  413. /*
  414. * I2C transactions with error messages.
  415. */
  416. static int ab3550_i2c_master_send(struct ab3550 *ab, u8 bank, u8 *data,
  417. u8 count)
  418. {
  419. int err;
  420. err = i2c_master_send(ab->i2c_client[bank], data, count);
  421. if (err < 0) {
  422. dev_err(&ab->i2c_client[0]->dev, "send error: %d\n", err);
  423. return err;
  424. }
  425. return 0;
  426. }
  427. static int ab3550_i2c_master_recv(struct ab3550 *ab, u8 bank, u8 *data,
  428. u8 count)
  429. {
  430. int err;
  431. err = i2c_master_recv(ab->i2c_client[bank], data, count);
  432. if (err < 0) {
  433. dev_err(&ab->i2c_client[0]->dev, "receive error: %d\n", err);
  434. return err;
  435. }
  436. return 0;
  437. }
  438. /*
  439. * Functionality for getting/setting register values.
  440. */
  441. static int get_register_interruptible(struct ab3550 *ab, u8 bank, u8 reg,
  442. u8 *value)
  443. {
  444. int err;
  445. err = mutex_lock_interruptible(&ab->access_mutex);
  446. if (err)
  447. return err;
  448. err = ab3550_i2c_master_send(ab, bank, &reg, 1);
  449. if (!err)
  450. err = ab3550_i2c_master_recv(ab, bank, value, 1);
  451. mutex_unlock(&ab->access_mutex);
  452. return err;
  453. }
  454. static int get_register_page_interruptible(struct ab3550 *ab, u8 bank,
  455. u8 first_reg, u8 *regvals, u8 numregs)
  456. {
  457. int err;
  458. err = mutex_lock_interruptible(&ab->access_mutex);
  459. if (err)
  460. return err;
  461. err = ab3550_i2c_master_send(ab, bank, &first_reg, 1);
  462. if (!err)
  463. err = ab3550_i2c_master_recv(ab, bank, regvals, numregs);
  464. mutex_unlock(&ab->access_mutex);
  465. return err;
  466. }
  467. static int mask_and_set_register_interruptible(struct ab3550 *ab, u8 bank,
  468. u8 reg, u8 bitmask, u8 bitvalues)
  469. {
  470. int err = 0;
  471. if (likely(bitmask)) {
  472. u8 reg_bits[2] = {reg, 0};
  473. err = mutex_lock_interruptible(&ab->access_mutex);
  474. if (err)
  475. return err;
  476. if (bitmask == 0xFF) /* No need to read in this case. */
  477. reg_bits[1] = bitvalues;
  478. else { /* Read and modify the register value. */
  479. u8 bits;
  480. err = ab3550_i2c_master_send(ab, bank, &reg, 1);
  481. if (err)
  482. goto unlock_and_return;
  483. err = ab3550_i2c_master_recv(ab, bank, &bits, 1);
  484. if (err)
  485. goto unlock_and_return;
  486. reg_bits[1] = ((~bitmask & bits) |
  487. (bitmask & bitvalues));
  488. }
  489. /* Write the new value. */
  490. err = ab3550_i2c_master_send(ab, bank, reg_bits, 2);
  491. unlock_and_return:
  492. mutex_unlock(&ab->access_mutex);
  493. }
  494. return err;
  495. }
  496. /*
  497. * Read/write permission checking functions.
  498. */
  499. static bool page_write_allowed(const struct ab3550_reg_ranges *ranges,
  500. u8 first_reg, u8 last_reg)
  501. {
  502. u8 i;
  503. if (last_reg < first_reg)
  504. return false;
  505. for (i = 0; i < ranges->count; i++) {
  506. if (first_reg < ranges->range[i].first)
  507. break;
  508. if ((last_reg <= ranges->range[i].last) &&
  509. (ranges->range[i].perm & AB3550_PERM_WR))
  510. return true;
  511. }
  512. return false;
  513. }
  514. static bool reg_write_allowed(const struct ab3550_reg_ranges *ranges, u8 reg)
  515. {
  516. return page_write_allowed(ranges, reg, reg);
  517. }
  518. static bool page_read_allowed(const struct ab3550_reg_ranges *ranges,
  519. u8 first_reg, u8 last_reg)
  520. {
  521. u8 i;
  522. if (last_reg < first_reg)
  523. return false;
  524. /* Find the range (if it exists in the list) that includes first_reg. */
  525. for (i = 0; i < ranges->count; i++) {
  526. if (first_reg < ranges->range[i].first)
  527. return false;
  528. if (first_reg <= ranges->range[i].last)
  529. break;
  530. }
  531. /* Make sure that the entire range up to and including last_reg is
  532. * readable. This may span several of the ranges in the list.
  533. */
  534. while ((i < ranges->count) &&
  535. (ranges->range[i].perm & AB3550_PERM_RD)) {
  536. if (last_reg <= ranges->range[i].last)
  537. return true;
  538. if ((++i >= ranges->count) ||
  539. (ranges->range[i].first !=
  540. (ranges->range[i - 1].last + 1))) {
  541. break;
  542. }
  543. }
  544. return false;
  545. }
  546. static bool reg_read_allowed(const struct ab3550_reg_ranges *ranges, u8 reg)
  547. {
  548. return page_read_allowed(ranges, reg, reg);
  549. }
  550. /*
  551. * The register access functionality.
  552. */
  553. static int ab3550_get_chip_id(struct device *dev)
  554. {
  555. struct ab3550 *ab = dev_get_drvdata(dev->parent);
  556. return (int)ab->chip_id;
  557. }
  558. static int ab3550_mask_and_set_register_interruptible(struct device *dev,
  559. u8 bank, u8 reg, u8 bitmask, u8 bitvalues)
  560. {
  561. struct ab3550 *ab;
  562. struct platform_device *pdev = to_platform_device(dev);
  563. if ((AB3550_NUM_BANKS <= bank) ||
  564. !reg_write_allowed(&ab3550_reg_ranges[pdev->id][bank], reg))
  565. return -EINVAL;
  566. ab = dev_get_drvdata(dev->parent);
  567. return mask_and_set_register_interruptible(ab, bank, reg,
  568. bitmask, bitvalues);
  569. }
  570. static int ab3550_set_register_interruptible(struct device *dev, u8 bank,
  571. u8 reg, u8 value)
  572. {
  573. return ab3550_mask_and_set_register_interruptible(dev, bank, reg, 0xFF,
  574. value);
  575. }
  576. static int ab3550_get_register_interruptible(struct device *dev, u8 bank,
  577. u8 reg, u8 *value)
  578. {
  579. struct ab3550 *ab;
  580. struct platform_device *pdev = to_platform_device(dev);
  581. if ((AB3550_NUM_BANKS <= bank) ||
  582. !reg_read_allowed(&ab3550_reg_ranges[pdev->id][bank], reg))
  583. return -EINVAL;
  584. ab = dev_get_drvdata(dev->parent);
  585. return get_register_interruptible(ab, bank, reg, value);
  586. }
  587. static int ab3550_get_register_page_interruptible(struct device *dev, u8 bank,
  588. u8 first_reg, u8 *regvals, u8 numregs)
  589. {
  590. struct ab3550 *ab;
  591. struct platform_device *pdev = to_platform_device(dev);
  592. if ((AB3550_NUM_BANKS <= bank) ||
  593. !page_read_allowed(&ab3550_reg_ranges[pdev->id][bank],
  594. first_reg, (first_reg + numregs - 1)))
  595. return -EINVAL;
  596. ab = dev_get_drvdata(dev->parent);
  597. return get_register_page_interruptible(ab, bank, first_reg, regvals,
  598. numregs);
  599. }
  600. static int ab3550_event_registers_startup_state_get(struct device *dev,
  601. u8 *event)
  602. {
  603. struct ab3550 *ab;
  604. ab = dev_get_drvdata(dev->parent);
  605. if (!ab->startup_events_read)
  606. return -EAGAIN; /* Try again later */
  607. memcpy(event, ab->startup_events, AB3550_NUM_EVENT_REG);
  608. return 0;
  609. }
  610. static int ab3550_startup_irq_enabled(struct device *dev, unsigned int irq)
  611. {
  612. struct ab3550 *ab;
  613. struct ab3550_platform_data *plf_data;
  614. bool val;
  615. ab = irq_get_chip_data(irq);
  616. plf_data = ab->i2c_client[0]->dev.platform_data;
  617. irq -= plf_data->irq.base;
  618. val = ((ab->startup_events[irq / 8] & BIT(irq % 8)) != 0);
  619. return val;
  620. }
  621. static struct abx500_ops ab3550_ops = {
  622. .get_chip_id = ab3550_get_chip_id,
  623. .get_register = ab3550_get_register_interruptible,
  624. .set_register = ab3550_set_register_interruptible,
  625. .get_register_page = ab3550_get_register_page_interruptible,
  626. .set_register_page = NULL,
  627. .mask_and_set_register = ab3550_mask_and_set_register_interruptible,
  628. .event_registers_startup_state_get =
  629. ab3550_event_registers_startup_state_get,
  630. .startup_irq_enabled = ab3550_startup_irq_enabled,
  631. };
  632. static irqreturn_t ab3550_irq_handler(int irq, void *data)
  633. {
  634. struct ab3550 *ab = data;
  635. int err;
  636. unsigned int i;
  637. u8 e[AB3550_NUM_EVENT_REG];
  638. u8 *events;
  639. unsigned long flags;
  640. events = (ab->startup_events_read ? e : ab->startup_events);
  641. err = get_register_page_interruptible(ab, AB3550_EVENT_BANK,
  642. AB3550_EVENT_REG, events, AB3550_NUM_EVENT_REG);
  643. if (err)
  644. goto err_event_rd;
  645. if (!ab->startup_events_read) {
  646. dev_info(&ab->i2c_client[0]->dev,
  647. "startup events 0x%x,0x%x,0x%x,0x%x,0x%x\n",
  648. ab->startup_events[0], ab->startup_events[1],
  649. ab->startup_events[2], ab->startup_events[3],
  650. ab->startup_events[4]);
  651. ab->startup_events_read = true;
  652. goto out;
  653. }
  654. /* The two highest bits in event[4] are not used. */
  655. events[4] &= 0x3f;
  656. spin_lock_irqsave(&ab->event_lock, flags);
  657. for (i = 0; i < AB3550_NUM_EVENT_REG; i++)
  658. events[i] &= ~ab->event_mask[i];
  659. spin_unlock_irqrestore(&ab->event_lock, flags);
  660. for (i = 0; i < AB3550_NUM_EVENT_REG; i++) {
  661. u8 bit;
  662. u8 event_reg;
  663. dev_dbg(&ab->i2c_client[0]->dev, "IRQ Event[%d]: 0x%2x\n",
  664. i, events[i]);
  665. event_reg = events[i];
  666. for (bit = 0; event_reg; bit++, event_reg /= 2) {
  667. if (event_reg % 2) {
  668. unsigned int irq;
  669. struct ab3550_platform_data *plf_data;
  670. plf_data = ab->i2c_client[0]->dev.platform_data;
  671. irq = plf_data->irq.base + (i * 8) + bit;
  672. handle_nested_irq(irq);
  673. }
  674. }
  675. }
  676. out:
  677. return IRQ_HANDLED;
  678. err_event_rd:
  679. dev_dbg(&ab->i2c_client[0]->dev, "error reading event registers\n");
  680. return IRQ_HANDLED;
  681. }
  682. #ifdef CONFIG_DEBUG_FS
  683. static struct ab3550_reg_ranges debug_ranges[AB3550_NUM_BANKS] = {
  684. {
  685. .count = 6,
  686. .range = (struct ab3550_reg_range[]) {
  687. {
  688. .first = 0x00,
  689. .last = 0x0e,
  690. },
  691. {
  692. .first = 0x10,
  693. .last = 0x1a,
  694. },
  695. {
  696. .first = 0x1e,
  697. .last = 0x4f,
  698. },
  699. {
  700. .first = 0x51,
  701. .last = 0x63,
  702. },
  703. {
  704. .first = 0x65,
  705. .last = 0xa3,
  706. },
  707. {
  708. .first = 0xa5,
  709. .last = 0xa8,
  710. },
  711. }
  712. },
  713. {
  714. .count = 8,
  715. .range = (struct ab3550_reg_range[]) {
  716. {
  717. .first = 0x00,
  718. .last = 0x0e,
  719. },
  720. {
  721. .first = 0x10,
  722. .last = 0x17,
  723. },
  724. {
  725. .first = 0x1a,
  726. .last = 0x1c,
  727. },
  728. {
  729. .first = 0x20,
  730. .last = 0x56,
  731. },
  732. {
  733. .first = 0x5a,
  734. .last = 0x88,
  735. },
  736. {
  737. .first = 0x8a,
  738. .last = 0xad,
  739. },
  740. {
  741. .first = 0xb0,
  742. .last = 0xba,
  743. },
  744. {
  745. .first = 0xbc,
  746. .last = 0xc3,
  747. },
  748. }
  749. },
  750. };
  751. static int ab3550_registers_print(struct seq_file *s, void *p)
  752. {
  753. struct ab3550 *ab = s->private;
  754. int bank;
  755. seq_printf(s, AB3550_NAME_STRING " register values:\n");
  756. for (bank = 0; bank < AB3550_NUM_BANKS; bank++) {
  757. unsigned int i;
  758. seq_printf(s, " bank %d:\n", bank);
  759. for (i = 0; i < debug_ranges[bank].count; i++) {
  760. u8 reg;
  761. for (reg = debug_ranges[bank].range[i].first;
  762. reg <= debug_ranges[bank].range[i].last;
  763. reg++) {
  764. u8 value;
  765. get_register_interruptible(ab, bank, reg,
  766. &value);
  767. seq_printf(s, " [%d/0x%02X]: 0x%02X\n", bank,
  768. reg, value);
  769. }
  770. }
  771. }
  772. return 0;
  773. }
  774. static int ab3550_registers_open(struct inode *inode, struct file *file)
  775. {
  776. return single_open(file, ab3550_registers_print, inode->i_private);
  777. }
  778. static const struct file_operations ab3550_registers_fops = {
  779. .open = ab3550_registers_open,
  780. .read = seq_read,
  781. .llseek = seq_lseek,
  782. .release = single_release,
  783. .owner = THIS_MODULE,
  784. };
  785. static int ab3550_bank_print(struct seq_file *s, void *p)
  786. {
  787. struct ab3550 *ab = s->private;
  788. seq_printf(s, "%d\n", ab->debug_bank);
  789. return 0;
  790. }
  791. static int ab3550_bank_open(struct inode *inode, struct file *file)
  792. {
  793. return single_open(file, ab3550_bank_print, inode->i_private);
  794. }
  795. static ssize_t ab3550_bank_write(struct file *file,
  796. const char __user *user_buf,
  797. size_t count, loff_t *ppos)
  798. {
  799. struct ab3550 *ab = ((struct seq_file *)(file->private_data))->private;
  800. unsigned long user_bank;
  801. int err;
  802. /* Get userspace string and assure termination */
  803. err = kstrtoul_from_user(user_buf, count, 0, &user_bank);
  804. if (err)
  805. return err;
  806. if (user_bank >= AB3550_NUM_BANKS) {
  807. dev_err(&ab->i2c_client[0]->dev,
  808. "debugfs error input > number of banks\n");
  809. return -EINVAL;
  810. }
  811. ab->debug_bank = user_bank;
  812. return count;
  813. }
  814. static int ab3550_address_print(struct seq_file *s, void *p)
  815. {
  816. struct ab3550 *ab = s->private;
  817. seq_printf(s, "0x%02X\n", ab->debug_address);
  818. return 0;
  819. }
  820. static int ab3550_address_open(struct inode *inode, struct file *file)
  821. {
  822. return single_open(file, ab3550_address_print, inode->i_private);
  823. }
  824. static ssize_t ab3550_address_write(struct file *file,
  825. const char __user *user_buf,
  826. size_t count, loff_t *ppos)
  827. {
  828. struct ab3550 *ab = ((struct seq_file *)(file->private_data))->private;
  829. unsigned long user_address;
  830. int err;
  831. /* Get userspace string and assure termination */
  832. err = kstrtoul_from_user(user_buf, count, 0, &user_address);
  833. if (err)
  834. return err;
  835. if (user_address > 0xff) {
  836. dev_err(&ab->i2c_client[0]->dev,
  837. "debugfs error input > 0xff\n");
  838. return -EINVAL;
  839. }
  840. ab->debug_address = user_address;
  841. return count;
  842. }
  843. static int ab3550_val_print(struct seq_file *s, void *p)
  844. {
  845. struct ab3550 *ab = s->private;
  846. int err;
  847. u8 regvalue;
  848. err = get_register_interruptible(ab, (u8)ab->debug_bank,
  849. (u8)ab->debug_address, &regvalue);
  850. if (err)
  851. return -EINVAL;
  852. seq_printf(s, "0x%02X\n", regvalue);
  853. return 0;
  854. }
  855. static int ab3550_val_open(struct inode *inode, struct file *file)
  856. {
  857. return single_open(file, ab3550_val_print, inode->i_private);
  858. }
  859. static ssize_t ab3550_val_write(struct file *file,
  860. const char __user *user_buf,
  861. size_t count, loff_t *ppos)
  862. {
  863. struct ab3550 *ab = ((struct seq_file *)(file->private_data))->private;
  864. unsigned long user_val;
  865. int err;
  866. u8 regvalue;
  867. /* Get userspace string and assure termination */
  868. err = kstrtoul_from_user(user_buf, count, 0, &user_val);
  869. if (err)
  870. return err;
  871. if (user_val > 0xff) {
  872. dev_err(&ab->i2c_client[0]->dev,
  873. "debugfs error input > 0xff\n");
  874. return -EINVAL;
  875. }
  876. err = mask_and_set_register_interruptible(
  877. ab, (u8)ab->debug_bank,
  878. (u8)ab->debug_address, 0xFF, (u8)user_val);
  879. if (err)
  880. return -EINVAL;
  881. get_register_interruptible(ab, (u8)ab->debug_bank,
  882. (u8)ab->debug_address, &regvalue);
  883. if (err)
  884. return -EINVAL;
  885. return count;
  886. }
  887. static const struct file_operations ab3550_bank_fops = {
  888. .open = ab3550_bank_open,
  889. .write = ab3550_bank_write,
  890. .read = seq_read,
  891. .llseek = seq_lseek,
  892. .release = single_release,
  893. .owner = THIS_MODULE,
  894. };
  895. static const struct file_operations ab3550_address_fops = {
  896. .open = ab3550_address_open,
  897. .write = ab3550_address_write,
  898. .read = seq_read,
  899. .llseek = seq_lseek,
  900. .release = single_release,
  901. .owner = THIS_MODULE,
  902. };
  903. static const struct file_operations ab3550_val_fops = {
  904. .open = ab3550_val_open,
  905. .write = ab3550_val_write,
  906. .read = seq_read,
  907. .llseek = seq_lseek,
  908. .release = single_release,
  909. .owner = THIS_MODULE,
  910. };
  911. static struct dentry *ab3550_dir;
  912. static struct dentry *ab3550_reg_file;
  913. static struct dentry *ab3550_bank_file;
  914. static struct dentry *ab3550_address_file;
  915. static struct dentry *ab3550_val_file;
  916. static inline void ab3550_setup_debugfs(struct ab3550 *ab)
  917. {
  918. ab->debug_bank = 0;
  919. ab->debug_address = 0x00;
  920. ab3550_dir = debugfs_create_dir(AB3550_NAME_STRING, NULL);
  921. if (!ab3550_dir)
  922. goto exit_no_debugfs;
  923. ab3550_reg_file = debugfs_create_file("all-registers",
  924. S_IRUGO, ab3550_dir, ab, &ab3550_registers_fops);
  925. if (!ab3550_reg_file)
  926. goto exit_destroy_dir;
  927. ab3550_bank_file = debugfs_create_file("register-bank",
  928. (S_IRUGO | S_IWUSR), ab3550_dir, ab, &ab3550_bank_fops);
  929. if (!ab3550_bank_file)
  930. goto exit_destroy_reg;
  931. ab3550_address_file = debugfs_create_file("register-address",
  932. (S_IRUGO | S_IWUSR), ab3550_dir, ab, &ab3550_address_fops);
  933. if (!ab3550_address_file)
  934. goto exit_destroy_bank;
  935. ab3550_val_file = debugfs_create_file("register-value",
  936. (S_IRUGO | S_IWUSR), ab3550_dir, ab, &ab3550_val_fops);
  937. if (!ab3550_val_file)
  938. goto exit_destroy_address;
  939. return;
  940. exit_destroy_address:
  941. debugfs_remove(ab3550_address_file);
  942. exit_destroy_bank:
  943. debugfs_remove(ab3550_bank_file);
  944. exit_destroy_reg:
  945. debugfs_remove(ab3550_reg_file);
  946. exit_destroy_dir:
  947. debugfs_remove(ab3550_dir);
  948. exit_no_debugfs:
  949. dev_err(&ab->i2c_client[0]->dev, "failed to create debugfs entries.\n");
  950. return;
  951. }
  952. static inline void ab3550_remove_debugfs(void)
  953. {
  954. debugfs_remove(ab3550_val_file);
  955. debugfs_remove(ab3550_address_file);
  956. debugfs_remove(ab3550_bank_file);
  957. debugfs_remove(ab3550_reg_file);
  958. debugfs_remove(ab3550_dir);
  959. }
  960. #else /* !CONFIG_DEBUG_FS */
  961. static inline void ab3550_setup_debugfs(struct ab3550 *ab)
  962. {
  963. }
  964. static inline void ab3550_remove_debugfs(void)
  965. {
  966. }
  967. #endif
  968. /*
  969. * Basic set-up, datastructure creation/destruction and I2C interface.
  970. * This sets up a default config in the AB3550 chip so that it
  971. * will work as expected.
  972. */
  973. static int __init ab3550_setup(struct ab3550 *ab)
  974. {
  975. int err = 0;
  976. int i;
  977. struct ab3550_platform_data *plf_data;
  978. struct abx500_init_settings *settings;
  979. plf_data = ab->i2c_client[0]->dev.platform_data;
  980. settings = plf_data->init_settings;
  981. for (i = 0; i < plf_data->init_settings_sz; i++) {
  982. err = mask_and_set_register_interruptible(ab,
  983. settings[i].bank,
  984. settings[i].reg,
  985. 0xFF, settings[i].setting);
  986. if (err)
  987. goto exit_no_setup;
  988. /* If event mask register update the event mask in ab3550 */
  989. if ((settings[i].bank == 0) &&
  990. (AB3550_IMR1 <= settings[i].reg) &&
  991. (settings[i].reg <= AB3550_IMR5)) {
  992. ab->event_mask[settings[i].reg - AB3550_IMR1] =
  993. settings[i].setting;
  994. }
  995. }
  996. exit_no_setup:
  997. return err;
  998. }
  999. static void ab3550_mask_work(struct work_struct *work)
  1000. {
  1001. struct ab3550 *ab = container_of(work, struct ab3550, mask_work);
  1002. int i;
  1003. unsigned long flags;
  1004. u8 mask[AB3550_NUM_EVENT_REG];
  1005. spin_lock_irqsave(&ab->event_lock, flags);
  1006. for (i = 0; i < AB3550_NUM_EVENT_REG; i++)
  1007. mask[i] = ab->event_mask[i];
  1008. spin_unlock_irqrestore(&ab->event_lock, flags);
  1009. for (i = 0; i < AB3550_NUM_EVENT_REG; i++) {
  1010. int err;
  1011. err = mask_and_set_register_interruptible(ab, 0,
  1012. (AB3550_IMR1 + i), ~0, mask[i]);
  1013. if (err)
  1014. dev_err(&ab->i2c_client[0]->dev,
  1015. "ab3550_mask_work failed 0x%x,0x%x\n",
  1016. (AB3550_IMR1 + i), mask[i]);
  1017. }
  1018. }
  1019. static void ab3550_mask(struct irq_data *data)
  1020. {
  1021. unsigned long flags;
  1022. struct ab3550 *ab;
  1023. struct ab3550_platform_data *plf_data;
  1024. int irq;
  1025. ab = irq_data_get_irq_chip_data(data);
  1026. plf_data = ab->i2c_client[0]->dev.platform_data;
  1027. irq = data->irq - plf_data->irq.base;
  1028. spin_lock_irqsave(&ab->event_lock, flags);
  1029. ab->event_mask[irq / 8] |= BIT(irq % 8);
  1030. spin_unlock_irqrestore(&ab->event_lock, flags);
  1031. schedule_work(&ab->mask_work);
  1032. }
  1033. static void ab3550_unmask(struct irq_data *data)
  1034. {
  1035. unsigned long flags;
  1036. struct ab3550 *ab;
  1037. struct ab3550_platform_data *plf_data;
  1038. int irq;
  1039. ab = irq_data_get_irq_chip_data(data);
  1040. plf_data = ab->i2c_client[0]->dev.platform_data;
  1041. irq = data->irq - plf_data->irq.base;
  1042. spin_lock_irqsave(&ab->event_lock, flags);
  1043. ab->event_mask[irq / 8] &= ~BIT(irq % 8);
  1044. spin_unlock_irqrestore(&ab->event_lock, flags);
  1045. schedule_work(&ab->mask_work);
  1046. }
  1047. static void noop(struct irq_data *data)
  1048. {
  1049. }
  1050. static struct irq_chip ab3550_irq_chip = {
  1051. .name = "ab3550-core", /* Keep the same name as the request */
  1052. .irq_disable = ab3550_mask, /* No default to mask in chip.c */
  1053. .irq_ack = noop,
  1054. .irq_mask = ab3550_mask,
  1055. .irq_unmask = ab3550_unmask,
  1056. };
  1057. struct ab_family_id {
  1058. u8 id;
  1059. char *name;
  1060. };
  1061. static const struct ab_family_id ids[] __initdata = {
  1062. /* AB3550 */
  1063. {
  1064. .id = AB3550_P1A,
  1065. .name = "P1A"
  1066. },
  1067. /* Terminator */
  1068. {
  1069. .id = 0x00,
  1070. }
  1071. };
  1072. static int __init ab3550_probe(struct i2c_client *client,
  1073. const struct i2c_device_id *id)
  1074. {
  1075. struct ab3550 *ab;
  1076. struct ab3550_platform_data *ab3550_plf_data =
  1077. client->dev.platform_data;
  1078. int err;
  1079. int i;
  1080. int num_i2c_clients = 0;
  1081. ab = kzalloc(sizeof(struct ab3550), GFP_KERNEL);
  1082. if (!ab) {
  1083. dev_err(&client->dev,
  1084. "could not allocate " AB3550_NAME_STRING " device\n");
  1085. return -ENOMEM;
  1086. }
  1087. /* Initialize data structure */
  1088. mutex_init(&ab->access_mutex);
  1089. spin_lock_init(&ab->event_lock);
  1090. ab->i2c_client[0] = client;
  1091. i2c_set_clientdata(client, ab);
  1092. /* Read chip ID register */
  1093. err = get_register_interruptible(ab, 0, AB3550_CID_REG, &ab->chip_id);
  1094. if (err) {
  1095. dev_err(&client->dev, "could not communicate with the analog "
  1096. "baseband chip\n");
  1097. goto exit_no_detect;
  1098. }
  1099. for (i = 0; ids[i].id != 0x0; i++) {
  1100. if (ids[i].id == ab->chip_id) {
  1101. snprintf(&ab->chip_name[0], sizeof(ab->chip_name) - 1,
  1102. AB3550_ID_FORMAT_STRING, ids[i].name);
  1103. break;
  1104. }
  1105. }
  1106. if (ids[i].id == 0x0) {
  1107. dev_err(&client->dev, "unknown analog baseband chip id: 0x%x\n",
  1108. ab->chip_id);
  1109. dev_err(&client->dev, "driver not started!\n");
  1110. goto exit_no_detect;
  1111. }
  1112. dev_info(&client->dev, "detected AB chip: %s\n", &ab->chip_name[0]);
  1113. /* Attach other dummy I2C clients. */
  1114. while (++num_i2c_clients < AB3550_NUM_BANKS) {
  1115. ab->i2c_client[num_i2c_clients] =
  1116. i2c_new_dummy(client->adapter,
  1117. (client->addr + num_i2c_clients));
  1118. if (!ab->i2c_client[num_i2c_clients]) {
  1119. err = -ENOMEM;
  1120. goto exit_no_dummy_client;
  1121. }
  1122. strlcpy(ab->i2c_client[num_i2c_clients]->name, id->name,
  1123. sizeof(ab->i2c_client[num_i2c_clients]->name));
  1124. }
  1125. err = ab3550_setup(ab);
  1126. if (err)
  1127. goto exit_no_setup;
  1128. INIT_WORK(&ab->mask_work, ab3550_mask_work);
  1129. for (i = 0; i < ab3550_plf_data->irq.count; i++) {
  1130. unsigned int irq;
  1131. irq = ab3550_plf_data->irq.base + i;
  1132. irq_set_chip_data(irq, ab);
  1133. irq_set_chip_and_handler(irq, &ab3550_irq_chip,
  1134. handle_simple_irq);
  1135. irq_set_nested_thread(irq, 1);
  1136. #ifdef CONFIG_ARM
  1137. set_irq_flags(irq, IRQF_VALID);
  1138. #else
  1139. irq_set_noprobe(irq);
  1140. #endif
  1141. }
  1142. err = request_threaded_irq(client->irq, NULL, ab3550_irq_handler,
  1143. IRQF_ONESHOT, "ab3550-core", ab);
  1144. /* This real unpredictable IRQ is of course sampled for entropy */
  1145. rand_initialize_irq(client->irq);
  1146. if (err)
  1147. goto exit_no_irq;
  1148. err = abx500_register_ops(&client->dev, &ab3550_ops);
  1149. if (err)
  1150. goto exit_no_ops;
  1151. /* Set up and register the platform devices. */
  1152. for (i = 0; i < AB3550_NUM_DEVICES; i++) {
  1153. ab3550_devs[i].platform_data = ab3550_plf_data->dev_data[i];
  1154. ab3550_devs[i].pdata_size = ab3550_plf_data->dev_data_sz[i];
  1155. }
  1156. err = mfd_add_devices(&client->dev, 0, ab3550_devs,
  1157. ARRAY_SIZE(ab3550_devs), NULL,
  1158. ab3550_plf_data->irq.base);
  1159. ab3550_setup_debugfs(ab);
  1160. return 0;
  1161. exit_no_ops:
  1162. exit_no_irq:
  1163. exit_no_setup:
  1164. exit_no_dummy_client:
  1165. /* Unregister the dummy i2c clients. */
  1166. while (--num_i2c_clients)
  1167. i2c_unregister_device(ab->i2c_client[num_i2c_clients]);
  1168. exit_no_detect:
  1169. kfree(ab);
  1170. return err;
  1171. }
  1172. static int __exit ab3550_remove(struct i2c_client *client)
  1173. {
  1174. struct ab3550 *ab = i2c_get_clientdata(client);
  1175. int num_i2c_clients = AB3550_NUM_BANKS;
  1176. mfd_remove_devices(&client->dev);
  1177. ab3550_remove_debugfs();
  1178. while (--num_i2c_clients)
  1179. i2c_unregister_device(ab->i2c_client[num_i2c_clients]);
  1180. /*
  1181. * At this point, all subscribers should have unregistered
  1182. * their notifiers so deactivate IRQ
  1183. */
  1184. free_irq(client->irq, ab);
  1185. kfree(ab);
  1186. return 0;
  1187. }
  1188. static const struct i2c_device_id ab3550_id[] = {
  1189. {AB3550_NAME_STRING, 0},
  1190. {}
  1191. };
  1192. MODULE_DEVICE_TABLE(i2c, ab3550_id);
  1193. static struct i2c_driver ab3550_driver = {
  1194. .driver = {
  1195. .name = AB3550_NAME_STRING,
  1196. .owner = THIS_MODULE,
  1197. },
  1198. .id_table = ab3550_id,
  1199. .probe = ab3550_probe,
  1200. .remove = __exit_p(ab3550_remove),
  1201. };
  1202. static int __init ab3550_i2c_init(void)
  1203. {
  1204. return i2c_add_driver(&ab3550_driver);
  1205. }
  1206. static void __exit ab3550_i2c_exit(void)
  1207. {
  1208. i2c_del_driver(&ab3550_driver);
  1209. }
  1210. subsys_initcall(ab3550_i2c_init);
  1211. module_exit(ab3550_i2c_exit);
  1212. MODULE_AUTHOR("Mattias Wallin <mattias.wallin@stericsson.com>");
  1213. MODULE_DESCRIPTION("AB3550 core driver");
  1214. MODULE_LICENSE("GPL");