iwl-agn.c 91 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330
  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/mac80211.h>
  42. #include <asm/div64.h>
  43. #define DRV_NAME "iwlagn"
  44. #include "iwl-eeprom.h"
  45. #include "iwl-dev.h"
  46. #include "iwl-core.h"
  47. #include "iwl-io.h"
  48. #include "iwl-helpers.h"
  49. #include "iwl-sta.h"
  50. #include "iwl-calib.h"
  51. /******************************************************************************
  52. *
  53. * module boiler plate
  54. *
  55. ******************************************************************************/
  56. /*
  57. * module name, copyright, version, etc.
  58. */
  59. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  60. #ifdef CONFIG_IWLWIFI_DEBUG
  61. #define VD "d"
  62. #else
  63. #define VD
  64. #endif
  65. #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
  66. #define VS "s"
  67. #else
  68. #define VS
  69. #endif
  70. #define DRV_VERSION IWLWIFI_VERSION VD VS
  71. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  72. MODULE_VERSION(DRV_VERSION);
  73. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  74. MODULE_LICENSE("GPL");
  75. MODULE_ALIAS("iwl4965");
  76. /*************** STATION TABLE MANAGEMENT ****
  77. * mac80211 should be examined to determine if sta_info is duplicating
  78. * the functionality provided here
  79. */
  80. /**************************************************************/
  81. /**
  82. * iwl_commit_rxon - commit staging_rxon to hardware
  83. *
  84. * The RXON command in staging_rxon is committed to the hardware and
  85. * the active_rxon structure is updated with the new data. This
  86. * function correctly transitions out of the RXON_ASSOC_MSK state if
  87. * a HW tune is required based on the RXON structure changes.
  88. */
  89. int iwl_commit_rxon(struct iwl_priv *priv)
  90. {
  91. /* cast away the const for active_rxon in this function */
  92. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  93. int ret;
  94. bool new_assoc =
  95. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  96. if (!iwl_is_alive(priv))
  97. return -EBUSY;
  98. /* always get timestamp with Rx frame */
  99. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  100. ret = iwl_check_rxon_cmd(priv);
  101. if (ret) {
  102. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  103. return -EINVAL;
  104. }
  105. /* If we don't need to send a full RXON, we can use
  106. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  107. * and other flags for the current radio configuration. */
  108. if (!iwl_full_rxon_required(priv)) {
  109. ret = iwl_send_rxon_assoc(priv);
  110. if (ret) {
  111. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  112. return ret;
  113. }
  114. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  115. return 0;
  116. }
  117. /* station table will be cleared */
  118. priv->assoc_station_added = 0;
  119. /* If we are currently associated and the new config requires
  120. * an RXON_ASSOC and the new config wants the associated mask enabled,
  121. * we must clear the associated from the active configuration
  122. * before we apply the new config */
  123. if (iwl_is_associated(priv) && new_assoc) {
  124. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  125. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  126. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  127. sizeof(struct iwl_rxon_cmd),
  128. &priv->active_rxon);
  129. /* If the mask clearing failed then we set
  130. * active_rxon back to what it was previously */
  131. if (ret) {
  132. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  133. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  134. return ret;
  135. }
  136. }
  137. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  138. "* with%s RXON_FILTER_ASSOC_MSK\n"
  139. "* channel = %d\n"
  140. "* bssid = %pM\n",
  141. (new_assoc ? "" : "out"),
  142. le16_to_cpu(priv->staging_rxon.channel),
  143. priv->staging_rxon.bssid_addr);
  144. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  145. /* Apply the new configuration
  146. * RXON unassoc clears the station table in uCode, send it before
  147. * we add the bcast station. If assoc bit is set, we will send RXON
  148. * after having added the bcast and bssid station.
  149. */
  150. if (!new_assoc) {
  151. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  152. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  153. if (ret) {
  154. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  155. return ret;
  156. }
  157. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  158. }
  159. iwl_clear_stations_table(priv);
  160. priv->start_calib = 0;
  161. /* Add the broadcast address so we can send broadcast frames */
  162. if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
  163. IWL_INVALID_STATION) {
  164. IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
  165. return -EIO;
  166. }
  167. /* If we have set the ASSOC_MSK and we are in BSS mode then
  168. * add the IWL_AP_ID to the station rate table */
  169. if (new_assoc) {
  170. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  171. ret = iwl_rxon_add_station(priv,
  172. priv->active_rxon.bssid_addr, 1);
  173. if (ret == IWL_INVALID_STATION) {
  174. IWL_ERR(priv,
  175. "Error adding AP address for TX.\n");
  176. return -EIO;
  177. }
  178. priv->assoc_station_added = 1;
  179. if (priv->default_wep_key &&
  180. iwl_send_static_wepkey_cmd(priv, 0))
  181. IWL_ERR(priv,
  182. "Could not send WEP static key.\n");
  183. }
  184. /*
  185. * allow CTS-to-self if possible for new association.
  186. * this is relevant only for 5000 series and up,
  187. * but will not damage 4965
  188. */
  189. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  190. /* Apply the new configuration
  191. * RXON assoc doesn't clear the station table in uCode,
  192. */
  193. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  194. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  195. if (ret) {
  196. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  197. return ret;
  198. }
  199. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  200. }
  201. iwl_init_sensitivity(priv);
  202. /* If we issue a new RXON command which required a tune then we must
  203. * send a new TXPOWER command or we won't be able to Tx any frames */
  204. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  205. if (ret) {
  206. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  207. return ret;
  208. }
  209. return 0;
  210. }
  211. void iwl_update_chain_flags(struct iwl_priv *priv)
  212. {
  213. if (priv->cfg->ops->hcmd->set_rxon_chain)
  214. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  215. iwlcore_commit_rxon(priv);
  216. }
  217. static void iwl_clear_free_frames(struct iwl_priv *priv)
  218. {
  219. struct list_head *element;
  220. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  221. priv->frames_count);
  222. while (!list_empty(&priv->free_frames)) {
  223. element = priv->free_frames.next;
  224. list_del(element);
  225. kfree(list_entry(element, struct iwl_frame, list));
  226. priv->frames_count--;
  227. }
  228. if (priv->frames_count) {
  229. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  230. priv->frames_count);
  231. priv->frames_count = 0;
  232. }
  233. }
  234. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  235. {
  236. struct iwl_frame *frame;
  237. struct list_head *element;
  238. if (list_empty(&priv->free_frames)) {
  239. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  240. if (!frame) {
  241. IWL_ERR(priv, "Could not allocate frame!\n");
  242. return NULL;
  243. }
  244. priv->frames_count++;
  245. return frame;
  246. }
  247. element = priv->free_frames.next;
  248. list_del(element);
  249. return list_entry(element, struct iwl_frame, list);
  250. }
  251. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  252. {
  253. memset(frame, 0, sizeof(*frame));
  254. list_add(&frame->list, &priv->free_frames);
  255. }
  256. static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
  257. struct ieee80211_hdr *hdr,
  258. int left)
  259. {
  260. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  261. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  262. (priv->iw_mode != NL80211_IFTYPE_AP)))
  263. return 0;
  264. if (priv->ibss_beacon->len > left)
  265. return 0;
  266. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  267. return priv->ibss_beacon->len;
  268. }
  269. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  270. struct iwl_frame *frame, u8 rate)
  271. {
  272. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  273. unsigned int frame_size;
  274. tx_beacon_cmd = &frame->u.beacon;
  275. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  276. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  277. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  278. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  279. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  280. BUG_ON(frame_size > MAX_MPDU_SIZE);
  281. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  282. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  283. tx_beacon_cmd->tx.rate_n_flags =
  284. iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  285. else
  286. tx_beacon_cmd->tx.rate_n_flags =
  287. iwl_hw_set_rate_n_flags(rate, 0);
  288. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  289. TX_CMD_FLG_TSF_MSK |
  290. TX_CMD_FLG_STA_RATE_MSK;
  291. return sizeof(*tx_beacon_cmd) + frame_size;
  292. }
  293. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  294. {
  295. struct iwl_frame *frame;
  296. unsigned int frame_size;
  297. int rc;
  298. u8 rate;
  299. frame = iwl_get_free_frame(priv);
  300. if (!frame) {
  301. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  302. "command.\n");
  303. return -ENOMEM;
  304. }
  305. rate = iwl_rate_get_lowest_plcp(priv);
  306. frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
  307. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  308. &frame->u.cmd[0]);
  309. iwl_free_frame(priv, frame);
  310. return rc;
  311. }
  312. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  313. {
  314. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  315. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  316. if (sizeof(dma_addr_t) > sizeof(u32))
  317. addr |=
  318. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  319. return addr;
  320. }
  321. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  322. {
  323. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  324. return le16_to_cpu(tb->hi_n_len) >> 4;
  325. }
  326. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  327. dma_addr_t addr, u16 len)
  328. {
  329. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  330. u16 hi_n_len = len << 4;
  331. put_unaligned_le32(addr, &tb->lo);
  332. if (sizeof(dma_addr_t) > sizeof(u32))
  333. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  334. tb->hi_n_len = cpu_to_le16(hi_n_len);
  335. tfd->num_tbs = idx + 1;
  336. }
  337. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  338. {
  339. return tfd->num_tbs & 0x1f;
  340. }
  341. /**
  342. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  343. * @priv - driver private data
  344. * @txq - tx queue
  345. *
  346. * Does NOT advance any TFD circular buffer read/write indexes
  347. * Does NOT free the TFD itself (which is within circular buffer)
  348. */
  349. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  350. {
  351. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  352. struct iwl_tfd *tfd;
  353. struct pci_dev *dev = priv->pci_dev;
  354. int index = txq->q.read_ptr;
  355. int i;
  356. int num_tbs;
  357. tfd = &tfd_tmp[index];
  358. /* Sanity check on number of chunks */
  359. num_tbs = iwl_tfd_get_num_tbs(tfd);
  360. if (num_tbs >= IWL_NUM_OF_TBS) {
  361. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  362. /* @todo issue fatal error, it is quite serious situation */
  363. return;
  364. }
  365. /* Unmap tx_cmd */
  366. if (num_tbs)
  367. pci_unmap_single(dev,
  368. pci_unmap_addr(&txq->meta[index], mapping),
  369. pci_unmap_len(&txq->meta[index], len),
  370. PCI_DMA_BIDIRECTIONAL);
  371. /* Unmap chunks, if any. */
  372. for (i = 1; i < num_tbs; i++) {
  373. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  374. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  375. if (txq->txb) {
  376. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  377. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  378. }
  379. }
  380. }
  381. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  382. struct iwl_tx_queue *txq,
  383. dma_addr_t addr, u16 len,
  384. u8 reset, u8 pad)
  385. {
  386. struct iwl_queue *q;
  387. struct iwl_tfd *tfd, *tfd_tmp;
  388. u32 num_tbs;
  389. q = &txq->q;
  390. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  391. tfd = &tfd_tmp[q->write_ptr];
  392. if (reset)
  393. memset(tfd, 0, sizeof(*tfd));
  394. num_tbs = iwl_tfd_get_num_tbs(tfd);
  395. /* Each TFD can point to a maximum 20 Tx buffers */
  396. if (num_tbs >= IWL_NUM_OF_TBS) {
  397. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  398. IWL_NUM_OF_TBS);
  399. return -EINVAL;
  400. }
  401. BUG_ON(addr & ~DMA_BIT_MASK(36));
  402. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  403. IWL_ERR(priv, "Unaligned address = %llx\n",
  404. (unsigned long long)addr);
  405. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  406. return 0;
  407. }
  408. /*
  409. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  410. * given Tx queue, and enable the DMA channel used for that queue.
  411. *
  412. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  413. * channels supported in hardware.
  414. */
  415. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  416. struct iwl_tx_queue *txq)
  417. {
  418. int txq_id = txq->q.id;
  419. /* Circular buffer (TFD queue in DRAM) physical base address */
  420. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  421. txq->q.dma_addr >> 8);
  422. return 0;
  423. }
  424. /******************************************************************************
  425. *
  426. * Generic RX handler implementations
  427. *
  428. ******************************************************************************/
  429. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  430. struct iwl_rx_mem_buffer *rxb)
  431. {
  432. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  433. struct iwl_alive_resp *palive;
  434. struct delayed_work *pwork;
  435. palive = &pkt->u.alive_frame;
  436. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  437. "0x%01X 0x%01X\n",
  438. palive->is_valid, palive->ver_type,
  439. palive->ver_subtype);
  440. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  441. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  442. memcpy(&priv->card_alive_init,
  443. &pkt->u.alive_frame,
  444. sizeof(struct iwl_init_alive_resp));
  445. pwork = &priv->init_alive_start;
  446. } else {
  447. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  448. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  449. sizeof(struct iwl_alive_resp));
  450. pwork = &priv->alive_start;
  451. }
  452. /* We delay the ALIVE response by 5ms to
  453. * give the HW RF Kill time to activate... */
  454. if (palive->is_valid == UCODE_VALID_OK)
  455. queue_delayed_work(priv->workqueue, pwork,
  456. msecs_to_jiffies(5));
  457. else
  458. IWL_WARN(priv, "uCode did not respond OK.\n");
  459. }
  460. static void iwl_bg_beacon_update(struct work_struct *work)
  461. {
  462. struct iwl_priv *priv =
  463. container_of(work, struct iwl_priv, beacon_update);
  464. struct sk_buff *beacon;
  465. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  466. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  467. if (!beacon) {
  468. IWL_ERR(priv, "update beacon failed\n");
  469. return;
  470. }
  471. mutex_lock(&priv->mutex);
  472. /* new beacon skb is allocated every time; dispose previous.*/
  473. if (priv->ibss_beacon)
  474. dev_kfree_skb(priv->ibss_beacon);
  475. priv->ibss_beacon = beacon;
  476. mutex_unlock(&priv->mutex);
  477. iwl_send_beacon_cmd(priv);
  478. }
  479. /**
  480. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  481. *
  482. * This callback is provided in order to send a statistics request.
  483. *
  484. * This timer function is continually reset to execute within
  485. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  486. * was received. We need to ensure we receive the statistics in order
  487. * to update the temperature used for calibrating the TXPOWER.
  488. */
  489. static void iwl_bg_statistics_periodic(unsigned long data)
  490. {
  491. struct iwl_priv *priv = (struct iwl_priv *)data;
  492. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  493. return;
  494. /* dont send host command if rf-kill is on */
  495. if (!iwl_is_ready_rf(priv))
  496. return;
  497. iwl_send_statistics_request(priv, CMD_ASYNC);
  498. }
  499. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  500. struct iwl_rx_mem_buffer *rxb)
  501. {
  502. #ifdef CONFIG_IWLWIFI_DEBUG
  503. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  504. struct iwl4965_beacon_notif *beacon =
  505. (struct iwl4965_beacon_notif *)pkt->u.raw;
  506. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  507. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  508. "tsf %d %d rate %d\n",
  509. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  510. beacon->beacon_notify_hdr.failure_frame,
  511. le32_to_cpu(beacon->ibss_mgr_status),
  512. le32_to_cpu(beacon->high_tsf),
  513. le32_to_cpu(beacon->low_tsf), rate);
  514. #endif
  515. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  516. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  517. queue_work(priv->workqueue, &priv->beacon_update);
  518. }
  519. /* Handle notification from uCode that card's power state is changing
  520. * due to software, hardware, or critical temperature RFKILL */
  521. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  522. struct iwl_rx_mem_buffer *rxb)
  523. {
  524. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  525. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  526. unsigned long status = priv->status;
  527. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
  528. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  529. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  530. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  531. RF_CARD_DISABLED)) {
  532. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  533. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  534. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  535. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  536. if (!(flags & RXON_CARD_DISABLED)) {
  537. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  538. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  539. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  540. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  541. }
  542. if (flags & RF_CARD_DISABLED)
  543. iwl_tt_enter_ct_kill(priv);
  544. }
  545. if (!(flags & RF_CARD_DISABLED))
  546. iwl_tt_exit_ct_kill(priv);
  547. if (flags & HW_CARD_DISABLED)
  548. set_bit(STATUS_RF_KILL_HW, &priv->status);
  549. else
  550. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  551. if (!(flags & RXON_CARD_DISABLED))
  552. iwl_scan_cancel(priv);
  553. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  554. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  555. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  556. test_bit(STATUS_RF_KILL_HW, &priv->status));
  557. else
  558. wake_up_interruptible(&priv->wait_command_queue);
  559. }
  560. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  561. {
  562. if (src == IWL_PWR_SRC_VAUX) {
  563. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  564. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  565. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  566. ~APMG_PS_CTRL_MSK_PWR_SRC);
  567. } else {
  568. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  569. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  570. ~APMG_PS_CTRL_MSK_PWR_SRC);
  571. }
  572. return 0;
  573. }
  574. /**
  575. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  576. *
  577. * Setup the RX handlers for each of the reply types sent from the uCode
  578. * to the host.
  579. *
  580. * This function chains into the hardware specific files for them to setup
  581. * any hardware specific handlers as well.
  582. */
  583. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  584. {
  585. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  586. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  587. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  588. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  589. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  590. iwl_rx_pm_debug_statistics_notif;
  591. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  592. /*
  593. * The same handler is used for both the REPLY to a discrete
  594. * statistics request from the host as well as for the periodic
  595. * statistics notifications (after received beacons) from the uCode.
  596. */
  597. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
  598. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  599. iwl_setup_spectrum_handlers(priv);
  600. iwl_setup_rx_scan_handlers(priv);
  601. /* status change handler */
  602. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  603. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  604. iwl_rx_missed_beacon_notif;
  605. /* Rx handlers */
  606. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  607. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  608. /* block ack */
  609. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  610. /* Set up hardware specific Rx handlers */
  611. priv->cfg->ops->lib->rx_handler_setup(priv);
  612. }
  613. /**
  614. * iwl_rx_handle - Main entry function for receiving responses from uCode
  615. *
  616. * Uses the priv->rx_handlers callback function array to invoke
  617. * the appropriate handlers, including command responses,
  618. * frame-received notifications, and other notifications.
  619. */
  620. void iwl_rx_handle(struct iwl_priv *priv)
  621. {
  622. struct iwl_rx_mem_buffer *rxb;
  623. struct iwl_rx_packet *pkt;
  624. struct iwl_rx_queue *rxq = &priv->rxq;
  625. u32 r, i;
  626. int reclaim;
  627. unsigned long flags;
  628. u8 fill_rx = 0;
  629. u32 count = 8;
  630. int total_empty;
  631. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  632. * buffer that the driver may process (last buffer filled by ucode). */
  633. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  634. i = rxq->read;
  635. /* Rx interrupt, but nothing sent from uCode */
  636. if (i == r)
  637. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  638. /* calculate total frames need to be restock after handling RX */
  639. total_empty = r - priv->rxq.write_actual;
  640. if (total_empty < 0)
  641. total_empty += RX_QUEUE_SIZE;
  642. if (total_empty > (RX_QUEUE_SIZE / 2))
  643. fill_rx = 1;
  644. while (i != r) {
  645. rxb = rxq->queue[i];
  646. /* If an RXB doesn't have a Rx queue slot associated with it,
  647. * then a bug has been introduced in the queue refilling
  648. * routines -- catch it here */
  649. BUG_ON(rxb == NULL);
  650. rxq->queue[i] = NULL;
  651. pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
  652. priv->hw_params.rx_buf_size + 256,
  653. PCI_DMA_FROMDEVICE);
  654. pkt = (struct iwl_rx_packet *)rxb->skb->data;
  655. /* Reclaim a command buffer only if this packet is a response
  656. * to a (driver-originated) command.
  657. * If the packet (e.g. Rx frame) originated from uCode,
  658. * there is no command buffer to reclaim.
  659. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  660. * but apparently a few don't get set; catch them here. */
  661. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  662. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  663. (pkt->hdr.cmd != REPLY_RX) &&
  664. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  665. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  666. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  667. (pkt->hdr.cmd != REPLY_TX);
  668. /* Based on type of command response or notification,
  669. * handle those that need handling via function in
  670. * rx_handlers table. See iwl_setup_rx_handlers() */
  671. if (priv->rx_handlers[pkt->hdr.cmd]) {
  672. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  673. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  674. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  675. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  676. } else {
  677. /* No handling needed */
  678. IWL_DEBUG_RX(priv,
  679. "r %d i %d No handler needed for %s, 0x%02x\n",
  680. r, i, get_cmd_string(pkt->hdr.cmd),
  681. pkt->hdr.cmd);
  682. }
  683. if (reclaim) {
  684. /* Invoke any callbacks, transfer the skb to caller, and
  685. * fire off the (possibly) blocking iwl_send_cmd()
  686. * as we reclaim the driver command queue */
  687. if (rxb && rxb->skb)
  688. iwl_tx_cmd_complete(priv, rxb);
  689. else
  690. IWL_WARN(priv, "Claim null rxb?\n");
  691. }
  692. /* For now we just don't re-use anything. We can tweak this
  693. * later to try and re-use notification packets and SKBs that
  694. * fail to Rx correctly */
  695. if (rxb->skb != NULL) {
  696. priv->alloc_rxb_skb--;
  697. dev_kfree_skb_any(rxb->skb);
  698. rxb->skb = NULL;
  699. }
  700. spin_lock_irqsave(&rxq->lock, flags);
  701. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  702. spin_unlock_irqrestore(&rxq->lock, flags);
  703. i = (i + 1) & RX_QUEUE_MASK;
  704. /* If there are a lot of unused frames,
  705. * restock the Rx queue so ucode wont assert. */
  706. if (fill_rx) {
  707. count++;
  708. if (count >= 8) {
  709. priv->rxq.read = i;
  710. iwl_rx_replenish_now(priv);
  711. count = 0;
  712. }
  713. }
  714. }
  715. /* Backtrack one entry */
  716. priv->rxq.read = i;
  717. if (fill_rx)
  718. iwl_rx_replenish_now(priv);
  719. else
  720. iwl_rx_queue_restock(priv);
  721. }
  722. /* call this function to flush any scheduled tasklet */
  723. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  724. {
  725. /* wait to make sure we flush pending tasklet*/
  726. synchronize_irq(priv->pci_dev->irq);
  727. tasklet_kill(&priv->irq_tasklet);
  728. }
  729. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  730. {
  731. u32 inta, handled = 0;
  732. u32 inta_fh;
  733. unsigned long flags;
  734. #ifdef CONFIG_IWLWIFI_DEBUG
  735. u32 inta_mask;
  736. #endif
  737. spin_lock_irqsave(&priv->lock, flags);
  738. /* Ack/clear/reset pending uCode interrupts.
  739. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  740. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  741. inta = iwl_read32(priv, CSR_INT);
  742. iwl_write32(priv, CSR_INT, inta);
  743. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  744. * Any new interrupts that happen after this, either while we're
  745. * in this tasklet, or later, will show up in next ISR/tasklet. */
  746. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  747. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  748. #ifdef CONFIG_IWLWIFI_DEBUG
  749. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  750. /* just for debug */
  751. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  752. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  753. inta, inta_mask, inta_fh);
  754. }
  755. #endif
  756. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  757. * atomic, make sure that inta covers all the interrupts that
  758. * we've discovered, even if FH interrupt came in just after
  759. * reading CSR_INT. */
  760. if (inta_fh & CSR49_FH_INT_RX_MASK)
  761. inta |= CSR_INT_BIT_FH_RX;
  762. if (inta_fh & CSR49_FH_INT_TX_MASK)
  763. inta |= CSR_INT_BIT_FH_TX;
  764. /* Now service all interrupt bits discovered above. */
  765. if (inta & CSR_INT_BIT_HW_ERR) {
  766. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  767. /* Tell the device to stop sending interrupts */
  768. iwl_disable_interrupts(priv);
  769. priv->isr_stats.hw++;
  770. iwl_irq_handle_error(priv);
  771. handled |= CSR_INT_BIT_HW_ERR;
  772. spin_unlock_irqrestore(&priv->lock, flags);
  773. return;
  774. }
  775. #ifdef CONFIG_IWLWIFI_DEBUG
  776. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  777. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  778. if (inta & CSR_INT_BIT_SCD) {
  779. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  780. "the frame/frames.\n");
  781. priv->isr_stats.sch++;
  782. }
  783. /* Alive notification via Rx interrupt will do the real work */
  784. if (inta & CSR_INT_BIT_ALIVE) {
  785. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  786. priv->isr_stats.alive++;
  787. }
  788. }
  789. #endif
  790. /* Safely ignore these bits for debug checks below */
  791. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  792. /* HW RF KILL switch toggled */
  793. if (inta & CSR_INT_BIT_RF_KILL) {
  794. int hw_rf_kill = 0;
  795. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  796. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  797. hw_rf_kill = 1;
  798. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  799. hw_rf_kill ? "disable radio" : "enable radio");
  800. priv->isr_stats.rfkill++;
  801. /* driver only loads ucode once setting the interface up.
  802. * the driver allows loading the ucode even if the radio
  803. * is killed. Hence update the killswitch state here. The
  804. * rfkill handler will care about restarting if needed.
  805. */
  806. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  807. if (hw_rf_kill)
  808. set_bit(STATUS_RF_KILL_HW, &priv->status);
  809. else
  810. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  811. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  812. }
  813. handled |= CSR_INT_BIT_RF_KILL;
  814. }
  815. /* Chip got too hot and stopped itself */
  816. if (inta & CSR_INT_BIT_CT_KILL) {
  817. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  818. priv->isr_stats.ctkill++;
  819. handled |= CSR_INT_BIT_CT_KILL;
  820. }
  821. /* Error detected by uCode */
  822. if (inta & CSR_INT_BIT_SW_ERR) {
  823. IWL_ERR(priv, "Microcode SW error detected. "
  824. " Restarting 0x%X.\n", inta);
  825. priv->isr_stats.sw++;
  826. priv->isr_stats.sw_err = inta;
  827. iwl_irq_handle_error(priv);
  828. handled |= CSR_INT_BIT_SW_ERR;
  829. }
  830. /* uCode wakes up after power-down sleep */
  831. if (inta & CSR_INT_BIT_WAKEUP) {
  832. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  833. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  834. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  835. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  836. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  837. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  838. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  839. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  840. priv->isr_stats.wakeup++;
  841. handled |= CSR_INT_BIT_WAKEUP;
  842. }
  843. /* All uCode command responses, including Tx command responses,
  844. * Rx "responses" (frame-received notification), and other
  845. * notifications from uCode come through here*/
  846. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  847. iwl_rx_handle(priv);
  848. priv->isr_stats.rx++;
  849. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  850. }
  851. if (inta & CSR_INT_BIT_FH_TX) {
  852. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  853. priv->isr_stats.tx++;
  854. handled |= CSR_INT_BIT_FH_TX;
  855. /* FH finished to write, send event */
  856. priv->ucode_write_complete = 1;
  857. wake_up_interruptible(&priv->wait_command_queue);
  858. }
  859. if (inta & ~handled) {
  860. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  861. priv->isr_stats.unhandled++;
  862. }
  863. if (inta & ~(priv->inta_mask)) {
  864. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  865. inta & ~priv->inta_mask);
  866. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  867. }
  868. /* Re-enable all interrupts */
  869. /* only Re-enable if diabled by irq */
  870. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  871. iwl_enable_interrupts(priv);
  872. #ifdef CONFIG_IWLWIFI_DEBUG
  873. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  874. inta = iwl_read32(priv, CSR_INT);
  875. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  876. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  877. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  878. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  879. }
  880. #endif
  881. spin_unlock_irqrestore(&priv->lock, flags);
  882. }
  883. /* tasklet for iwlagn interrupt */
  884. static void iwl_irq_tasklet(struct iwl_priv *priv)
  885. {
  886. u32 inta = 0;
  887. u32 handled = 0;
  888. unsigned long flags;
  889. #ifdef CONFIG_IWLWIFI_DEBUG
  890. u32 inta_mask;
  891. #endif
  892. spin_lock_irqsave(&priv->lock, flags);
  893. /* Ack/clear/reset pending uCode interrupts.
  894. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  895. */
  896. iwl_write32(priv, CSR_INT, priv->inta);
  897. inta = priv->inta;
  898. #ifdef CONFIG_IWLWIFI_DEBUG
  899. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  900. /* just for debug */
  901. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  902. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  903. inta, inta_mask);
  904. }
  905. #endif
  906. /* saved interrupt in inta variable now we can reset priv->inta */
  907. priv->inta = 0;
  908. /* Now service all interrupt bits discovered above. */
  909. if (inta & CSR_INT_BIT_HW_ERR) {
  910. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  911. /* Tell the device to stop sending interrupts */
  912. iwl_disable_interrupts(priv);
  913. priv->isr_stats.hw++;
  914. iwl_irq_handle_error(priv);
  915. handled |= CSR_INT_BIT_HW_ERR;
  916. spin_unlock_irqrestore(&priv->lock, flags);
  917. return;
  918. }
  919. #ifdef CONFIG_IWLWIFI_DEBUG
  920. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  921. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  922. if (inta & CSR_INT_BIT_SCD) {
  923. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  924. "the frame/frames.\n");
  925. priv->isr_stats.sch++;
  926. }
  927. /* Alive notification via Rx interrupt will do the real work */
  928. if (inta & CSR_INT_BIT_ALIVE) {
  929. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  930. priv->isr_stats.alive++;
  931. }
  932. }
  933. #endif
  934. /* Safely ignore these bits for debug checks below */
  935. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  936. /* HW RF KILL switch toggled */
  937. if (inta & CSR_INT_BIT_RF_KILL) {
  938. int hw_rf_kill = 0;
  939. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  940. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  941. hw_rf_kill = 1;
  942. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  943. hw_rf_kill ? "disable radio" : "enable radio");
  944. priv->isr_stats.rfkill++;
  945. /* driver only loads ucode once setting the interface up.
  946. * the driver allows loading the ucode even if the radio
  947. * is killed. Hence update the killswitch state here. The
  948. * rfkill handler will care about restarting if needed.
  949. */
  950. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  951. if (hw_rf_kill)
  952. set_bit(STATUS_RF_KILL_HW, &priv->status);
  953. else
  954. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  955. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  956. }
  957. handled |= CSR_INT_BIT_RF_KILL;
  958. }
  959. /* Chip got too hot and stopped itself */
  960. if (inta & CSR_INT_BIT_CT_KILL) {
  961. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  962. priv->isr_stats.ctkill++;
  963. handled |= CSR_INT_BIT_CT_KILL;
  964. }
  965. /* Error detected by uCode */
  966. if (inta & CSR_INT_BIT_SW_ERR) {
  967. IWL_ERR(priv, "Microcode SW error detected. "
  968. " Restarting 0x%X.\n", inta);
  969. priv->isr_stats.sw++;
  970. priv->isr_stats.sw_err = inta;
  971. iwl_irq_handle_error(priv);
  972. handled |= CSR_INT_BIT_SW_ERR;
  973. }
  974. /* uCode wakes up after power-down sleep */
  975. if (inta & CSR_INT_BIT_WAKEUP) {
  976. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  977. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  978. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  979. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  980. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  981. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  982. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  983. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  984. priv->isr_stats.wakeup++;
  985. handled |= CSR_INT_BIT_WAKEUP;
  986. }
  987. /* All uCode command responses, including Tx command responses,
  988. * Rx "responses" (frame-received notification), and other
  989. * notifications from uCode come through here*/
  990. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  991. CSR_INT_BIT_RX_PERIODIC)) {
  992. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  993. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  994. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  995. iwl_write32(priv, CSR_FH_INT_STATUS,
  996. CSR49_FH_INT_RX_MASK);
  997. }
  998. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  999. handled |= CSR_INT_BIT_RX_PERIODIC;
  1000. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1001. }
  1002. /* Sending RX interrupt require many steps to be done in the
  1003. * the device:
  1004. * 1- write interrupt to current index in ICT table.
  1005. * 2- dma RX frame.
  1006. * 3- update RX shared data to indicate last write index.
  1007. * 4- send interrupt.
  1008. * This could lead to RX race, driver could receive RX interrupt
  1009. * but the shared data changes does not reflect this.
  1010. * this could lead to RX race, RX periodic will solve this race
  1011. */
  1012. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1013. CSR_INT_PERIODIC_DIS);
  1014. iwl_rx_handle(priv);
  1015. /* Only set RX periodic if real RX is received. */
  1016. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1017. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1018. CSR_INT_PERIODIC_ENA);
  1019. priv->isr_stats.rx++;
  1020. }
  1021. if (inta & CSR_INT_BIT_FH_TX) {
  1022. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1023. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  1024. priv->isr_stats.tx++;
  1025. handled |= CSR_INT_BIT_FH_TX;
  1026. /* FH finished to write, send event */
  1027. priv->ucode_write_complete = 1;
  1028. wake_up_interruptible(&priv->wait_command_queue);
  1029. }
  1030. if (inta & ~handled) {
  1031. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1032. priv->isr_stats.unhandled++;
  1033. }
  1034. if (inta & ~(priv->inta_mask)) {
  1035. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1036. inta & ~priv->inta_mask);
  1037. }
  1038. /* Re-enable all interrupts */
  1039. /* only Re-enable if diabled by irq */
  1040. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1041. iwl_enable_interrupts(priv);
  1042. spin_unlock_irqrestore(&priv->lock, flags);
  1043. }
  1044. /******************************************************************************
  1045. *
  1046. * uCode download functions
  1047. *
  1048. ******************************************************************************/
  1049. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1050. {
  1051. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1052. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1053. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1054. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1055. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1056. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1057. }
  1058. static void iwl_nic_start(struct iwl_priv *priv)
  1059. {
  1060. /* Remove all resets to allow NIC to operate */
  1061. iwl_write32(priv, CSR_RESET, 0);
  1062. }
  1063. /**
  1064. * iwl_read_ucode - Read uCode images from disk file.
  1065. *
  1066. * Copy into buffers for card to fetch via bus-mastering
  1067. */
  1068. static int iwl_read_ucode(struct iwl_priv *priv)
  1069. {
  1070. struct iwl_ucode_header *ucode;
  1071. int ret = -EINVAL, index;
  1072. const struct firmware *ucode_raw;
  1073. const char *name_pre = priv->cfg->fw_name_pre;
  1074. const unsigned int api_max = priv->cfg->ucode_api_max;
  1075. const unsigned int api_min = priv->cfg->ucode_api_min;
  1076. char buf[25];
  1077. u8 *src;
  1078. size_t len;
  1079. u32 api_ver, build;
  1080. u32 inst_size, data_size, init_size, init_data_size, boot_size;
  1081. u16 eeprom_ver;
  1082. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1083. * request_firmware() is synchronous, file is in memory on return. */
  1084. for (index = api_max; index >= api_min; index--) {
  1085. sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
  1086. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1087. if (ret < 0) {
  1088. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1089. buf, ret);
  1090. if (ret == -ENOENT)
  1091. continue;
  1092. else
  1093. goto error;
  1094. } else {
  1095. if (index < api_max)
  1096. IWL_ERR(priv, "Loaded firmware %s, "
  1097. "which is deprecated. "
  1098. "Please use API v%u instead.\n",
  1099. buf, api_max);
  1100. IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
  1101. buf, ucode_raw->size);
  1102. break;
  1103. }
  1104. }
  1105. if (ret < 0)
  1106. goto error;
  1107. /* Make sure that we got at least the v1 header! */
  1108. if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
  1109. IWL_ERR(priv, "File size way too small!\n");
  1110. ret = -EINVAL;
  1111. goto err_release;
  1112. }
  1113. /* Data from ucode file: header followed by uCode images */
  1114. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1115. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1116. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1117. build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
  1118. inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
  1119. data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
  1120. init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
  1121. init_data_size =
  1122. priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
  1123. boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
  1124. src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
  1125. /* api_ver should match the api version forming part of the
  1126. * firmware filename ... but we don't check for that and only rely
  1127. * on the API version read from firmware header from here on forward */
  1128. if (api_ver < api_min || api_ver > api_max) {
  1129. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1130. "Driver supports v%u, firmware is v%u.\n",
  1131. api_max, api_ver);
  1132. priv->ucode_ver = 0;
  1133. ret = -EINVAL;
  1134. goto err_release;
  1135. }
  1136. if (api_ver != api_max)
  1137. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1138. "got v%u. New firmware can be obtained "
  1139. "from http://www.intellinuxwireless.org.\n",
  1140. api_max, api_ver);
  1141. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1142. IWL_UCODE_MAJOR(priv->ucode_ver),
  1143. IWL_UCODE_MINOR(priv->ucode_ver),
  1144. IWL_UCODE_API(priv->ucode_ver),
  1145. IWL_UCODE_SERIAL(priv->ucode_ver));
  1146. if (build)
  1147. IWL_DEBUG_INFO(priv, "Build %u\n", build);
  1148. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1149. IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
  1150. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  1151. ? "OTP" : "EEPROM", eeprom_ver);
  1152. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1153. priv->ucode_ver);
  1154. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1155. inst_size);
  1156. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1157. data_size);
  1158. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1159. init_size);
  1160. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1161. init_data_size);
  1162. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1163. boot_size);
  1164. /* Verify size of file vs. image size info in file's header */
  1165. if (ucode_raw->size !=
  1166. priv->cfg->ops->ucode->get_header_size(api_ver) +
  1167. inst_size + data_size + init_size +
  1168. init_data_size + boot_size) {
  1169. IWL_DEBUG_INFO(priv,
  1170. "uCode file size %d does not match expected size\n",
  1171. (int)ucode_raw->size);
  1172. ret = -EINVAL;
  1173. goto err_release;
  1174. }
  1175. /* Verify that uCode images will fit in card's SRAM */
  1176. if (inst_size > priv->hw_params.max_inst_size) {
  1177. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1178. inst_size);
  1179. ret = -EINVAL;
  1180. goto err_release;
  1181. }
  1182. if (data_size > priv->hw_params.max_data_size) {
  1183. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1184. data_size);
  1185. ret = -EINVAL;
  1186. goto err_release;
  1187. }
  1188. if (init_size > priv->hw_params.max_inst_size) {
  1189. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1190. init_size);
  1191. ret = -EINVAL;
  1192. goto err_release;
  1193. }
  1194. if (init_data_size > priv->hw_params.max_data_size) {
  1195. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1196. init_data_size);
  1197. ret = -EINVAL;
  1198. goto err_release;
  1199. }
  1200. if (boot_size > priv->hw_params.max_bsm_size) {
  1201. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1202. boot_size);
  1203. ret = -EINVAL;
  1204. goto err_release;
  1205. }
  1206. /* Allocate ucode buffers for card's bus-master loading ... */
  1207. /* Runtime instructions and 2 copies of data:
  1208. * 1) unmodified from disk
  1209. * 2) backup cache for save/restore during power-downs */
  1210. priv->ucode_code.len = inst_size;
  1211. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1212. priv->ucode_data.len = data_size;
  1213. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1214. priv->ucode_data_backup.len = data_size;
  1215. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1216. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1217. !priv->ucode_data_backup.v_addr)
  1218. goto err_pci_alloc;
  1219. /* Initialization instructions and data */
  1220. if (init_size && init_data_size) {
  1221. priv->ucode_init.len = init_size;
  1222. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1223. priv->ucode_init_data.len = init_data_size;
  1224. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1225. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1226. goto err_pci_alloc;
  1227. }
  1228. /* Bootstrap (instructions only, no data) */
  1229. if (boot_size) {
  1230. priv->ucode_boot.len = boot_size;
  1231. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1232. if (!priv->ucode_boot.v_addr)
  1233. goto err_pci_alloc;
  1234. }
  1235. /* Copy images into buffers for card's bus-master reads ... */
  1236. /* Runtime instructions (first block of data in file) */
  1237. len = inst_size;
  1238. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1239. memcpy(priv->ucode_code.v_addr, src, len);
  1240. src += len;
  1241. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1242. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1243. /* Runtime data (2nd block)
  1244. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1245. len = data_size;
  1246. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1247. memcpy(priv->ucode_data.v_addr, src, len);
  1248. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1249. src += len;
  1250. /* Initialization instructions (3rd block) */
  1251. if (init_size) {
  1252. len = init_size;
  1253. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1254. len);
  1255. memcpy(priv->ucode_init.v_addr, src, len);
  1256. src += len;
  1257. }
  1258. /* Initialization data (4th block) */
  1259. if (init_data_size) {
  1260. len = init_data_size;
  1261. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1262. len);
  1263. memcpy(priv->ucode_init_data.v_addr, src, len);
  1264. src += len;
  1265. }
  1266. /* Bootstrap instructions (5th block) */
  1267. len = boot_size;
  1268. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1269. memcpy(priv->ucode_boot.v_addr, src, len);
  1270. /* We have our copies now, allow OS release its copies */
  1271. release_firmware(ucode_raw);
  1272. return 0;
  1273. err_pci_alloc:
  1274. IWL_ERR(priv, "failed to allocate pci memory\n");
  1275. ret = -ENOMEM;
  1276. iwl_dealloc_ucode_pci(priv);
  1277. err_release:
  1278. release_firmware(ucode_raw);
  1279. error:
  1280. return ret;
  1281. }
  1282. #ifdef CONFIG_IWLWIFI_DEBUG
  1283. static const char *desc_lookup_text[] = {
  1284. "OK",
  1285. "FAIL",
  1286. "BAD_PARAM",
  1287. "BAD_CHECKSUM",
  1288. "NMI_INTERRUPT_WDG",
  1289. "SYSASSERT",
  1290. "FATAL_ERROR",
  1291. "BAD_COMMAND",
  1292. "HW_ERROR_TUNE_LOCK",
  1293. "HW_ERROR_TEMPERATURE",
  1294. "ILLEGAL_CHAN_FREQ",
  1295. "VCC_NOT_STABLE",
  1296. "FH_ERROR",
  1297. "NMI_INTERRUPT_HOST",
  1298. "NMI_INTERRUPT_ACTION_PT",
  1299. "NMI_INTERRUPT_UNKNOWN",
  1300. "UCODE_VERSION_MISMATCH",
  1301. "HW_ERROR_ABS_LOCK",
  1302. "HW_ERROR_CAL_LOCK_FAIL",
  1303. "NMI_INTERRUPT_INST_ACTION_PT",
  1304. "NMI_INTERRUPT_DATA_ACTION_PT",
  1305. "NMI_TRM_HW_ER",
  1306. "NMI_INTERRUPT_TRM",
  1307. "NMI_INTERRUPT_BREAK_POINT"
  1308. "DEBUG_0",
  1309. "DEBUG_1",
  1310. "DEBUG_2",
  1311. "DEBUG_3",
  1312. "UNKNOWN"
  1313. };
  1314. static const char *desc_lookup(int i)
  1315. {
  1316. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1317. if (i < 0 || i > max)
  1318. i = max;
  1319. return desc_lookup_text[i];
  1320. }
  1321. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1322. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1323. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1324. {
  1325. u32 data2, line;
  1326. u32 desc, time, count, base, data1;
  1327. u32 blink1, blink2, ilink1, ilink2;
  1328. if (priv->ucode_type == UCODE_INIT)
  1329. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1330. else
  1331. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1332. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1333. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  1334. return;
  1335. }
  1336. count = iwl_read_targ_mem(priv, base);
  1337. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1338. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1339. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1340. priv->status, count);
  1341. }
  1342. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1343. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1344. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1345. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1346. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1347. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1348. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1349. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1350. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1351. IWL_ERR(priv, "Desc Time "
  1352. "data1 data2 line\n");
  1353. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1354. desc_lookup(desc), desc, time, data1, data2, line);
  1355. IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
  1356. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
  1357. ilink1, ilink2);
  1358. }
  1359. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1360. /**
  1361. * iwl_print_event_log - Dump error event log to syslog
  1362. *
  1363. */
  1364. static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1365. u32 num_events, u32 mode)
  1366. {
  1367. u32 i;
  1368. u32 base; /* SRAM byte address of event log header */
  1369. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1370. u32 ptr; /* SRAM byte address of log data */
  1371. u32 ev, time, data; /* event log data */
  1372. if (num_events == 0)
  1373. return;
  1374. if (priv->ucode_type == UCODE_INIT)
  1375. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1376. else
  1377. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1378. if (mode == 0)
  1379. event_size = 2 * sizeof(u32);
  1380. else
  1381. event_size = 3 * sizeof(u32);
  1382. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1383. /* "time" is actually "data" for mode 0 (no timestamp).
  1384. * place event id # at far right for easier visual parsing. */
  1385. for (i = 0; i < num_events; i++) {
  1386. ev = iwl_read_targ_mem(priv, ptr);
  1387. ptr += sizeof(u32);
  1388. time = iwl_read_targ_mem(priv, ptr);
  1389. ptr += sizeof(u32);
  1390. if (mode == 0) {
  1391. /* data, ev */
  1392. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
  1393. } else {
  1394. data = iwl_read_targ_mem(priv, ptr);
  1395. ptr += sizeof(u32);
  1396. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1397. time, data, ev);
  1398. }
  1399. }
  1400. }
  1401. void iwl_dump_nic_event_log(struct iwl_priv *priv)
  1402. {
  1403. u32 base; /* SRAM byte address of event log header */
  1404. u32 capacity; /* event log capacity in # entries */
  1405. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1406. u32 num_wraps; /* # times uCode wrapped to top of log */
  1407. u32 next_entry; /* index of next entry to be written by uCode */
  1408. u32 size; /* # entries that we'll print */
  1409. if (priv->ucode_type == UCODE_INIT)
  1410. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1411. else
  1412. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1413. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1414. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  1415. return;
  1416. }
  1417. /* event log header */
  1418. capacity = iwl_read_targ_mem(priv, base);
  1419. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1420. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1421. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1422. size = num_wraps ? capacity : next_entry;
  1423. /* bail out if nothing in log */
  1424. if (size == 0) {
  1425. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1426. return;
  1427. }
  1428. IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
  1429. size, num_wraps);
  1430. /* if uCode has wrapped back to top of log, start at the oldest entry,
  1431. * i.e the next one that uCode would fill. */
  1432. if (num_wraps)
  1433. iwl_print_event_log(priv, next_entry,
  1434. capacity - next_entry, mode);
  1435. /* (then/else) start at top of log */
  1436. iwl_print_event_log(priv, 0, next_entry, mode);
  1437. }
  1438. #endif
  1439. /**
  1440. * iwl_alive_start - called after REPLY_ALIVE notification received
  1441. * from protocol/runtime uCode (initialization uCode's
  1442. * Alive gets handled by iwl_init_alive_start()).
  1443. */
  1444. static void iwl_alive_start(struct iwl_priv *priv)
  1445. {
  1446. int ret = 0;
  1447. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1448. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1449. /* We had an error bringing up the hardware, so take it
  1450. * all the way back down so we can try again */
  1451. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1452. goto restart;
  1453. }
  1454. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1455. * This is a paranoid check, because we would not have gotten the
  1456. * "runtime" alive if code weren't properly loaded. */
  1457. if (iwl_verify_ucode(priv)) {
  1458. /* Runtime instruction load was bad;
  1459. * take it all the way back down so we can try again */
  1460. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1461. goto restart;
  1462. }
  1463. iwl_clear_stations_table(priv);
  1464. ret = priv->cfg->ops->lib->alive_notify(priv);
  1465. if (ret) {
  1466. IWL_WARN(priv,
  1467. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1468. goto restart;
  1469. }
  1470. /* After the ALIVE response, we can send host commands to the uCode */
  1471. set_bit(STATUS_ALIVE, &priv->status);
  1472. if (iwl_is_rfkill(priv))
  1473. return;
  1474. ieee80211_wake_queues(priv->hw);
  1475. priv->active_rate = priv->rates_mask;
  1476. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1477. if (iwl_is_associated(priv)) {
  1478. struct iwl_rxon_cmd *active_rxon =
  1479. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1480. /* apply any changes in staging */
  1481. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1482. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1483. } else {
  1484. /* Initialize our rx_config data */
  1485. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1486. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1487. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1488. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1489. }
  1490. /* Configure Bluetooth device coexistence support */
  1491. iwl_send_bt_config(priv);
  1492. iwl_reset_run_time_calib(priv);
  1493. /* Configure the adapter for unassociated operation */
  1494. iwlcore_commit_rxon(priv);
  1495. /* At this point, the NIC is initialized and operational */
  1496. iwl_rf_kill_ct_config(priv);
  1497. iwl_leds_register(priv);
  1498. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1499. set_bit(STATUS_READY, &priv->status);
  1500. wake_up_interruptible(&priv->wait_command_queue);
  1501. iwl_power_update_mode(priv, true);
  1502. /* reassociate for ADHOC mode */
  1503. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  1504. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  1505. priv->vif);
  1506. if (beacon)
  1507. iwl_mac_beacon_update(priv->hw, beacon);
  1508. }
  1509. if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
  1510. iwl_set_mode(priv, priv->iw_mode);
  1511. return;
  1512. restart:
  1513. queue_work(priv->workqueue, &priv->restart);
  1514. }
  1515. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1516. static void __iwl_down(struct iwl_priv *priv)
  1517. {
  1518. unsigned long flags;
  1519. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1520. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1521. if (!exit_pending)
  1522. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1523. iwl_leds_unregister(priv);
  1524. iwl_clear_stations_table(priv);
  1525. /* Unblock any waiting calls */
  1526. wake_up_interruptible_all(&priv->wait_command_queue);
  1527. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1528. * exiting the module */
  1529. if (!exit_pending)
  1530. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1531. /* stop and reset the on-board processor */
  1532. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1533. /* tell the device to stop sending interrupts */
  1534. spin_lock_irqsave(&priv->lock, flags);
  1535. iwl_disable_interrupts(priv);
  1536. spin_unlock_irqrestore(&priv->lock, flags);
  1537. iwl_synchronize_irq(priv);
  1538. if (priv->mac80211_registered)
  1539. ieee80211_stop_queues(priv->hw);
  1540. /* If we have not previously called iwl_init() then
  1541. * clear all bits but the RF Kill bit and return */
  1542. if (!iwl_is_init(priv)) {
  1543. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1544. STATUS_RF_KILL_HW |
  1545. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1546. STATUS_GEO_CONFIGURED |
  1547. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1548. STATUS_EXIT_PENDING;
  1549. goto exit;
  1550. }
  1551. /* ...otherwise clear out all the status bits but the RF Kill
  1552. * bit and continue taking the NIC down. */
  1553. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1554. STATUS_RF_KILL_HW |
  1555. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1556. STATUS_GEO_CONFIGURED |
  1557. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1558. STATUS_FW_ERROR |
  1559. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1560. STATUS_EXIT_PENDING;
  1561. /* device going down, Stop using ICT table */
  1562. iwl_disable_ict(priv);
  1563. spin_lock_irqsave(&priv->lock, flags);
  1564. iwl_clear_bit(priv, CSR_GP_CNTRL,
  1565. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1566. spin_unlock_irqrestore(&priv->lock, flags);
  1567. iwl_txq_ctx_stop(priv);
  1568. iwl_rxq_stop(priv);
  1569. iwl_write_prph(priv, APMG_CLK_DIS_REG,
  1570. APMG_CLK_VAL_DMA_CLK_RQT);
  1571. udelay(5);
  1572. /* FIXME: apm_ops.suspend(priv) */
  1573. if (exit_pending)
  1574. priv->cfg->ops->lib->apm_ops.stop(priv);
  1575. else
  1576. priv->cfg->ops->lib->apm_ops.reset(priv);
  1577. exit:
  1578. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1579. if (priv->ibss_beacon)
  1580. dev_kfree_skb(priv->ibss_beacon);
  1581. priv->ibss_beacon = NULL;
  1582. /* clear out any free frames */
  1583. iwl_clear_free_frames(priv);
  1584. }
  1585. static void iwl_down(struct iwl_priv *priv)
  1586. {
  1587. mutex_lock(&priv->mutex);
  1588. __iwl_down(priv);
  1589. mutex_unlock(&priv->mutex);
  1590. iwl_cancel_deferred_work(priv);
  1591. }
  1592. #define HW_READY_TIMEOUT (50)
  1593. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1594. {
  1595. int ret = 0;
  1596. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1597. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1598. /* See if we got it */
  1599. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1600. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1601. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1602. HW_READY_TIMEOUT);
  1603. if (ret != -ETIMEDOUT)
  1604. priv->hw_ready = true;
  1605. else
  1606. priv->hw_ready = false;
  1607. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1608. (priv->hw_ready == 1) ? "ready" : "not ready");
  1609. return ret;
  1610. }
  1611. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  1612. {
  1613. int ret = 0;
  1614. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
  1615. ret = iwl_set_hw_ready(priv);
  1616. if (priv->hw_ready)
  1617. return ret;
  1618. /* If HW is not ready, prepare the conditions to check again */
  1619. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1620. CSR_HW_IF_CONFIG_REG_PREPARE);
  1621. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1622. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1623. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1624. /* HW should be ready by now, check again. */
  1625. if (ret != -ETIMEDOUT)
  1626. iwl_set_hw_ready(priv);
  1627. return ret;
  1628. }
  1629. #define MAX_HW_RESTARTS 5
  1630. static int __iwl_up(struct iwl_priv *priv)
  1631. {
  1632. int i;
  1633. int ret;
  1634. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1635. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1636. return -EIO;
  1637. }
  1638. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1639. IWL_ERR(priv, "ucode not available for device bringup\n");
  1640. return -EIO;
  1641. }
  1642. iwl_prepare_card_hw(priv);
  1643. if (!priv->hw_ready) {
  1644. IWL_WARN(priv, "Exit HW not ready\n");
  1645. return -EIO;
  1646. }
  1647. /* If platform's RF_KILL switch is NOT set to KILL */
  1648. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1649. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1650. else
  1651. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1652. if (iwl_is_rfkill(priv)) {
  1653. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  1654. iwl_enable_interrupts(priv);
  1655. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  1656. return 0;
  1657. }
  1658. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1659. ret = iwl_hw_nic_init(priv);
  1660. if (ret) {
  1661. IWL_ERR(priv, "Unable to init nic\n");
  1662. return ret;
  1663. }
  1664. /* make sure rfkill handshake bits are cleared */
  1665. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1666. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1667. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1668. /* clear (again), then enable host interrupts */
  1669. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1670. iwl_enable_interrupts(priv);
  1671. /* really make sure rfkill handshake bits are cleared */
  1672. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1673. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1674. /* Copy original ucode data image from disk into backup cache.
  1675. * This will be used to initialize the on-board processor's
  1676. * data SRAM for a clean start when the runtime program first loads. */
  1677. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1678. priv->ucode_data.len);
  1679. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1680. iwl_clear_stations_table(priv);
  1681. /* load bootstrap state machine,
  1682. * load bootstrap program into processor's memory,
  1683. * prepare to load the "initialize" uCode */
  1684. ret = priv->cfg->ops->lib->load_ucode(priv);
  1685. if (ret) {
  1686. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1687. ret);
  1688. continue;
  1689. }
  1690. /* start card; "initialize" will load runtime ucode */
  1691. iwl_nic_start(priv);
  1692. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1693. return 0;
  1694. }
  1695. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1696. __iwl_down(priv);
  1697. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1698. /* tried to restart and config the device for as long as our
  1699. * patience could withstand */
  1700. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1701. return -EIO;
  1702. }
  1703. /*****************************************************************************
  1704. *
  1705. * Workqueue callbacks
  1706. *
  1707. *****************************************************************************/
  1708. static void iwl_bg_init_alive_start(struct work_struct *data)
  1709. {
  1710. struct iwl_priv *priv =
  1711. container_of(data, struct iwl_priv, init_alive_start.work);
  1712. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1713. return;
  1714. mutex_lock(&priv->mutex);
  1715. priv->cfg->ops->lib->init_alive_start(priv);
  1716. mutex_unlock(&priv->mutex);
  1717. }
  1718. static void iwl_bg_alive_start(struct work_struct *data)
  1719. {
  1720. struct iwl_priv *priv =
  1721. container_of(data, struct iwl_priv, alive_start.work);
  1722. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1723. return;
  1724. /* enable dram interrupt */
  1725. iwl_reset_ict(priv);
  1726. mutex_lock(&priv->mutex);
  1727. iwl_alive_start(priv);
  1728. mutex_unlock(&priv->mutex);
  1729. }
  1730. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  1731. {
  1732. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1733. run_time_calib_work);
  1734. mutex_lock(&priv->mutex);
  1735. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1736. test_bit(STATUS_SCANNING, &priv->status)) {
  1737. mutex_unlock(&priv->mutex);
  1738. return;
  1739. }
  1740. if (priv->start_calib) {
  1741. iwl_chain_noise_calibration(priv, &priv->statistics);
  1742. iwl_sensitivity_calibration(priv, &priv->statistics);
  1743. }
  1744. mutex_unlock(&priv->mutex);
  1745. return;
  1746. }
  1747. static void iwl_bg_up(struct work_struct *data)
  1748. {
  1749. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  1750. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1751. return;
  1752. mutex_lock(&priv->mutex);
  1753. __iwl_up(priv);
  1754. mutex_unlock(&priv->mutex);
  1755. }
  1756. static void iwl_bg_restart(struct work_struct *data)
  1757. {
  1758. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  1759. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1760. return;
  1761. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  1762. mutex_lock(&priv->mutex);
  1763. priv->vif = NULL;
  1764. priv->is_open = 0;
  1765. mutex_unlock(&priv->mutex);
  1766. iwl_down(priv);
  1767. ieee80211_restart_hw(priv->hw);
  1768. } else {
  1769. iwl_down(priv);
  1770. queue_work(priv->workqueue, &priv->up);
  1771. }
  1772. }
  1773. static void iwl_bg_rx_replenish(struct work_struct *data)
  1774. {
  1775. struct iwl_priv *priv =
  1776. container_of(data, struct iwl_priv, rx_replenish);
  1777. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1778. return;
  1779. mutex_lock(&priv->mutex);
  1780. iwl_rx_replenish(priv);
  1781. mutex_unlock(&priv->mutex);
  1782. }
  1783. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  1784. void iwl_post_associate(struct iwl_priv *priv)
  1785. {
  1786. struct ieee80211_conf *conf = NULL;
  1787. int ret = 0;
  1788. unsigned long flags;
  1789. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  1790. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  1791. return;
  1792. }
  1793. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  1794. priv->assoc_id, priv->active_rxon.bssid_addr);
  1795. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1796. return;
  1797. if (!priv->vif || !priv->is_open)
  1798. return;
  1799. iwl_scan_cancel_timeout(priv, 200);
  1800. conf = ieee80211_get_hw_conf(priv->hw);
  1801. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1802. iwlcore_commit_rxon(priv);
  1803. iwl_setup_rxon_timing(priv);
  1804. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1805. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1806. if (ret)
  1807. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1808. "Attempting to continue.\n");
  1809. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1810. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  1811. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1812. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1813. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1814. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  1815. priv->assoc_id, priv->beacon_int);
  1816. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1817. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1818. else
  1819. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1820. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1821. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1822. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1823. else
  1824. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1825. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1826. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1827. }
  1828. iwlcore_commit_rxon(priv);
  1829. switch (priv->iw_mode) {
  1830. case NL80211_IFTYPE_STATION:
  1831. break;
  1832. case NL80211_IFTYPE_ADHOC:
  1833. /* assume default assoc id */
  1834. priv->assoc_id = 1;
  1835. iwl_rxon_add_station(priv, priv->bssid, 0);
  1836. iwl_send_beacon_cmd(priv);
  1837. break;
  1838. default:
  1839. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  1840. __func__, priv->iw_mode);
  1841. break;
  1842. }
  1843. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1844. priv->assoc_station_added = 1;
  1845. spin_lock_irqsave(&priv->lock, flags);
  1846. iwl_activate_qos(priv, 0);
  1847. spin_unlock_irqrestore(&priv->lock, flags);
  1848. /* the chain noise calibration will enabled PM upon completion
  1849. * If chain noise has already been run, then we need to enable
  1850. * power management here */
  1851. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  1852. iwl_power_update_mode(priv, false);
  1853. /* Enable Rx differential gain and sensitivity calibrations */
  1854. iwl_chain_noise_reset(priv);
  1855. priv->start_calib = 1;
  1856. }
  1857. /*****************************************************************************
  1858. *
  1859. * mac80211 entry point functions
  1860. *
  1861. *****************************************************************************/
  1862. #define UCODE_READY_TIMEOUT (4 * HZ)
  1863. static int iwl_mac_start(struct ieee80211_hw *hw)
  1864. {
  1865. struct iwl_priv *priv = hw->priv;
  1866. int ret;
  1867. IWL_DEBUG_MAC80211(priv, "enter\n");
  1868. /* we should be verifying the device is ready to be opened */
  1869. mutex_lock(&priv->mutex);
  1870. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  1871. * ucode filename and max sizes are card-specific. */
  1872. if (!priv->ucode_code.len) {
  1873. ret = iwl_read_ucode(priv);
  1874. if (ret) {
  1875. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  1876. mutex_unlock(&priv->mutex);
  1877. return ret;
  1878. }
  1879. }
  1880. ret = __iwl_up(priv);
  1881. mutex_unlock(&priv->mutex);
  1882. if (ret)
  1883. return ret;
  1884. if (iwl_is_rfkill(priv))
  1885. goto out;
  1886. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  1887. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  1888. * mac80211 will not be run successfully. */
  1889. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  1890. test_bit(STATUS_READY, &priv->status),
  1891. UCODE_READY_TIMEOUT);
  1892. if (!ret) {
  1893. if (!test_bit(STATUS_READY, &priv->status)) {
  1894. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  1895. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  1896. return -ETIMEDOUT;
  1897. }
  1898. }
  1899. out:
  1900. priv->is_open = 1;
  1901. IWL_DEBUG_MAC80211(priv, "leave\n");
  1902. return 0;
  1903. }
  1904. static void iwl_mac_stop(struct ieee80211_hw *hw)
  1905. {
  1906. struct iwl_priv *priv = hw->priv;
  1907. IWL_DEBUG_MAC80211(priv, "enter\n");
  1908. if (!priv->is_open)
  1909. return;
  1910. priv->is_open = 0;
  1911. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  1912. /* stop mac, cancel any scan request and clear
  1913. * RXON_FILTER_ASSOC_MSK BIT
  1914. */
  1915. mutex_lock(&priv->mutex);
  1916. iwl_scan_cancel_timeout(priv, 100);
  1917. mutex_unlock(&priv->mutex);
  1918. }
  1919. iwl_down(priv);
  1920. flush_workqueue(priv->workqueue);
  1921. /* enable interrupts again in order to receive rfkill changes */
  1922. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1923. iwl_enable_interrupts(priv);
  1924. IWL_DEBUG_MAC80211(priv, "leave\n");
  1925. }
  1926. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  1927. {
  1928. struct iwl_priv *priv = hw->priv;
  1929. IWL_DEBUG_MACDUMP(priv, "enter\n");
  1930. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  1931. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  1932. if (iwl_tx_skb(priv, skb))
  1933. dev_kfree_skb_any(skb);
  1934. IWL_DEBUG_MACDUMP(priv, "leave\n");
  1935. return NETDEV_TX_OK;
  1936. }
  1937. void iwl_config_ap(struct iwl_priv *priv)
  1938. {
  1939. int ret = 0;
  1940. unsigned long flags;
  1941. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1942. return;
  1943. /* The following should be done only at AP bring up */
  1944. if (!iwl_is_associated(priv)) {
  1945. /* RXON - unassoc (to set timing command) */
  1946. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1947. iwlcore_commit_rxon(priv);
  1948. /* RXON Timing */
  1949. iwl_setup_rxon_timing(priv);
  1950. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1951. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1952. if (ret)
  1953. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1954. "Attempting to continue.\n");
  1955. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1956. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1957. /* FIXME: what should be the assoc_id for AP? */
  1958. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1959. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1960. priv->staging_rxon.flags |=
  1961. RXON_FLG_SHORT_PREAMBLE_MSK;
  1962. else
  1963. priv->staging_rxon.flags &=
  1964. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1965. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1966. if (priv->assoc_capability &
  1967. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1968. priv->staging_rxon.flags |=
  1969. RXON_FLG_SHORT_SLOT_MSK;
  1970. else
  1971. priv->staging_rxon.flags &=
  1972. ~RXON_FLG_SHORT_SLOT_MSK;
  1973. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1974. priv->staging_rxon.flags &=
  1975. ~RXON_FLG_SHORT_SLOT_MSK;
  1976. }
  1977. /* restore RXON assoc */
  1978. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1979. iwlcore_commit_rxon(priv);
  1980. spin_lock_irqsave(&priv->lock, flags);
  1981. iwl_activate_qos(priv, 1);
  1982. spin_unlock_irqrestore(&priv->lock, flags);
  1983. iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
  1984. }
  1985. iwl_send_beacon_cmd(priv);
  1986. /* FIXME - we need to add code here to detect a totally new
  1987. * configuration, reset the AP, unassoc, rxon timing, assoc,
  1988. * clear sta table, add BCAST sta... */
  1989. }
  1990. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  1991. struct ieee80211_key_conf *keyconf, const u8 *addr,
  1992. u32 iv32, u16 *phase1key)
  1993. {
  1994. struct iwl_priv *priv = hw->priv;
  1995. IWL_DEBUG_MAC80211(priv, "enter\n");
  1996. iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
  1997. IWL_DEBUG_MAC80211(priv, "leave\n");
  1998. }
  1999. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2000. struct ieee80211_vif *vif,
  2001. struct ieee80211_sta *sta,
  2002. struct ieee80211_key_conf *key)
  2003. {
  2004. struct iwl_priv *priv = hw->priv;
  2005. const u8 *addr;
  2006. int ret;
  2007. u8 sta_id;
  2008. bool is_default_wep_key = false;
  2009. IWL_DEBUG_MAC80211(priv, "enter\n");
  2010. if (priv->cfg->mod_params->sw_crypto) {
  2011. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2012. return -EOPNOTSUPP;
  2013. }
  2014. addr = sta ? sta->addr : iwl_bcast_addr;
  2015. sta_id = iwl_find_station(priv, addr);
  2016. if (sta_id == IWL_INVALID_STATION) {
  2017. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  2018. addr);
  2019. return -EINVAL;
  2020. }
  2021. mutex_lock(&priv->mutex);
  2022. iwl_scan_cancel_timeout(priv, 100);
  2023. mutex_unlock(&priv->mutex);
  2024. /* If we are getting WEP group key and we didn't receive any key mapping
  2025. * so far, we are in legacy wep mode (group key only), otherwise we are
  2026. * in 1X mode.
  2027. * In legacy wep mode, we use another host command to the uCode */
  2028. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  2029. priv->iw_mode != NL80211_IFTYPE_AP) {
  2030. if (cmd == SET_KEY)
  2031. is_default_wep_key = !priv->key_mapping_key;
  2032. else
  2033. is_default_wep_key =
  2034. (key->hw_key_idx == HW_KEY_DEFAULT);
  2035. }
  2036. switch (cmd) {
  2037. case SET_KEY:
  2038. if (is_default_wep_key)
  2039. ret = iwl_set_default_wep_key(priv, key);
  2040. else
  2041. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2042. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2043. break;
  2044. case DISABLE_KEY:
  2045. if (is_default_wep_key)
  2046. ret = iwl_remove_default_wep_key(priv, key);
  2047. else
  2048. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2049. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2050. break;
  2051. default:
  2052. ret = -EINVAL;
  2053. }
  2054. IWL_DEBUG_MAC80211(priv, "leave\n");
  2055. return ret;
  2056. }
  2057. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2058. enum ieee80211_ampdu_mlme_action action,
  2059. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2060. {
  2061. struct iwl_priv *priv = hw->priv;
  2062. int ret;
  2063. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2064. sta->addr, tid);
  2065. if (!(priv->cfg->sku & IWL_SKU_N))
  2066. return -EACCES;
  2067. switch (action) {
  2068. case IEEE80211_AMPDU_RX_START:
  2069. IWL_DEBUG_HT(priv, "start Rx\n");
  2070. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  2071. case IEEE80211_AMPDU_RX_STOP:
  2072. IWL_DEBUG_HT(priv, "stop Rx\n");
  2073. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  2074. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2075. return 0;
  2076. else
  2077. return ret;
  2078. case IEEE80211_AMPDU_TX_START:
  2079. IWL_DEBUG_HT(priv, "start Tx\n");
  2080. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  2081. case IEEE80211_AMPDU_TX_STOP:
  2082. IWL_DEBUG_HT(priv, "stop Tx\n");
  2083. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  2084. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2085. return 0;
  2086. else
  2087. return ret;
  2088. default:
  2089. IWL_DEBUG_HT(priv, "unknown\n");
  2090. return -EINVAL;
  2091. break;
  2092. }
  2093. return 0;
  2094. }
  2095. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  2096. struct ieee80211_low_level_stats *stats)
  2097. {
  2098. struct iwl_priv *priv = hw->priv;
  2099. priv = hw->priv;
  2100. IWL_DEBUG_MAC80211(priv, "enter\n");
  2101. IWL_DEBUG_MAC80211(priv, "leave\n");
  2102. return 0;
  2103. }
  2104. /*****************************************************************************
  2105. *
  2106. * sysfs attributes
  2107. *
  2108. *****************************************************************************/
  2109. #ifdef CONFIG_IWLWIFI_DEBUG
  2110. /*
  2111. * The following adds a new attribute to the sysfs representation
  2112. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  2113. * used for controlling the debug level.
  2114. *
  2115. * See the level definitions in iwl for details.
  2116. *
  2117. * The debug_level being managed using sysfs below is a per device debug
  2118. * level that is used instead of the global debug level if it (the per
  2119. * device debug level) is set.
  2120. */
  2121. static ssize_t show_debug_level(struct device *d,
  2122. struct device_attribute *attr, char *buf)
  2123. {
  2124. struct iwl_priv *priv = dev_get_drvdata(d);
  2125. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2126. }
  2127. static ssize_t store_debug_level(struct device *d,
  2128. struct device_attribute *attr,
  2129. const char *buf, size_t count)
  2130. {
  2131. struct iwl_priv *priv = dev_get_drvdata(d);
  2132. unsigned long val;
  2133. int ret;
  2134. ret = strict_strtoul(buf, 0, &val);
  2135. if (ret)
  2136. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  2137. else {
  2138. priv->debug_level = val;
  2139. if (iwl_alloc_traffic_mem(priv))
  2140. IWL_ERR(priv,
  2141. "Not enough memory to generate traffic log\n");
  2142. }
  2143. return strnlen(buf, count);
  2144. }
  2145. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2146. show_debug_level, store_debug_level);
  2147. #endif /* CONFIG_IWLWIFI_DEBUG */
  2148. static ssize_t show_temperature(struct device *d,
  2149. struct device_attribute *attr, char *buf)
  2150. {
  2151. struct iwl_priv *priv = dev_get_drvdata(d);
  2152. if (!iwl_is_alive(priv))
  2153. return -EAGAIN;
  2154. return sprintf(buf, "%d\n", priv->temperature);
  2155. }
  2156. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2157. static ssize_t show_tx_power(struct device *d,
  2158. struct device_attribute *attr, char *buf)
  2159. {
  2160. struct iwl_priv *priv = dev_get_drvdata(d);
  2161. if (!iwl_is_ready_rf(priv))
  2162. return sprintf(buf, "off\n");
  2163. else
  2164. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2165. }
  2166. static ssize_t store_tx_power(struct device *d,
  2167. struct device_attribute *attr,
  2168. const char *buf, size_t count)
  2169. {
  2170. struct iwl_priv *priv = dev_get_drvdata(d);
  2171. unsigned long val;
  2172. int ret;
  2173. ret = strict_strtoul(buf, 10, &val);
  2174. if (ret)
  2175. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2176. else {
  2177. ret = iwl_set_tx_power(priv, val, false);
  2178. if (ret)
  2179. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  2180. ret);
  2181. else
  2182. ret = count;
  2183. }
  2184. return ret;
  2185. }
  2186. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2187. static ssize_t show_flags(struct device *d,
  2188. struct device_attribute *attr, char *buf)
  2189. {
  2190. struct iwl_priv *priv = dev_get_drvdata(d);
  2191. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  2192. }
  2193. static ssize_t store_flags(struct device *d,
  2194. struct device_attribute *attr,
  2195. const char *buf, size_t count)
  2196. {
  2197. struct iwl_priv *priv = dev_get_drvdata(d);
  2198. unsigned long val;
  2199. u32 flags;
  2200. int ret = strict_strtoul(buf, 0, &val);
  2201. if (ret)
  2202. return ret;
  2203. flags = (u32)val;
  2204. mutex_lock(&priv->mutex);
  2205. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  2206. /* Cancel any currently running scans... */
  2207. if (iwl_scan_cancel_timeout(priv, 100))
  2208. IWL_WARN(priv, "Could not cancel scan.\n");
  2209. else {
  2210. IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
  2211. priv->staging_rxon.flags = cpu_to_le32(flags);
  2212. iwlcore_commit_rxon(priv);
  2213. }
  2214. }
  2215. mutex_unlock(&priv->mutex);
  2216. return count;
  2217. }
  2218. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2219. static ssize_t show_filter_flags(struct device *d,
  2220. struct device_attribute *attr, char *buf)
  2221. {
  2222. struct iwl_priv *priv = dev_get_drvdata(d);
  2223. return sprintf(buf, "0x%04X\n",
  2224. le32_to_cpu(priv->active_rxon.filter_flags));
  2225. }
  2226. static ssize_t store_filter_flags(struct device *d,
  2227. struct device_attribute *attr,
  2228. const char *buf, size_t count)
  2229. {
  2230. struct iwl_priv *priv = dev_get_drvdata(d);
  2231. unsigned long val;
  2232. u32 filter_flags;
  2233. int ret = strict_strtoul(buf, 0, &val);
  2234. if (ret)
  2235. return ret;
  2236. filter_flags = (u32)val;
  2237. mutex_lock(&priv->mutex);
  2238. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  2239. /* Cancel any currently running scans... */
  2240. if (iwl_scan_cancel_timeout(priv, 100))
  2241. IWL_WARN(priv, "Could not cancel scan.\n");
  2242. else {
  2243. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2244. "0x%04X\n", filter_flags);
  2245. priv->staging_rxon.filter_flags =
  2246. cpu_to_le32(filter_flags);
  2247. iwlcore_commit_rxon(priv);
  2248. }
  2249. }
  2250. mutex_unlock(&priv->mutex);
  2251. return count;
  2252. }
  2253. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  2254. store_filter_flags);
  2255. static ssize_t show_statistics(struct device *d,
  2256. struct device_attribute *attr, char *buf)
  2257. {
  2258. struct iwl_priv *priv = dev_get_drvdata(d);
  2259. u32 size = sizeof(struct iwl_notif_statistics);
  2260. u32 len = 0, ofs = 0;
  2261. u8 *data = (u8 *)&priv->statistics;
  2262. int rc = 0;
  2263. if (!iwl_is_alive(priv))
  2264. return -EAGAIN;
  2265. mutex_lock(&priv->mutex);
  2266. rc = iwl_send_statistics_request(priv, 0);
  2267. mutex_unlock(&priv->mutex);
  2268. if (rc) {
  2269. len = sprintf(buf,
  2270. "Error sending statistics request: 0x%08X\n", rc);
  2271. return len;
  2272. }
  2273. while (size && (PAGE_SIZE - len)) {
  2274. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2275. PAGE_SIZE - len, 1);
  2276. len = strlen(buf);
  2277. if (PAGE_SIZE - len)
  2278. buf[len++] = '\n';
  2279. ofs += 16;
  2280. size -= min(size, 16U);
  2281. }
  2282. return len;
  2283. }
  2284. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2285. static ssize_t show_rts_ht_protection(struct device *d,
  2286. struct device_attribute *attr, char *buf)
  2287. {
  2288. struct iwl_priv *priv = dev_get_drvdata(d);
  2289. return sprintf(buf, "%s\n",
  2290. priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
  2291. }
  2292. static ssize_t store_rts_ht_protection(struct device *d,
  2293. struct device_attribute *attr,
  2294. const char *buf, size_t count)
  2295. {
  2296. struct iwl_priv *priv = dev_get_drvdata(d);
  2297. unsigned long val;
  2298. int ret;
  2299. ret = strict_strtoul(buf, 10, &val);
  2300. if (ret)
  2301. IWL_INFO(priv, "Input is not in decimal form.\n");
  2302. else {
  2303. if (!iwl_is_associated(priv))
  2304. priv->cfg->use_rts_for_ht = val ? true : false;
  2305. else
  2306. IWL_ERR(priv, "Sta associated with AP - "
  2307. "Change protection mechanism is not allowed\n");
  2308. ret = count;
  2309. }
  2310. return ret;
  2311. }
  2312. static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
  2313. show_rts_ht_protection, store_rts_ht_protection);
  2314. /*****************************************************************************
  2315. *
  2316. * driver setup and teardown
  2317. *
  2318. *****************************************************************************/
  2319. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2320. {
  2321. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2322. init_waitqueue_head(&priv->wait_command_queue);
  2323. INIT_WORK(&priv->up, iwl_bg_up);
  2324. INIT_WORK(&priv->restart, iwl_bg_restart);
  2325. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2326. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2327. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2328. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2329. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2330. iwl_setup_scan_deferred_work(priv);
  2331. if (priv->cfg->ops->lib->setup_deferred_work)
  2332. priv->cfg->ops->lib->setup_deferred_work(priv);
  2333. init_timer(&priv->statistics_periodic);
  2334. priv->statistics_periodic.data = (unsigned long)priv;
  2335. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2336. if (!priv->cfg->use_isr_legacy)
  2337. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2338. iwl_irq_tasklet, (unsigned long)priv);
  2339. else
  2340. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2341. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2342. }
  2343. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2344. {
  2345. if (priv->cfg->ops->lib->cancel_deferred_work)
  2346. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2347. cancel_delayed_work_sync(&priv->init_alive_start);
  2348. cancel_delayed_work(&priv->scan_check);
  2349. cancel_delayed_work(&priv->alive_start);
  2350. cancel_work_sync(&priv->beacon_update);
  2351. del_timer_sync(&priv->statistics_periodic);
  2352. }
  2353. static struct attribute *iwl_sysfs_entries[] = {
  2354. &dev_attr_flags.attr,
  2355. &dev_attr_filter_flags.attr,
  2356. &dev_attr_statistics.attr,
  2357. &dev_attr_temperature.attr,
  2358. &dev_attr_tx_power.attr,
  2359. &dev_attr_rts_ht_protection.attr,
  2360. #ifdef CONFIG_IWLWIFI_DEBUG
  2361. &dev_attr_debug_level.attr,
  2362. #endif
  2363. NULL
  2364. };
  2365. static struct attribute_group iwl_attribute_group = {
  2366. .name = NULL, /* put in device directory */
  2367. .attrs = iwl_sysfs_entries,
  2368. };
  2369. static struct ieee80211_ops iwl_hw_ops = {
  2370. .tx = iwl_mac_tx,
  2371. .start = iwl_mac_start,
  2372. .stop = iwl_mac_stop,
  2373. .add_interface = iwl_mac_add_interface,
  2374. .remove_interface = iwl_mac_remove_interface,
  2375. .config = iwl_mac_config,
  2376. .configure_filter = iwl_configure_filter,
  2377. .set_key = iwl_mac_set_key,
  2378. .update_tkip_key = iwl_mac_update_tkip_key,
  2379. .get_stats = iwl_mac_get_stats,
  2380. .get_tx_stats = iwl_mac_get_tx_stats,
  2381. .conf_tx = iwl_mac_conf_tx,
  2382. .reset_tsf = iwl_mac_reset_tsf,
  2383. .bss_info_changed = iwl_bss_info_changed,
  2384. .ampdu_action = iwl_mac_ampdu_action,
  2385. .hw_scan = iwl_mac_hw_scan
  2386. };
  2387. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2388. {
  2389. int err = 0;
  2390. struct iwl_priv *priv;
  2391. struct ieee80211_hw *hw;
  2392. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2393. unsigned long flags;
  2394. u16 pci_cmd;
  2395. /************************
  2396. * 1. Allocating HW data
  2397. ************************/
  2398. /* Disabling hardware scan means that mac80211 will perform scans
  2399. * "the hard way", rather than using device's scan. */
  2400. if (cfg->mod_params->disable_hw_scan) {
  2401. if (iwl_debug_level & IWL_DL_INFO)
  2402. dev_printk(KERN_DEBUG, &(pdev->dev),
  2403. "Disabling hw_scan\n");
  2404. iwl_hw_ops.hw_scan = NULL;
  2405. }
  2406. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2407. if (!hw) {
  2408. err = -ENOMEM;
  2409. goto out;
  2410. }
  2411. priv = hw->priv;
  2412. /* At this point both hw and priv are allocated. */
  2413. SET_IEEE80211_DEV(hw, &pdev->dev);
  2414. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2415. priv->cfg = cfg;
  2416. priv->pci_dev = pdev;
  2417. priv->inta_mask = CSR_INI_SET_MASK;
  2418. #ifdef CONFIG_IWLWIFI_DEBUG
  2419. atomic_set(&priv->restrict_refcnt, 0);
  2420. #endif
  2421. if (iwl_alloc_traffic_mem(priv))
  2422. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  2423. /**************************
  2424. * 2. Initializing PCI bus
  2425. **************************/
  2426. if (pci_enable_device(pdev)) {
  2427. err = -ENODEV;
  2428. goto out_ieee80211_free_hw;
  2429. }
  2430. pci_set_master(pdev);
  2431. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2432. if (!err)
  2433. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2434. if (err) {
  2435. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2436. if (!err)
  2437. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2438. /* both attempts failed: */
  2439. if (err) {
  2440. IWL_WARN(priv, "No suitable DMA available.\n");
  2441. goto out_pci_disable_device;
  2442. }
  2443. }
  2444. err = pci_request_regions(pdev, DRV_NAME);
  2445. if (err)
  2446. goto out_pci_disable_device;
  2447. pci_set_drvdata(pdev, priv);
  2448. /***********************
  2449. * 3. Read REV register
  2450. ***********************/
  2451. priv->hw_base = pci_iomap(pdev, 0, 0);
  2452. if (!priv->hw_base) {
  2453. err = -ENODEV;
  2454. goto out_pci_release_regions;
  2455. }
  2456. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2457. (unsigned long long) pci_resource_len(pdev, 0));
  2458. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2459. /* this spin lock will be used in apm_ops.init and EEPROM access
  2460. * we should init now
  2461. */
  2462. spin_lock_init(&priv->reg_lock);
  2463. iwl_hw_detect(priv);
  2464. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2465. priv->cfg->name, priv->hw_rev);
  2466. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2467. * PCI Tx retries from interfering with C3 CPU state */
  2468. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2469. iwl_prepare_card_hw(priv);
  2470. if (!priv->hw_ready) {
  2471. IWL_WARN(priv, "Failed, HW not ready\n");
  2472. goto out_iounmap;
  2473. }
  2474. /* amp init */
  2475. err = priv->cfg->ops->lib->apm_ops.init(priv);
  2476. if (err < 0) {
  2477. IWL_ERR(priv, "Failed to init APMG\n");
  2478. goto out_iounmap;
  2479. }
  2480. /*****************
  2481. * 4. Read EEPROM
  2482. *****************/
  2483. /* Read the EEPROM */
  2484. err = iwl_eeprom_init(priv);
  2485. if (err) {
  2486. IWL_ERR(priv, "Unable to init EEPROM\n");
  2487. goto out_iounmap;
  2488. }
  2489. err = iwl_eeprom_check_version(priv);
  2490. if (err)
  2491. goto out_free_eeprom;
  2492. /* extract MAC Address */
  2493. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2494. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2495. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2496. /************************
  2497. * 5. Setup HW constants
  2498. ************************/
  2499. if (iwl_set_hw_params(priv)) {
  2500. IWL_ERR(priv, "failed to set hw parameters\n");
  2501. goto out_free_eeprom;
  2502. }
  2503. /*******************
  2504. * 6. Setup priv
  2505. *******************/
  2506. err = iwl_init_drv(priv);
  2507. if (err)
  2508. goto out_free_eeprom;
  2509. /* At this point both hw and priv are initialized. */
  2510. /********************
  2511. * 7. Setup services
  2512. ********************/
  2513. spin_lock_irqsave(&priv->lock, flags);
  2514. iwl_disable_interrupts(priv);
  2515. spin_unlock_irqrestore(&priv->lock, flags);
  2516. pci_enable_msi(priv->pci_dev);
  2517. iwl_alloc_isr_ict(priv);
  2518. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  2519. IRQF_SHARED, DRV_NAME, priv);
  2520. if (err) {
  2521. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2522. goto out_disable_msi;
  2523. }
  2524. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2525. if (err) {
  2526. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2527. goto out_free_irq;
  2528. }
  2529. iwl_setup_deferred_work(priv);
  2530. iwl_setup_rx_handlers(priv);
  2531. /**********************************
  2532. * 8. Setup and register mac80211
  2533. **********************************/
  2534. /* enable interrupts if needed: hw bug w/a */
  2535. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  2536. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  2537. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  2538. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  2539. }
  2540. iwl_enable_interrupts(priv);
  2541. err = iwl_setup_mac(priv);
  2542. if (err)
  2543. goto out_remove_sysfs;
  2544. err = iwl_dbgfs_register(priv, DRV_NAME);
  2545. if (err)
  2546. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  2547. /* If platform's RF_KILL switch is NOT set to KILL */
  2548. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2549. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2550. else
  2551. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2552. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  2553. test_bit(STATUS_RF_KILL_HW, &priv->status));
  2554. iwl_power_initialize(priv);
  2555. iwl_tt_initialize(priv);
  2556. return 0;
  2557. out_remove_sysfs:
  2558. destroy_workqueue(priv->workqueue);
  2559. priv->workqueue = NULL;
  2560. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2561. out_free_irq:
  2562. free_irq(priv->pci_dev->irq, priv);
  2563. iwl_free_isr_ict(priv);
  2564. out_disable_msi:
  2565. pci_disable_msi(priv->pci_dev);
  2566. iwl_uninit_drv(priv);
  2567. out_free_eeprom:
  2568. iwl_eeprom_free(priv);
  2569. out_iounmap:
  2570. pci_iounmap(pdev, priv->hw_base);
  2571. out_pci_release_regions:
  2572. pci_set_drvdata(pdev, NULL);
  2573. pci_release_regions(pdev);
  2574. out_pci_disable_device:
  2575. pci_disable_device(pdev);
  2576. out_ieee80211_free_hw:
  2577. ieee80211_free_hw(priv->hw);
  2578. iwl_free_traffic_mem(priv);
  2579. out:
  2580. return err;
  2581. }
  2582. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  2583. {
  2584. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2585. unsigned long flags;
  2586. if (!priv)
  2587. return;
  2588. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  2589. iwl_dbgfs_unregister(priv);
  2590. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2591. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  2592. * to be called and iwl_down since we are removing the device
  2593. * we need to set STATUS_EXIT_PENDING bit.
  2594. */
  2595. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2596. if (priv->mac80211_registered) {
  2597. ieee80211_unregister_hw(priv->hw);
  2598. priv->mac80211_registered = 0;
  2599. } else {
  2600. iwl_down(priv);
  2601. }
  2602. iwl_tt_exit(priv);
  2603. /* make sure we flush any pending irq or
  2604. * tasklet for the driver
  2605. */
  2606. spin_lock_irqsave(&priv->lock, flags);
  2607. iwl_disable_interrupts(priv);
  2608. spin_unlock_irqrestore(&priv->lock, flags);
  2609. iwl_synchronize_irq(priv);
  2610. iwl_dealloc_ucode_pci(priv);
  2611. if (priv->rxq.bd)
  2612. iwl_rx_queue_free(priv, &priv->rxq);
  2613. iwl_hw_txq_ctx_free(priv);
  2614. iwl_clear_stations_table(priv);
  2615. iwl_eeprom_free(priv);
  2616. /*netif_stop_queue(dev); */
  2617. flush_workqueue(priv->workqueue);
  2618. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  2619. * priv->workqueue... so we can't take down the workqueue
  2620. * until now... */
  2621. destroy_workqueue(priv->workqueue);
  2622. priv->workqueue = NULL;
  2623. iwl_free_traffic_mem(priv);
  2624. free_irq(priv->pci_dev->irq, priv);
  2625. pci_disable_msi(priv->pci_dev);
  2626. pci_iounmap(pdev, priv->hw_base);
  2627. pci_release_regions(pdev);
  2628. pci_disable_device(pdev);
  2629. pci_set_drvdata(pdev, NULL);
  2630. iwl_uninit_drv(priv);
  2631. iwl_free_isr_ict(priv);
  2632. if (priv->ibss_beacon)
  2633. dev_kfree_skb(priv->ibss_beacon);
  2634. ieee80211_free_hw(priv->hw);
  2635. }
  2636. /*****************************************************************************
  2637. *
  2638. * driver and module entry point
  2639. *
  2640. *****************************************************************************/
  2641. /* Hardware specific file defines the PCI IDs table for that hardware module */
  2642. static struct pci_device_id iwl_hw_card_ids[] = {
  2643. #ifdef CONFIG_IWL4965
  2644. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  2645. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  2646. #endif /* CONFIG_IWL4965 */
  2647. #ifdef CONFIG_IWL5000
  2648. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
  2649. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
  2650. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
  2651. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
  2652. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
  2653. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
  2654. {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
  2655. {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
  2656. {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
  2657. {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
  2658. /* 5350 WiFi/WiMax */
  2659. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
  2660. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
  2661. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
  2662. /* 5150 Wifi/WiMax */
  2663. {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
  2664. {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
  2665. /* 6000/6050 Series */
  2666. {IWL_PCI_DEVICE(0x008D, PCI_ANY_ID, iwl6000h_2agn_cfg)},
  2667. {IWL_PCI_DEVICE(0x008E, PCI_ANY_ID, iwl6000h_2agn_cfg)},
  2668. {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2669. {IWL_PCI_DEVICE(0x422C, PCI_ANY_ID, iwl6000i_2agn_cfg)},
  2670. {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2671. {IWL_PCI_DEVICE(0x4239, PCI_ANY_ID, iwl6000i_2agn_cfg)},
  2672. {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)},
  2673. {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)},
  2674. {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)},
  2675. {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)},
  2676. /* 1000 Series WiFi */
  2677. {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl1000_bgn_cfg)},
  2678. {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl1000_bgn_cfg)},
  2679. #endif /* CONFIG_IWL5000 */
  2680. {0}
  2681. };
  2682. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  2683. static struct pci_driver iwl_driver = {
  2684. .name = DRV_NAME,
  2685. .id_table = iwl_hw_card_ids,
  2686. .probe = iwl_pci_probe,
  2687. .remove = __devexit_p(iwl_pci_remove),
  2688. #ifdef CONFIG_PM
  2689. .suspend = iwl_pci_suspend,
  2690. .resume = iwl_pci_resume,
  2691. #endif
  2692. };
  2693. static int __init iwl_init(void)
  2694. {
  2695. int ret;
  2696. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  2697. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  2698. ret = iwlagn_rate_control_register();
  2699. if (ret) {
  2700. printk(KERN_ERR DRV_NAME
  2701. "Unable to register rate control algorithm: %d\n", ret);
  2702. return ret;
  2703. }
  2704. ret = pci_register_driver(&iwl_driver);
  2705. if (ret) {
  2706. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  2707. goto error_register;
  2708. }
  2709. return ret;
  2710. error_register:
  2711. iwlagn_rate_control_unregister();
  2712. return ret;
  2713. }
  2714. static void __exit iwl_exit(void)
  2715. {
  2716. pci_unregister_driver(&iwl_driver);
  2717. iwlagn_rate_control_unregister();
  2718. }
  2719. module_exit(iwl_exit);
  2720. module_init(iwl_init);
  2721. #ifdef CONFIG_IWLWIFI_DEBUG
  2722. module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
  2723. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  2724. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  2725. MODULE_PARM_DESC(debug, "debug output mask");
  2726. #endif