solos-pci.c 34 KB

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  1. /*
  2. * Driver for the Solos PCI ADSL2+ card, designed to support Linux by
  3. * Traverse Technologies -- http://www.traverse.com.au/
  4. * Xrio Limited -- http://www.xrio.com/
  5. *
  6. *
  7. * Copyright © 2008 Traverse Technologies
  8. * Copyright © 2008 Intel Corporation
  9. *
  10. * Authors: Nathan Williams <nathan@traverse.com.au>
  11. * David Woodhouse <dwmw2@infradead.org>
  12. * Treker Chen <treker@xrio.com>
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License
  16. * version 2, as published by the Free Software Foundation.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. */
  23. #define DEBUG
  24. #define VERBOSE_DEBUG
  25. #include <linux/interrupt.h>
  26. #include <linux/module.h>
  27. #include <linux/kernel.h>
  28. #include <linux/errno.h>
  29. #include <linux/ioport.h>
  30. #include <linux/types.h>
  31. #include <linux/pci.h>
  32. #include <linux/atm.h>
  33. #include <linux/atmdev.h>
  34. #include <linux/skbuff.h>
  35. #include <linux/sysfs.h>
  36. #include <linux/device.h>
  37. #include <linux/kobject.h>
  38. #include <linux/firmware.h>
  39. #include <linux/ctype.h>
  40. #include <linux/swab.h>
  41. #define VERSION "0.07"
  42. #define PTAG "solos-pci"
  43. #define CONFIG_RAM_SIZE 128
  44. #define FLAGS_ADDR 0x7C
  45. #define IRQ_EN_ADDR 0x78
  46. #define FPGA_VER 0x74
  47. #define IRQ_CLEAR 0x70
  48. #define WRITE_FLASH 0x6C
  49. #define PORTS 0x68
  50. #define FLASH_BLOCK 0x64
  51. #define FLASH_BUSY 0x60
  52. #define FPGA_MODE 0x5C
  53. #define FLASH_MODE 0x58
  54. #define TX_DMA_ADDR(port) (0x40 + (4 * (port)))
  55. #define RX_DMA_ADDR(port) (0x30 + (4 * (port)))
  56. #define DATA_RAM_SIZE 32768
  57. #define BUF_SIZE 2048
  58. #define OLD_BUF_SIZE 4096 /* For FPGA versions <= 2*/
  59. #define FPGA_PAGE 528 /* FPGA flash page size*/
  60. #define SOLOS_PAGE 512 /* Solos flash page size*/
  61. #define FPGA_BLOCK (FPGA_PAGE * 8) /* FPGA flash block size*/
  62. #define SOLOS_BLOCK (SOLOS_PAGE * 8) /* Solos flash block size*/
  63. #define RX_BUF(card, nr) ((card->buffers) + (nr)*(card->buffer_size)*2)
  64. #define TX_BUF(card, nr) ((card->buffers) + (nr)*(card->buffer_size)*2 + (card->buffer_size))
  65. #define FLASH_BUF ((card->buffers) + 4*(card->buffer_size)*2)
  66. #define RX_DMA_SIZE 2048
  67. #define FPGA_VERSION(a,b) (((a) << 8) + (b))
  68. #define LEGACY_BUFFERS 2
  69. #define DMA_SUPPORTED 4
  70. static int reset = 0;
  71. static int atmdebug = 0;
  72. static int firmware_upgrade = 0;
  73. static int fpga_upgrade = 0;
  74. static int db_firmware_upgrade = 0;
  75. static int db_fpga_upgrade = 0;
  76. struct pkt_hdr {
  77. __le16 size;
  78. __le16 vpi;
  79. __le16 vci;
  80. __le16 type;
  81. };
  82. struct solos_skb_cb {
  83. struct atm_vcc *vcc;
  84. uint32_t dma_addr;
  85. };
  86. #define SKB_CB(skb) ((struct solos_skb_cb *)skb->cb)
  87. #define PKT_DATA 0
  88. #define PKT_COMMAND 1
  89. #define PKT_POPEN 3
  90. #define PKT_PCLOSE 4
  91. #define PKT_STATUS 5
  92. struct solos_card {
  93. void __iomem *config_regs;
  94. void __iomem *buffers;
  95. int nr_ports;
  96. int tx_mask;
  97. struct pci_dev *dev;
  98. struct atm_dev *atmdev[4];
  99. struct tasklet_struct tlet;
  100. spinlock_t tx_lock;
  101. spinlock_t tx_queue_lock;
  102. spinlock_t cli_queue_lock;
  103. spinlock_t param_queue_lock;
  104. struct list_head param_queue;
  105. struct sk_buff_head tx_queue[4];
  106. struct sk_buff_head cli_queue[4];
  107. struct sk_buff *tx_skb[4];
  108. struct sk_buff *rx_skb[4];
  109. wait_queue_head_t param_wq;
  110. wait_queue_head_t fw_wq;
  111. int using_dma;
  112. int fpga_version;
  113. int buffer_size;
  114. };
  115. struct solos_param {
  116. struct list_head list;
  117. pid_t pid;
  118. int port;
  119. struct sk_buff *response;
  120. };
  121. #define SOLOS_CHAN(atmdev) ((int)(unsigned long)(atmdev)->phy_data)
  122. MODULE_AUTHOR("Traverse Technologies <support@traverse.com.au>");
  123. MODULE_DESCRIPTION("Solos PCI driver");
  124. MODULE_VERSION(VERSION);
  125. MODULE_LICENSE("GPL");
  126. MODULE_PARM_DESC(reset, "Reset Solos chips on startup");
  127. MODULE_PARM_DESC(atmdebug, "Print ATM data");
  128. MODULE_PARM_DESC(firmware_upgrade, "Initiate Solos firmware upgrade");
  129. MODULE_PARM_DESC(fpga_upgrade, "Initiate FPGA upgrade");
  130. MODULE_PARM_DESC(db_firmware_upgrade, "Initiate daughter board Solos firmware upgrade");
  131. MODULE_PARM_DESC(db_fpga_upgrade, "Initiate daughter board FPGA upgrade");
  132. module_param(reset, int, 0444);
  133. module_param(atmdebug, int, 0644);
  134. module_param(firmware_upgrade, int, 0444);
  135. module_param(fpga_upgrade, int, 0444);
  136. module_param(db_firmware_upgrade, int, 0444);
  137. module_param(db_fpga_upgrade, int, 0444);
  138. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  139. struct atm_vcc *vcc);
  140. static uint32_t fpga_tx(struct solos_card *);
  141. static irqreturn_t solos_irq(int irq, void *dev_id);
  142. static struct atm_vcc* find_vcc(struct atm_dev *dev, short vpi, int vci);
  143. static int list_vccs(int vci);
  144. static void release_vccs(struct atm_dev *dev);
  145. static int atm_init(struct solos_card *);
  146. static void atm_remove(struct solos_card *);
  147. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size);
  148. static void solos_bh(unsigned long);
  149. static int print_buffer(struct sk_buff *buf);
  150. static inline void solos_pop(struct atm_vcc *vcc, struct sk_buff *skb)
  151. {
  152. if (vcc->pop)
  153. vcc->pop(vcc, skb);
  154. else
  155. dev_kfree_skb_any(skb);
  156. }
  157. static ssize_t solos_param_show(struct device *dev, struct device_attribute *attr,
  158. char *buf)
  159. {
  160. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  161. struct solos_card *card = atmdev->dev_data;
  162. struct solos_param prm;
  163. struct sk_buff *skb;
  164. struct pkt_hdr *header;
  165. int buflen;
  166. buflen = strlen(attr->attr.name) + 10;
  167. skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
  168. if (!skb) {
  169. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_show()\n");
  170. return -ENOMEM;
  171. }
  172. header = (void *)skb_put(skb, sizeof(*header));
  173. buflen = snprintf((void *)&header[1], buflen - 1,
  174. "L%05d\n%s\n", current->pid, attr->attr.name);
  175. skb_put(skb, buflen);
  176. header->size = cpu_to_le16(buflen);
  177. header->vpi = cpu_to_le16(0);
  178. header->vci = cpu_to_le16(0);
  179. header->type = cpu_to_le16(PKT_COMMAND);
  180. prm.pid = current->pid;
  181. prm.response = NULL;
  182. prm.port = SOLOS_CHAN(atmdev);
  183. spin_lock_irq(&card->param_queue_lock);
  184. list_add(&prm.list, &card->param_queue);
  185. spin_unlock_irq(&card->param_queue_lock);
  186. fpga_queue(card, prm.port, skb, NULL);
  187. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  188. spin_lock_irq(&card->param_queue_lock);
  189. list_del(&prm.list);
  190. spin_unlock_irq(&card->param_queue_lock);
  191. if (!prm.response)
  192. return -EIO;
  193. buflen = prm.response->len;
  194. memcpy(buf, prm.response->data, buflen);
  195. kfree_skb(prm.response);
  196. return buflen;
  197. }
  198. static ssize_t solos_param_store(struct device *dev, struct device_attribute *attr,
  199. const char *buf, size_t count)
  200. {
  201. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  202. struct solos_card *card = atmdev->dev_data;
  203. struct solos_param prm;
  204. struct sk_buff *skb;
  205. struct pkt_hdr *header;
  206. int buflen;
  207. ssize_t ret;
  208. buflen = strlen(attr->attr.name) + 11 + count;
  209. skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
  210. if (!skb) {
  211. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_store()\n");
  212. return -ENOMEM;
  213. }
  214. header = (void *)skb_put(skb, sizeof(*header));
  215. buflen = snprintf((void *)&header[1], buflen - 1,
  216. "L%05d\n%s\n%s\n", current->pid, attr->attr.name, buf);
  217. skb_put(skb, buflen);
  218. header->size = cpu_to_le16(buflen);
  219. header->vpi = cpu_to_le16(0);
  220. header->vci = cpu_to_le16(0);
  221. header->type = cpu_to_le16(PKT_COMMAND);
  222. prm.pid = current->pid;
  223. prm.response = NULL;
  224. prm.port = SOLOS_CHAN(atmdev);
  225. spin_lock_irq(&card->param_queue_lock);
  226. list_add(&prm.list, &card->param_queue);
  227. spin_unlock_irq(&card->param_queue_lock);
  228. fpga_queue(card, prm.port, skb, NULL);
  229. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  230. spin_lock_irq(&card->param_queue_lock);
  231. list_del(&prm.list);
  232. spin_unlock_irq(&card->param_queue_lock);
  233. skb = prm.response;
  234. if (!skb)
  235. return -EIO;
  236. buflen = skb->len;
  237. /* Sometimes it has a newline, sometimes it doesn't. */
  238. if (skb->data[buflen - 1] == '\n')
  239. buflen--;
  240. if (buflen == 2 && !strncmp(skb->data, "OK", 2))
  241. ret = count;
  242. else if (buflen == 5 && !strncmp(skb->data, "ERROR", 5))
  243. ret = -EIO;
  244. else {
  245. /* We know we have enough space allocated for this; we allocated
  246. it ourselves */
  247. skb->data[buflen] = 0;
  248. dev_warn(&card->dev->dev, "Unexpected parameter response: '%s'\n",
  249. skb->data);
  250. ret = -EIO;
  251. }
  252. kfree_skb(skb);
  253. return ret;
  254. }
  255. static char *next_string(struct sk_buff *skb)
  256. {
  257. int i = 0;
  258. char *this = skb->data;
  259. for (i = 0; i < skb->len; i++) {
  260. if (this[i] == '\n') {
  261. this[i] = 0;
  262. skb_pull(skb, i + 1);
  263. return this;
  264. }
  265. if (!isprint(this[i]))
  266. return NULL;
  267. }
  268. return NULL;
  269. }
  270. /*
  271. * Status packet has fields separated by \n, starting with a version number
  272. * for the information therein. Fields are....
  273. *
  274. * packet version
  275. * RxBitRate (version >= 1)
  276. * TxBitRate (version >= 1)
  277. * State (version >= 1)
  278. * LocalSNRMargin (version >= 1)
  279. * LocalLineAttn (version >= 1)
  280. */
  281. static int process_status(struct solos_card *card, int port, struct sk_buff *skb)
  282. {
  283. char *str, *end, *state_str, *snr, *attn;
  284. int ver, rate_up, rate_down;
  285. if (!card->atmdev[port])
  286. return -ENODEV;
  287. str = next_string(skb);
  288. if (!str)
  289. return -EIO;
  290. ver = simple_strtol(str, NULL, 10);
  291. if (ver < 1) {
  292. dev_warn(&card->dev->dev, "Unexpected status interrupt version %d\n",
  293. ver);
  294. return -EIO;
  295. }
  296. str = next_string(skb);
  297. if (!str)
  298. return -EIO;
  299. if (!strcmp(str, "ERROR")) {
  300. dev_dbg(&card->dev->dev, "Status packet indicated Solos error on port %d (starting up?)\n",
  301. port);
  302. return 0;
  303. }
  304. rate_down = simple_strtol(str, &end, 10);
  305. if (*end)
  306. return -EIO;
  307. str = next_string(skb);
  308. if (!str)
  309. return -EIO;
  310. rate_up = simple_strtol(str, &end, 10);
  311. if (*end)
  312. return -EIO;
  313. state_str = next_string(skb);
  314. if (!state_str)
  315. return -EIO;
  316. /* Anything but 'Showtime' is down */
  317. if (strcmp(state_str, "Showtime")) {
  318. card->atmdev[port]->signal = ATM_PHY_SIG_LOST;
  319. release_vccs(card->atmdev[port]);
  320. dev_info(&card->dev->dev, "Port %d: %s\n", port, state_str);
  321. return 0;
  322. }
  323. snr = next_string(skb);
  324. if (!str)
  325. return -EIO;
  326. attn = next_string(skb);
  327. if (!attn)
  328. return -EIO;
  329. dev_info(&card->dev->dev, "Port %d: %s @%d/%d kb/s%s%s%s%s\n",
  330. port, state_str, rate_down/1000, rate_up/1000,
  331. snr[0]?", SNR ":"", snr, attn[0]?", Attn ":"", attn);
  332. card->atmdev[port]->link_rate = rate_down / 424;
  333. card->atmdev[port]->signal = ATM_PHY_SIG_FOUND;
  334. return 0;
  335. }
  336. static int process_command(struct solos_card *card, int port, struct sk_buff *skb)
  337. {
  338. struct solos_param *prm;
  339. unsigned long flags;
  340. int cmdpid;
  341. int found = 0;
  342. if (skb->len < 7)
  343. return 0;
  344. if (skb->data[0] != 'L' || !isdigit(skb->data[1]) ||
  345. !isdigit(skb->data[2]) || !isdigit(skb->data[3]) ||
  346. !isdigit(skb->data[4]) || !isdigit(skb->data[5]) ||
  347. skb->data[6] != '\n')
  348. return 0;
  349. cmdpid = simple_strtol(&skb->data[1], NULL, 10);
  350. spin_lock_irqsave(&card->param_queue_lock, flags);
  351. list_for_each_entry(prm, &card->param_queue, list) {
  352. if (prm->port == port && prm->pid == cmdpid) {
  353. prm->response = skb;
  354. skb_pull(skb, 7);
  355. wake_up(&card->param_wq);
  356. found = 1;
  357. break;
  358. }
  359. }
  360. spin_unlock_irqrestore(&card->param_queue_lock, flags);
  361. return found;
  362. }
  363. static ssize_t console_show(struct device *dev, struct device_attribute *attr,
  364. char *buf)
  365. {
  366. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  367. struct solos_card *card = atmdev->dev_data;
  368. struct sk_buff *skb;
  369. spin_lock(&card->cli_queue_lock);
  370. skb = skb_dequeue(&card->cli_queue[SOLOS_CHAN(atmdev)]);
  371. spin_unlock(&card->cli_queue_lock);
  372. if(skb == NULL)
  373. return sprintf(buf, "No data.\n");
  374. memcpy(buf, skb->data, skb->len);
  375. dev_dbg(&card->dev->dev, "len: %d\n", skb->len);
  376. kfree_skb(skb);
  377. return skb->len;
  378. }
  379. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size)
  380. {
  381. struct sk_buff *skb;
  382. struct pkt_hdr *header;
  383. if (size > (BUF_SIZE - sizeof(*header))) {
  384. dev_dbg(&card->dev->dev, "Command is too big. Dropping request\n");
  385. return 0;
  386. }
  387. skb = alloc_skb(size + sizeof(*header), GFP_ATOMIC);
  388. if (!skb) {
  389. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in send_command()\n");
  390. return 0;
  391. }
  392. header = (void *)skb_put(skb, sizeof(*header));
  393. header->size = cpu_to_le16(size);
  394. header->vpi = cpu_to_le16(0);
  395. header->vci = cpu_to_le16(0);
  396. header->type = cpu_to_le16(PKT_COMMAND);
  397. memcpy(skb_put(skb, size), buf, size);
  398. fpga_queue(card, dev, skb, NULL);
  399. return 0;
  400. }
  401. static ssize_t console_store(struct device *dev, struct device_attribute *attr,
  402. const char *buf, size_t count)
  403. {
  404. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  405. struct solos_card *card = atmdev->dev_data;
  406. int err;
  407. err = send_command(card, SOLOS_CHAN(atmdev), buf, count);
  408. return err?:count;
  409. }
  410. static DEVICE_ATTR(console, 0644, console_show, console_store);
  411. #define SOLOS_ATTR_RO(x) static DEVICE_ATTR(x, 0444, solos_param_show, NULL);
  412. #define SOLOS_ATTR_RW(x) static DEVICE_ATTR(x, 0644, solos_param_show, solos_param_store);
  413. #include "solos-attrlist.c"
  414. #undef SOLOS_ATTR_RO
  415. #undef SOLOS_ATTR_RW
  416. #define SOLOS_ATTR_RO(x) &dev_attr_##x.attr,
  417. #define SOLOS_ATTR_RW(x) &dev_attr_##x.attr,
  418. static struct attribute *solos_attrs[] = {
  419. #include "solos-attrlist.c"
  420. NULL
  421. };
  422. static struct attribute_group solos_attr_group = {
  423. .attrs = solos_attrs,
  424. .name = "parameters",
  425. };
  426. static int flash_upgrade(struct solos_card *card, int chip)
  427. {
  428. const struct firmware *fw;
  429. const char *fw_name;
  430. uint32_t data32 = 0;
  431. int blocksize = 0;
  432. int numblocks = 0;
  433. int offset;
  434. if (chip == 0) {
  435. fw_name = "solos-FPGA.bin";
  436. blocksize = FPGA_BLOCK;
  437. }
  438. if (chip == 1) {
  439. fw_name = "solos-Firmware.bin";
  440. blocksize = SOLOS_BLOCK;
  441. }
  442. if (chip == 2){
  443. if (card->fpga_version > LEGACY_BUFFERS){
  444. fw_name = "solos-db-FPGA.bin";
  445. blocksize = FPGA_BLOCK;
  446. } else {
  447. dev_info(&card->dev->dev, "FPGA version doesn't support daughter board upgrades\n");
  448. return -EPERM;
  449. }
  450. }
  451. if (chip == 3){
  452. if (card->fpga_version > LEGACY_BUFFERS){
  453. fw_name = "solos-Firmware.bin";
  454. blocksize = SOLOS_BLOCK;
  455. } else {
  456. dev_info(&card->dev->dev, "FPGA version doesn't support daughter board upgrades\n");
  457. return -EPERM;
  458. }
  459. }
  460. if (request_firmware(&fw, fw_name, &card->dev->dev))
  461. return -ENOENT;
  462. dev_info(&card->dev->dev, "Flash upgrade starting\n");
  463. numblocks = fw->size / blocksize;
  464. dev_info(&card->dev->dev, "Firmware size: %zd\n", fw->size);
  465. dev_info(&card->dev->dev, "Number of blocks: %d\n", numblocks);
  466. dev_info(&card->dev->dev, "Changing FPGA to Update mode\n");
  467. iowrite32(1, card->config_regs + FPGA_MODE);
  468. data32 = ioread32(card->config_regs + FPGA_MODE);
  469. /* Set mode to Chip Erase */
  470. if(chip == 0 || chip == 2)
  471. dev_info(&card->dev->dev, "Set FPGA Flash mode to FPGA Chip Erase\n");
  472. if(chip == 1 || chip == 3)
  473. dev_info(&card->dev->dev, "Set FPGA Flash mode to Solos Chip Erase\n");
  474. iowrite32((chip * 2), card->config_regs + FLASH_MODE);
  475. iowrite32(1, card->config_regs + WRITE_FLASH);
  476. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  477. for (offset = 0; offset < fw->size; offset += blocksize) {
  478. int i;
  479. /* Clear write flag */
  480. iowrite32(0, card->config_regs + WRITE_FLASH);
  481. /* Set mode to Block Write */
  482. /* dev_info(&card->dev->dev, "Set FPGA Flash mode to Block Write\n"); */
  483. iowrite32(((chip * 2) + 1), card->config_regs + FLASH_MODE);
  484. /* Copy block to buffer, swapping each 16 bits */
  485. for(i = 0; i < blocksize; i += 4) {
  486. uint32_t word = swahb32p((uint32_t *)(fw->data + offset + i));
  487. if(card->fpga_version > LEGACY_BUFFERS)
  488. iowrite32(word, FLASH_BUF + i);
  489. else
  490. iowrite32(word, RX_BUF(card, 3) + i);
  491. }
  492. /* Specify block number and then trigger flash write */
  493. iowrite32(offset / blocksize, card->config_regs + FLASH_BLOCK);
  494. iowrite32(1, card->config_regs + WRITE_FLASH);
  495. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  496. }
  497. release_firmware(fw);
  498. iowrite32(0, card->config_regs + WRITE_FLASH);
  499. iowrite32(0, card->config_regs + FPGA_MODE);
  500. iowrite32(0, card->config_regs + FLASH_MODE);
  501. dev_info(&card->dev->dev, "Returning FPGA to Data mode\n");
  502. return 0;
  503. }
  504. static irqreturn_t solos_irq(int irq, void *dev_id)
  505. {
  506. struct solos_card *card = dev_id;
  507. int handled = 1;
  508. iowrite32(0, card->config_regs + IRQ_CLEAR);
  509. /* If we're up and running, just kick the tasklet to process TX/RX */
  510. if (card->atmdev[0])
  511. tasklet_schedule(&card->tlet);
  512. else
  513. wake_up(&card->fw_wq);
  514. return IRQ_RETVAL(handled);
  515. }
  516. void solos_bh(unsigned long card_arg)
  517. {
  518. struct solos_card *card = (void *)card_arg;
  519. uint32_t card_flags;
  520. uint32_t rx_done = 0;
  521. int port;
  522. /*
  523. * Since fpga_tx() is going to need to read the flags under its lock,
  524. * it can return them to us so that we don't have to hit PCI MMIO
  525. * again for the same information
  526. */
  527. card_flags = fpga_tx(card);
  528. for (port = 0; port < card->nr_ports; port++) {
  529. if (card_flags & (0x10 << port)) {
  530. struct pkt_hdr _hdr, *header;
  531. struct sk_buff *skb;
  532. struct atm_vcc *vcc;
  533. int size;
  534. if (card->using_dma) {
  535. skb = card->rx_skb[port];
  536. card->rx_skb[port] = NULL;
  537. pci_unmap_single(card->dev, SKB_CB(skb)->dma_addr,
  538. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  539. header = (void *)skb->data;
  540. size = le16_to_cpu(header->size);
  541. skb_put(skb, size + sizeof(*header));
  542. skb_pull(skb, sizeof(*header));
  543. } else {
  544. header = &_hdr;
  545. rx_done |= 0x10 << port;
  546. memcpy_fromio(header, RX_BUF(card, port), sizeof(*header));
  547. size = le16_to_cpu(header->size);
  548. skb = alloc_skb(size + 1, GFP_ATOMIC);
  549. if (!skb) {
  550. if (net_ratelimit())
  551. dev_warn(&card->dev->dev, "Failed to allocate sk_buff for RX\n");
  552. continue;
  553. }
  554. memcpy_fromio(skb_put(skb, size),
  555. RX_BUF(card, port) + sizeof(*header),
  556. size);
  557. }
  558. if (atmdebug) {
  559. dev_info(&card->dev->dev, "Received: device %d\n", port);
  560. dev_info(&card->dev->dev, "size: %d VPI: %d VCI: %d\n",
  561. size, le16_to_cpu(header->vpi),
  562. le16_to_cpu(header->vci));
  563. print_buffer(skb);
  564. }
  565. switch (le16_to_cpu(header->type)) {
  566. case PKT_DATA:
  567. vcc = find_vcc(card->atmdev[port], le16_to_cpu(header->vpi),
  568. le16_to_cpu(header->vci));
  569. if (!vcc) {
  570. if (net_ratelimit())
  571. dev_warn(&card->dev->dev, "Received packet for unknown VCI.VPI %d.%d on port %d\n",
  572. le16_to_cpu(header->vci), le16_to_cpu(header->vpi),
  573. port);
  574. continue;
  575. }
  576. atm_charge(vcc, skb->truesize);
  577. vcc->push(vcc, skb);
  578. atomic_inc(&vcc->stats->rx);
  579. break;
  580. case PKT_STATUS:
  581. if (process_status(card, port, skb) &&
  582. net_ratelimit()) {
  583. dev_warn(&card->dev->dev, "Bad status packet of %d bytes on port %d:\n", skb->len, port);
  584. print_buffer(skb);
  585. }
  586. dev_kfree_skb_any(skb);
  587. break;
  588. case PKT_COMMAND:
  589. default: /* FIXME: Not really, surely? */
  590. if (process_command(card, port, skb))
  591. break;
  592. spin_lock(&card->cli_queue_lock);
  593. if (skb_queue_len(&card->cli_queue[port]) > 10) {
  594. if (net_ratelimit())
  595. dev_warn(&card->dev->dev, "Dropping console response on port %d\n",
  596. port);
  597. dev_kfree_skb_any(skb);
  598. } else
  599. skb_queue_tail(&card->cli_queue[port], skb);
  600. spin_unlock(&card->cli_queue_lock);
  601. break;
  602. }
  603. }
  604. /* Allocate RX skbs for any ports which need them */
  605. if (card->using_dma && card->atmdev[port] &&
  606. !card->rx_skb[port]) {
  607. struct sk_buff *skb = alloc_skb(RX_DMA_SIZE, GFP_ATOMIC);
  608. if (skb) {
  609. SKB_CB(skb)->dma_addr =
  610. pci_map_single(card->dev, skb->data,
  611. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  612. iowrite32(SKB_CB(skb)->dma_addr,
  613. card->config_regs + RX_DMA_ADDR(port));
  614. card->rx_skb[port] = skb;
  615. } else {
  616. if (net_ratelimit())
  617. dev_warn(&card->dev->dev, "Failed to allocate RX skb");
  618. /* We'll have to try again later */
  619. tasklet_schedule(&card->tlet);
  620. }
  621. }
  622. }
  623. if (rx_done)
  624. iowrite32(rx_done, card->config_regs + FLAGS_ADDR);
  625. return;
  626. }
  627. static struct atm_vcc *find_vcc(struct atm_dev *dev, short vpi, int vci)
  628. {
  629. struct hlist_head *head;
  630. struct atm_vcc *vcc = NULL;
  631. struct hlist_node *node;
  632. struct sock *s;
  633. read_lock(&vcc_sklist_lock);
  634. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  635. sk_for_each(s, node, head) {
  636. vcc = atm_sk(s);
  637. if (vcc->dev == dev && vcc->vci == vci &&
  638. vcc->vpi == vpi && vcc->qos.rxtp.traffic_class != ATM_NONE)
  639. goto out;
  640. }
  641. vcc = NULL;
  642. out:
  643. read_unlock(&vcc_sklist_lock);
  644. return vcc;
  645. }
  646. static int list_vccs(int vci)
  647. {
  648. struct hlist_head *head;
  649. struct atm_vcc *vcc;
  650. struct hlist_node *node;
  651. struct sock *s;
  652. int num_found = 0;
  653. int i;
  654. read_lock(&vcc_sklist_lock);
  655. if (vci != 0){
  656. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  657. sk_for_each(s, node, head) {
  658. num_found ++;
  659. vcc = atm_sk(s);
  660. printk(KERN_DEBUG "Device: %d Vpi: %d Vci: %d\n",
  661. vcc->dev->number,
  662. vcc->vpi,
  663. vcc->vci);
  664. }
  665. } else {
  666. for(i = 0; i < VCC_HTABLE_SIZE; i++){
  667. head = &vcc_hash[i];
  668. sk_for_each(s, node, head) {
  669. num_found ++;
  670. vcc = atm_sk(s);
  671. printk(KERN_DEBUG "Device: %d Vpi: %d Vci: %d\n",
  672. vcc->dev->number,
  673. vcc->vpi,
  674. vcc->vci);
  675. }
  676. }
  677. }
  678. read_unlock(&vcc_sklist_lock);
  679. return num_found;
  680. }
  681. static void release_vccs(struct atm_dev *dev)
  682. {
  683. int i;
  684. write_lock_irq(&vcc_sklist_lock);
  685. for (i = 0; i < VCC_HTABLE_SIZE; i++) {
  686. struct hlist_head *head = &vcc_hash[i];
  687. struct hlist_node *node, *tmp;
  688. struct sock *s;
  689. struct atm_vcc *vcc;
  690. sk_for_each_safe(s, node, tmp, head) {
  691. vcc = atm_sk(s);
  692. if (vcc->dev == dev) {
  693. vcc_release_async(vcc, -EPIPE);
  694. sk_del_node_init(s);
  695. }
  696. }
  697. }
  698. write_unlock_irq(&vcc_sklist_lock);
  699. }
  700. static int popen(struct atm_vcc *vcc)
  701. {
  702. struct solos_card *card = vcc->dev->dev_data;
  703. struct sk_buff *skb;
  704. struct pkt_hdr *header;
  705. if (vcc->qos.aal != ATM_AAL5) {
  706. dev_warn(&card->dev->dev, "Unsupported ATM type %d\n",
  707. vcc->qos.aal);
  708. return -EINVAL;
  709. }
  710. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  711. if (!skb && net_ratelimit()) {
  712. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in popen()\n");
  713. return -ENOMEM;
  714. }
  715. header = (void *)skb_put(skb, sizeof(*header));
  716. header->size = cpu_to_le16(0);
  717. header->vpi = cpu_to_le16(vcc->vpi);
  718. header->vci = cpu_to_le16(vcc->vci);
  719. header->type = cpu_to_le16(PKT_POPEN);
  720. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  721. set_bit(ATM_VF_ADDR, &vcc->flags);
  722. set_bit(ATM_VF_READY, &vcc->flags);
  723. list_vccs(0);
  724. return 0;
  725. }
  726. static void pclose(struct atm_vcc *vcc)
  727. {
  728. struct solos_card *card = vcc->dev->dev_data;
  729. struct sk_buff *skb;
  730. struct pkt_hdr *header;
  731. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  732. if (!skb) {
  733. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in pclose()\n");
  734. return;
  735. }
  736. header = (void *)skb_put(skb, sizeof(*header));
  737. header->size = cpu_to_le16(0);
  738. header->vpi = cpu_to_le16(vcc->vpi);
  739. header->vci = cpu_to_le16(vcc->vci);
  740. header->type = cpu_to_le16(PKT_PCLOSE);
  741. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  742. clear_bit(ATM_VF_ADDR, &vcc->flags);
  743. clear_bit(ATM_VF_READY, &vcc->flags);
  744. return;
  745. }
  746. static int print_buffer(struct sk_buff *buf)
  747. {
  748. int len,i;
  749. char msg[500];
  750. char item[10];
  751. len = buf->len;
  752. for (i = 0; i < len; i++){
  753. if(i % 8 == 0)
  754. sprintf(msg, "%02X: ", i);
  755. sprintf(item,"%02X ",*(buf->data + i));
  756. strcat(msg, item);
  757. if(i % 8 == 7) {
  758. sprintf(item, "\n");
  759. strcat(msg, item);
  760. printk(KERN_DEBUG "%s", msg);
  761. }
  762. }
  763. if (i % 8 != 0) {
  764. sprintf(item, "\n");
  765. strcat(msg, item);
  766. printk(KERN_DEBUG "%s", msg);
  767. }
  768. printk(KERN_DEBUG "\n");
  769. return 0;
  770. }
  771. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  772. struct atm_vcc *vcc)
  773. {
  774. int old_len;
  775. unsigned long flags;
  776. SKB_CB(skb)->vcc = vcc;
  777. spin_lock_irqsave(&card->tx_queue_lock, flags);
  778. old_len = skb_queue_len(&card->tx_queue[port]);
  779. skb_queue_tail(&card->tx_queue[port], skb);
  780. if (!old_len)
  781. card->tx_mask |= (1 << port);
  782. spin_unlock_irqrestore(&card->tx_queue_lock, flags);
  783. /* Theoretically we could just schedule the tasklet here, but
  784. that introduces latency we don't want -- it's noticeable */
  785. if (!old_len)
  786. fpga_tx(card);
  787. }
  788. static uint32_t fpga_tx(struct solos_card *card)
  789. {
  790. uint32_t tx_pending, card_flags;
  791. uint32_t tx_started = 0;
  792. struct sk_buff *skb;
  793. struct atm_vcc *vcc;
  794. unsigned char port;
  795. unsigned long flags;
  796. spin_lock_irqsave(&card->tx_lock, flags);
  797. card_flags = ioread32(card->config_regs + FLAGS_ADDR);
  798. /*
  799. * The queue lock is required for _writing_ to tx_mask, but we're
  800. * OK to read it here without locking. The only potential update
  801. * that we could race with is in fpga_queue() where it sets a bit
  802. * for a new port... but it's going to call this function again if
  803. * it's doing that, anyway.
  804. */
  805. tx_pending = card->tx_mask & ~card_flags;
  806. for (port = 0; tx_pending; tx_pending >>= 1, port++) {
  807. if (tx_pending & 1) {
  808. struct sk_buff *oldskb = card->tx_skb[port];
  809. if (oldskb)
  810. pci_unmap_single(card->dev, SKB_CB(oldskb)->dma_addr,
  811. oldskb->len, PCI_DMA_TODEVICE);
  812. spin_lock(&card->tx_queue_lock);
  813. skb = skb_dequeue(&card->tx_queue[port]);
  814. if (!skb)
  815. card->tx_mask &= ~(1 << port);
  816. spin_unlock(&card->tx_queue_lock);
  817. if (skb && !card->using_dma) {
  818. memcpy_toio(TX_BUF(card, port), skb->data, skb->len);
  819. tx_started |= 1 << port;
  820. oldskb = skb; /* We're done with this skb already */
  821. } else if (skb && card->using_dma) {
  822. SKB_CB(skb)->dma_addr = pci_map_single(card->dev, skb->data,
  823. skb->len, PCI_DMA_TODEVICE);
  824. iowrite32(SKB_CB(skb)->dma_addr,
  825. card->config_regs + TX_DMA_ADDR(port));
  826. }
  827. if (!oldskb)
  828. continue;
  829. /* Clean up and free oldskb now it's gone */
  830. if (atmdebug) {
  831. dev_info(&card->dev->dev, "Transmitted: port %d\n",
  832. port);
  833. print_buffer(oldskb);
  834. }
  835. vcc = SKB_CB(oldskb)->vcc;
  836. if (vcc) {
  837. atomic_inc(&vcc->stats->tx);
  838. solos_pop(vcc, oldskb);
  839. } else
  840. dev_kfree_skb_irq(oldskb);
  841. }
  842. }
  843. /* For non-DMA TX, write the 'TX start' bit for all four ports simultaneously */
  844. if (tx_started)
  845. iowrite32(tx_started, card->config_regs + FLAGS_ADDR);
  846. spin_unlock_irqrestore(&card->tx_lock, flags);
  847. return card_flags;
  848. }
  849. static int psend(struct atm_vcc *vcc, struct sk_buff *skb)
  850. {
  851. struct solos_card *card = vcc->dev->dev_data;
  852. struct pkt_hdr *header;
  853. int pktlen;
  854. pktlen = skb->len;
  855. if (pktlen > (BUF_SIZE - sizeof(*header))) {
  856. dev_warn(&card->dev->dev, "Length of PDU is too large. Dropping PDU.\n");
  857. solos_pop(vcc, skb);
  858. return 0;
  859. }
  860. if (!skb_clone_writable(skb, sizeof(*header))) {
  861. int expand_by = 0;
  862. int ret;
  863. if (skb_headroom(skb) < sizeof(*header))
  864. expand_by = sizeof(*header) - skb_headroom(skb);
  865. ret = pskb_expand_head(skb, expand_by, 0, GFP_ATOMIC);
  866. if (ret) {
  867. dev_warn(&card->dev->dev, "pskb_expand_head failed.\n");
  868. solos_pop(vcc, skb);
  869. return ret;
  870. }
  871. }
  872. header = (void *)skb_push(skb, sizeof(*header));
  873. /* This does _not_ include the size of the header */
  874. header->size = cpu_to_le16(pktlen);
  875. header->vpi = cpu_to_le16(vcc->vpi);
  876. header->vci = cpu_to_le16(vcc->vci);
  877. header->type = cpu_to_le16(PKT_DATA);
  878. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, vcc);
  879. return 0;
  880. }
  881. static struct atmdev_ops fpga_ops = {
  882. .open = popen,
  883. .close = pclose,
  884. .ioctl = NULL,
  885. .getsockopt = NULL,
  886. .setsockopt = NULL,
  887. .send = psend,
  888. .send_oam = NULL,
  889. .phy_put = NULL,
  890. .phy_get = NULL,
  891. .change_qos = NULL,
  892. .proc_read = NULL,
  893. .owner = THIS_MODULE
  894. };
  895. static int fpga_probe(struct pci_dev *dev, const struct pci_device_id *id)
  896. {
  897. int err;
  898. uint16_t fpga_ver;
  899. uint8_t major_ver, minor_ver;
  900. uint32_t data32;
  901. struct solos_card *card;
  902. card = kzalloc(sizeof(*card), GFP_KERNEL);
  903. if (!card)
  904. return -ENOMEM;
  905. card->dev = dev;
  906. init_waitqueue_head(&card->fw_wq);
  907. init_waitqueue_head(&card->param_wq);
  908. err = pci_enable_device(dev);
  909. if (err) {
  910. dev_warn(&dev->dev, "Failed to enable PCI device\n");
  911. goto out;
  912. }
  913. err = pci_set_dma_mask(dev, DMA_32BIT_MASK);
  914. if (err) {
  915. dev_warn(&dev->dev, "Failed to set 32-bit DMA mask\n");
  916. goto out;
  917. }
  918. err = pci_request_regions(dev, "solos");
  919. if (err) {
  920. dev_warn(&dev->dev, "Failed to request regions\n");
  921. goto out;
  922. }
  923. card->config_regs = pci_iomap(dev, 0, CONFIG_RAM_SIZE);
  924. if (!card->config_regs) {
  925. dev_warn(&dev->dev, "Failed to ioremap config registers\n");
  926. goto out_release_regions;
  927. }
  928. card->buffers = pci_iomap(dev, 1, DATA_RAM_SIZE);
  929. if (!card->buffers) {
  930. dev_warn(&dev->dev, "Failed to ioremap data buffers\n");
  931. goto out_unmap_config;
  932. }
  933. if (reset) {
  934. iowrite32(1, card->config_regs + FPGA_MODE);
  935. data32 = ioread32(card->config_regs + FPGA_MODE);
  936. iowrite32(0, card->config_regs + FPGA_MODE);
  937. data32 = ioread32(card->config_regs + FPGA_MODE);
  938. }
  939. data32 = ioread32(card->config_regs + FPGA_VER);
  940. fpga_ver = (data32 & 0x0000FFFF);
  941. major_ver = ((data32 & 0xFF000000) >> 24);
  942. minor_ver = ((data32 & 0x00FF0000) >> 16);
  943. card->fpga_version = FPGA_VERSION(major_ver,minor_ver);
  944. if (card->fpga_version > LEGACY_BUFFERS)
  945. card->buffer_size = BUF_SIZE;
  946. else
  947. card->buffer_size = OLD_BUF_SIZE;
  948. dev_info(&dev->dev, "Solos FPGA Version %d.%02d svn-%d\n",
  949. major_ver, minor_ver, fpga_ver);
  950. if (card->fpga_version >= DMA_SUPPORTED){
  951. card->using_dma = 1;
  952. } else {
  953. card->using_dma = 0;
  954. /* Set RX empty flag for all ports */
  955. iowrite32(0xF0, card->config_regs + FLAGS_ADDR);
  956. }
  957. data32 = ioread32(card->config_regs + PORTS);
  958. card->nr_ports = (data32 & 0x000000FF);
  959. pci_set_drvdata(dev, card);
  960. tasklet_init(&card->tlet, solos_bh, (unsigned long)card);
  961. spin_lock_init(&card->tx_lock);
  962. spin_lock_init(&card->tx_queue_lock);
  963. spin_lock_init(&card->cli_queue_lock);
  964. spin_lock_init(&card->param_queue_lock);
  965. INIT_LIST_HEAD(&card->param_queue);
  966. err = request_irq(dev->irq, solos_irq, IRQF_SHARED,
  967. "solos-pci", card);
  968. if (err) {
  969. dev_dbg(&card->dev->dev, "Failed to request interrupt IRQ: %d\n", dev->irq);
  970. goto out_unmap_both;
  971. }
  972. iowrite32(1, card->config_regs + IRQ_EN_ADDR);
  973. if (fpga_upgrade)
  974. flash_upgrade(card, 0);
  975. if (firmware_upgrade)
  976. flash_upgrade(card, 1);
  977. if (db_fpga_upgrade)
  978. flash_upgrade(card, 2);
  979. if (db_firmware_upgrade)
  980. flash_upgrade(card, 3);
  981. err = atm_init(card);
  982. if (err)
  983. goto out_free_irq;
  984. return 0;
  985. out_free_irq:
  986. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  987. free_irq(dev->irq, card);
  988. tasklet_kill(&card->tlet);
  989. out_unmap_both:
  990. pci_set_drvdata(dev, NULL);
  991. pci_iounmap(dev, card->config_regs);
  992. out_unmap_config:
  993. pci_iounmap(dev, card->buffers);
  994. out_release_regions:
  995. pci_release_regions(dev);
  996. out:
  997. return err;
  998. }
  999. static int atm_init(struct solos_card *card)
  1000. {
  1001. int i;
  1002. for (i = 0; i < card->nr_ports; i++) {
  1003. struct sk_buff *skb;
  1004. struct pkt_hdr *header;
  1005. skb_queue_head_init(&card->tx_queue[i]);
  1006. skb_queue_head_init(&card->cli_queue[i]);
  1007. card->atmdev[i] = atm_dev_register("solos-pci", &fpga_ops, -1, NULL);
  1008. if (!card->atmdev[i]) {
  1009. dev_err(&card->dev->dev, "Could not register ATM device %d\n", i);
  1010. atm_remove(card);
  1011. return -ENODEV;
  1012. }
  1013. if (device_create_file(&card->atmdev[i]->class_dev, &dev_attr_console))
  1014. dev_err(&card->dev->dev, "Could not register console for ATM device %d\n", i);
  1015. if (sysfs_create_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group))
  1016. dev_err(&card->dev->dev, "Could not register parameter group for ATM device %d\n", i);
  1017. dev_info(&card->dev->dev, "Registered ATM device %d\n", card->atmdev[i]->number);
  1018. card->atmdev[i]->ci_range.vpi_bits = 8;
  1019. card->atmdev[i]->ci_range.vci_bits = 16;
  1020. card->atmdev[i]->dev_data = card;
  1021. card->atmdev[i]->phy_data = (void *)(unsigned long)i;
  1022. card->atmdev[i]->signal = ATM_PHY_SIG_UNKNOWN;
  1023. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  1024. if (!skb) {
  1025. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in atm_init()\n");
  1026. continue;
  1027. }
  1028. header = (void *)skb_put(skb, sizeof(*header));
  1029. header->size = cpu_to_le16(0);
  1030. header->vpi = cpu_to_le16(0);
  1031. header->vci = cpu_to_le16(0);
  1032. header->type = cpu_to_le16(PKT_STATUS);
  1033. fpga_queue(card, i, skb, NULL);
  1034. }
  1035. return 0;
  1036. }
  1037. static void atm_remove(struct solos_card *card)
  1038. {
  1039. int i;
  1040. for (i = 0; i < card->nr_ports; i++) {
  1041. if (card->atmdev[i]) {
  1042. struct sk_buff *skb;
  1043. dev_info(&card->dev->dev, "Unregistering ATM device %d\n", card->atmdev[i]->number);
  1044. sysfs_remove_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group);
  1045. atm_dev_deregister(card->atmdev[i]);
  1046. skb = card->rx_skb[i];
  1047. if (skb) {
  1048. pci_unmap_single(card->dev, SKB_CB(skb)->dma_addr,
  1049. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  1050. dev_kfree_skb(skb);
  1051. }
  1052. skb = card->tx_skb[i];
  1053. if (skb) {
  1054. pci_unmap_single(card->dev, SKB_CB(skb)->dma_addr,
  1055. skb->len, PCI_DMA_TODEVICE);
  1056. dev_kfree_skb(skb);
  1057. }
  1058. while ((skb = skb_dequeue(&card->tx_queue[i])))
  1059. dev_kfree_skb(skb);
  1060. }
  1061. }
  1062. }
  1063. static void fpga_remove(struct pci_dev *dev)
  1064. {
  1065. struct solos_card *card = pci_get_drvdata(dev);
  1066. /* Disable IRQs */
  1067. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  1068. /* Reset FPGA */
  1069. iowrite32(1, card->config_regs + FPGA_MODE);
  1070. (void)ioread32(card->config_regs + FPGA_MODE);
  1071. atm_remove(card);
  1072. free_irq(dev->irq, card);
  1073. tasklet_kill(&card->tlet);
  1074. /* Release device from reset */
  1075. iowrite32(0, card->config_regs + FPGA_MODE);
  1076. (void)ioread32(card->config_regs + FPGA_MODE);
  1077. pci_iounmap(dev, card->buffers);
  1078. pci_iounmap(dev, card->config_regs);
  1079. pci_release_regions(dev);
  1080. pci_disable_device(dev);
  1081. pci_set_drvdata(dev, NULL);
  1082. kfree(card);
  1083. }
  1084. static struct pci_device_id fpga_pci_tbl[] __devinitdata = {
  1085. { 0x10ee, 0x0300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  1086. { 0, }
  1087. };
  1088. MODULE_DEVICE_TABLE(pci,fpga_pci_tbl);
  1089. static struct pci_driver fpga_driver = {
  1090. .name = "solos",
  1091. .id_table = fpga_pci_tbl,
  1092. .probe = fpga_probe,
  1093. .remove = fpga_remove,
  1094. };
  1095. static int __init solos_pci_init(void)
  1096. {
  1097. printk(KERN_INFO "Solos PCI Driver Version %s\n", VERSION);
  1098. return pci_register_driver(&fpga_driver);
  1099. }
  1100. static void __exit solos_pci_exit(void)
  1101. {
  1102. pci_unregister_driver(&fpga_driver);
  1103. printk(KERN_INFO "Solos PCI Driver %s Unloaded\n", VERSION);
  1104. }
  1105. module_init(solos_pci_init);
  1106. module_exit(solos_pci_exit);