qla_os.c 108 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2010 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include <linux/moduleparam.h>
  9. #include <linux/vmalloc.h>
  10. #include <linux/delay.h>
  11. #include <linux/kthread.h>
  12. #include <linux/mutex.h>
  13. #include <linux/kobject.h>
  14. #include <linux/slab.h>
  15. #include <scsi/scsi_tcq.h>
  16. #include <scsi/scsicam.h>
  17. #include <scsi/scsi_transport.h>
  18. #include <scsi/scsi_transport_fc.h>
  19. /*
  20. * Driver version
  21. */
  22. char qla2x00_version_str[40];
  23. static int apidev_major;
  24. /*
  25. * SRB allocation cache
  26. */
  27. static struct kmem_cache *srb_cachep;
  28. /*
  29. * CT6 CTX allocation cache
  30. */
  31. static struct kmem_cache *ctx_cachep;
  32. int ql2xlogintimeout = 20;
  33. module_param(ql2xlogintimeout, int, S_IRUGO|S_IRUSR);
  34. MODULE_PARM_DESC(ql2xlogintimeout,
  35. "Login timeout value in seconds.");
  36. int qlport_down_retry;
  37. module_param(qlport_down_retry, int, S_IRUGO|S_IRUSR);
  38. MODULE_PARM_DESC(qlport_down_retry,
  39. "Maximum number of command retries to a port that returns "
  40. "a PORT-DOWN status.");
  41. int ql2xplogiabsentdevice;
  42. module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
  43. MODULE_PARM_DESC(ql2xplogiabsentdevice,
  44. "Option to enable PLOGI to devices that are not present after "
  45. "a Fabric scan. This is needed for several broken switches. "
  46. "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
  47. int ql2xloginretrycount = 0;
  48. module_param(ql2xloginretrycount, int, S_IRUGO|S_IRUSR);
  49. MODULE_PARM_DESC(ql2xloginretrycount,
  50. "Specify an alternate value for the NVRAM login retry count.");
  51. int ql2xallocfwdump = 1;
  52. module_param(ql2xallocfwdump, int, S_IRUGO|S_IRUSR);
  53. MODULE_PARM_DESC(ql2xallocfwdump,
  54. "Option to enable allocation of memory for a firmware dump "
  55. "during HBA initialization. Memory allocation requirements "
  56. "vary by ISP type. Default is 1 - allocate memory.");
  57. int ql2xextended_error_logging;
  58. module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
  59. MODULE_PARM_DESC(ql2xextended_error_logging,
  60. "Option to enable extended error logging, "
  61. "Default is 0 - no logging. 1 - log errors.");
  62. int ql2xshiftctondsd = 6;
  63. module_param(ql2xshiftctondsd, int, S_IRUGO|S_IRUSR);
  64. MODULE_PARM_DESC(ql2xshiftctondsd,
  65. "Set to control shifting of command type processing "
  66. "based on total number of SG elements.");
  67. static void qla2x00_free_device(scsi_qla_host_t *);
  68. int ql2xfdmienable=1;
  69. module_param(ql2xfdmienable, int, S_IRUGO|S_IRUSR);
  70. MODULE_PARM_DESC(ql2xfdmienable,
  71. "Enables FDMI registrations. "
  72. "0 - no FDMI. Default is 1 - perform FDMI.");
  73. #define MAX_Q_DEPTH 32
  74. static int ql2xmaxqdepth = MAX_Q_DEPTH;
  75. module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
  76. MODULE_PARM_DESC(ql2xmaxqdepth,
  77. "Maximum queue depth to report for target devices.");
  78. /* Do not change the value of this after module load */
  79. int ql2xenabledif = 1;
  80. module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR);
  81. MODULE_PARM_DESC(ql2xenabledif,
  82. " Enable T10-CRC-DIF "
  83. " Default is 0 - No DIF Support. 1 - Enable it");
  84. int ql2xenablehba_err_chk;
  85. module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
  86. MODULE_PARM_DESC(ql2xenablehba_err_chk,
  87. " Enable T10-CRC-DIF Error isolation by HBA"
  88. " Default is 0 - Error isolation disabled, 1 - Enable it");
  89. int ql2xiidmaenable=1;
  90. module_param(ql2xiidmaenable, int, S_IRUGO|S_IRUSR);
  91. MODULE_PARM_DESC(ql2xiidmaenable,
  92. "Enables iIDMA settings "
  93. "Default is 1 - perform iIDMA. 0 - no iIDMA.");
  94. int ql2xmaxqueues = 1;
  95. module_param(ql2xmaxqueues, int, S_IRUGO|S_IRUSR);
  96. MODULE_PARM_DESC(ql2xmaxqueues,
  97. "Enables MQ settings "
  98. "Default is 1 for single queue. Set it to number "
  99. "of queues in MQ mode.");
  100. int ql2xmultique_tag;
  101. module_param(ql2xmultique_tag, int, S_IRUGO|S_IRUSR);
  102. MODULE_PARM_DESC(ql2xmultique_tag,
  103. "Enables CPU affinity settings for the driver "
  104. "Default is 0 for no affinity of request and response IO. "
  105. "Set it to 1 to turn on the cpu affinity.");
  106. int ql2xfwloadbin;
  107. module_param(ql2xfwloadbin, int, S_IRUGO|S_IRUSR);
  108. MODULE_PARM_DESC(ql2xfwloadbin,
  109. "Option to specify location from which to load ISP firmware:\n"
  110. " 2 -- load firmware via the request_firmware() (hotplug)\n"
  111. " interface.\n"
  112. " 1 -- load firmware from flash.\n"
  113. " 0 -- use default semantics.\n");
  114. int ql2xetsenable;
  115. module_param(ql2xetsenable, int, S_IRUGO|S_IRUSR);
  116. MODULE_PARM_DESC(ql2xetsenable,
  117. "Enables firmware ETS burst."
  118. "Default is 0 - skip ETS enablement.");
  119. int ql2xdbwr = 1;
  120. module_param(ql2xdbwr, int, S_IRUGO|S_IRUSR);
  121. MODULE_PARM_DESC(ql2xdbwr,
  122. "Option to specify scheme for request queue posting\n"
  123. " 0 -- Regular doorbell.\n"
  124. " 1 -- CAMRAM doorbell (faster).\n");
  125. int ql2xdontresethba;
  126. module_param(ql2xdontresethba, int, S_IRUGO|S_IRUSR);
  127. MODULE_PARM_DESC(ql2xdontresethba,
  128. "Option to specify reset behaviour\n"
  129. " 0 (Default) -- Reset on failure.\n"
  130. " 1 -- Do not reset on failure.\n");
  131. int ql2xtargetreset = 1;
  132. module_param(ql2xtargetreset, int, S_IRUGO|S_IRUSR);
  133. MODULE_PARM_DESC(ql2xtargetreset,
  134. "Enable target reset."
  135. "Default is 1 - use hw defaults.");
  136. int ql2xgffidenable;
  137. module_param(ql2xgffidenable, int, S_IRUGO|S_IRUSR);
  138. MODULE_PARM_DESC(ql2xgffidenable,
  139. "Enables GFF_ID checks of port type. "
  140. "Default is 0 - Do not use GFF_ID information.");
  141. int ql2xasynctmfenable;
  142. module_param(ql2xasynctmfenable, int, S_IRUGO|S_IRUSR);
  143. MODULE_PARM_DESC(ql2xasynctmfenable,
  144. "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
  145. "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
  146. /*
  147. * SCSI host template entry points
  148. */
  149. static int qla2xxx_slave_configure(struct scsi_device * device);
  150. static int qla2xxx_slave_alloc(struct scsi_device *);
  151. static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
  152. static void qla2xxx_scan_start(struct Scsi_Host *);
  153. static void qla2xxx_slave_destroy(struct scsi_device *);
  154. static int qla2xxx_queuecommand(struct scsi_cmnd *cmd,
  155. void (*fn)(struct scsi_cmnd *));
  156. static int qla2xxx_eh_abort(struct scsi_cmnd *);
  157. static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
  158. static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
  159. static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
  160. static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
  161. static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
  162. static int qla2x00_change_queue_type(struct scsi_device *, int);
  163. struct scsi_host_template qla2xxx_driver_template = {
  164. .module = THIS_MODULE,
  165. .name = QLA2XXX_DRIVER_NAME,
  166. .queuecommand = qla2xxx_queuecommand,
  167. .eh_abort_handler = qla2xxx_eh_abort,
  168. .eh_device_reset_handler = qla2xxx_eh_device_reset,
  169. .eh_target_reset_handler = qla2xxx_eh_target_reset,
  170. .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
  171. .eh_host_reset_handler = qla2xxx_eh_host_reset,
  172. .slave_configure = qla2xxx_slave_configure,
  173. .slave_alloc = qla2xxx_slave_alloc,
  174. .slave_destroy = qla2xxx_slave_destroy,
  175. .scan_finished = qla2xxx_scan_finished,
  176. .scan_start = qla2xxx_scan_start,
  177. .change_queue_depth = qla2x00_change_queue_depth,
  178. .change_queue_type = qla2x00_change_queue_type,
  179. .this_id = -1,
  180. .cmd_per_lun = 3,
  181. .use_clustering = ENABLE_CLUSTERING,
  182. .sg_tablesize = SG_ALL,
  183. .max_sectors = 0xFFFF,
  184. .shost_attrs = qla2x00_host_attrs,
  185. };
  186. static struct scsi_transport_template *qla2xxx_transport_template = NULL;
  187. struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
  188. /* TODO Convert to inlines
  189. *
  190. * Timer routines
  191. */
  192. __inline__ void
  193. qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
  194. {
  195. init_timer(&vha->timer);
  196. vha->timer.expires = jiffies + interval * HZ;
  197. vha->timer.data = (unsigned long)vha;
  198. vha->timer.function = (void (*)(unsigned long))func;
  199. add_timer(&vha->timer);
  200. vha->timer_active = 1;
  201. }
  202. static inline void
  203. qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
  204. {
  205. /* Currently used for 82XX only. */
  206. if (vha->device_flags & DFLG_DEV_FAILED)
  207. return;
  208. mod_timer(&vha->timer, jiffies + interval * HZ);
  209. }
  210. static __inline__ void
  211. qla2x00_stop_timer(scsi_qla_host_t *vha)
  212. {
  213. del_timer_sync(&vha->timer);
  214. vha->timer_active = 0;
  215. }
  216. static int qla2x00_do_dpc(void *data);
  217. static void qla2x00_rst_aen(scsi_qla_host_t *);
  218. static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
  219. struct req_que **, struct rsp_que **);
  220. static void qla2x00_mem_free(struct qla_hw_data *);
  221. static void qla2x00_sp_free_dma(srb_t *);
  222. /* -------------------------------------------------------------------------- */
  223. static int qla2x00_alloc_queues(struct qla_hw_data *ha)
  224. {
  225. ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
  226. GFP_KERNEL);
  227. if (!ha->req_q_map) {
  228. qla_printk(KERN_WARNING, ha,
  229. "Unable to allocate memory for request queue ptrs\n");
  230. goto fail_req_map;
  231. }
  232. ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
  233. GFP_KERNEL);
  234. if (!ha->rsp_q_map) {
  235. qla_printk(KERN_WARNING, ha,
  236. "Unable to allocate memory for response queue ptrs\n");
  237. goto fail_rsp_map;
  238. }
  239. set_bit(0, ha->rsp_qid_map);
  240. set_bit(0, ha->req_qid_map);
  241. return 1;
  242. fail_rsp_map:
  243. kfree(ha->req_q_map);
  244. ha->req_q_map = NULL;
  245. fail_req_map:
  246. return -ENOMEM;
  247. }
  248. static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
  249. {
  250. if (req && req->ring)
  251. dma_free_coherent(&ha->pdev->dev,
  252. (req->length + 1) * sizeof(request_t),
  253. req->ring, req->dma);
  254. kfree(req);
  255. req = NULL;
  256. }
  257. static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
  258. {
  259. if (rsp && rsp->ring)
  260. dma_free_coherent(&ha->pdev->dev,
  261. (rsp->length + 1) * sizeof(response_t),
  262. rsp->ring, rsp->dma);
  263. kfree(rsp);
  264. rsp = NULL;
  265. }
  266. static void qla2x00_free_queues(struct qla_hw_data *ha)
  267. {
  268. struct req_que *req;
  269. struct rsp_que *rsp;
  270. int cnt;
  271. for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
  272. req = ha->req_q_map[cnt];
  273. qla2x00_free_req_que(ha, req);
  274. }
  275. kfree(ha->req_q_map);
  276. ha->req_q_map = NULL;
  277. for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
  278. rsp = ha->rsp_q_map[cnt];
  279. qla2x00_free_rsp_que(ha, rsp);
  280. }
  281. kfree(ha->rsp_q_map);
  282. ha->rsp_q_map = NULL;
  283. }
  284. static int qla25xx_setup_mode(struct scsi_qla_host *vha)
  285. {
  286. uint16_t options = 0;
  287. int ques, req, ret;
  288. struct qla_hw_data *ha = vha->hw;
  289. if (!(ha->fw_attributes & BIT_6)) {
  290. qla_printk(KERN_INFO, ha,
  291. "Firmware is not multi-queue capable\n");
  292. goto fail;
  293. }
  294. if (ql2xmultique_tag) {
  295. /* create a request queue for IO */
  296. options |= BIT_7;
  297. req = qla25xx_create_req_que(ha, options, 0, 0, -1,
  298. QLA_DEFAULT_QUE_QOS);
  299. if (!req) {
  300. qla_printk(KERN_WARNING, ha,
  301. "Can't create request queue\n");
  302. goto fail;
  303. }
  304. ha->wq = create_workqueue("qla2xxx_wq");
  305. vha->req = ha->req_q_map[req];
  306. options |= BIT_1;
  307. for (ques = 1; ques < ha->max_rsp_queues; ques++) {
  308. ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
  309. if (!ret) {
  310. qla_printk(KERN_WARNING, ha,
  311. "Response Queue create failed\n");
  312. goto fail2;
  313. }
  314. }
  315. ha->flags.cpu_affinity_enabled = 1;
  316. DEBUG2(qla_printk(KERN_INFO, ha,
  317. "CPU affinity mode enabled, no. of response"
  318. " queues:%d, no. of request queues:%d\n",
  319. ha->max_rsp_queues, ha->max_req_queues));
  320. }
  321. return 0;
  322. fail2:
  323. qla25xx_delete_queues(vha);
  324. destroy_workqueue(ha->wq);
  325. ha->wq = NULL;
  326. fail:
  327. ha->mqenable = 0;
  328. kfree(ha->req_q_map);
  329. kfree(ha->rsp_q_map);
  330. ha->max_req_queues = ha->max_rsp_queues = 1;
  331. return 1;
  332. }
  333. static char *
  334. qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
  335. {
  336. struct qla_hw_data *ha = vha->hw;
  337. static char *pci_bus_modes[] = {
  338. "33", "66", "100", "133",
  339. };
  340. uint16_t pci_bus;
  341. strcpy(str, "PCI");
  342. pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
  343. if (pci_bus) {
  344. strcat(str, "-X (");
  345. strcat(str, pci_bus_modes[pci_bus]);
  346. } else {
  347. pci_bus = (ha->pci_attr & BIT_8) >> 8;
  348. strcat(str, " (");
  349. strcat(str, pci_bus_modes[pci_bus]);
  350. }
  351. strcat(str, " MHz)");
  352. return (str);
  353. }
  354. static char *
  355. qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
  356. {
  357. static char *pci_bus_modes[] = { "33", "66", "100", "133", };
  358. struct qla_hw_data *ha = vha->hw;
  359. uint32_t pci_bus;
  360. int pcie_reg;
  361. pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
  362. if (pcie_reg) {
  363. char lwstr[6];
  364. uint16_t pcie_lstat, lspeed, lwidth;
  365. pcie_reg += 0x12;
  366. pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
  367. lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
  368. lwidth = (pcie_lstat &
  369. (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
  370. strcpy(str, "PCIe (");
  371. if (lspeed == 1)
  372. strcat(str, "2.5GT/s ");
  373. else if (lspeed == 2)
  374. strcat(str, "5.0GT/s ");
  375. else
  376. strcat(str, "<unknown> ");
  377. snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
  378. strcat(str, lwstr);
  379. return str;
  380. }
  381. strcpy(str, "PCI");
  382. pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
  383. if (pci_bus == 0 || pci_bus == 8) {
  384. strcat(str, " (");
  385. strcat(str, pci_bus_modes[pci_bus >> 3]);
  386. } else {
  387. strcat(str, "-X ");
  388. if (pci_bus & BIT_2)
  389. strcat(str, "Mode 2");
  390. else
  391. strcat(str, "Mode 1");
  392. strcat(str, " (");
  393. strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
  394. }
  395. strcat(str, " MHz)");
  396. return str;
  397. }
  398. static char *
  399. qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
  400. {
  401. char un_str[10];
  402. struct qla_hw_data *ha = vha->hw;
  403. sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
  404. ha->fw_minor_version,
  405. ha->fw_subminor_version);
  406. if (ha->fw_attributes & BIT_9) {
  407. strcat(str, "FLX");
  408. return (str);
  409. }
  410. switch (ha->fw_attributes & 0xFF) {
  411. case 0x7:
  412. strcat(str, "EF");
  413. break;
  414. case 0x17:
  415. strcat(str, "TP");
  416. break;
  417. case 0x37:
  418. strcat(str, "IP");
  419. break;
  420. case 0x77:
  421. strcat(str, "VI");
  422. break;
  423. default:
  424. sprintf(un_str, "(%x)", ha->fw_attributes);
  425. strcat(str, un_str);
  426. break;
  427. }
  428. if (ha->fw_attributes & 0x100)
  429. strcat(str, "X");
  430. return (str);
  431. }
  432. static char *
  433. qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
  434. {
  435. struct qla_hw_data *ha = vha->hw;
  436. sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
  437. ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
  438. return str;
  439. }
  440. static inline srb_t *
  441. qla2x00_get_new_sp(scsi_qla_host_t *vha, fc_port_t *fcport,
  442. struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
  443. {
  444. srb_t *sp;
  445. struct qla_hw_data *ha = vha->hw;
  446. sp = mempool_alloc(ha->srb_mempool, GFP_ATOMIC);
  447. if (!sp)
  448. return sp;
  449. atomic_set(&sp->ref_count, 1);
  450. sp->fcport = fcport;
  451. sp->cmd = cmd;
  452. sp->flags = 0;
  453. CMD_SP(cmd) = (void *)sp;
  454. cmd->scsi_done = done;
  455. sp->ctx = NULL;
  456. return sp;
  457. }
  458. static int
  459. qla2xxx_queuecommand(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
  460. {
  461. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  462. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  463. struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
  464. struct qla_hw_data *ha = vha->hw;
  465. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  466. srb_t *sp;
  467. int rval;
  468. if (ha->flags.eeh_busy) {
  469. if (ha->flags.pci_channel_io_perm_failure)
  470. cmd->result = DID_NO_CONNECT << 16;
  471. else
  472. cmd->result = DID_REQUEUE << 16;
  473. goto qc24_fail_command;
  474. }
  475. rval = fc_remote_port_chkready(rport);
  476. if (rval) {
  477. cmd->result = rval;
  478. goto qc24_fail_command;
  479. }
  480. /* Close window on fcport/rport state-transitioning. */
  481. if (fcport->drport)
  482. goto qc24_target_busy;
  483. if (!vha->flags.difdix_supported &&
  484. scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
  485. DEBUG2(qla_printk(KERN_ERR, ha,
  486. "DIF Cap Not Reg, fail DIF capable cmd's:%x\n",
  487. cmd->cmnd[0]));
  488. cmd->result = DID_NO_CONNECT << 16;
  489. goto qc24_fail_command;
  490. }
  491. if (atomic_read(&fcport->state) != FCS_ONLINE) {
  492. if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
  493. atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
  494. cmd->result = DID_NO_CONNECT << 16;
  495. goto qc24_fail_command;
  496. }
  497. goto qc24_target_busy;
  498. }
  499. spin_unlock_irq(vha->host->host_lock);
  500. sp = qla2x00_get_new_sp(base_vha, fcport, cmd, done);
  501. if (!sp)
  502. goto qc24_host_busy_lock;
  503. rval = ha->isp_ops->start_scsi(sp);
  504. if (rval != QLA_SUCCESS)
  505. goto qc24_host_busy_free_sp;
  506. spin_lock_irq(vha->host->host_lock);
  507. return 0;
  508. qc24_host_busy_free_sp:
  509. qla2x00_sp_free_dma(sp);
  510. mempool_free(sp, ha->srb_mempool);
  511. qc24_host_busy_lock:
  512. spin_lock_irq(vha->host->host_lock);
  513. return SCSI_MLQUEUE_HOST_BUSY;
  514. qc24_target_busy:
  515. return SCSI_MLQUEUE_TARGET_BUSY;
  516. qc24_fail_command:
  517. done(cmd);
  518. return 0;
  519. }
  520. /*
  521. * qla2x00_eh_wait_on_command
  522. * Waits for the command to be returned by the Firmware for some
  523. * max time.
  524. *
  525. * Input:
  526. * cmd = Scsi Command to wait on.
  527. *
  528. * Return:
  529. * Not Found : 0
  530. * Found : 1
  531. */
  532. static int
  533. qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
  534. {
  535. #define ABORT_POLLING_PERIOD 1000
  536. #define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
  537. unsigned long wait_iter = ABORT_WAIT_ITER;
  538. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  539. struct qla_hw_data *ha = vha->hw;
  540. int ret = QLA_SUCCESS;
  541. if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
  542. DEBUG17(qla_printk(KERN_WARNING, ha, "return:eh_wait\n"));
  543. return ret;
  544. }
  545. while (CMD_SP(cmd) && wait_iter--) {
  546. msleep(ABORT_POLLING_PERIOD);
  547. }
  548. if (CMD_SP(cmd))
  549. ret = QLA_FUNCTION_FAILED;
  550. return ret;
  551. }
  552. /*
  553. * qla2x00_wait_for_hba_online
  554. * Wait till the HBA is online after going through
  555. * <= MAX_RETRIES_OF_ISP_ABORT or
  556. * finally HBA is disabled ie marked offline
  557. *
  558. * Input:
  559. * ha - pointer to host adapter structure
  560. *
  561. * Note:
  562. * Does context switching-Release SPIN_LOCK
  563. * (if any) before calling this routine.
  564. *
  565. * Return:
  566. * Success (Adapter is online) : 0
  567. * Failed (Adapter is offline/disabled) : 1
  568. */
  569. int
  570. qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
  571. {
  572. int return_status;
  573. unsigned long wait_online;
  574. struct qla_hw_data *ha = vha->hw;
  575. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  576. wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  577. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  578. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  579. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  580. ha->dpc_active) && time_before(jiffies, wait_online)) {
  581. msleep(1000);
  582. }
  583. if (base_vha->flags.online)
  584. return_status = QLA_SUCCESS;
  585. else
  586. return_status = QLA_FUNCTION_FAILED;
  587. return (return_status);
  588. }
  589. /*
  590. * qla2x00_wait_for_reset_ready
  591. * Wait till the HBA is online after going through
  592. * <= MAX_RETRIES_OF_ISP_ABORT or
  593. * finally HBA is disabled ie marked offline or flash
  594. * operations are in progress.
  595. *
  596. * Input:
  597. * ha - pointer to host adapter structure
  598. *
  599. * Note:
  600. * Does context switching-Release SPIN_LOCK
  601. * (if any) before calling this routine.
  602. *
  603. * Return:
  604. * Success (Adapter is online/no flash ops) : 0
  605. * Failed (Adapter is offline/disabled/flash ops in progress) : 1
  606. */
  607. static int
  608. qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
  609. {
  610. int return_status;
  611. unsigned long wait_online;
  612. struct qla_hw_data *ha = vha->hw;
  613. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  614. wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  615. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  616. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  617. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  618. ha->optrom_state != QLA_SWAITING ||
  619. ha->dpc_active) && time_before(jiffies, wait_online))
  620. msleep(1000);
  621. if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
  622. return_status = QLA_SUCCESS;
  623. else
  624. return_status = QLA_FUNCTION_FAILED;
  625. DEBUG2(printk("%s return_status=%d\n", __func__, return_status));
  626. return return_status;
  627. }
  628. int
  629. qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
  630. {
  631. int return_status;
  632. unsigned long wait_reset;
  633. struct qla_hw_data *ha = vha->hw;
  634. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  635. wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  636. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  637. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  638. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  639. ha->dpc_active) && time_before(jiffies, wait_reset)) {
  640. msleep(1000);
  641. if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
  642. ha->flags.chip_reset_done)
  643. break;
  644. }
  645. if (ha->flags.chip_reset_done)
  646. return_status = QLA_SUCCESS;
  647. else
  648. return_status = QLA_FUNCTION_FAILED;
  649. return return_status;
  650. }
  651. /*
  652. * qla2x00_wait_for_loop_ready
  653. * Wait for MAX_LOOP_TIMEOUT(5 min) value for loop
  654. * to be in LOOP_READY state.
  655. * Input:
  656. * ha - pointer to host adapter structure
  657. *
  658. * Note:
  659. * Does context switching-Release SPIN_LOCK
  660. * (if any) before calling this routine.
  661. *
  662. *
  663. * Return:
  664. * Success (LOOP_READY) : 0
  665. * Failed (LOOP_NOT_READY) : 1
  666. */
  667. static inline int
  668. qla2x00_wait_for_loop_ready(scsi_qla_host_t *vha)
  669. {
  670. int return_status = QLA_SUCCESS;
  671. unsigned long loop_timeout ;
  672. struct qla_hw_data *ha = vha->hw;
  673. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  674. /* wait for 5 min at the max for loop to be ready */
  675. loop_timeout = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  676. while ((!atomic_read(&base_vha->loop_down_timer) &&
  677. atomic_read(&base_vha->loop_state) == LOOP_DOWN) ||
  678. atomic_read(&base_vha->loop_state) != LOOP_READY) {
  679. if (atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
  680. return_status = QLA_FUNCTION_FAILED;
  681. break;
  682. }
  683. msleep(1000);
  684. if (time_after_eq(jiffies, loop_timeout)) {
  685. return_status = QLA_FUNCTION_FAILED;
  686. break;
  687. }
  688. }
  689. return (return_status);
  690. }
  691. static void
  692. sp_get(struct srb *sp)
  693. {
  694. atomic_inc(&sp->ref_count);
  695. }
  696. /**************************************************************************
  697. * qla2xxx_eh_abort
  698. *
  699. * Description:
  700. * The abort function will abort the specified command.
  701. *
  702. * Input:
  703. * cmd = Linux SCSI command packet to be aborted.
  704. *
  705. * Returns:
  706. * Either SUCCESS or FAILED.
  707. *
  708. * Note:
  709. * Only return FAILED if command not returned by firmware.
  710. **************************************************************************/
  711. static int
  712. qla2xxx_eh_abort(struct scsi_cmnd *cmd)
  713. {
  714. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  715. srb_t *sp;
  716. int ret, i;
  717. unsigned int id, lun;
  718. unsigned long serial;
  719. unsigned long flags;
  720. int wait = 0;
  721. struct qla_hw_data *ha = vha->hw;
  722. struct req_que *req = vha->req;
  723. srb_t *spt;
  724. int got_ref = 0;
  725. fc_block_scsi_eh(cmd);
  726. if (!CMD_SP(cmd))
  727. return SUCCESS;
  728. ret = SUCCESS;
  729. id = cmd->device->id;
  730. lun = cmd->device->lun;
  731. serial = cmd->serial_number;
  732. spt = (srb_t *) CMD_SP(cmd);
  733. if (!spt)
  734. return SUCCESS;
  735. /* Check active list for command command. */
  736. spin_lock_irqsave(&ha->hardware_lock, flags);
  737. for (i = 1; i < MAX_OUTSTANDING_COMMANDS; i++) {
  738. sp = req->outstanding_cmds[i];
  739. if (sp == NULL)
  740. continue;
  741. if ((sp->ctx) && !(sp->flags & SRB_FCP_CMND_DMA_VALID) &&
  742. !IS_PROT_IO(sp))
  743. continue;
  744. if (sp->cmd != cmd)
  745. continue;
  746. DEBUG2(printk("%s(%ld): aborting sp %p from RISC."
  747. " pid=%ld.\n", __func__, vha->host_no, sp, serial));
  748. /* Get a reference to the sp and drop the lock.*/
  749. sp_get(sp);
  750. got_ref++;
  751. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  752. if (ha->isp_ops->abort_command(sp)) {
  753. DEBUG2(printk("%s(%ld): abort_command "
  754. "mbx failed.\n", __func__, vha->host_no));
  755. ret = FAILED;
  756. } else {
  757. DEBUG3(printk("%s(%ld): abort_command "
  758. "mbx success.\n", __func__, vha->host_no));
  759. wait = 1;
  760. }
  761. spin_lock_irqsave(&ha->hardware_lock, flags);
  762. break;
  763. }
  764. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  765. /* Wait for the command to be returned. */
  766. if (wait) {
  767. if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
  768. qla_printk(KERN_ERR, ha,
  769. "scsi(%ld:%d:%d): Abort handler timed out -- %lx "
  770. "%x.\n", vha->host_no, id, lun, serial, ret);
  771. ret = FAILED;
  772. }
  773. }
  774. if (got_ref)
  775. qla2x00_sp_compl(ha, sp);
  776. qla_printk(KERN_INFO, ha,
  777. "scsi(%ld:%d:%d): Abort command issued -- %d %lx %x.\n",
  778. vha->host_no, id, lun, wait, serial, ret);
  779. return ret;
  780. }
  781. int
  782. qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
  783. unsigned int l, enum nexus_wait_type type)
  784. {
  785. int cnt, match, status;
  786. unsigned long flags;
  787. struct qla_hw_data *ha = vha->hw;
  788. struct req_que *req;
  789. srb_t *sp;
  790. status = QLA_SUCCESS;
  791. spin_lock_irqsave(&ha->hardware_lock, flags);
  792. req = vha->req;
  793. for (cnt = 1; status == QLA_SUCCESS &&
  794. cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
  795. sp = req->outstanding_cmds[cnt];
  796. if (!sp)
  797. continue;
  798. if ((sp->ctx) && !IS_PROT_IO(sp))
  799. continue;
  800. if (vha->vp_idx != sp->fcport->vha->vp_idx)
  801. continue;
  802. match = 0;
  803. switch (type) {
  804. case WAIT_HOST:
  805. match = 1;
  806. break;
  807. case WAIT_TARGET:
  808. match = sp->cmd->device->id == t;
  809. break;
  810. case WAIT_LUN:
  811. match = (sp->cmd->device->id == t &&
  812. sp->cmd->device->lun == l);
  813. break;
  814. }
  815. if (!match)
  816. continue;
  817. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  818. status = qla2x00_eh_wait_on_command(sp->cmd);
  819. spin_lock_irqsave(&ha->hardware_lock, flags);
  820. }
  821. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  822. return status;
  823. }
  824. static char *reset_errors[] = {
  825. "HBA not online",
  826. "HBA not ready",
  827. "Task management failed",
  828. "Waiting for command completions",
  829. };
  830. static int
  831. __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
  832. struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
  833. {
  834. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  835. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  836. int err;
  837. fc_block_scsi_eh(cmd);
  838. if (!fcport)
  839. return FAILED;
  840. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET ISSUED.\n",
  841. vha->host_no, cmd->device->id, cmd->device->lun, name);
  842. err = 0;
  843. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS)
  844. goto eh_reset_failed;
  845. err = 1;
  846. if (qla2x00_wait_for_loop_ready(vha) != QLA_SUCCESS)
  847. goto eh_reset_failed;
  848. err = 2;
  849. if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
  850. != QLA_SUCCESS)
  851. goto eh_reset_failed;
  852. err = 3;
  853. if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
  854. cmd->device->lun, type) != QLA_SUCCESS)
  855. goto eh_reset_failed;
  856. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET SUCCEEDED.\n",
  857. vha->host_no, cmd->device->id, cmd->device->lun, name);
  858. return SUCCESS;
  859. eh_reset_failed:
  860. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET FAILED: %s.\n"
  861. , vha->host_no, cmd->device->id, cmd->device->lun, name,
  862. reset_errors[err]);
  863. return FAILED;
  864. }
  865. static int
  866. qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
  867. {
  868. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  869. struct qla_hw_data *ha = vha->hw;
  870. return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
  871. ha->isp_ops->lun_reset);
  872. }
  873. static int
  874. qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
  875. {
  876. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  877. struct qla_hw_data *ha = vha->hw;
  878. return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
  879. ha->isp_ops->target_reset);
  880. }
  881. /**************************************************************************
  882. * qla2xxx_eh_bus_reset
  883. *
  884. * Description:
  885. * The bus reset function will reset the bus and abort any executing
  886. * commands.
  887. *
  888. * Input:
  889. * cmd = Linux SCSI command packet of the command that cause the
  890. * bus reset.
  891. *
  892. * Returns:
  893. * SUCCESS/FAILURE (defined as macro in scsi.h).
  894. *
  895. **************************************************************************/
  896. static int
  897. qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
  898. {
  899. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  900. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  901. int ret = FAILED;
  902. unsigned int id, lun;
  903. unsigned long serial;
  904. fc_block_scsi_eh(cmd);
  905. id = cmd->device->id;
  906. lun = cmd->device->lun;
  907. serial = cmd->serial_number;
  908. if (!fcport)
  909. return ret;
  910. qla_printk(KERN_INFO, vha->hw,
  911. "scsi(%ld:%d:%d): BUS RESET ISSUED.\n", vha->host_no, id, lun);
  912. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
  913. DEBUG2(printk("%s failed:board disabled\n",__func__));
  914. goto eh_bus_reset_done;
  915. }
  916. if (qla2x00_wait_for_loop_ready(vha) == QLA_SUCCESS) {
  917. if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
  918. ret = SUCCESS;
  919. }
  920. if (ret == FAILED)
  921. goto eh_bus_reset_done;
  922. /* Flush outstanding commands. */
  923. if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
  924. QLA_SUCCESS)
  925. ret = FAILED;
  926. eh_bus_reset_done:
  927. qla_printk(KERN_INFO, vha->hw, "%s: reset %s\n", __func__,
  928. (ret == FAILED) ? "failed" : "succeded");
  929. return ret;
  930. }
  931. /**************************************************************************
  932. * qla2xxx_eh_host_reset
  933. *
  934. * Description:
  935. * The reset function will reset the Adapter.
  936. *
  937. * Input:
  938. * cmd = Linux SCSI command packet of the command that cause the
  939. * adapter reset.
  940. *
  941. * Returns:
  942. * Either SUCCESS or FAILED.
  943. *
  944. * Note:
  945. **************************************************************************/
  946. static int
  947. qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
  948. {
  949. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  950. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  951. struct qla_hw_data *ha = vha->hw;
  952. int ret = FAILED;
  953. unsigned int id, lun;
  954. unsigned long serial;
  955. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  956. fc_block_scsi_eh(cmd);
  957. id = cmd->device->id;
  958. lun = cmd->device->lun;
  959. serial = cmd->serial_number;
  960. if (!fcport)
  961. return ret;
  962. qla_printk(KERN_INFO, ha,
  963. "scsi(%ld:%d:%d): ADAPTER RESET ISSUED.\n", vha->host_no, id, lun);
  964. if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
  965. goto eh_host_reset_lock;
  966. /*
  967. * Fixme-may be dpc thread is active and processing
  968. * loop_resync,so wait a while for it to
  969. * be completed and then issue big hammer.Otherwise
  970. * it may cause I/O failure as big hammer marks the
  971. * devices as lost kicking of the port_down_timer
  972. * while dpc is stuck for the mailbox to complete.
  973. */
  974. qla2x00_wait_for_loop_ready(vha);
  975. if (vha != base_vha) {
  976. if (qla2x00_vp_abort_isp(vha))
  977. goto eh_host_reset_lock;
  978. } else {
  979. if (IS_QLA82XX(vha->hw)) {
  980. if (!qla82xx_fcoe_ctx_reset(vha)) {
  981. /* Ctx reset success */
  982. ret = SUCCESS;
  983. goto eh_host_reset_lock;
  984. }
  985. /* fall thru if ctx reset failed */
  986. }
  987. if (ha->wq)
  988. flush_workqueue(ha->wq);
  989. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  990. if (ha->isp_ops->abort_isp(base_vha)) {
  991. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  992. /* failed. schedule dpc to try */
  993. set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
  994. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS)
  995. goto eh_host_reset_lock;
  996. }
  997. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  998. }
  999. /* Waiting for command to be returned to OS.*/
  1000. if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
  1001. QLA_SUCCESS)
  1002. ret = SUCCESS;
  1003. eh_host_reset_lock:
  1004. qla_printk(KERN_INFO, ha, "%s: reset %s\n", __func__,
  1005. (ret == FAILED) ? "failed" : "succeded");
  1006. return ret;
  1007. }
  1008. /*
  1009. * qla2x00_loop_reset
  1010. * Issue loop reset.
  1011. *
  1012. * Input:
  1013. * ha = adapter block pointer.
  1014. *
  1015. * Returns:
  1016. * 0 = success
  1017. */
  1018. int
  1019. qla2x00_loop_reset(scsi_qla_host_t *vha)
  1020. {
  1021. int ret;
  1022. struct fc_port *fcport;
  1023. struct qla_hw_data *ha = vha->hw;
  1024. if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
  1025. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1026. if (fcport->port_type != FCT_TARGET)
  1027. continue;
  1028. ret = ha->isp_ops->target_reset(fcport, 0, 0);
  1029. if (ret != QLA_SUCCESS) {
  1030. DEBUG2_3(printk("%s(%ld): bus_reset failed: "
  1031. "target_reset=%d d_id=%x.\n", __func__,
  1032. vha->host_no, ret, fcport->d_id.b24));
  1033. }
  1034. }
  1035. }
  1036. if (ha->flags.enable_lip_full_login && !IS_QLA8XXX_TYPE(ha)) {
  1037. ret = qla2x00_full_login_lip(vha);
  1038. if (ret != QLA_SUCCESS) {
  1039. DEBUG2_3(printk("%s(%ld): failed: "
  1040. "full_login_lip=%d.\n", __func__, vha->host_no,
  1041. ret));
  1042. }
  1043. atomic_set(&vha->loop_state, LOOP_DOWN);
  1044. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  1045. qla2x00_mark_all_devices_lost(vha, 0);
  1046. qla2x00_wait_for_loop_ready(vha);
  1047. }
  1048. if (ha->flags.enable_lip_reset) {
  1049. ret = qla2x00_lip_reset(vha);
  1050. if (ret != QLA_SUCCESS) {
  1051. DEBUG2_3(printk("%s(%ld): failed: "
  1052. "lip_reset=%d.\n", __func__, vha->host_no, ret));
  1053. } else
  1054. qla2x00_wait_for_loop_ready(vha);
  1055. }
  1056. /* Issue marker command only when we are going to start the I/O */
  1057. vha->marker_needed = 1;
  1058. return QLA_SUCCESS;
  1059. }
  1060. void
  1061. qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
  1062. {
  1063. int que, cnt;
  1064. unsigned long flags;
  1065. srb_t *sp;
  1066. struct srb_ctx *ctx;
  1067. struct qla_hw_data *ha = vha->hw;
  1068. struct req_que *req;
  1069. spin_lock_irqsave(&ha->hardware_lock, flags);
  1070. for (que = 0; que < ha->max_req_queues; que++) {
  1071. req = ha->req_q_map[que];
  1072. if (!req)
  1073. continue;
  1074. for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
  1075. sp = req->outstanding_cmds[cnt];
  1076. if (sp) {
  1077. req->outstanding_cmds[cnt] = NULL;
  1078. if (!sp->ctx ||
  1079. (sp->flags & SRB_FCP_CMND_DMA_VALID) ||
  1080. IS_PROT_IO(sp)) {
  1081. sp->cmd->result = res;
  1082. qla2x00_sp_compl(ha, sp);
  1083. } else {
  1084. ctx = sp->ctx;
  1085. if (ctx->type == SRB_LOGIN_CMD ||
  1086. ctx->type == SRB_LOGOUT_CMD) {
  1087. ctx->u.iocb_cmd->free(sp);
  1088. } else {
  1089. struct fc_bsg_job *bsg_job =
  1090. ctx->u.bsg_job;
  1091. if (bsg_job->request->msgcode
  1092. == FC_BSG_HST_CT)
  1093. kfree(sp->fcport);
  1094. bsg_job->req->errors = 0;
  1095. bsg_job->reply->result = res;
  1096. bsg_job->job_done(bsg_job);
  1097. kfree(sp->ctx);
  1098. mempool_free(sp,
  1099. ha->srb_mempool);
  1100. }
  1101. }
  1102. }
  1103. }
  1104. }
  1105. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1106. }
  1107. static int
  1108. qla2xxx_slave_alloc(struct scsi_device *sdev)
  1109. {
  1110. struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
  1111. if (!rport || fc_remote_port_chkready(rport))
  1112. return -ENXIO;
  1113. sdev->hostdata = *(fc_port_t **)rport->dd_data;
  1114. return 0;
  1115. }
  1116. static int
  1117. qla2xxx_slave_configure(struct scsi_device *sdev)
  1118. {
  1119. scsi_qla_host_t *vha = shost_priv(sdev->host);
  1120. struct req_que *req = vha->req;
  1121. if (sdev->tagged_supported)
  1122. scsi_activate_tcq(sdev, req->max_q_depth);
  1123. else
  1124. scsi_deactivate_tcq(sdev, req->max_q_depth);
  1125. return 0;
  1126. }
  1127. static void
  1128. qla2xxx_slave_destroy(struct scsi_device *sdev)
  1129. {
  1130. sdev->hostdata = NULL;
  1131. }
  1132. static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
  1133. {
  1134. fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
  1135. if (!scsi_track_queue_full(sdev, qdepth))
  1136. return;
  1137. DEBUG2(qla_printk(KERN_INFO, fcport->vha->hw,
  1138. "scsi(%ld:%d:%d:%d): Queue depth adjusted-down to %d.\n",
  1139. fcport->vha->host_no, sdev->channel, sdev->id, sdev->lun,
  1140. sdev->queue_depth));
  1141. }
  1142. static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
  1143. {
  1144. fc_port_t *fcport = sdev->hostdata;
  1145. struct scsi_qla_host *vha = fcport->vha;
  1146. struct qla_hw_data *ha = vha->hw;
  1147. struct req_que *req = NULL;
  1148. req = vha->req;
  1149. if (!req)
  1150. return;
  1151. if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
  1152. return;
  1153. if (sdev->ordered_tags)
  1154. scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
  1155. else
  1156. scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
  1157. DEBUG2(qla_printk(KERN_INFO, ha,
  1158. "scsi(%ld:%d:%d:%d): Queue depth adjusted-up to %d.\n",
  1159. fcport->vha->host_no, sdev->channel, sdev->id, sdev->lun,
  1160. sdev->queue_depth));
  1161. }
  1162. static int
  1163. qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
  1164. {
  1165. switch (reason) {
  1166. case SCSI_QDEPTH_DEFAULT:
  1167. scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
  1168. break;
  1169. case SCSI_QDEPTH_QFULL:
  1170. qla2x00_handle_queue_full(sdev, qdepth);
  1171. break;
  1172. case SCSI_QDEPTH_RAMP_UP:
  1173. qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
  1174. break;
  1175. default:
  1176. return -EOPNOTSUPP;
  1177. }
  1178. return sdev->queue_depth;
  1179. }
  1180. static int
  1181. qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
  1182. {
  1183. if (sdev->tagged_supported) {
  1184. scsi_set_tag_type(sdev, tag_type);
  1185. if (tag_type)
  1186. scsi_activate_tcq(sdev, sdev->queue_depth);
  1187. else
  1188. scsi_deactivate_tcq(sdev, sdev->queue_depth);
  1189. } else
  1190. tag_type = 0;
  1191. return tag_type;
  1192. }
  1193. /**
  1194. * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
  1195. * @ha: HA context
  1196. *
  1197. * At exit, the @ha's flags.enable_64bit_addressing set to indicated
  1198. * supported addressing method.
  1199. */
  1200. static void
  1201. qla2x00_config_dma_addressing(struct qla_hw_data *ha)
  1202. {
  1203. /* Assume a 32bit DMA mask. */
  1204. ha->flags.enable_64bit_addressing = 0;
  1205. if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
  1206. /* Any upper-dword bits set? */
  1207. if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
  1208. !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
  1209. /* Ok, a 64bit DMA mask is applicable. */
  1210. ha->flags.enable_64bit_addressing = 1;
  1211. ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
  1212. ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
  1213. return;
  1214. }
  1215. }
  1216. dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
  1217. pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
  1218. }
  1219. static void
  1220. qla2x00_enable_intrs(struct qla_hw_data *ha)
  1221. {
  1222. unsigned long flags = 0;
  1223. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1224. spin_lock_irqsave(&ha->hardware_lock, flags);
  1225. ha->interrupts_on = 1;
  1226. /* enable risc and host interrupts */
  1227. WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
  1228. RD_REG_WORD(&reg->ictrl);
  1229. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1230. }
  1231. static void
  1232. qla2x00_disable_intrs(struct qla_hw_data *ha)
  1233. {
  1234. unsigned long flags = 0;
  1235. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1236. spin_lock_irqsave(&ha->hardware_lock, flags);
  1237. ha->interrupts_on = 0;
  1238. /* disable risc and host interrupts */
  1239. WRT_REG_WORD(&reg->ictrl, 0);
  1240. RD_REG_WORD(&reg->ictrl);
  1241. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1242. }
  1243. static void
  1244. qla24xx_enable_intrs(struct qla_hw_data *ha)
  1245. {
  1246. unsigned long flags = 0;
  1247. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  1248. spin_lock_irqsave(&ha->hardware_lock, flags);
  1249. ha->interrupts_on = 1;
  1250. WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
  1251. RD_REG_DWORD(&reg->ictrl);
  1252. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1253. }
  1254. static void
  1255. qla24xx_disable_intrs(struct qla_hw_data *ha)
  1256. {
  1257. unsigned long flags = 0;
  1258. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  1259. if (IS_NOPOLLING_TYPE(ha))
  1260. return;
  1261. spin_lock_irqsave(&ha->hardware_lock, flags);
  1262. ha->interrupts_on = 0;
  1263. WRT_REG_DWORD(&reg->ictrl, 0);
  1264. RD_REG_DWORD(&reg->ictrl);
  1265. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1266. }
  1267. static struct isp_operations qla2100_isp_ops = {
  1268. .pci_config = qla2100_pci_config,
  1269. .reset_chip = qla2x00_reset_chip,
  1270. .chip_diag = qla2x00_chip_diag,
  1271. .config_rings = qla2x00_config_rings,
  1272. .reset_adapter = qla2x00_reset_adapter,
  1273. .nvram_config = qla2x00_nvram_config,
  1274. .update_fw_options = qla2x00_update_fw_options,
  1275. .load_risc = qla2x00_load_risc,
  1276. .pci_info_str = qla2x00_pci_info_str,
  1277. .fw_version_str = qla2x00_fw_version_str,
  1278. .intr_handler = qla2100_intr_handler,
  1279. .enable_intrs = qla2x00_enable_intrs,
  1280. .disable_intrs = qla2x00_disable_intrs,
  1281. .abort_command = qla2x00_abort_command,
  1282. .target_reset = qla2x00_abort_target,
  1283. .lun_reset = qla2x00_lun_reset,
  1284. .fabric_login = qla2x00_login_fabric,
  1285. .fabric_logout = qla2x00_fabric_logout,
  1286. .calc_req_entries = qla2x00_calc_iocbs_32,
  1287. .build_iocbs = qla2x00_build_scsi_iocbs_32,
  1288. .prep_ms_iocb = qla2x00_prep_ms_iocb,
  1289. .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
  1290. .read_nvram = qla2x00_read_nvram_data,
  1291. .write_nvram = qla2x00_write_nvram_data,
  1292. .fw_dump = qla2100_fw_dump,
  1293. .beacon_on = NULL,
  1294. .beacon_off = NULL,
  1295. .beacon_blink = NULL,
  1296. .read_optrom = qla2x00_read_optrom_data,
  1297. .write_optrom = qla2x00_write_optrom_data,
  1298. .get_flash_version = qla2x00_get_flash_version,
  1299. .start_scsi = qla2x00_start_scsi,
  1300. .abort_isp = qla2x00_abort_isp,
  1301. };
  1302. static struct isp_operations qla2300_isp_ops = {
  1303. .pci_config = qla2300_pci_config,
  1304. .reset_chip = qla2x00_reset_chip,
  1305. .chip_diag = qla2x00_chip_diag,
  1306. .config_rings = qla2x00_config_rings,
  1307. .reset_adapter = qla2x00_reset_adapter,
  1308. .nvram_config = qla2x00_nvram_config,
  1309. .update_fw_options = qla2x00_update_fw_options,
  1310. .load_risc = qla2x00_load_risc,
  1311. .pci_info_str = qla2x00_pci_info_str,
  1312. .fw_version_str = qla2x00_fw_version_str,
  1313. .intr_handler = qla2300_intr_handler,
  1314. .enable_intrs = qla2x00_enable_intrs,
  1315. .disable_intrs = qla2x00_disable_intrs,
  1316. .abort_command = qla2x00_abort_command,
  1317. .target_reset = qla2x00_abort_target,
  1318. .lun_reset = qla2x00_lun_reset,
  1319. .fabric_login = qla2x00_login_fabric,
  1320. .fabric_logout = qla2x00_fabric_logout,
  1321. .calc_req_entries = qla2x00_calc_iocbs_32,
  1322. .build_iocbs = qla2x00_build_scsi_iocbs_32,
  1323. .prep_ms_iocb = qla2x00_prep_ms_iocb,
  1324. .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
  1325. .read_nvram = qla2x00_read_nvram_data,
  1326. .write_nvram = qla2x00_write_nvram_data,
  1327. .fw_dump = qla2300_fw_dump,
  1328. .beacon_on = qla2x00_beacon_on,
  1329. .beacon_off = qla2x00_beacon_off,
  1330. .beacon_blink = qla2x00_beacon_blink,
  1331. .read_optrom = qla2x00_read_optrom_data,
  1332. .write_optrom = qla2x00_write_optrom_data,
  1333. .get_flash_version = qla2x00_get_flash_version,
  1334. .start_scsi = qla2x00_start_scsi,
  1335. .abort_isp = qla2x00_abort_isp,
  1336. };
  1337. static struct isp_operations qla24xx_isp_ops = {
  1338. .pci_config = qla24xx_pci_config,
  1339. .reset_chip = qla24xx_reset_chip,
  1340. .chip_diag = qla24xx_chip_diag,
  1341. .config_rings = qla24xx_config_rings,
  1342. .reset_adapter = qla24xx_reset_adapter,
  1343. .nvram_config = qla24xx_nvram_config,
  1344. .update_fw_options = qla24xx_update_fw_options,
  1345. .load_risc = qla24xx_load_risc,
  1346. .pci_info_str = qla24xx_pci_info_str,
  1347. .fw_version_str = qla24xx_fw_version_str,
  1348. .intr_handler = qla24xx_intr_handler,
  1349. .enable_intrs = qla24xx_enable_intrs,
  1350. .disable_intrs = qla24xx_disable_intrs,
  1351. .abort_command = qla24xx_abort_command,
  1352. .target_reset = qla24xx_abort_target,
  1353. .lun_reset = qla24xx_lun_reset,
  1354. .fabric_login = qla24xx_login_fabric,
  1355. .fabric_logout = qla24xx_fabric_logout,
  1356. .calc_req_entries = NULL,
  1357. .build_iocbs = NULL,
  1358. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1359. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1360. .read_nvram = qla24xx_read_nvram_data,
  1361. .write_nvram = qla24xx_write_nvram_data,
  1362. .fw_dump = qla24xx_fw_dump,
  1363. .beacon_on = qla24xx_beacon_on,
  1364. .beacon_off = qla24xx_beacon_off,
  1365. .beacon_blink = qla24xx_beacon_blink,
  1366. .read_optrom = qla24xx_read_optrom_data,
  1367. .write_optrom = qla24xx_write_optrom_data,
  1368. .get_flash_version = qla24xx_get_flash_version,
  1369. .start_scsi = qla24xx_start_scsi,
  1370. .abort_isp = qla2x00_abort_isp,
  1371. };
  1372. static struct isp_operations qla25xx_isp_ops = {
  1373. .pci_config = qla25xx_pci_config,
  1374. .reset_chip = qla24xx_reset_chip,
  1375. .chip_diag = qla24xx_chip_diag,
  1376. .config_rings = qla24xx_config_rings,
  1377. .reset_adapter = qla24xx_reset_adapter,
  1378. .nvram_config = qla24xx_nvram_config,
  1379. .update_fw_options = qla24xx_update_fw_options,
  1380. .load_risc = qla24xx_load_risc,
  1381. .pci_info_str = qla24xx_pci_info_str,
  1382. .fw_version_str = qla24xx_fw_version_str,
  1383. .intr_handler = qla24xx_intr_handler,
  1384. .enable_intrs = qla24xx_enable_intrs,
  1385. .disable_intrs = qla24xx_disable_intrs,
  1386. .abort_command = qla24xx_abort_command,
  1387. .target_reset = qla24xx_abort_target,
  1388. .lun_reset = qla24xx_lun_reset,
  1389. .fabric_login = qla24xx_login_fabric,
  1390. .fabric_logout = qla24xx_fabric_logout,
  1391. .calc_req_entries = NULL,
  1392. .build_iocbs = NULL,
  1393. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1394. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1395. .read_nvram = qla25xx_read_nvram_data,
  1396. .write_nvram = qla25xx_write_nvram_data,
  1397. .fw_dump = qla25xx_fw_dump,
  1398. .beacon_on = qla24xx_beacon_on,
  1399. .beacon_off = qla24xx_beacon_off,
  1400. .beacon_blink = qla24xx_beacon_blink,
  1401. .read_optrom = qla25xx_read_optrom_data,
  1402. .write_optrom = qla24xx_write_optrom_data,
  1403. .get_flash_version = qla24xx_get_flash_version,
  1404. .start_scsi = qla24xx_dif_start_scsi,
  1405. .abort_isp = qla2x00_abort_isp,
  1406. };
  1407. static struct isp_operations qla81xx_isp_ops = {
  1408. .pci_config = qla25xx_pci_config,
  1409. .reset_chip = qla24xx_reset_chip,
  1410. .chip_diag = qla24xx_chip_diag,
  1411. .config_rings = qla24xx_config_rings,
  1412. .reset_adapter = qla24xx_reset_adapter,
  1413. .nvram_config = qla81xx_nvram_config,
  1414. .update_fw_options = qla81xx_update_fw_options,
  1415. .load_risc = qla81xx_load_risc,
  1416. .pci_info_str = qla24xx_pci_info_str,
  1417. .fw_version_str = qla24xx_fw_version_str,
  1418. .intr_handler = qla24xx_intr_handler,
  1419. .enable_intrs = qla24xx_enable_intrs,
  1420. .disable_intrs = qla24xx_disable_intrs,
  1421. .abort_command = qla24xx_abort_command,
  1422. .target_reset = qla24xx_abort_target,
  1423. .lun_reset = qla24xx_lun_reset,
  1424. .fabric_login = qla24xx_login_fabric,
  1425. .fabric_logout = qla24xx_fabric_logout,
  1426. .calc_req_entries = NULL,
  1427. .build_iocbs = NULL,
  1428. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1429. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1430. .read_nvram = NULL,
  1431. .write_nvram = NULL,
  1432. .fw_dump = qla81xx_fw_dump,
  1433. .beacon_on = qla24xx_beacon_on,
  1434. .beacon_off = qla24xx_beacon_off,
  1435. .beacon_blink = qla24xx_beacon_blink,
  1436. .read_optrom = qla25xx_read_optrom_data,
  1437. .write_optrom = qla24xx_write_optrom_data,
  1438. .get_flash_version = qla24xx_get_flash_version,
  1439. .start_scsi = qla24xx_dif_start_scsi,
  1440. .abort_isp = qla2x00_abort_isp,
  1441. };
  1442. static struct isp_operations qla82xx_isp_ops = {
  1443. .pci_config = qla82xx_pci_config,
  1444. .reset_chip = qla82xx_reset_chip,
  1445. .chip_diag = qla24xx_chip_diag,
  1446. .config_rings = qla82xx_config_rings,
  1447. .reset_adapter = qla24xx_reset_adapter,
  1448. .nvram_config = qla81xx_nvram_config,
  1449. .update_fw_options = qla24xx_update_fw_options,
  1450. .load_risc = qla82xx_load_risc,
  1451. .pci_info_str = qla82xx_pci_info_str,
  1452. .fw_version_str = qla24xx_fw_version_str,
  1453. .intr_handler = qla82xx_intr_handler,
  1454. .enable_intrs = qla82xx_enable_intrs,
  1455. .disable_intrs = qla82xx_disable_intrs,
  1456. .abort_command = qla24xx_abort_command,
  1457. .target_reset = qla24xx_abort_target,
  1458. .lun_reset = qla24xx_lun_reset,
  1459. .fabric_login = qla24xx_login_fabric,
  1460. .fabric_logout = qla24xx_fabric_logout,
  1461. .calc_req_entries = NULL,
  1462. .build_iocbs = NULL,
  1463. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1464. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1465. .read_nvram = qla24xx_read_nvram_data,
  1466. .write_nvram = qla24xx_write_nvram_data,
  1467. .fw_dump = qla24xx_fw_dump,
  1468. .beacon_on = qla24xx_beacon_on,
  1469. .beacon_off = qla24xx_beacon_off,
  1470. .beacon_blink = qla24xx_beacon_blink,
  1471. .read_optrom = qla82xx_read_optrom_data,
  1472. .write_optrom = qla82xx_write_optrom_data,
  1473. .get_flash_version = qla24xx_get_flash_version,
  1474. .start_scsi = qla82xx_start_scsi,
  1475. .abort_isp = qla82xx_abort_isp,
  1476. };
  1477. static inline void
  1478. qla2x00_set_isp_flags(struct qla_hw_data *ha)
  1479. {
  1480. ha->device_type = DT_EXTENDED_IDS;
  1481. switch (ha->pdev->device) {
  1482. case PCI_DEVICE_ID_QLOGIC_ISP2100:
  1483. ha->device_type |= DT_ISP2100;
  1484. ha->device_type &= ~DT_EXTENDED_IDS;
  1485. ha->fw_srisc_address = RISC_START_ADDRESS_2100;
  1486. break;
  1487. case PCI_DEVICE_ID_QLOGIC_ISP2200:
  1488. ha->device_type |= DT_ISP2200;
  1489. ha->device_type &= ~DT_EXTENDED_IDS;
  1490. ha->fw_srisc_address = RISC_START_ADDRESS_2100;
  1491. break;
  1492. case PCI_DEVICE_ID_QLOGIC_ISP2300:
  1493. ha->device_type |= DT_ISP2300;
  1494. ha->device_type |= DT_ZIO_SUPPORTED;
  1495. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1496. break;
  1497. case PCI_DEVICE_ID_QLOGIC_ISP2312:
  1498. ha->device_type |= DT_ISP2312;
  1499. ha->device_type |= DT_ZIO_SUPPORTED;
  1500. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1501. break;
  1502. case PCI_DEVICE_ID_QLOGIC_ISP2322:
  1503. ha->device_type |= DT_ISP2322;
  1504. ha->device_type |= DT_ZIO_SUPPORTED;
  1505. if (ha->pdev->subsystem_vendor == 0x1028 &&
  1506. ha->pdev->subsystem_device == 0x0170)
  1507. ha->device_type |= DT_OEM_001;
  1508. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1509. break;
  1510. case PCI_DEVICE_ID_QLOGIC_ISP6312:
  1511. ha->device_type |= DT_ISP6312;
  1512. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1513. break;
  1514. case PCI_DEVICE_ID_QLOGIC_ISP6322:
  1515. ha->device_type |= DT_ISP6322;
  1516. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1517. break;
  1518. case PCI_DEVICE_ID_QLOGIC_ISP2422:
  1519. ha->device_type |= DT_ISP2422;
  1520. ha->device_type |= DT_ZIO_SUPPORTED;
  1521. ha->device_type |= DT_FWI2;
  1522. ha->device_type |= DT_IIDMA;
  1523. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1524. break;
  1525. case PCI_DEVICE_ID_QLOGIC_ISP2432:
  1526. ha->device_type |= DT_ISP2432;
  1527. ha->device_type |= DT_ZIO_SUPPORTED;
  1528. ha->device_type |= DT_FWI2;
  1529. ha->device_type |= DT_IIDMA;
  1530. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1531. break;
  1532. case PCI_DEVICE_ID_QLOGIC_ISP8432:
  1533. ha->device_type |= DT_ISP8432;
  1534. ha->device_type |= DT_ZIO_SUPPORTED;
  1535. ha->device_type |= DT_FWI2;
  1536. ha->device_type |= DT_IIDMA;
  1537. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1538. break;
  1539. case PCI_DEVICE_ID_QLOGIC_ISP5422:
  1540. ha->device_type |= DT_ISP5422;
  1541. ha->device_type |= DT_FWI2;
  1542. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1543. break;
  1544. case PCI_DEVICE_ID_QLOGIC_ISP5432:
  1545. ha->device_type |= DT_ISP5432;
  1546. ha->device_type |= DT_FWI2;
  1547. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1548. break;
  1549. case PCI_DEVICE_ID_QLOGIC_ISP2532:
  1550. ha->device_type |= DT_ISP2532;
  1551. ha->device_type |= DT_ZIO_SUPPORTED;
  1552. ha->device_type |= DT_FWI2;
  1553. ha->device_type |= DT_IIDMA;
  1554. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1555. break;
  1556. case PCI_DEVICE_ID_QLOGIC_ISP8001:
  1557. ha->device_type |= DT_ISP8001;
  1558. ha->device_type |= DT_ZIO_SUPPORTED;
  1559. ha->device_type |= DT_FWI2;
  1560. ha->device_type |= DT_IIDMA;
  1561. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1562. break;
  1563. case PCI_DEVICE_ID_QLOGIC_ISP8021:
  1564. ha->device_type |= DT_ISP8021;
  1565. ha->device_type |= DT_ZIO_SUPPORTED;
  1566. ha->device_type |= DT_FWI2;
  1567. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1568. /* Initialize 82XX ISP flags */
  1569. qla82xx_init_flags(ha);
  1570. break;
  1571. }
  1572. if (IS_QLA82XX(ha))
  1573. ha->port_no = !(ha->portnum & 1);
  1574. else
  1575. /* Get adapter physical port no from interrupt pin register. */
  1576. pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
  1577. if (ha->port_no & 1)
  1578. ha->flags.port0 = 1;
  1579. else
  1580. ha->flags.port0 = 0;
  1581. }
  1582. static int
  1583. qla2x00_iospace_config(struct qla_hw_data *ha)
  1584. {
  1585. resource_size_t pio;
  1586. uint16_t msix;
  1587. int cpus;
  1588. if (IS_QLA82XX(ha))
  1589. return qla82xx_iospace_config(ha);
  1590. if (pci_request_selected_regions(ha->pdev, ha->bars,
  1591. QLA2XXX_DRIVER_NAME)) {
  1592. qla_printk(KERN_WARNING, ha,
  1593. "Failed to reserve PIO/MMIO regions (%s)\n",
  1594. pci_name(ha->pdev));
  1595. goto iospace_error_exit;
  1596. }
  1597. if (!(ha->bars & 1))
  1598. goto skip_pio;
  1599. /* We only need PIO for Flash operations on ISP2312 v2 chips. */
  1600. pio = pci_resource_start(ha->pdev, 0);
  1601. if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
  1602. if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
  1603. qla_printk(KERN_WARNING, ha,
  1604. "Invalid PCI I/O region size (%s)...\n",
  1605. pci_name(ha->pdev));
  1606. pio = 0;
  1607. }
  1608. } else {
  1609. qla_printk(KERN_WARNING, ha,
  1610. "region #0 not a PIO resource (%s)...\n",
  1611. pci_name(ha->pdev));
  1612. pio = 0;
  1613. }
  1614. ha->pio_address = pio;
  1615. skip_pio:
  1616. /* Use MMIO operations for all accesses. */
  1617. if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
  1618. qla_printk(KERN_ERR, ha,
  1619. "region #1 not an MMIO resource (%s), aborting\n",
  1620. pci_name(ha->pdev));
  1621. goto iospace_error_exit;
  1622. }
  1623. if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
  1624. qla_printk(KERN_ERR, ha,
  1625. "Invalid PCI mem region size (%s), aborting\n",
  1626. pci_name(ha->pdev));
  1627. goto iospace_error_exit;
  1628. }
  1629. ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
  1630. if (!ha->iobase) {
  1631. qla_printk(KERN_ERR, ha,
  1632. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  1633. goto iospace_error_exit;
  1634. }
  1635. /* Determine queue resources */
  1636. ha->max_req_queues = ha->max_rsp_queues = 1;
  1637. if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
  1638. (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
  1639. (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
  1640. goto mqiobase_exit;
  1641. ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
  1642. pci_resource_len(ha->pdev, 3));
  1643. if (ha->mqiobase) {
  1644. /* Read MSIX vector size of the board */
  1645. pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
  1646. ha->msix_count = msix;
  1647. /* Max queues are bounded by available msix vectors */
  1648. /* queue 0 uses two msix vectors */
  1649. if (ql2xmultique_tag) {
  1650. cpus = num_online_cpus();
  1651. ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
  1652. (cpus + 1) : (ha->msix_count - 1);
  1653. ha->max_req_queues = 2;
  1654. } else if (ql2xmaxqueues > 1) {
  1655. ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
  1656. QLA_MQ_SIZE : ql2xmaxqueues;
  1657. DEBUG2(qla_printk(KERN_INFO, ha, "QoS mode set, max no"
  1658. " of request queues:%d\n", ha->max_req_queues));
  1659. }
  1660. qla_printk(KERN_INFO, ha,
  1661. "MSI-X vector count: %d\n", msix);
  1662. } else
  1663. qla_printk(KERN_INFO, ha, "BAR 3 not enabled\n");
  1664. mqiobase_exit:
  1665. ha->msix_count = ha->max_rsp_queues + 1;
  1666. return (0);
  1667. iospace_error_exit:
  1668. return (-ENOMEM);
  1669. }
  1670. static void
  1671. qla2xxx_scan_start(struct Scsi_Host *shost)
  1672. {
  1673. scsi_qla_host_t *vha = shost_priv(shost);
  1674. if (vha->hw->flags.running_gold_fw)
  1675. return;
  1676. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1677. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  1678. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  1679. set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
  1680. }
  1681. static int
  1682. qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
  1683. {
  1684. scsi_qla_host_t *vha = shost_priv(shost);
  1685. if (!vha->host)
  1686. return 1;
  1687. if (time > vha->hw->loop_reset_delay * HZ)
  1688. return 1;
  1689. return atomic_read(&vha->loop_state) == LOOP_READY;
  1690. }
  1691. /*
  1692. * PCI driver interface
  1693. */
  1694. static int __devinit
  1695. qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
  1696. {
  1697. int ret = -ENODEV;
  1698. struct Scsi_Host *host;
  1699. scsi_qla_host_t *base_vha = NULL;
  1700. struct qla_hw_data *ha;
  1701. char pci_info[30];
  1702. char fw_str[30];
  1703. struct scsi_host_template *sht;
  1704. int bars, max_id, mem_only = 0;
  1705. uint16_t req_length = 0, rsp_length = 0;
  1706. struct req_que *req = NULL;
  1707. struct rsp_que *rsp = NULL;
  1708. bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
  1709. sht = &qla2xxx_driver_template;
  1710. if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
  1711. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
  1712. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
  1713. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
  1714. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
  1715. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
  1716. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
  1717. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021) {
  1718. bars = pci_select_bars(pdev, IORESOURCE_MEM);
  1719. mem_only = 1;
  1720. }
  1721. if (mem_only) {
  1722. if (pci_enable_device_mem(pdev))
  1723. goto probe_out;
  1724. } else {
  1725. if (pci_enable_device(pdev))
  1726. goto probe_out;
  1727. }
  1728. /* This may fail but that's ok */
  1729. pci_enable_pcie_error_reporting(pdev);
  1730. ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
  1731. if (!ha) {
  1732. DEBUG(printk("Unable to allocate memory for ha\n"));
  1733. goto probe_out;
  1734. }
  1735. ha->pdev = pdev;
  1736. /* Clear our data area */
  1737. ha->bars = bars;
  1738. ha->mem_only = mem_only;
  1739. spin_lock_init(&ha->hardware_lock);
  1740. /* Set ISP-type information. */
  1741. qla2x00_set_isp_flags(ha);
  1742. /* Set EEH reset type to fundamental if required by hba */
  1743. if ( IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) {
  1744. pdev->needs_freset = 1;
  1745. }
  1746. /* Configure PCI I/O space */
  1747. ret = qla2x00_iospace_config(ha);
  1748. if (ret)
  1749. goto probe_hw_failed;
  1750. qla_printk(KERN_INFO, ha,
  1751. "Found an ISP%04X, irq %d, iobase 0x%p\n", pdev->device, pdev->irq,
  1752. ha->iobase);
  1753. ha->prev_topology = 0;
  1754. ha->init_cb_size = sizeof(init_cb_t);
  1755. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  1756. ha->optrom_size = OPTROM_SIZE_2300;
  1757. /* Assign ISP specific operations. */
  1758. max_id = MAX_TARGETS_2200;
  1759. if (IS_QLA2100(ha)) {
  1760. max_id = MAX_TARGETS_2100;
  1761. ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
  1762. req_length = REQUEST_ENTRY_CNT_2100;
  1763. rsp_length = RESPONSE_ENTRY_CNT_2100;
  1764. ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
  1765. ha->gid_list_info_size = 4;
  1766. ha->flash_conf_off = ~0;
  1767. ha->flash_data_off = ~0;
  1768. ha->nvram_conf_off = ~0;
  1769. ha->nvram_data_off = ~0;
  1770. ha->isp_ops = &qla2100_isp_ops;
  1771. } else if (IS_QLA2200(ha)) {
  1772. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1773. req_length = REQUEST_ENTRY_CNT_2200;
  1774. rsp_length = RESPONSE_ENTRY_CNT_2100;
  1775. ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
  1776. ha->gid_list_info_size = 4;
  1777. ha->flash_conf_off = ~0;
  1778. ha->flash_data_off = ~0;
  1779. ha->nvram_conf_off = ~0;
  1780. ha->nvram_data_off = ~0;
  1781. ha->isp_ops = &qla2100_isp_ops;
  1782. } else if (IS_QLA23XX(ha)) {
  1783. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1784. req_length = REQUEST_ENTRY_CNT_2200;
  1785. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1786. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1787. ha->gid_list_info_size = 6;
  1788. if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1789. ha->optrom_size = OPTROM_SIZE_2322;
  1790. ha->flash_conf_off = ~0;
  1791. ha->flash_data_off = ~0;
  1792. ha->nvram_conf_off = ~0;
  1793. ha->nvram_data_off = ~0;
  1794. ha->isp_ops = &qla2300_isp_ops;
  1795. } else if (IS_QLA24XX_TYPE(ha)) {
  1796. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1797. req_length = REQUEST_ENTRY_CNT_24XX;
  1798. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1799. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1800. ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
  1801. ha->gid_list_info_size = 8;
  1802. ha->optrom_size = OPTROM_SIZE_24XX;
  1803. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
  1804. ha->isp_ops = &qla24xx_isp_ops;
  1805. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1806. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1807. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1808. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1809. } else if (IS_QLA25XX(ha)) {
  1810. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1811. req_length = REQUEST_ENTRY_CNT_24XX;
  1812. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1813. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1814. ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
  1815. ha->gid_list_info_size = 8;
  1816. ha->optrom_size = OPTROM_SIZE_25XX;
  1817. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  1818. ha->isp_ops = &qla25xx_isp_ops;
  1819. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1820. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1821. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1822. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1823. } else if (IS_QLA81XX(ha)) {
  1824. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1825. req_length = REQUEST_ENTRY_CNT_24XX;
  1826. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1827. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1828. ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
  1829. ha->gid_list_info_size = 8;
  1830. ha->optrom_size = OPTROM_SIZE_81XX;
  1831. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  1832. ha->isp_ops = &qla81xx_isp_ops;
  1833. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
  1834. ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
  1835. ha->nvram_conf_off = ~0;
  1836. ha->nvram_data_off = ~0;
  1837. } else if (IS_QLA82XX(ha)) {
  1838. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1839. req_length = REQUEST_ENTRY_CNT_82XX;
  1840. rsp_length = RESPONSE_ENTRY_CNT_82XX;
  1841. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1842. ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
  1843. ha->gid_list_info_size = 8;
  1844. ha->optrom_size = OPTROM_SIZE_82XX;
  1845. ha->isp_ops = &qla82xx_isp_ops;
  1846. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1847. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1848. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1849. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1850. }
  1851. mutex_init(&ha->vport_lock);
  1852. init_completion(&ha->mbx_cmd_comp);
  1853. complete(&ha->mbx_cmd_comp);
  1854. init_completion(&ha->mbx_intr_comp);
  1855. init_completion(&ha->dcbx_comp);
  1856. set_bit(0, (unsigned long *) ha->vp_idx_map);
  1857. qla2x00_config_dma_addressing(ha);
  1858. ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
  1859. if (!ret) {
  1860. qla_printk(KERN_WARNING, ha,
  1861. "[ERROR] Failed to allocate memory for adapter\n");
  1862. goto probe_hw_failed;
  1863. }
  1864. req->max_q_depth = MAX_Q_DEPTH;
  1865. if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
  1866. req->max_q_depth = ql2xmaxqdepth;
  1867. base_vha = qla2x00_create_host(sht, ha);
  1868. if (!base_vha) {
  1869. qla_printk(KERN_WARNING, ha,
  1870. "[ERROR] Failed to allocate memory for scsi_host\n");
  1871. ret = -ENOMEM;
  1872. qla2x00_mem_free(ha);
  1873. qla2x00_free_req_que(ha, req);
  1874. qla2x00_free_rsp_que(ha, rsp);
  1875. goto probe_hw_failed;
  1876. }
  1877. pci_set_drvdata(pdev, base_vha);
  1878. host = base_vha->host;
  1879. base_vha->req = req;
  1880. host->can_queue = req->length + 128;
  1881. if (IS_QLA2XXX_MIDTYPE(ha))
  1882. base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
  1883. else
  1884. base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
  1885. base_vha->vp_idx;
  1886. /* Set the SG table size based on ISP type */
  1887. if (!IS_FWI2_CAPABLE(ha)) {
  1888. if (IS_QLA2100(ha))
  1889. host->sg_tablesize = 32;
  1890. } else {
  1891. if (!IS_QLA82XX(ha))
  1892. host->sg_tablesize = QLA_SG_ALL;
  1893. }
  1894. host->max_id = max_id;
  1895. host->this_id = 255;
  1896. host->cmd_per_lun = 3;
  1897. host->unique_id = host->host_no;
  1898. if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && ql2xenabledif)
  1899. host->max_cmd_len = 32;
  1900. else
  1901. host->max_cmd_len = MAX_CMDSZ;
  1902. host->max_channel = MAX_BUSES - 1;
  1903. host->max_lun = MAX_LUNS;
  1904. host->transportt = qla2xxx_transport_template;
  1905. sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
  1906. /* Set up the irqs */
  1907. ret = qla2x00_request_irqs(ha, rsp);
  1908. if (ret)
  1909. goto probe_init_failed;
  1910. pci_save_state(pdev);
  1911. /* Alloc arrays of request and response ring ptrs */
  1912. que_init:
  1913. if (!qla2x00_alloc_queues(ha)) {
  1914. qla_printk(KERN_WARNING, ha,
  1915. "[ERROR] Failed to allocate memory for queue"
  1916. " pointers\n");
  1917. goto probe_init_failed;
  1918. }
  1919. ha->rsp_q_map[0] = rsp;
  1920. ha->req_q_map[0] = req;
  1921. rsp->req = req;
  1922. req->rsp = rsp;
  1923. set_bit(0, ha->req_qid_map);
  1924. set_bit(0, ha->rsp_qid_map);
  1925. /* FWI2-capable only. */
  1926. req->req_q_in = &ha->iobase->isp24.req_q_in;
  1927. req->req_q_out = &ha->iobase->isp24.req_q_out;
  1928. rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
  1929. rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
  1930. if (ha->mqenable) {
  1931. req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
  1932. req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
  1933. rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
  1934. rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
  1935. }
  1936. if (IS_QLA82XX(ha)) {
  1937. req->req_q_out = &ha->iobase->isp82.req_q_out[0];
  1938. rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
  1939. rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
  1940. }
  1941. if (qla2x00_initialize_adapter(base_vha)) {
  1942. qla_printk(KERN_WARNING, ha,
  1943. "Failed to initialize adapter\n");
  1944. DEBUG2(printk("scsi(%ld): Failed to initialize adapter - "
  1945. "Adapter flags %x.\n",
  1946. base_vha->host_no, base_vha->device_flags));
  1947. if (IS_QLA82XX(ha)) {
  1948. qla82xx_idc_lock(ha);
  1949. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  1950. QLA82XX_DEV_FAILED);
  1951. qla82xx_idc_unlock(ha);
  1952. qla_printk(KERN_INFO, ha, "HW State: FAILED\n");
  1953. }
  1954. ret = -ENODEV;
  1955. goto probe_failed;
  1956. }
  1957. if (ha->mqenable) {
  1958. if (qla25xx_setup_mode(base_vha)) {
  1959. qla_printk(KERN_WARNING, ha,
  1960. "Can't create queues, falling back to single"
  1961. " queue mode\n");
  1962. goto que_init;
  1963. }
  1964. }
  1965. if (ha->flags.running_gold_fw)
  1966. goto skip_dpc;
  1967. /*
  1968. * Startup the kernel thread for this host adapter
  1969. */
  1970. ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
  1971. "%s_dpc", base_vha->host_str);
  1972. if (IS_ERR(ha->dpc_thread)) {
  1973. qla_printk(KERN_WARNING, ha,
  1974. "Unable to start DPC thread!\n");
  1975. ret = PTR_ERR(ha->dpc_thread);
  1976. goto probe_failed;
  1977. }
  1978. skip_dpc:
  1979. list_add_tail(&base_vha->list, &ha->vp_list);
  1980. base_vha->host->irq = ha->pdev->irq;
  1981. /* Initialized the timer */
  1982. qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
  1983. DEBUG2(printk("DEBUG: detect hba %ld at address = %p\n",
  1984. base_vha->host_no, ha));
  1985. if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && ql2xenabledif) {
  1986. if (ha->fw_attributes & BIT_4) {
  1987. base_vha->flags.difdix_supported = 1;
  1988. DEBUG18(qla_printk(KERN_INFO, ha,
  1989. "Registering for DIF/DIX type 1 and 3"
  1990. " protection.\n"));
  1991. scsi_host_set_prot(host,
  1992. SHOST_DIF_TYPE1_PROTECTION
  1993. | SHOST_DIF_TYPE2_PROTECTION
  1994. | SHOST_DIF_TYPE3_PROTECTION
  1995. | SHOST_DIX_TYPE1_PROTECTION
  1996. | SHOST_DIX_TYPE2_PROTECTION
  1997. | SHOST_DIX_TYPE3_PROTECTION);
  1998. scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC);
  1999. } else
  2000. base_vha->flags.difdix_supported = 0;
  2001. }
  2002. ha->isp_ops->enable_intrs(ha);
  2003. ret = scsi_add_host(host, &pdev->dev);
  2004. if (ret)
  2005. goto probe_failed;
  2006. base_vha->flags.init_done = 1;
  2007. base_vha->flags.online = 1;
  2008. scsi_scan_host(host);
  2009. qla2x00_alloc_sysfs_attr(base_vha);
  2010. qla2x00_init_host_attr(base_vha);
  2011. qla2x00_dfs_setup(base_vha);
  2012. qla_printk(KERN_INFO, ha, "\n"
  2013. " QLogic Fibre Channel HBA Driver: %s\n"
  2014. " QLogic %s - %s\n"
  2015. " ISP%04X: %s @ %s hdma%c, host#=%ld, fw=%s\n",
  2016. qla2x00_version_str, ha->model_number,
  2017. ha->model_desc ? ha->model_desc : "", pdev->device,
  2018. ha->isp_ops->pci_info_str(base_vha, pci_info), pci_name(pdev),
  2019. ha->flags.enable_64bit_addressing ? '+' : '-', base_vha->host_no,
  2020. ha->isp_ops->fw_version_str(base_vha, fw_str));
  2021. return 0;
  2022. probe_init_failed:
  2023. qla2x00_free_req_que(ha, req);
  2024. qla2x00_free_rsp_que(ha, rsp);
  2025. ha->max_req_queues = ha->max_rsp_queues = 0;
  2026. probe_failed:
  2027. if (base_vha->timer_active)
  2028. qla2x00_stop_timer(base_vha);
  2029. base_vha->flags.online = 0;
  2030. if (ha->dpc_thread) {
  2031. struct task_struct *t = ha->dpc_thread;
  2032. ha->dpc_thread = NULL;
  2033. kthread_stop(t);
  2034. }
  2035. qla2x00_free_device(base_vha);
  2036. scsi_host_put(base_vha->host);
  2037. probe_hw_failed:
  2038. if (IS_QLA82XX(ha)) {
  2039. qla82xx_idc_lock(ha);
  2040. qla82xx_clear_drv_active(ha);
  2041. qla82xx_idc_unlock(ha);
  2042. iounmap((device_reg_t __iomem *)ha->nx_pcibase);
  2043. if (!ql2xdbwr)
  2044. iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
  2045. } else {
  2046. if (ha->iobase)
  2047. iounmap(ha->iobase);
  2048. }
  2049. pci_release_selected_regions(ha->pdev, ha->bars);
  2050. kfree(ha);
  2051. ha = NULL;
  2052. probe_out:
  2053. pci_disable_device(pdev);
  2054. return ret;
  2055. }
  2056. static void
  2057. qla2x00_remove_one(struct pci_dev *pdev)
  2058. {
  2059. scsi_qla_host_t *base_vha, *vha;
  2060. struct qla_hw_data *ha;
  2061. unsigned long flags;
  2062. base_vha = pci_get_drvdata(pdev);
  2063. ha = base_vha->hw;
  2064. spin_lock_irqsave(&ha->vport_slock, flags);
  2065. list_for_each_entry(vha, &ha->vp_list, list) {
  2066. atomic_inc(&vha->vref_count);
  2067. if (vha && vha->fc_vport) {
  2068. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2069. fc_vport_terminate(vha->fc_vport);
  2070. spin_lock_irqsave(&ha->vport_slock, flags);
  2071. }
  2072. atomic_dec(&vha->vref_count);
  2073. }
  2074. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2075. set_bit(UNLOADING, &base_vha->dpc_flags);
  2076. qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
  2077. qla2x00_dfs_remove(base_vha);
  2078. qla84xx_put_chip(base_vha);
  2079. /* Disable timer */
  2080. if (base_vha->timer_active)
  2081. qla2x00_stop_timer(base_vha);
  2082. base_vha->flags.online = 0;
  2083. /* Flush the work queue and remove it */
  2084. if (ha->wq) {
  2085. flush_workqueue(ha->wq);
  2086. destroy_workqueue(ha->wq);
  2087. ha->wq = NULL;
  2088. }
  2089. /* Kill the kernel thread for this host */
  2090. if (ha->dpc_thread) {
  2091. struct task_struct *t = ha->dpc_thread;
  2092. /*
  2093. * qla2xxx_wake_dpc checks for ->dpc_thread
  2094. * so we need to zero it out.
  2095. */
  2096. ha->dpc_thread = NULL;
  2097. kthread_stop(t);
  2098. }
  2099. qla2x00_free_sysfs_attr(base_vha);
  2100. fc_remove_host(base_vha->host);
  2101. scsi_remove_host(base_vha->host);
  2102. qla2x00_free_device(base_vha);
  2103. scsi_host_put(base_vha->host);
  2104. if (IS_QLA82XX(ha)) {
  2105. qla82xx_idc_lock(ha);
  2106. qla82xx_clear_drv_active(ha);
  2107. qla82xx_idc_unlock(ha);
  2108. iounmap((device_reg_t __iomem *)ha->nx_pcibase);
  2109. if (!ql2xdbwr)
  2110. iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
  2111. } else {
  2112. if (ha->iobase)
  2113. iounmap(ha->iobase);
  2114. if (ha->mqiobase)
  2115. iounmap(ha->mqiobase);
  2116. }
  2117. pci_release_selected_regions(ha->pdev, ha->bars);
  2118. kfree(ha);
  2119. ha = NULL;
  2120. pci_disable_pcie_error_reporting(pdev);
  2121. pci_disable_device(pdev);
  2122. pci_set_drvdata(pdev, NULL);
  2123. }
  2124. static void
  2125. qla2x00_free_device(scsi_qla_host_t *vha)
  2126. {
  2127. struct qla_hw_data *ha = vha->hw;
  2128. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  2129. /* Disable timer */
  2130. if (vha->timer_active)
  2131. qla2x00_stop_timer(vha);
  2132. /* Kill the kernel thread for this host */
  2133. if (ha->dpc_thread) {
  2134. struct task_struct *t = ha->dpc_thread;
  2135. /*
  2136. * qla2xxx_wake_dpc checks for ->dpc_thread
  2137. * so we need to zero it out.
  2138. */
  2139. ha->dpc_thread = NULL;
  2140. kthread_stop(t);
  2141. }
  2142. qla25xx_delete_queues(vha);
  2143. if (ha->flags.fce_enabled)
  2144. qla2x00_disable_fce_trace(vha, NULL, NULL);
  2145. if (ha->eft)
  2146. qla2x00_disable_eft_trace(vha);
  2147. /* Stop currently executing firmware. */
  2148. qla2x00_try_to_stop_firmware(vha);
  2149. vha->flags.online = 0;
  2150. /* turn-off interrupts on the card */
  2151. if (ha->interrupts_on) {
  2152. vha->flags.init_done = 0;
  2153. ha->isp_ops->disable_intrs(ha);
  2154. }
  2155. qla2x00_free_irqs(vha);
  2156. qla2x00_free_fcports(vha);
  2157. qla2x00_mem_free(ha);
  2158. qla2x00_free_queues(ha);
  2159. }
  2160. void qla2x00_free_fcports(struct scsi_qla_host *vha)
  2161. {
  2162. fc_port_t *fcport, *tfcport;
  2163. list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
  2164. list_del(&fcport->list);
  2165. kfree(fcport);
  2166. fcport = NULL;
  2167. }
  2168. }
  2169. static inline void
  2170. qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
  2171. int defer)
  2172. {
  2173. struct fc_rport *rport;
  2174. scsi_qla_host_t *base_vha;
  2175. if (!fcport->rport)
  2176. return;
  2177. rport = fcport->rport;
  2178. if (defer) {
  2179. base_vha = pci_get_drvdata(vha->hw->pdev);
  2180. spin_lock_irq(vha->host->host_lock);
  2181. fcport->drport = rport;
  2182. spin_unlock_irq(vha->host->host_lock);
  2183. set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
  2184. qla2xxx_wake_dpc(base_vha);
  2185. } else
  2186. fc_remote_port_delete(rport);
  2187. }
  2188. /*
  2189. * qla2x00_mark_device_lost Updates fcport state when device goes offline.
  2190. *
  2191. * Input: ha = adapter block pointer. fcport = port structure pointer.
  2192. *
  2193. * Return: None.
  2194. *
  2195. * Context:
  2196. */
  2197. void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
  2198. int do_login, int defer)
  2199. {
  2200. if (atomic_read(&fcport->state) == FCS_ONLINE &&
  2201. vha->vp_idx == fcport->vp_idx) {
  2202. atomic_set(&fcport->state, FCS_DEVICE_LOST);
  2203. qla2x00_schedule_rport_del(vha, fcport, defer);
  2204. }
  2205. /*
  2206. * We may need to retry the login, so don't change the state of the
  2207. * port but do the retries.
  2208. */
  2209. if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
  2210. atomic_set(&fcport->state, FCS_DEVICE_LOST);
  2211. if (!do_login)
  2212. return;
  2213. if (fcport->login_retry == 0) {
  2214. fcport->login_retry = vha->hw->login_retry_count;
  2215. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  2216. DEBUG(printk("scsi(%ld): Port login retry: "
  2217. "%02x%02x%02x%02x%02x%02x%02x%02x, "
  2218. "id = 0x%04x retry cnt=%d\n",
  2219. vha->host_no,
  2220. fcport->port_name[0],
  2221. fcport->port_name[1],
  2222. fcport->port_name[2],
  2223. fcport->port_name[3],
  2224. fcport->port_name[4],
  2225. fcport->port_name[5],
  2226. fcport->port_name[6],
  2227. fcport->port_name[7],
  2228. fcport->loop_id,
  2229. fcport->login_retry));
  2230. }
  2231. }
  2232. /*
  2233. * qla2x00_mark_all_devices_lost
  2234. * Updates fcport state when device goes offline.
  2235. *
  2236. * Input:
  2237. * ha = adapter block pointer.
  2238. * fcport = port structure pointer.
  2239. *
  2240. * Return:
  2241. * None.
  2242. *
  2243. * Context:
  2244. */
  2245. void
  2246. qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
  2247. {
  2248. fc_port_t *fcport;
  2249. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2250. if (vha->vp_idx != 0 && vha->vp_idx != fcport->vp_idx)
  2251. continue;
  2252. /*
  2253. * No point in marking the device as lost, if the device is
  2254. * already DEAD.
  2255. */
  2256. if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
  2257. continue;
  2258. if (atomic_read(&fcport->state) == FCS_ONLINE) {
  2259. if (defer)
  2260. qla2x00_schedule_rport_del(vha, fcport, defer);
  2261. else if (vha->vp_idx == fcport->vp_idx)
  2262. qla2x00_schedule_rport_del(vha, fcport, defer);
  2263. }
  2264. atomic_set(&fcport->state, FCS_DEVICE_LOST);
  2265. }
  2266. }
  2267. /*
  2268. * qla2x00_mem_alloc
  2269. * Allocates adapter memory.
  2270. *
  2271. * Returns:
  2272. * 0 = success.
  2273. * !0 = failure.
  2274. */
  2275. static int
  2276. qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
  2277. struct req_que **req, struct rsp_que **rsp)
  2278. {
  2279. char name[16];
  2280. ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
  2281. &ha->init_cb_dma, GFP_KERNEL);
  2282. if (!ha->init_cb)
  2283. goto fail;
  2284. ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, GID_LIST_SIZE,
  2285. &ha->gid_list_dma, GFP_KERNEL);
  2286. if (!ha->gid_list)
  2287. goto fail_free_init_cb;
  2288. ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
  2289. if (!ha->srb_mempool)
  2290. goto fail_free_gid_list;
  2291. if (IS_QLA82XX(ha)) {
  2292. /* Allocate cache for CT6 Ctx. */
  2293. if (!ctx_cachep) {
  2294. ctx_cachep = kmem_cache_create("qla2xxx_ctx",
  2295. sizeof(struct ct6_dsd), 0,
  2296. SLAB_HWCACHE_ALIGN, NULL);
  2297. if (!ctx_cachep)
  2298. goto fail_free_gid_list;
  2299. }
  2300. ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
  2301. ctx_cachep);
  2302. if (!ha->ctx_mempool)
  2303. goto fail_free_srb_mempool;
  2304. }
  2305. /* Get memory for cached NVRAM */
  2306. ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
  2307. if (!ha->nvram)
  2308. goto fail_free_ctx_mempool;
  2309. snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
  2310. ha->pdev->device);
  2311. ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2312. DMA_POOL_SIZE, 8, 0);
  2313. if (!ha->s_dma_pool)
  2314. goto fail_free_nvram;
  2315. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2316. ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2317. DSD_LIST_DMA_POOL_SIZE, 8, 0);
  2318. if (!ha->dl_dma_pool) {
  2319. qla_printk(KERN_WARNING, ha,
  2320. "Memory Allocation failed - dl_dma_pool\n");
  2321. goto fail_s_dma_pool;
  2322. }
  2323. ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2324. FCP_CMND_DMA_POOL_SIZE, 8, 0);
  2325. if (!ha->fcp_cmnd_dma_pool) {
  2326. qla_printk(KERN_WARNING, ha,
  2327. "Memory Allocation failed - fcp_cmnd_dma_pool\n");
  2328. goto fail_dl_dma_pool;
  2329. }
  2330. }
  2331. /* Allocate memory for SNS commands */
  2332. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  2333. /* Get consistent memory allocated for SNS commands */
  2334. ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
  2335. sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
  2336. if (!ha->sns_cmd)
  2337. goto fail_dma_pool;
  2338. } else {
  2339. /* Get consistent memory allocated for MS IOCB */
  2340. ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2341. &ha->ms_iocb_dma);
  2342. if (!ha->ms_iocb)
  2343. goto fail_dma_pool;
  2344. /* Get consistent memory allocated for CT SNS commands */
  2345. ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
  2346. sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
  2347. if (!ha->ct_sns)
  2348. goto fail_free_ms_iocb;
  2349. }
  2350. /* Allocate memory for request ring */
  2351. *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
  2352. if (!*req) {
  2353. DEBUG(printk("Unable to allocate memory for req\n"));
  2354. goto fail_req;
  2355. }
  2356. (*req)->length = req_len;
  2357. (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
  2358. ((*req)->length + 1) * sizeof(request_t),
  2359. &(*req)->dma, GFP_KERNEL);
  2360. if (!(*req)->ring) {
  2361. DEBUG(printk("Unable to allocate memory for req_ring\n"));
  2362. goto fail_req_ring;
  2363. }
  2364. /* Allocate memory for response ring */
  2365. *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
  2366. if (!*rsp) {
  2367. qla_printk(KERN_WARNING, ha,
  2368. "Unable to allocate memory for rsp\n");
  2369. goto fail_rsp;
  2370. }
  2371. (*rsp)->hw = ha;
  2372. (*rsp)->length = rsp_len;
  2373. (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
  2374. ((*rsp)->length + 1) * sizeof(response_t),
  2375. &(*rsp)->dma, GFP_KERNEL);
  2376. if (!(*rsp)->ring) {
  2377. qla_printk(KERN_WARNING, ha,
  2378. "Unable to allocate memory for rsp_ring\n");
  2379. goto fail_rsp_ring;
  2380. }
  2381. (*req)->rsp = *rsp;
  2382. (*rsp)->req = *req;
  2383. /* Allocate memory for NVRAM data for vports */
  2384. if (ha->nvram_npiv_size) {
  2385. ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
  2386. ha->nvram_npiv_size, GFP_KERNEL);
  2387. if (!ha->npiv_info) {
  2388. qla_printk(KERN_WARNING, ha,
  2389. "Unable to allocate memory for npiv info\n");
  2390. goto fail_npiv_info;
  2391. }
  2392. } else
  2393. ha->npiv_info = NULL;
  2394. /* Get consistent memory allocated for EX-INIT-CB. */
  2395. if (IS_QLA8XXX_TYPE(ha)) {
  2396. ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2397. &ha->ex_init_cb_dma);
  2398. if (!ha->ex_init_cb)
  2399. goto fail_ex_init_cb;
  2400. }
  2401. INIT_LIST_HEAD(&ha->gbl_dsd_list);
  2402. /* Get consistent memory allocated for Async Port-Database. */
  2403. if (!IS_FWI2_CAPABLE(ha)) {
  2404. ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2405. &ha->async_pd_dma);
  2406. if (!ha->async_pd)
  2407. goto fail_async_pd;
  2408. }
  2409. INIT_LIST_HEAD(&ha->vp_list);
  2410. return 1;
  2411. fail_async_pd:
  2412. dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
  2413. fail_ex_init_cb:
  2414. kfree(ha->npiv_info);
  2415. fail_npiv_info:
  2416. dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
  2417. sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
  2418. (*rsp)->ring = NULL;
  2419. (*rsp)->dma = 0;
  2420. fail_rsp_ring:
  2421. kfree(*rsp);
  2422. fail_rsp:
  2423. dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
  2424. sizeof(request_t), (*req)->ring, (*req)->dma);
  2425. (*req)->ring = NULL;
  2426. (*req)->dma = 0;
  2427. fail_req_ring:
  2428. kfree(*req);
  2429. fail_req:
  2430. dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
  2431. ha->ct_sns, ha->ct_sns_dma);
  2432. ha->ct_sns = NULL;
  2433. ha->ct_sns_dma = 0;
  2434. fail_free_ms_iocb:
  2435. dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
  2436. ha->ms_iocb = NULL;
  2437. ha->ms_iocb_dma = 0;
  2438. fail_dma_pool:
  2439. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2440. dma_pool_destroy(ha->fcp_cmnd_dma_pool);
  2441. ha->fcp_cmnd_dma_pool = NULL;
  2442. }
  2443. fail_dl_dma_pool:
  2444. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2445. dma_pool_destroy(ha->dl_dma_pool);
  2446. ha->dl_dma_pool = NULL;
  2447. }
  2448. fail_s_dma_pool:
  2449. dma_pool_destroy(ha->s_dma_pool);
  2450. ha->s_dma_pool = NULL;
  2451. fail_free_nvram:
  2452. kfree(ha->nvram);
  2453. ha->nvram = NULL;
  2454. fail_free_ctx_mempool:
  2455. mempool_destroy(ha->ctx_mempool);
  2456. ha->ctx_mempool = NULL;
  2457. fail_free_srb_mempool:
  2458. mempool_destroy(ha->srb_mempool);
  2459. ha->srb_mempool = NULL;
  2460. fail_free_gid_list:
  2461. dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
  2462. ha->gid_list_dma);
  2463. ha->gid_list = NULL;
  2464. ha->gid_list_dma = 0;
  2465. fail_free_init_cb:
  2466. dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
  2467. ha->init_cb_dma);
  2468. ha->init_cb = NULL;
  2469. ha->init_cb_dma = 0;
  2470. fail:
  2471. DEBUG(printk("%s: Memory allocation failure\n", __func__));
  2472. return -ENOMEM;
  2473. }
  2474. /*
  2475. * qla2x00_mem_free
  2476. * Frees all adapter allocated memory.
  2477. *
  2478. * Input:
  2479. * ha = adapter block pointer.
  2480. */
  2481. static void
  2482. qla2x00_mem_free(struct qla_hw_data *ha)
  2483. {
  2484. if (ha->srb_mempool)
  2485. mempool_destroy(ha->srb_mempool);
  2486. if (ha->fce)
  2487. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
  2488. ha->fce_dma);
  2489. if (ha->fw_dump) {
  2490. if (ha->eft)
  2491. dma_free_coherent(&ha->pdev->dev,
  2492. ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
  2493. vfree(ha->fw_dump);
  2494. }
  2495. if (ha->dcbx_tlv)
  2496. dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
  2497. ha->dcbx_tlv, ha->dcbx_tlv_dma);
  2498. if (ha->xgmac_data)
  2499. dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
  2500. ha->xgmac_data, ha->xgmac_data_dma);
  2501. if (ha->sns_cmd)
  2502. dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
  2503. ha->sns_cmd, ha->sns_cmd_dma);
  2504. if (ha->ct_sns)
  2505. dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
  2506. ha->ct_sns, ha->ct_sns_dma);
  2507. if (ha->sfp_data)
  2508. dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
  2509. if (ha->edc_data)
  2510. dma_pool_free(ha->s_dma_pool, ha->edc_data, ha->edc_data_dma);
  2511. if (ha->ms_iocb)
  2512. dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
  2513. if (ha->ex_init_cb)
  2514. dma_pool_free(ha->s_dma_pool,
  2515. ha->ex_init_cb, ha->ex_init_cb_dma);
  2516. if (ha->async_pd)
  2517. dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
  2518. if (ha->s_dma_pool)
  2519. dma_pool_destroy(ha->s_dma_pool);
  2520. if (ha->gid_list)
  2521. dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
  2522. ha->gid_list_dma);
  2523. if (IS_QLA82XX(ha)) {
  2524. if (!list_empty(&ha->gbl_dsd_list)) {
  2525. struct dsd_dma *dsd_ptr, *tdsd_ptr;
  2526. /* clean up allocated prev pool */
  2527. list_for_each_entry_safe(dsd_ptr,
  2528. tdsd_ptr, &ha->gbl_dsd_list, list) {
  2529. dma_pool_free(ha->dl_dma_pool,
  2530. dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
  2531. list_del(&dsd_ptr->list);
  2532. kfree(dsd_ptr);
  2533. }
  2534. }
  2535. }
  2536. if (ha->dl_dma_pool)
  2537. dma_pool_destroy(ha->dl_dma_pool);
  2538. if (ha->fcp_cmnd_dma_pool)
  2539. dma_pool_destroy(ha->fcp_cmnd_dma_pool);
  2540. if (ha->ctx_mempool)
  2541. mempool_destroy(ha->ctx_mempool);
  2542. if (ha->init_cb)
  2543. dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
  2544. ha->init_cb, ha->init_cb_dma);
  2545. vfree(ha->optrom_buffer);
  2546. kfree(ha->nvram);
  2547. kfree(ha->npiv_info);
  2548. ha->srb_mempool = NULL;
  2549. ha->ctx_mempool = NULL;
  2550. ha->eft = NULL;
  2551. ha->eft_dma = 0;
  2552. ha->sns_cmd = NULL;
  2553. ha->sns_cmd_dma = 0;
  2554. ha->ct_sns = NULL;
  2555. ha->ct_sns_dma = 0;
  2556. ha->ms_iocb = NULL;
  2557. ha->ms_iocb_dma = 0;
  2558. ha->init_cb = NULL;
  2559. ha->init_cb_dma = 0;
  2560. ha->ex_init_cb = NULL;
  2561. ha->ex_init_cb_dma = 0;
  2562. ha->async_pd = NULL;
  2563. ha->async_pd_dma = 0;
  2564. ha->s_dma_pool = NULL;
  2565. ha->dl_dma_pool = NULL;
  2566. ha->fcp_cmnd_dma_pool = NULL;
  2567. ha->gid_list = NULL;
  2568. ha->gid_list_dma = 0;
  2569. ha->fw_dump = NULL;
  2570. ha->fw_dumped = 0;
  2571. ha->fw_dump_reading = 0;
  2572. }
  2573. struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
  2574. struct qla_hw_data *ha)
  2575. {
  2576. struct Scsi_Host *host;
  2577. struct scsi_qla_host *vha = NULL;
  2578. host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
  2579. if (host == NULL) {
  2580. printk(KERN_WARNING
  2581. "qla2xxx: Couldn't allocate host from scsi layer!\n");
  2582. goto fail;
  2583. }
  2584. /* Clear our data area */
  2585. vha = shost_priv(host);
  2586. memset(vha, 0, sizeof(scsi_qla_host_t));
  2587. vha->host = host;
  2588. vha->host_no = host->host_no;
  2589. vha->hw = ha;
  2590. INIT_LIST_HEAD(&vha->vp_fcports);
  2591. INIT_LIST_HEAD(&vha->work_list);
  2592. INIT_LIST_HEAD(&vha->list);
  2593. spin_lock_init(&vha->work_lock);
  2594. sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
  2595. return vha;
  2596. fail:
  2597. return vha;
  2598. }
  2599. static struct qla_work_evt *
  2600. qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
  2601. {
  2602. struct qla_work_evt *e;
  2603. uint8_t bail;
  2604. QLA_VHA_MARK_BUSY(vha, bail);
  2605. if (bail)
  2606. return NULL;
  2607. e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
  2608. if (!e) {
  2609. QLA_VHA_MARK_NOT_BUSY(vha);
  2610. return NULL;
  2611. }
  2612. INIT_LIST_HEAD(&e->list);
  2613. e->type = type;
  2614. e->flags = QLA_EVT_FLAG_FREE;
  2615. return e;
  2616. }
  2617. static int
  2618. qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
  2619. {
  2620. unsigned long flags;
  2621. spin_lock_irqsave(&vha->work_lock, flags);
  2622. list_add_tail(&e->list, &vha->work_list);
  2623. spin_unlock_irqrestore(&vha->work_lock, flags);
  2624. qla2xxx_wake_dpc(vha);
  2625. return QLA_SUCCESS;
  2626. }
  2627. int
  2628. qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
  2629. u32 data)
  2630. {
  2631. struct qla_work_evt *e;
  2632. e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
  2633. if (!e)
  2634. return QLA_FUNCTION_FAILED;
  2635. e->u.aen.code = code;
  2636. e->u.aen.data = data;
  2637. return qla2x00_post_work(vha, e);
  2638. }
  2639. int
  2640. qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
  2641. {
  2642. struct qla_work_evt *e;
  2643. e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
  2644. if (!e)
  2645. return QLA_FUNCTION_FAILED;
  2646. memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
  2647. return qla2x00_post_work(vha, e);
  2648. }
  2649. #define qla2x00_post_async_work(name, type) \
  2650. int qla2x00_post_async_##name##_work( \
  2651. struct scsi_qla_host *vha, \
  2652. fc_port_t *fcport, uint16_t *data) \
  2653. { \
  2654. struct qla_work_evt *e; \
  2655. \
  2656. e = qla2x00_alloc_work(vha, type); \
  2657. if (!e) \
  2658. return QLA_FUNCTION_FAILED; \
  2659. \
  2660. e->u.logio.fcport = fcport; \
  2661. if (data) { \
  2662. e->u.logio.data[0] = data[0]; \
  2663. e->u.logio.data[1] = data[1]; \
  2664. } \
  2665. return qla2x00_post_work(vha, e); \
  2666. }
  2667. qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
  2668. qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
  2669. qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
  2670. qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
  2671. qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
  2672. qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
  2673. int
  2674. qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
  2675. {
  2676. struct qla_work_evt *e;
  2677. e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
  2678. if (!e)
  2679. return QLA_FUNCTION_FAILED;
  2680. e->u.uevent.code = code;
  2681. return qla2x00_post_work(vha, e);
  2682. }
  2683. static void
  2684. qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
  2685. {
  2686. char event_string[40];
  2687. char *envp[] = { event_string, NULL };
  2688. switch (code) {
  2689. case QLA_UEVENT_CODE_FW_DUMP:
  2690. snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
  2691. vha->host_no);
  2692. break;
  2693. default:
  2694. /* do nothing */
  2695. break;
  2696. }
  2697. kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
  2698. }
  2699. void
  2700. qla2x00_do_work(struct scsi_qla_host *vha)
  2701. {
  2702. struct qla_work_evt *e, *tmp;
  2703. unsigned long flags;
  2704. LIST_HEAD(work);
  2705. spin_lock_irqsave(&vha->work_lock, flags);
  2706. list_splice_init(&vha->work_list, &work);
  2707. spin_unlock_irqrestore(&vha->work_lock, flags);
  2708. list_for_each_entry_safe(e, tmp, &work, list) {
  2709. list_del_init(&e->list);
  2710. switch (e->type) {
  2711. case QLA_EVT_AEN:
  2712. fc_host_post_event(vha->host, fc_get_event_number(),
  2713. e->u.aen.code, e->u.aen.data);
  2714. break;
  2715. case QLA_EVT_IDC_ACK:
  2716. qla81xx_idc_ack(vha, e->u.idc_ack.mb);
  2717. break;
  2718. case QLA_EVT_ASYNC_LOGIN:
  2719. qla2x00_async_login(vha, e->u.logio.fcport,
  2720. e->u.logio.data);
  2721. break;
  2722. case QLA_EVT_ASYNC_LOGIN_DONE:
  2723. qla2x00_async_login_done(vha, e->u.logio.fcport,
  2724. e->u.logio.data);
  2725. break;
  2726. case QLA_EVT_ASYNC_LOGOUT:
  2727. qla2x00_async_logout(vha, e->u.logio.fcport);
  2728. break;
  2729. case QLA_EVT_ASYNC_LOGOUT_DONE:
  2730. qla2x00_async_logout_done(vha, e->u.logio.fcport,
  2731. e->u.logio.data);
  2732. break;
  2733. case QLA_EVT_ASYNC_ADISC:
  2734. qla2x00_async_adisc(vha, e->u.logio.fcport,
  2735. e->u.logio.data);
  2736. break;
  2737. case QLA_EVT_ASYNC_ADISC_DONE:
  2738. qla2x00_async_adisc_done(vha, e->u.logio.fcport,
  2739. e->u.logio.data);
  2740. break;
  2741. case QLA_EVT_UEVENT:
  2742. qla2x00_uevent_emit(vha, e->u.uevent.code);
  2743. break;
  2744. }
  2745. if (e->flags & QLA_EVT_FLAG_FREE)
  2746. kfree(e);
  2747. /* For each work completed decrement vha ref count */
  2748. QLA_VHA_MARK_NOT_BUSY(vha);
  2749. }
  2750. }
  2751. /* Relogins all the fcports of a vport
  2752. * Context: dpc thread
  2753. */
  2754. void qla2x00_relogin(struct scsi_qla_host *vha)
  2755. {
  2756. fc_port_t *fcport;
  2757. int status;
  2758. uint16_t next_loopid = 0;
  2759. struct qla_hw_data *ha = vha->hw;
  2760. uint16_t data[2];
  2761. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2762. /*
  2763. * If the port is not ONLINE then try to login
  2764. * to it if we haven't run out of retries.
  2765. */
  2766. if (atomic_read(&fcport->state) != FCS_ONLINE &&
  2767. fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
  2768. fcport->login_retry--;
  2769. if (fcport->flags & FCF_FABRIC_DEVICE) {
  2770. if (fcport->flags & FCF_FCP2_DEVICE)
  2771. ha->isp_ops->fabric_logout(vha,
  2772. fcport->loop_id,
  2773. fcport->d_id.b.domain,
  2774. fcport->d_id.b.area,
  2775. fcport->d_id.b.al_pa);
  2776. if (IS_ALOGIO_CAPABLE(ha)) {
  2777. fcport->flags |= FCF_ASYNC_SENT;
  2778. data[0] = 0;
  2779. data[1] = QLA_LOGIO_LOGIN_RETRIED;
  2780. status = qla2x00_post_async_login_work(
  2781. vha, fcport, data);
  2782. if (status == QLA_SUCCESS)
  2783. continue;
  2784. /* Attempt a retry. */
  2785. status = 1;
  2786. } else
  2787. status = qla2x00_fabric_login(vha,
  2788. fcport, &next_loopid);
  2789. } else
  2790. status = qla2x00_local_device_login(vha,
  2791. fcport);
  2792. if (status == QLA_SUCCESS) {
  2793. fcport->old_loop_id = fcport->loop_id;
  2794. DEBUG(printk("scsi(%ld): port login OK: logged "
  2795. "in ID 0x%x\n", vha->host_no, fcport->loop_id));
  2796. qla2x00_update_fcport(vha, fcport);
  2797. } else if (status == 1) {
  2798. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  2799. /* retry the login again */
  2800. DEBUG(printk("scsi(%ld): Retrying"
  2801. " %d login again loop_id 0x%x\n",
  2802. vha->host_no, fcport->login_retry,
  2803. fcport->loop_id));
  2804. } else {
  2805. fcport->login_retry = 0;
  2806. }
  2807. if (fcport->login_retry == 0 && status != QLA_SUCCESS)
  2808. fcport->loop_id = FC_NO_LOOP_ID;
  2809. }
  2810. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2811. break;
  2812. }
  2813. }
  2814. /**************************************************************************
  2815. * qla2x00_do_dpc
  2816. * This kernel thread is a task that is schedule by the interrupt handler
  2817. * to perform the background processing for interrupts.
  2818. *
  2819. * Notes:
  2820. * This task always run in the context of a kernel thread. It
  2821. * is kick-off by the driver's detect code and starts up
  2822. * up one per adapter. It immediately goes to sleep and waits for
  2823. * some fibre event. When either the interrupt handler or
  2824. * the timer routine detects a event it will one of the task
  2825. * bits then wake us up.
  2826. **************************************************************************/
  2827. static int
  2828. qla2x00_do_dpc(void *data)
  2829. {
  2830. int rval;
  2831. scsi_qla_host_t *base_vha;
  2832. struct qla_hw_data *ha;
  2833. ha = (struct qla_hw_data *)data;
  2834. base_vha = pci_get_drvdata(ha->pdev);
  2835. set_user_nice(current, -20);
  2836. while (!kthread_should_stop()) {
  2837. DEBUG3(printk("qla2x00: DPC handler sleeping\n"));
  2838. set_current_state(TASK_INTERRUPTIBLE);
  2839. schedule();
  2840. __set_current_state(TASK_RUNNING);
  2841. DEBUG3(printk("qla2x00: DPC handler waking up\n"));
  2842. /* Initialization not yet finished. Don't do anything yet. */
  2843. if (!base_vha->flags.init_done)
  2844. continue;
  2845. if (ha->flags.eeh_busy) {
  2846. DEBUG17(qla_printk(KERN_WARNING, ha,
  2847. "qla2x00_do_dpc: dpc_flags: %lx\n",
  2848. base_vha->dpc_flags));
  2849. continue;
  2850. }
  2851. DEBUG3(printk("scsi(%ld): DPC handler\n", base_vha->host_no));
  2852. ha->dpc_active = 1;
  2853. if (ha->flags.mbox_busy) {
  2854. ha->dpc_active = 0;
  2855. continue;
  2856. }
  2857. qla2x00_do_work(base_vha);
  2858. if (IS_QLA82XX(ha)) {
  2859. if (test_and_clear_bit(ISP_UNRECOVERABLE,
  2860. &base_vha->dpc_flags)) {
  2861. qla82xx_idc_lock(ha);
  2862. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  2863. QLA82XX_DEV_FAILED);
  2864. qla82xx_idc_unlock(ha);
  2865. qla_printk(KERN_INFO, ha,
  2866. "HW State: FAILED\n");
  2867. qla82xx_device_state_handler(base_vha);
  2868. continue;
  2869. }
  2870. if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
  2871. &base_vha->dpc_flags)) {
  2872. DEBUG(printk(KERN_INFO
  2873. "scsi(%ld): dpc: sched "
  2874. "qla82xx_fcoe_ctx_reset ha = %p\n",
  2875. base_vha->host_no, ha));
  2876. if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
  2877. &base_vha->dpc_flags))) {
  2878. if (qla82xx_fcoe_ctx_reset(base_vha)) {
  2879. /* FCoE-ctx reset failed.
  2880. * Escalate to chip-reset
  2881. */
  2882. set_bit(ISP_ABORT_NEEDED,
  2883. &base_vha->dpc_flags);
  2884. }
  2885. clear_bit(ABORT_ISP_ACTIVE,
  2886. &base_vha->dpc_flags);
  2887. }
  2888. DEBUG(printk("scsi(%ld): dpc:"
  2889. " qla82xx_fcoe_ctx_reset end\n",
  2890. base_vha->host_no));
  2891. }
  2892. }
  2893. if (test_and_clear_bit(ISP_ABORT_NEEDED,
  2894. &base_vha->dpc_flags)) {
  2895. DEBUG(printk("scsi(%ld): dpc: sched "
  2896. "qla2x00_abort_isp ha = %p\n",
  2897. base_vha->host_no, ha));
  2898. if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
  2899. &base_vha->dpc_flags))) {
  2900. if (ha->isp_ops->abort_isp(base_vha)) {
  2901. /* failed. retry later */
  2902. set_bit(ISP_ABORT_NEEDED,
  2903. &base_vha->dpc_flags);
  2904. }
  2905. clear_bit(ABORT_ISP_ACTIVE,
  2906. &base_vha->dpc_flags);
  2907. }
  2908. DEBUG(printk("scsi(%ld): dpc: qla2x00_abort_isp end\n",
  2909. base_vha->host_no));
  2910. }
  2911. if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) {
  2912. qla2x00_update_fcports(base_vha);
  2913. clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
  2914. }
  2915. if (test_and_clear_bit(RESET_MARKER_NEEDED,
  2916. &base_vha->dpc_flags) &&
  2917. (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
  2918. DEBUG(printk("scsi(%ld): qla2x00_reset_marker()\n",
  2919. base_vha->host_no));
  2920. qla2x00_rst_aen(base_vha);
  2921. clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
  2922. }
  2923. /* Retry each device up to login retry count */
  2924. if ((test_and_clear_bit(RELOGIN_NEEDED,
  2925. &base_vha->dpc_flags)) &&
  2926. !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
  2927. atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
  2928. DEBUG(printk("scsi(%ld): qla2x00_port_login()\n",
  2929. base_vha->host_no));
  2930. qla2x00_relogin(base_vha);
  2931. DEBUG(printk("scsi(%ld): qla2x00_port_login - end\n",
  2932. base_vha->host_no));
  2933. }
  2934. if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
  2935. &base_vha->dpc_flags)) {
  2936. DEBUG(printk("scsi(%ld): qla2x00_loop_resync()\n",
  2937. base_vha->host_no));
  2938. if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
  2939. &base_vha->dpc_flags))) {
  2940. rval = qla2x00_loop_resync(base_vha);
  2941. clear_bit(LOOP_RESYNC_ACTIVE,
  2942. &base_vha->dpc_flags);
  2943. }
  2944. DEBUG(printk("scsi(%ld): qla2x00_loop_resync - end\n",
  2945. base_vha->host_no));
  2946. }
  2947. if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
  2948. atomic_read(&base_vha->loop_state) == LOOP_READY) {
  2949. clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
  2950. qla2xxx_flash_npiv_conf(base_vha);
  2951. }
  2952. if (!ha->interrupts_on)
  2953. ha->isp_ops->enable_intrs(ha);
  2954. if (test_and_clear_bit(BEACON_BLINK_NEEDED,
  2955. &base_vha->dpc_flags))
  2956. ha->isp_ops->beacon_blink(base_vha);
  2957. qla2x00_do_dpc_all_vps(base_vha);
  2958. ha->dpc_active = 0;
  2959. } /* End of while(1) */
  2960. DEBUG(printk("scsi(%ld): DPC handler exiting\n", base_vha->host_no));
  2961. /*
  2962. * Make sure that nobody tries to wake us up again.
  2963. */
  2964. ha->dpc_active = 0;
  2965. /* Cleanup any residual CTX SRBs. */
  2966. qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
  2967. return 0;
  2968. }
  2969. void
  2970. qla2xxx_wake_dpc(struct scsi_qla_host *vha)
  2971. {
  2972. struct qla_hw_data *ha = vha->hw;
  2973. struct task_struct *t = ha->dpc_thread;
  2974. if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
  2975. wake_up_process(t);
  2976. }
  2977. /*
  2978. * qla2x00_rst_aen
  2979. * Processes asynchronous reset.
  2980. *
  2981. * Input:
  2982. * ha = adapter block pointer.
  2983. */
  2984. static void
  2985. qla2x00_rst_aen(scsi_qla_host_t *vha)
  2986. {
  2987. if (vha->flags.online && !vha->flags.reset_active &&
  2988. !atomic_read(&vha->loop_down_timer) &&
  2989. !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
  2990. do {
  2991. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  2992. /*
  2993. * Issue marker command only when we are going to start
  2994. * the I/O.
  2995. */
  2996. vha->marker_needed = 1;
  2997. } while (!atomic_read(&vha->loop_down_timer) &&
  2998. (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
  2999. }
  3000. }
  3001. static void
  3002. qla2x00_sp_free_dma(srb_t *sp)
  3003. {
  3004. struct scsi_cmnd *cmd = sp->cmd;
  3005. struct qla_hw_data *ha = sp->fcport->vha->hw;
  3006. if (sp->flags & SRB_DMA_VALID) {
  3007. scsi_dma_unmap(cmd);
  3008. sp->flags &= ~SRB_DMA_VALID;
  3009. }
  3010. if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
  3011. dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
  3012. scsi_prot_sg_count(cmd), cmd->sc_data_direction);
  3013. sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
  3014. }
  3015. if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
  3016. /* List assured to be having elements */
  3017. qla2x00_clean_dsd_pool(ha, sp);
  3018. sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
  3019. }
  3020. if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
  3021. dma_pool_free(ha->dl_dma_pool, sp->ctx,
  3022. ((struct crc_context *)sp->ctx)->crc_ctx_dma);
  3023. sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
  3024. }
  3025. CMD_SP(cmd) = NULL;
  3026. }
  3027. static void
  3028. qla2x00_sp_final_compl(struct qla_hw_data *ha, srb_t *sp)
  3029. {
  3030. struct scsi_cmnd *cmd = sp->cmd;
  3031. qla2x00_sp_free_dma(sp);
  3032. if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
  3033. struct ct6_dsd *ctx = sp->ctx;
  3034. dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd,
  3035. ctx->fcp_cmnd_dma);
  3036. list_splice(&ctx->dsd_list, &ha->gbl_dsd_list);
  3037. ha->gbl_dsd_inuse -= ctx->dsd_use_cnt;
  3038. ha->gbl_dsd_avail += ctx->dsd_use_cnt;
  3039. mempool_free(sp->ctx, ha->ctx_mempool);
  3040. sp->ctx = NULL;
  3041. }
  3042. mempool_free(sp, ha->srb_mempool);
  3043. cmd->scsi_done(cmd);
  3044. }
  3045. void
  3046. qla2x00_sp_compl(struct qla_hw_data *ha, srb_t *sp)
  3047. {
  3048. if (atomic_read(&sp->ref_count) == 0) {
  3049. DEBUG2(qla_printk(KERN_WARNING, ha,
  3050. "SP reference-count to ZERO -- sp=%p\n", sp));
  3051. DEBUG2(BUG());
  3052. return;
  3053. }
  3054. if (!atomic_dec_and_test(&sp->ref_count))
  3055. return;
  3056. qla2x00_sp_final_compl(ha, sp);
  3057. }
  3058. /**************************************************************************
  3059. * qla2x00_timer
  3060. *
  3061. * Description:
  3062. * One second timer
  3063. *
  3064. * Context: Interrupt
  3065. ***************************************************************************/
  3066. void
  3067. qla2x00_timer(scsi_qla_host_t *vha)
  3068. {
  3069. unsigned long cpu_flags = 0;
  3070. int start_dpc = 0;
  3071. int index;
  3072. srb_t *sp;
  3073. uint16_t w;
  3074. struct qla_hw_data *ha = vha->hw;
  3075. struct req_que *req;
  3076. if (ha->flags.eeh_busy) {
  3077. qla2x00_restart_timer(vha, WATCH_INTERVAL);
  3078. return;
  3079. }
  3080. if (IS_QLA82XX(ha))
  3081. qla82xx_watchdog(vha);
  3082. /* Hardware read to raise pending EEH errors during mailbox waits. */
  3083. if (!pci_channel_offline(ha->pdev))
  3084. pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
  3085. /* Loop down handler. */
  3086. if (atomic_read(&vha->loop_down_timer) > 0 &&
  3087. !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
  3088. && vha->flags.online) {
  3089. if (atomic_read(&vha->loop_down_timer) ==
  3090. vha->loop_down_abort_time) {
  3091. DEBUG(printk("scsi(%ld): Loop Down - aborting the "
  3092. "queues before time expire\n",
  3093. vha->host_no));
  3094. if (!IS_QLA2100(ha) && vha->link_down_timeout)
  3095. atomic_set(&vha->loop_state, LOOP_DEAD);
  3096. /*
  3097. * Schedule an ISP abort to return any FCP2-device
  3098. * commands.
  3099. */
  3100. /* NPIV - scan physical port only */
  3101. if (!vha->vp_idx) {
  3102. spin_lock_irqsave(&ha->hardware_lock,
  3103. cpu_flags);
  3104. req = ha->req_q_map[0];
  3105. for (index = 1;
  3106. index < MAX_OUTSTANDING_COMMANDS;
  3107. index++) {
  3108. fc_port_t *sfcp;
  3109. sp = req->outstanding_cmds[index];
  3110. if (!sp)
  3111. continue;
  3112. if (sp->ctx && !IS_PROT_IO(sp))
  3113. continue;
  3114. sfcp = sp->fcport;
  3115. if (!(sfcp->flags & FCF_FCP2_DEVICE))
  3116. continue;
  3117. set_bit(ISP_ABORT_NEEDED,
  3118. &vha->dpc_flags);
  3119. break;
  3120. }
  3121. spin_unlock_irqrestore(&ha->hardware_lock,
  3122. cpu_flags);
  3123. }
  3124. start_dpc++;
  3125. }
  3126. /* if the loop has been down for 4 minutes, reinit adapter */
  3127. if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
  3128. if (!(vha->device_flags & DFLG_NO_CABLE)) {
  3129. DEBUG(printk("scsi(%ld): Loop down - "
  3130. "aborting ISP.\n",
  3131. vha->host_no));
  3132. qla_printk(KERN_WARNING, ha,
  3133. "Loop down - aborting ISP.\n");
  3134. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  3135. }
  3136. }
  3137. DEBUG3(printk("scsi(%ld): Loop Down - seconds remaining %d\n",
  3138. vha->host_no,
  3139. atomic_read(&vha->loop_down_timer)));
  3140. }
  3141. /* Check if beacon LED needs to be blinked */
  3142. if (ha->beacon_blink_led == 1) {
  3143. set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
  3144. start_dpc++;
  3145. }
  3146. /* Process any deferred work. */
  3147. if (!list_empty(&vha->work_list))
  3148. start_dpc++;
  3149. /* Schedule the DPC routine if needed */
  3150. if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
  3151. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
  3152. test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
  3153. start_dpc ||
  3154. test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
  3155. test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
  3156. test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
  3157. test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
  3158. test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
  3159. test_bit(RELOGIN_NEEDED, &vha->dpc_flags)))
  3160. qla2xxx_wake_dpc(vha);
  3161. qla2x00_restart_timer(vha, WATCH_INTERVAL);
  3162. }
  3163. /* Firmware interface routines. */
  3164. #define FW_BLOBS 8
  3165. #define FW_ISP21XX 0
  3166. #define FW_ISP22XX 1
  3167. #define FW_ISP2300 2
  3168. #define FW_ISP2322 3
  3169. #define FW_ISP24XX 4
  3170. #define FW_ISP25XX 5
  3171. #define FW_ISP81XX 6
  3172. #define FW_ISP82XX 7
  3173. #define FW_FILE_ISP21XX "ql2100_fw.bin"
  3174. #define FW_FILE_ISP22XX "ql2200_fw.bin"
  3175. #define FW_FILE_ISP2300 "ql2300_fw.bin"
  3176. #define FW_FILE_ISP2322 "ql2322_fw.bin"
  3177. #define FW_FILE_ISP24XX "ql2400_fw.bin"
  3178. #define FW_FILE_ISP25XX "ql2500_fw.bin"
  3179. #define FW_FILE_ISP81XX "ql8100_fw.bin"
  3180. #define FW_FILE_ISP82XX "ql8200_fw.bin"
  3181. static DEFINE_MUTEX(qla_fw_lock);
  3182. static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
  3183. { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
  3184. { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
  3185. { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
  3186. { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
  3187. { .name = FW_FILE_ISP24XX, },
  3188. { .name = FW_FILE_ISP25XX, },
  3189. { .name = FW_FILE_ISP81XX, },
  3190. { .name = FW_FILE_ISP82XX, },
  3191. };
  3192. struct fw_blob *
  3193. qla2x00_request_firmware(scsi_qla_host_t *vha)
  3194. {
  3195. struct qla_hw_data *ha = vha->hw;
  3196. struct fw_blob *blob;
  3197. blob = NULL;
  3198. if (IS_QLA2100(ha)) {
  3199. blob = &qla_fw_blobs[FW_ISP21XX];
  3200. } else if (IS_QLA2200(ha)) {
  3201. blob = &qla_fw_blobs[FW_ISP22XX];
  3202. } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  3203. blob = &qla_fw_blobs[FW_ISP2300];
  3204. } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
  3205. blob = &qla_fw_blobs[FW_ISP2322];
  3206. } else if (IS_QLA24XX_TYPE(ha)) {
  3207. blob = &qla_fw_blobs[FW_ISP24XX];
  3208. } else if (IS_QLA25XX(ha)) {
  3209. blob = &qla_fw_blobs[FW_ISP25XX];
  3210. } else if (IS_QLA81XX(ha)) {
  3211. blob = &qla_fw_blobs[FW_ISP81XX];
  3212. } else if (IS_QLA82XX(ha)) {
  3213. blob = &qla_fw_blobs[FW_ISP82XX];
  3214. }
  3215. mutex_lock(&qla_fw_lock);
  3216. if (blob->fw)
  3217. goto out;
  3218. if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
  3219. DEBUG2(printk("scsi(%ld): Failed to load firmware image "
  3220. "(%s).\n", vha->host_no, blob->name));
  3221. blob->fw = NULL;
  3222. blob = NULL;
  3223. goto out;
  3224. }
  3225. out:
  3226. mutex_unlock(&qla_fw_lock);
  3227. return blob;
  3228. }
  3229. static void
  3230. qla2x00_release_firmware(void)
  3231. {
  3232. int idx;
  3233. mutex_lock(&qla_fw_lock);
  3234. for (idx = 0; idx < FW_BLOBS; idx++)
  3235. if (qla_fw_blobs[idx].fw)
  3236. release_firmware(qla_fw_blobs[idx].fw);
  3237. mutex_unlock(&qla_fw_lock);
  3238. }
  3239. static pci_ers_result_t
  3240. qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
  3241. {
  3242. scsi_qla_host_t *vha = pci_get_drvdata(pdev);
  3243. struct qla_hw_data *ha = vha->hw;
  3244. DEBUG2(qla_printk(KERN_WARNING, ha, "error_detected:state %x\n",
  3245. state));
  3246. switch (state) {
  3247. case pci_channel_io_normal:
  3248. ha->flags.eeh_busy = 0;
  3249. return PCI_ERS_RESULT_CAN_RECOVER;
  3250. case pci_channel_io_frozen:
  3251. ha->flags.eeh_busy = 1;
  3252. /* For ISP82XX complete any pending mailbox cmd */
  3253. if (IS_QLA82XX(ha)) {
  3254. ha->flags.fw_hung = 1;
  3255. if (ha->flags.mbox_busy) {
  3256. ha->flags.mbox_int = 1;
  3257. DEBUG2(qla_printk(KERN_ERR, ha,
  3258. "Due to pci channel io frozen, doing premature "
  3259. "completion of mbx command\n"));
  3260. complete(&ha->mbx_intr_comp);
  3261. }
  3262. }
  3263. qla2x00_free_irqs(vha);
  3264. pci_disable_device(pdev);
  3265. /* Return back all IOs */
  3266. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  3267. return PCI_ERS_RESULT_NEED_RESET;
  3268. case pci_channel_io_perm_failure:
  3269. ha->flags.pci_channel_io_perm_failure = 1;
  3270. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  3271. return PCI_ERS_RESULT_DISCONNECT;
  3272. }
  3273. return PCI_ERS_RESULT_NEED_RESET;
  3274. }
  3275. static pci_ers_result_t
  3276. qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
  3277. {
  3278. int risc_paused = 0;
  3279. uint32_t stat;
  3280. unsigned long flags;
  3281. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3282. struct qla_hw_data *ha = base_vha->hw;
  3283. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  3284. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  3285. if (IS_QLA82XX(ha))
  3286. return PCI_ERS_RESULT_RECOVERED;
  3287. spin_lock_irqsave(&ha->hardware_lock, flags);
  3288. if (IS_QLA2100(ha) || IS_QLA2200(ha)){
  3289. stat = RD_REG_DWORD(&reg->hccr);
  3290. if (stat & HCCR_RISC_PAUSE)
  3291. risc_paused = 1;
  3292. } else if (IS_QLA23XX(ha)) {
  3293. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  3294. if (stat & HSR_RISC_PAUSED)
  3295. risc_paused = 1;
  3296. } else if (IS_FWI2_CAPABLE(ha)) {
  3297. stat = RD_REG_DWORD(&reg24->host_status);
  3298. if (stat & HSRX_RISC_PAUSED)
  3299. risc_paused = 1;
  3300. }
  3301. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3302. if (risc_paused) {
  3303. qla_printk(KERN_INFO, ha, "RISC paused -- mmio_enabled, "
  3304. "Dumping firmware!\n");
  3305. ha->isp_ops->fw_dump(base_vha, 0);
  3306. return PCI_ERS_RESULT_NEED_RESET;
  3307. } else
  3308. return PCI_ERS_RESULT_RECOVERED;
  3309. }
  3310. uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha)
  3311. {
  3312. uint32_t rval = QLA_FUNCTION_FAILED;
  3313. uint32_t drv_active = 0;
  3314. struct qla_hw_data *ha = base_vha->hw;
  3315. int fn;
  3316. struct pci_dev *other_pdev = NULL;
  3317. DEBUG17(qla_printk(KERN_INFO, ha,
  3318. "scsi(%ld): In qla82xx_error_recovery\n", base_vha->host_no));
  3319. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3320. if (base_vha->flags.online) {
  3321. /* Abort all outstanding commands,
  3322. * so as to be requeued later */
  3323. qla2x00_abort_isp_cleanup(base_vha);
  3324. }
  3325. fn = PCI_FUNC(ha->pdev->devfn);
  3326. while (fn > 0) {
  3327. fn--;
  3328. DEBUG17(qla_printk(KERN_INFO, ha,
  3329. "Finding pci device at function = 0x%x\n", fn));
  3330. other_pdev =
  3331. pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
  3332. ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
  3333. fn));
  3334. if (!other_pdev)
  3335. continue;
  3336. if (atomic_read(&other_pdev->enable_cnt)) {
  3337. DEBUG17(qla_printk(KERN_INFO, ha,
  3338. "Found PCI func availabe and enabled at 0x%x\n",
  3339. fn));
  3340. pci_dev_put(other_pdev);
  3341. break;
  3342. }
  3343. pci_dev_put(other_pdev);
  3344. }
  3345. if (!fn) {
  3346. /* Reset owner */
  3347. DEBUG17(qla_printk(KERN_INFO, ha,
  3348. "This devfn is reset owner = 0x%x\n", ha->pdev->devfn));
  3349. qla82xx_idc_lock(ha);
  3350. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3351. QLA82XX_DEV_INITIALIZING);
  3352. qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
  3353. QLA82XX_IDC_VERSION);
  3354. drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
  3355. DEBUG17(qla_printk(KERN_INFO, ha,
  3356. "drv_active = 0x%x\n", drv_active));
  3357. qla82xx_idc_unlock(ha);
  3358. /* Reset if device is not already reset
  3359. * drv_active would be 0 if a reset has already been done
  3360. */
  3361. if (drv_active)
  3362. rval = qla82xx_start_firmware(base_vha);
  3363. else
  3364. rval = QLA_SUCCESS;
  3365. qla82xx_idc_lock(ha);
  3366. if (rval != QLA_SUCCESS) {
  3367. qla_printk(KERN_INFO, ha, "HW State: FAILED\n");
  3368. qla82xx_clear_drv_active(ha);
  3369. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3370. QLA82XX_DEV_FAILED);
  3371. } else {
  3372. qla_printk(KERN_INFO, ha, "HW State: READY\n");
  3373. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3374. QLA82XX_DEV_READY);
  3375. qla82xx_idc_unlock(ha);
  3376. ha->flags.fw_hung = 0;
  3377. rval = qla82xx_restart_isp(base_vha);
  3378. qla82xx_idc_lock(ha);
  3379. /* Clear driver state register */
  3380. qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
  3381. qla82xx_set_drv_active(base_vha);
  3382. }
  3383. qla82xx_idc_unlock(ha);
  3384. } else {
  3385. DEBUG17(qla_printk(KERN_INFO, ha,
  3386. "This devfn is not reset owner = 0x%x\n", ha->pdev->devfn));
  3387. if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
  3388. QLA82XX_DEV_READY)) {
  3389. ha->flags.fw_hung = 0;
  3390. rval = qla82xx_restart_isp(base_vha);
  3391. qla82xx_idc_lock(ha);
  3392. qla82xx_set_drv_active(base_vha);
  3393. qla82xx_idc_unlock(ha);
  3394. }
  3395. }
  3396. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3397. return rval;
  3398. }
  3399. static pci_ers_result_t
  3400. qla2xxx_pci_slot_reset(struct pci_dev *pdev)
  3401. {
  3402. pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
  3403. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3404. struct qla_hw_data *ha = base_vha->hw;
  3405. struct rsp_que *rsp;
  3406. int rc, retries = 10;
  3407. DEBUG17(qla_printk(KERN_WARNING, ha, "slot_reset\n"));
  3408. /* Workaround: qla2xxx driver which access hardware earlier
  3409. * needs error state to be pci_channel_io_online.
  3410. * Otherwise mailbox command timesout.
  3411. */
  3412. pdev->error_state = pci_channel_io_normal;
  3413. pci_restore_state(pdev);
  3414. /* pci_restore_state() clears the saved_state flag of the device
  3415. * save restored state which resets saved_state flag
  3416. */
  3417. pci_save_state(pdev);
  3418. if (ha->mem_only)
  3419. rc = pci_enable_device_mem(pdev);
  3420. else
  3421. rc = pci_enable_device(pdev);
  3422. if (rc) {
  3423. qla_printk(KERN_WARNING, ha,
  3424. "Can't re-enable PCI device after reset.\n");
  3425. goto exit_slot_reset;
  3426. }
  3427. rsp = ha->rsp_q_map[0];
  3428. if (qla2x00_request_irqs(ha, rsp))
  3429. goto exit_slot_reset;
  3430. if (ha->isp_ops->pci_config(base_vha))
  3431. goto exit_slot_reset;
  3432. if (IS_QLA82XX(ha)) {
  3433. if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
  3434. ret = PCI_ERS_RESULT_RECOVERED;
  3435. goto exit_slot_reset;
  3436. } else
  3437. goto exit_slot_reset;
  3438. }
  3439. while (ha->flags.mbox_busy && retries--)
  3440. msleep(1000);
  3441. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3442. if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
  3443. ret = PCI_ERS_RESULT_RECOVERED;
  3444. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3445. exit_slot_reset:
  3446. DEBUG17(qla_printk(KERN_WARNING, ha,
  3447. "slot_reset-return:ret=%x\n", ret));
  3448. return ret;
  3449. }
  3450. static void
  3451. qla2xxx_pci_resume(struct pci_dev *pdev)
  3452. {
  3453. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3454. struct qla_hw_data *ha = base_vha->hw;
  3455. int ret;
  3456. DEBUG17(qla_printk(KERN_WARNING, ha, "pci_resume\n"));
  3457. ret = qla2x00_wait_for_hba_online(base_vha);
  3458. if (ret != QLA_SUCCESS) {
  3459. qla_printk(KERN_ERR, ha,
  3460. "the device failed to resume I/O "
  3461. "from slot/link_reset");
  3462. }
  3463. pci_cleanup_aer_uncorrect_error_status(pdev);
  3464. ha->flags.eeh_busy = 0;
  3465. }
  3466. static struct pci_error_handlers qla2xxx_err_handler = {
  3467. .error_detected = qla2xxx_pci_error_detected,
  3468. .mmio_enabled = qla2xxx_pci_mmio_enabled,
  3469. .slot_reset = qla2xxx_pci_slot_reset,
  3470. .resume = qla2xxx_pci_resume,
  3471. };
  3472. static struct pci_device_id qla2xxx_pci_tbl[] = {
  3473. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
  3474. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
  3475. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
  3476. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
  3477. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
  3478. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
  3479. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
  3480. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
  3481. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
  3482. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
  3483. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
  3484. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
  3485. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
  3486. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
  3487. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
  3488. { 0 },
  3489. };
  3490. MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
  3491. static struct pci_driver qla2xxx_pci_driver = {
  3492. .name = QLA2XXX_DRIVER_NAME,
  3493. .driver = {
  3494. .owner = THIS_MODULE,
  3495. },
  3496. .id_table = qla2xxx_pci_tbl,
  3497. .probe = qla2x00_probe_one,
  3498. .remove = qla2x00_remove_one,
  3499. .err_handler = &qla2xxx_err_handler,
  3500. };
  3501. static struct file_operations apidev_fops = {
  3502. .owner = THIS_MODULE,
  3503. .llseek = noop_llseek,
  3504. };
  3505. /**
  3506. * qla2x00_module_init - Module initialization.
  3507. **/
  3508. static int __init
  3509. qla2x00_module_init(void)
  3510. {
  3511. int ret = 0;
  3512. /* Allocate cache for SRBs. */
  3513. srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
  3514. SLAB_HWCACHE_ALIGN, NULL);
  3515. if (srb_cachep == NULL) {
  3516. printk(KERN_ERR
  3517. "qla2xxx: Unable to allocate SRB cache...Failing load!\n");
  3518. return -ENOMEM;
  3519. }
  3520. /* Derive version string. */
  3521. strcpy(qla2x00_version_str, QLA2XXX_VERSION);
  3522. if (ql2xextended_error_logging)
  3523. strcat(qla2x00_version_str, "-debug");
  3524. qla2xxx_transport_template =
  3525. fc_attach_transport(&qla2xxx_transport_functions);
  3526. if (!qla2xxx_transport_template) {
  3527. kmem_cache_destroy(srb_cachep);
  3528. return -ENODEV;
  3529. }
  3530. apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
  3531. if (apidev_major < 0) {
  3532. printk(KERN_WARNING "qla2xxx: Unable to register char device "
  3533. "%s\n", QLA2XXX_APIDEV);
  3534. }
  3535. qla2xxx_transport_vport_template =
  3536. fc_attach_transport(&qla2xxx_transport_vport_functions);
  3537. if (!qla2xxx_transport_vport_template) {
  3538. kmem_cache_destroy(srb_cachep);
  3539. fc_release_transport(qla2xxx_transport_template);
  3540. return -ENODEV;
  3541. }
  3542. printk(KERN_INFO "QLogic Fibre Channel HBA Driver: %s\n",
  3543. qla2x00_version_str);
  3544. ret = pci_register_driver(&qla2xxx_pci_driver);
  3545. if (ret) {
  3546. kmem_cache_destroy(srb_cachep);
  3547. fc_release_transport(qla2xxx_transport_template);
  3548. fc_release_transport(qla2xxx_transport_vport_template);
  3549. }
  3550. return ret;
  3551. }
  3552. /**
  3553. * qla2x00_module_exit - Module cleanup.
  3554. **/
  3555. static void __exit
  3556. qla2x00_module_exit(void)
  3557. {
  3558. unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
  3559. pci_unregister_driver(&qla2xxx_pci_driver);
  3560. qla2x00_release_firmware();
  3561. kmem_cache_destroy(srb_cachep);
  3562. if (ctx_cachep)
  3563. kmem_cache_destroy(ctx_cachep);
  3564. fc_release_transport(qla2xxx_transport_template);
  3565. fc_release_transport(qla2xxx_transport_vport_template);
  3566. }
  3567. module_init(qla2x00_module_init);
  3568. module_exit(qla2x00_module_exit);
  3569. MODULE_AUTHOR("QLogic Corporation");
  3570. MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
  3571. MODULE_LICENSE("GPL");
  3572. MODULE_VERSION(QLA2XXX_VERSION);
  3573. MODULE_FIRMWARE(FW_FILE_ISP21XX);
  3574. MODULE_FIRMWARE(FW_FILE_ISP22XX);
  3575. MODULE_FIRMWARE(FW_FILE_ISP2300);
  3576. MODULE_FIRMWARE(FW_FILE_ISP2322);
  3577. MODULE_FIRMWARE(FW_FILE_ISP24XX);
  3578. MODULE_FIRMWARE(FW_FILE_ISP25XX);