iwl-agn-ucode.c 18 KB

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  1. /******************************************************************************
  2. *
  3. * GPL LICENSE SUMMARY
  4. *
  5. * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19. * USA
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/sched.h>
  33. #include "iwl-dev.h"
  34. #include "iwl-core.h"
  35. #include "iwl-io.h"
  36. #include "iwl-helpers.h"
  37. #include "iwl-agn-hw.h"
  38. #include "iwl-agn.h"
  39. #include "iwl-agn-calib.h"
  40. #include "iwl-trans.h"
  41. #include "iwl-fh.h"
  42. static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
  43. {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
  44. 0, COEX_UNASSOC_IDLE_FLAGS},
  45. {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
  46. 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
  47. {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
  48. 0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
  49. {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
  50. 0, COEX_CALIBRATION_FLAGS},
  51. {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
  52. 0, COEX_PERIODIC_CALIBRATION_FLAGS},
  53. {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
  54. 0, COEX_CONNECTION_ESTAB_FLAGS},
  55. {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
  56. 0, COEX_ASSOCIATED_IDLE_FLAGS},
  57. {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
  58. 0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
  59. {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
  60. 0, COEX_ASSOC_AUTO_SCAN_FLAGS},
  61. {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
  62. 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
  63. {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
  64. {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
  65. {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
  66. 0, COEX_STAND_ALONE_DEBUG_FLAGS},
  67. {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
  68. 0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
  69. {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
  70. {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
  71. };
  72. /*
  73. * ucode
  74. */
  75. static int iwlagn_load_section(struct iwl_priv *priv, const char *name,
  76. struct fw_desc *image, u32 dst_addr)
  77. {
  78. dma_addr_t phy_addr = image->p_addr;
  79. u32 byte_cnt = image->len;
  80. int ret;
  81. priv->ucode_write_complete = 0;
  82. iwl_write_direct32(bus(priv),
  83. FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
  84. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
  85. iwl_write_direct32(bus(priv),
  86. FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
  87. iwl_write_direct32(bus(priv),
  88. FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
  89. phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
  90. iwl_write_direct32(bus(priv),
  91. FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
  92. (iwl_get_dma_hi_addr(phy_addr)
  93. << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
  94. iwl_write_direct32(bus(priv),
  95. FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
  96. 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
  97. 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
  98. FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
  99. iwl_write_direct32(bus(priv),
  100. FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
  101. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
  102. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
  103. FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
  104. IWL_DEBUG_FW(priv, "%s uCode section being loaded...\n", name);
  105. ret = wait_event_timeout(priv->shrd->wait_command_queue,
  106. priv->ucode_write_complete, 5 * HZ);
  107. if (!ret) {
  108. IWL_ERR(priv, "Could not load the %s uCode section\n",
  109. name);
  110. return -ETIMEDOUT;
  111. }
  112. return 0;
  113. }
  114. static int iwlagn_load_given_ucode(struct iwl_priv *priv,
  115. struct fw_img *image)
  116. {
  117. int ret = 0;
  118. ret = iwlagn_load_section(priv, "INST", &image->code,
  119. IWLAGN_RTC_INST_LOWER_BOUND);
  120. if (ret)
  121. return ret;
  122. return iwlagn_load_section(priv, "DATA", &image->data,
  123. IWLAGN_RTC_DATA_LOWER_BOUND);
  124. }
  125. /*
  126. * Calibration
  127. */
  128. static int iwlagn_set_Xtal_calib(struct iwl_priv *priv)
  129. {
  130. struct iwl_calib_xtal_freq_cmd cmd;
  131. __le16 *xtal_calib =
  132. (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_XTAL);
  133. iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD);
  134. cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
  135. cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
  136. return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
  137. (u8 *)&cmd, sizeof(cmd));
  138. }
  139. static int iwlagn_set_temperature_offset_calib(struct iwl_priv *priv)
  140. {
  141. struct iwl_calib_temperature_offset_cmd cmd;
  142. __le16 *offset_calib =
  143. (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_RAW_TEMPERATURE);
  144. memset(&cmd, 0, sizeof(cmd));
  145. iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD);
  146. memcpy(&cmd.radio_sensor_offset, offset_calib, sizeof(*offset_calib));
  147. if (!(cmd.radio_sensor_offset))
  148. cmd.radio_sensor_offset = DEFAULT_RADIO_SENSOR_OFFSET;
  149. IWL_DEBUG_CALIB(priv, "Radio sensor offset: %d\n",
  150. le16_to_cpu(cmd.radio_sensor_offset));
  151. return iwl_calib_set(&priv->calib_results[IWL_CALIB_TEMP_OFFSET],
  152. (u8 *)&cmd, sizeof(cmd));
  153. }
  154. static int iwlagn_set_temperature_offset_calib_v2(struct iwl_priv *priv)
  155. {
  156. struct iwl_calib_temperature_offset_v2_cmd cmd;
  157. __le16 *offset_calib_high = (__le16 *)iwl_eeprom_query_addr(priv,
  158. EEPROM_KELVIN_TEMPERATURE);
  159. __le16 *offset_calib_low =
  160. (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_RAW_TEMPERATURE);
  161. struct iwl_eeprom_calib_hdr *hdr;
  162. memset(&cmd, 0, sizeof(cmd));
  163. iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD);
  164. hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
  165. EEPROM_CALIB_ALL);
  166. memcpy(&cmd.radio_sensor_offset_high, offset_calib_high,
  167. sizeof(*offset_calib_high));
  168. memcpy(&cmd.radio_sensor_offset_low, offset_calib_low,
  169. sizeof(*offset_calib_low));
  170. if (!(cmd.radio_sensor_offset_low)) {
  171. IWL_DEBUG_CALIB(priv, "no info in EEPROM, use default\n");
  172. cmd.radio_sensor_offset_low = DEFAULT_RADIO_SENSOR_OFFSET;
  173. cmd.radio_sensor_offset_high = DEFAULT_RADIO_SENSOR_OFFSET;
  174. }
  175. memcpy(&cmd.burntVoltageRef, &hdr->voltage,
  176. sizeof(hdr->voltage));
  177. IWL_DEBUG_CALIB(priv, "Radio sensor offset high: %d\n",
  178. le16_to_cpu(cmd.radio_sensor_offset_high));
  179. IWL_DEBUG_CALIB(priv, "Radio sensor offset low: %d\n",
  180. le16_to_cpu(cmd.radio_sensor_offset_low));
  181. IWL_DEBUG_CALIB(priv, "Voltage Ref: %d\n",
  182. le16_to_cpu(cmd.burntVoltageRef));
  183. return iwl_calib_set(&priv->calib_results[IWL_CALIB_TEMP_OFFSET],
  184. (u8 *)&cmd, sizeof(cmd));
  185. }
  186. static int iwlagn_send_calib_cfg(struct iwl_priv *priv)
  187. {
  188. struct iwl_calib_cfg_cmd calib_cfg_cmd;
  189. struct iwl_host_cmd cmd = {
  190. .id = CALIBRATION_CFG_CMD,
  191. .len = { sizeof(struct iwl_calib_cfg_cmd), },
  192. .data = { &calib_cfg_cmd, },
  193. };
  194. memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
  195. calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
  196. calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
  197. calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
  198. calib_cfg_cmd.ucd_calib_cfg.flags =
  199. IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK;
  200. return iwl_trans_send_cmd(trans(priv), &cmd);
  201. }
  202. void iwlagn_rx_calib_result(struct iwl_priv *priv,
  203. struct iwl_rx_mem_buffer *rxb)
  204. {
  205. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  206. struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
  207. int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  208. int index;
  209. /* reduce the size of the length field itself */
  210. len -= 4;
  211. /* Define the order in which the results will be sent to the runtime
  212. * uCode. iwl_send_calib_results sends them in a row according to
  213. * their index. We sort them here
  214. */
  215. switch (hdr->op_code) {
  216. case IWL_PHY_CALIBRATE_DC_CMD:
  217. index = IWL_CALIB_DC;
  218. break;
  219. case IWL_PHY_CALIBRATE_LO_CMD:
  220. index = IWL_CALIB_LO;
  221. break;
  222. case IWL_PHY_CALIBRATE_TX_IQ_CMD:
  223. index = IWL_CALIB_TX_IQ;
  224. break;
  225. case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
  226. index = IWL_CALIB_TX_IQ_PERD;
  227. break;
  228. case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
  229. index = IWL_CALIB_BASE_BAND;
  230. break;
  231. default:
  232. IWL_ERR(priv, "Unknown calibration notification %d\n",
  233. hdr->op_code);
  234. return;
  235. }
  236. iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
  237. }
  238. int iwlagn_init_alive_start(struct iwl_priv *priv)
  239. {
  240. int ret;
  241. if (priv->cfg->bt_params &&
  242. priv->cfg->bt_params->advanced_bt_coexist) {
  243. /*
  244. * Tell uCode we are ready to perform calibration
  245. * need to perform this before any calibration
  246. * no need to close the envlope since we are going
  247. * to load the runtime uCode later.
  248. */
  249. ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
  250. BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
  251. if (ret)
  252. return ret;
  253. }
  254. ret = iwlagn_send_calib_cfg(priv);
  255. if (ret)
  256. return ret;
  257. /**
  258. * temperature offset calibration is only needed for runtime ucode,
  259. * so prepare the value now.
  260. */
  261. if (priv->cfg->need_temp_offset_calib) {
  262. if (priv->cfg->temp_offset_v2)
  263. return iwlagn_set_temperature_offset_calib_v2(priv);
  264. else
  265. return iwlagn_set_temperature_offset_calib(priv);
  266. }
  267. return 0;
  268. }
  269. static int iwlagn_send_wimax_coex(struct iwl_priv *priv)
  270. {
  271. struct iwl_wimax_coex_cmd coex_cmd;
  272. if (priv->cfg->base_params->support_wimax_coexist) {
  273. /* UnMask wake up src at associated sleep */
  274. coex_cmd.flags = COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
  275. /* UnMask wake up src at unassociated sleep */
  276. coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
  277. memcpy(coex_cmd.sta_prio, cu_priorities,
  278. sizeof(struct iwl_wimax_coex_event_entry) *
  279. COEX_NUM_OF_EVENTS);
  280. /* enabling the coexistence feature */
  281. coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;
  282. /* enabling the priorities tables */
  283. coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
  284. } else {
  285. /* coexistence is disabled */
  286. memset(&coex_cmd, 0, sizeof(coex_cmd));
  287. }
  288. return iwl_trans_send_cmd_pdu(trans(priv),
  289. COEX_PRIORITY_TABLE_CMD, CMD_SYNC,
  290. sizeof(coex_cmd), &coex_cmd);
  291. }
  292. static const u8 iwlagn_bt_prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX] = {
  293. ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  294. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  295. ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  296. (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  297. ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  298. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  299. ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  300. (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  301. ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  302. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  303. ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  304. (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  305. ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  306. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  307. ((BT_COEX_PRIO_TBL_PRIO_COEX_OFF << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  308. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  309. ((BT_COEX_PRIO_TBL_PRIO_COEX_ON << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  310. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  311. 0, 0, 0, 0, 0, 0, 0
  312. };
  313. void iwlagn_send_prio_tbl(struct iwl_priv *priv)
  314. {
  315. struct iwl_bt_coex_prio_table_cmd prio_tbl_cmd;
  316. memcpy(prio_tbl_cmd.prio_tbl, iwlagn_bt_prio_tbl,
  317. sizeof(iwlagn_bt_prio_tbl));
  318. if (iwl_trans_send_cmd_pdu(trans(priv),
  319. REPLY_BT_COEX_PRIO_TABLE, CMD_SYNC,
  320. sizeof(prio_tbl_cmd), &prio_tbl_cmd))
  321. IWL_ERR(priv, "failed to send BT prio tbl command\n");
  322. }
  323. int iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type)
  324. {
  325. struct iwl_bt_coex_prot_env_cmd env_cmd;
  326. int ret;
  327. env_cmd.action = action;
  328. env_cmd.type = type;
  329. ret = iwl_trans_send_cmd_pdu(trans(priv),
  330. REPLY_BT_COEX_PROT_ENV, CMD_SYNC,
  331. sizeof(env_cmd), &env_cmd);
  332. if (ret)
  333. IWL_ERR(priv, "failed to send BT env command\n");
  334. return ret;
  335. }
  336. static int iwlagn_alive_notify(struct iwl_priv *priv)
  337. {
  338. struct iwl_rxon_context *ctx;
  339. int ret;
  340. if (!priv->tx_cmd_pool)
  341. priv->tx_cmd_pool =
  342. kmem_cache_create("iwlagn_dev_cmd",
  343. sizeof(struct iwl_device_cmd),
  344. sizeof(void *), 0, NULL);
  345. if (!priv->tx_cmd_pool)
  346. return -ENOMEM;
  347. iwl_trans_tx_start(trans(priv));
  348. for_each_context(priv, ctx)
  349. ctx->last_tx_rejected = false;
  350. ret = iwlagn_send_wimax_coex(priv);
  351. if (ret)
  352. return ret;
  353. ret = iwlagn_set_Xtal_calib(priv);
  354. if (ret)
  355. return ret;
  356. return iwl_send_calib_results(priv);
  357. }
  358. /**
  359. * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
  360. * using sample data 100 bytes apart. If these sample points are good,
  361. * it's a pretty good bet that everything between them is good, too.
  362. */
  363. static int iwl_verify_inst_sparse(struct iwl_priv *priv,
  364. struct fw_desc *fw_desc)
  365. {
  366. __le32 *image = (__le32 *)fw_desc->v_addr;
  367. u32 len = fw_desc->len;
  368. u32 val;
  369. u32 i;
  370. IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);
  371. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  372. /* read data comes through single port, auto-incr addr */
  373. /* NOTE: Use the debugless read so we don't flood kernel log
  374. * if IWL_DL_IO is set */
  375. iwl_write_direct32(bus(priv), HBUS_TARG_MEM_RADDR,
  376. i + IWLAGN_RTC_INST_LOWER_BOUND);
  377. val = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
  378. if (val != le32_to_cpu(*image))
  379. return -EIO;
  380. }
  381. return 0;
  382. }
  383. static void iwl_print_mismatch_inst(struct iwl_priv *priv,
  384. struct fw_desc *fw_desc)
  385. {
  386. __le32 *image = (__le32 *)fw_desc->v_addr;
  387. u32 len = fw_desc->len;
  388. u32 val;
  389. u32 offs;
  390. int errors = 0;
  391. IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);
  392. iwl_write_direct32(bus(priv), HBUS_TARG_MEM_RADDR,
  393. IWLAGN_RTC_INST_LOWER_BOUND);
  394. for (offs = 0;
  395. offs < len && errors < 20;
  396. offs += sizeof(u32), image++) {
  397. /* read data comes through single port, auto-incr addr */
  398. val = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
  399. if (val != le32_to_cpu(*image)) {
  400. IWL_ERR(priv, "uCode INST section at "
  401. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  402. offs, val, le32_to_cpu(*image));
  403. errors++;
  404. }
  405. }
  406. }
  407. /**
  408. * iwl_verify_ucode - determine which instruction image is in SRAM,
  409. * and verify its contents
  410. */
  411. static int iwl_verify_ucode(struct iwl_priv *priv, struct fw_img *img)
  412. {
  413. if (!iwl_verify_inst_sparse(priv, &img->code)) {
  414. IWL_DEBUG_FW(priv, "uCode is good in inst SRAM\n");
  415. return 0;
  416. }
  417. IWL_ERR(priv, "UCODE IMAGE IN INSTRUCTION SRAM NOT VALID!!\n");
  418. iwl_print_mismatch_inst(priv, &img->code);
  419. return -EIO;
  420. }
  421. struct iwlagn_alive_data {
  422. bool valid;
  423. u8 subtype;
  424. };
  425. static void iwlagn_alive_fn(struct iwl_priv *priv,
  426. struct iwl_rx_packet *pkt,
  427. void *data)
  428. {
  429. struct iwlagn_alive_data *alive_data = data;
  430. struct iwl_alive_resp *palive;
  431. palive = &pkt->u.alive_frame;
  432. IWL_DEBUG_FW(priv, "Alive ucode status 0x%08X revision "
  433. "0x%01X 0x%01X\n",
  434. palive->is_valid, palive->ver_type,
  435. palive->ver_subtype);
  436. priv->device_pointers.error_event_table =
  437. le32_to_cpu(palive->error_event_table_ptr);
  438. priv->device_pointers.log_event_table =
  439. le32_to_cpu(palive->log_event_table_ptr);
  440. alive_data->subtype = palive->ver_subtype;
  441. alive_data->valid = palive->is_valid == UCODE_VALID_OK;
  442. }
  443. #define UCODE_ALIVE_TIMEOUT HZ
  444. #define UCODE_CALIB_TIMEOUT (2*HZ)
  445. int iwlagn_load_ucode_wait_alive(struct iwl_priv *priv,
  446. struct fw_img *image,
  447. enum iwlagn_ucode_type ucode_type)
  448. {
  449. struct iwl_notification_wait alive_wait;
  450. struct iwlagn_alive_data alive_data;
  451. int ret;
  452. enum iwlagn_ucode_type old_type;
  453. ret = iwl_trans_start_device(trans(priv));
  454. if (ret)
  455. return ret;
  456. iwlagn_init_notification_wait(priv, &alive_wait, REPLY_ALIVE,
  457. iwlagn_alive_fn, &alive_data);
  458. old_type = priv->ucode_type;
  459. priv->ucode_type = ucode_type;
  460. ret = iwlagn_load_given_ucode(priv, image);
  461. if (ret) {
  462. priv->ucode_type = old_type;
  463. iwlagn_remove_notification(priv, &alive_wait);
  464. return ret;
  465. }
  466. iwl_trans_kick_nic(trans(priv));
  467. /*
  468. * Some things may run in the background now, but we
  469. * just wait for the ALIVE notification here.
  470. */
  471. ret = iwlagn_wait_notification(priv, &alive_wait, UCODE_ALIVE_TIMEOUT);
  472. if (ret) {
  473. priv->ucode_type = old_type;
  474. return ret;
  475. }
  476. if (!alive_data.valid) {
  477. IWL_ERR(priv, "Loaded ucode is not valid!\n");
  478. priv->ucode_type = old_type;
  479. return -EIO;
  480. }
  481. /*
  482. * This step takes a long time (60-80ms!!) and
  483. * WoWLAN image should be loaded quickly, so
  484. * skip it for WoWLAN.
  485. */
  486. if (ucode_type != IWL_UCODE_WOWLAN) {
  487. ret = iwl_verify_ucode(priv, image);
  488. if (ret) {
  489. priv->ucode_type = old_type;
  490. return ret;
  491. }
  492. /* delay a bit to give rfkill time to run */
  493. msleep(5);
  494. }
  495. ret = iwlagn_alive_notify(priv);
  496. if (ret) {
  497. IWL_WARN(priv,
  498. "Could not complete ALIVE transition: %d\n", ret);
  499. priv->ucode_type = old_type;
  500. return ret;
  501. }
  502. return 0;
  503. }
  504. int iwlagn_run_init_ucode(struct iwl_priv *priv)
  505. {
  506. struct iwl_notification_wait calib_wait;
  507. int ret;
  508. lockdep_assert_held(&priv->shrd->mutex);
  509. /* No init ucode required? Curious, but maybe ok */
  510. if (!priv->ucode_init.code.len)
  511. return 0;
  512. if (priv->ucode_type != IWL_UCODE_NONE)
  513. return 0;
  514. iwlagn_init_notification_wait(priv, &calib_wait,
  515. CALIBRATION_COMPLETE_NOTIFICATION,
  516. NULL, NULL);
  517. /* Will also start the device */
  518. ret = iwlagn_load_ucode_wait_alive(priv, &priv->ucode_init,
  519. IWL_UCODE_INIT);
  520. if (ret)
  521. goto error;
  522. ret = iwlagn_init_alive_start(priv);
  523. if (ret)
  524. goto error;
  525. /*
  526. * Some things may run in the background now, but we
  527. * just wait for the calibration complete notification.
  528. */
  529. ret = iwlagn_wait_notification(priv, &calib_wait, UCODE_CALIB_TIMEOUT);
  530. goto out;
  531. error:
  532. iwlagn_remove_notification(priv, &calib_wait);
  533. out:
  534. /* Whatever happened, stop the device */
  535. iwl_trans_stop_device(trans(priv));
  536. return ret;
  537. }