3945-mac.c 107 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006
  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/pci-aspm.h>
  35. #include <linux/slab.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/delay.h>
  38. #include <linux/sched.h>
  39. #include <linux/skbuff.h>
  40. #include <linux/netdevice.h>
  41. #include <linux/firmware.h>
  42. #include <linux/etherdevice.h>
  43. #include <linux/if_arp.h>
  44. #include <net/ieee80211_radiotap.h>
  45. #include <net/mac80211.h>
  46. #include <asm/div64.h>
  47. #define DRV_NAME "iwl3945"
  48. #include "iwl-fh.h"
  49. #include "iwl-commands.h"
  50. #include "iwl-sta.h"
  51. #include "3945.h"
  52. #include "iwl-core.h"
  53. #include "iwl-helpers.h"
  54. #include "iwl-dev.h"
  55. #include "iwl-spectrum.h"
  56. /*
  57. * module name, copyright, version, etc.
  58. */
  59. #define DRV_DESCRIPTION \
  60. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  61. #ifdef CONFIG_IWLEGACY_DEBUG
  62. #define VD "d"
  63. #else
  64. #define VD
  65. #endif
  66. /*
  67. * add "s" to indicate spectrum measurement included.
  68. * we add it here to be consistent with previous releases in which
  69. * this was configurable.
  70. */
  71. #define DRV_VERSION IWLWIFI_VERSION VD "s"
  72. #define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
  73. #define DRV_AUTHOR "<ilw@linux.intel.com>"
  74. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  75. MODULE_VERSION(DRV_VERSION);
  76. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  77. MODULE_LICENSE("GPL");
  78. /* module parameters */
  79. struct il_mod_params il3945_mod_params = {
  80. .sw_crypto = 1,
  81. .restart_fw = 1,
  82. .disable_hw_scan = 1,
  83. /* the rest are 0 by default */
  84. };
  85. /**
  86. * il3945_get_antenna_flags - Get antenna flags for RXON command
  87. * @il: eeprom and antenna fields are used to determine antenna flags
  88. *
  89. * il->eeprom39 is used to determine if antenna AUX/MAIN are reversed
  90. * il3945_mod_params.antenna specifies the antenna diversity mode:
  91. *
  92. * IL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
  93. * IL_ANTENNA_MAIN - Force MAIN antenna
  94. * IL_ANTENNA_AUX - Force AUX antenna
  95. */
  96. __le32 il3945_get_antenna_flags(const struct il_priv *il)
  97. {
  98. struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
  99. switch (il3945_mod_params.antenna) {
  100. case IL_ANTENNA_DIVERSITY:
  101. return 0;
  102. case IL_ANTENNA_MAIN:
  103. if (eeprom->antenna_switch_type)
  104. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
  105. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
  106. case IL_ANTENNA_AUX:
  107. if (eeprom->antenna_switch_type)
  108. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
  109. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
  110. }
  111. /* bad antenna selector value */
  112. IL_ERR("Bad antenna selector value (0x%x)\n",
  113. il3945_mod_params.antenna);
  114. return 0; /* "diversity" is default if error */
  115. }
  116. static int il3945_set_ccmp_dynamic_key_info(struct il_priv *il,
  117. struct ieee80211_key_conf *keyconf,
  118. u8 sta_id)
  119. {
  120. unsigned long flags;
  121. __le16 key_flags = 0;
  122. int ret;
  123. key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
  124. key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  125. if (sta_id == il->ctx.bcast_sta_id)
  126. key_flags |= STA_KEY_MULTICAST_MSK;
  127. keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  128. keyconf->hw_key_idx = keyconf->keyidx;
  129. key_flags &= ~STA_KEY_FLG_INVALID;
  130. spin_lock_irqsave(&il->sta_lock, flags);
  131. il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
  132. il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  133. memcpy(il->stations[sta_id].keyinfo.key, keyconf->key,
  134. keyconf->keylen);
  135. memcpy(il->stations[sta_id].sta.key.key, keyconf->key,
  136. keyconf->keylen);
  137. if ((il->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
  138. == STA_KEY_FLG_NO_ENC)
  139. il->stations[sta_id].sta.key.key_offset =
  140. il_get_free_ucode_key_idx(il);
  141. /* else, we are overriding an existing key => no need to allocated room
  142. * in uCode. */
  143. WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
  144. "no space for a new key");
  145. il->stations[sta_id].sta.key.key_flags = key_flags;
  146. il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  147. il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  148. D_INFO("hwcrypto: modify ucode station key info\n");
  149. ret = il_send_add_sta(il,
  150. &il->stations[sta_id].sta, CMD_ASYNC);
  151. spin_unlock_irqrestore(&il->sta_lock, flags);
  152. return ret;
  153. }
  154. static int il3945_set_tkip_dynamic_key_info(struct il_priv *il,
  155. struct ieee80211_key_conf *keyconf,
  156. u8 sta_id)
  157. {
  158. return -EOPNOTSUPP;
  159. }
  160. static int il3945_set_wep_dynamic_key_info(struct il_priv *il,
  161. struct ieee80211_key_conf *keyconf,
  162. u8 sta_id)
  163. {
  164. return -EOPNOTSUPP;
  165. }
  166. static int il3945_clear_sta_key_info(struct il_priv *il, u8 sta_id)
  167. {
  168. unsigned long flags;
  169. struct il_addsta_cmd sta_cmd;
  170. spin_lock_irqsave(&il->sta_lock, flags);
  171. memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key));
  172. memset(&il->stations[sta_id].sta.key, 0,
  173. sizeof(struct il4965_keyinfo));
  174. il->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  175. il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  176. il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  177. memcpy(&sta_cmd, &il->stations[sta_id].sta, sizeof(struct il_addsta_cmd));
  178. spin_unlock_irqrestore(&il->sta_lock, flags);
  179. D_INFO("hwcrypto: clear ucode station key info\n");
  180. return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
  181. }
  182. static int il3945_set_dynamic_key(struct il_priv *il,
  183. struct ieee80211_key_conf *keyconf, u8 sta_id)
  184. {
  185. int ret = 0;
  186. keyconf->hw_key_idx = HW_KEY_DYNAMIC;
  187. switch (keyconf->cipher) {
  188. case WLAN_CIPHER_SUITE_CCMP:
  189. ret = il3945_set_ccmp_dynamic_key_info(il, keyconf, sta_id);
  190. break;
  191. case WLAN_CIPHER_SUITE_TKIP:
  192. ret = il3945_set_tkip_dynamic_key_info(il, keyconf, sta_id);
  193. break;
  194. case WLAN_CIPHER_SUITE_WEP40:
  195. case WLAN_CIPHER_SUITE_WEP104:
  196. ret = il3945_set_wep_dynamic_key_info(il, keyconf, sta_id);
  197. break;
  198. default:
  199. IL_ERR("Unknown alg: %s alg=%x\n", __func__,
  200. keyconf->cipher);
  201. ret = -EINVAL;
  202. }
  203. D_WEP("Set dynamic key: alg=%x len=%d idx=%d sta=%d ret=%d\n",
  204. keyconf->cipher, keyconf->keylen, keyconf->keyidx,
  205. sta_id, ret);
  206. return ret;
  207. }
  208. static int il3945_remove_static_key(struct il_priv *il)
  209. {
  210. int ret = -EOPNOTSUPP;
  211. return ret;
  212. }
  213. static int il3945_set_static_key(struct il_priv *il,
  214. struct ieee80211_key_conf *key)
  215. {
  216. if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
  217. key->cipher == WLAN_CIPHER_SUITE_WEP104)
  218. return -EOPNOTSUPP;
  219. IL_ERR("Static key invalid: cipher %x\n", key->cipher);
  220. return -EINVAL;
  221. }
  222. static void il3945_clear_free_frames(struct il_priv *il)
  223. {
  224. struct list_head *element;
  225. D_INFO("%d frames on pre-allocated heap on clear.\n",
  226. il->frames_count);
  227. while (!list_empty(&il->free_frames)) {
  228. element = il->free_frames.next;
  229. list_del(element);
  230. kfree(list_entry(element, struct il3945_frame, list));
  231. il->frames_count--;
  232. }
  233. if (il->frames_count) {
  234. IL_WARN("%d frames still in use. Did we lose one?\n",
  235. il->frames_count);
  236. il->frames_count = 0;
  237. }
  238. }
  239. static struct il3945_frame *il3945_get_free_frame(struct il_priv *il)
  240. {
  241. struct il3945_frame *frame;
  242. struct list_head *element;
  243. if (list_empty(&il->free_frames)) {
  244. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  245. if (!frame) {
  246. IL_ERR("Could not allocate frame!\n");
  247. return NULL;
  248. }
  249. il->frames_count++;
  250. return frame;
  251. }
  252. element = il->free_frames.next;
  253. list_del(element);
  254. return list_entry(element, struct il3945_frame, list);
  255. }
  256. static void il3945_free_frame(struct il_priv *il, struct il3945_frame *frame)
  257. {
  258. memset(frame, 0, sizeof(*frame));
  259. list_add(&frame->list, &il->free_frames);
  260. }
  261. unsigned int il3945_fill_beacon_frame(struct il_priv *il,
  262. struct ieee80211_hdr *hdr,
  263. int left)
  264. {
  265. if (!il_is_associated(il) || !il->beacon_skb)
  266. return 0;
  267. if (il->beacon_skb->len > left)
  268. return 0;
  269. memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
  270. return il->beacon_skb->len;
  271. }
  272. static int il3945_send_beacon_cmd(struct il_priv *il)
  273. {
  274. struct il3945_frame *frame;
  275. unsigned int frame_size;
  276. int rc;
  277. u8 rate;
  278. frame = il3945_get_free_frame(il);
  279. if (!frame) {
  280. IL_ERR("Could not obtain free frame buffer for beacon "
  281. "command.\n");
  282. return -ENOMEM;
  283. }
  284. rate = il_get_lowest_plcp(il,
  285. &il->ctx);
  286. frame_size = il3945_hw_get_beacon_cmd(il, frame, rate);
  287. rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size,
  288. &frame->u.cmd[0]);
  289. il3945_free_frame(il, frame);
  290. return rc;
  291. }
  292. static void il3945_unset_hw_params(struct il_priv *il)
  293. {
  294. if (il->_3945.shared_virt)
  295. dma_free_coherent(&il->pci_dev->dev,
  296. sizeof(struct il3945_shared),
  297. il->_3945.shared_virt,
  298. il->_3945.shared_phys);
  299. }
  300. static void il3945_build_tx_cmd_hwcrypto(struct il_priv *il,
  301. struct ieee80211_tx_info *info,
  302. struct il_device_cmd *cmd,
  303. struct sk_buff *skb_frag,
  304. int sta_id)
  305. {
  306. struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
  307. struct il_hw_key *keyinfo = &il->stations[sta_id].keyinfo;
  308. tx_cmd->sec_ctl = 0;
  309. switch (keyinfo->cipher) {
  310. case WLAN_CIPHER_SUITE_CCMP:
  311. tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
  312. memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen);
  313. D_TX("tx_cmd with AES hwcrypto\n");
  314. break;
  315. case WLAN_CIPHER_SUITE_TKIP:
  316. break;
  317. case WLAN_CIPHER_SUITE_WEP104:
  318. tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
  319. /* fall through */
  320. case WLAN_CIPHER_SUITE_WEP40:
  321. tx_cmd->sec_ctl |= TX_CMD_SEC_WEP |
  322. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  323. memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen);
  324. D_TX("Configuring packet for WEP encryption "
  325. "with key %d\n", info->control.hw_key->hw_key_idx);
  326. break;
  327. default:
  328. IL_ERR("Unknown encode cipher %x\n", keyinfo->cipher);
  329. break;
  330. }
  331. }
  332. /*
  333. * handle build C_TX command notification.
  334. */
  335. static void il3945_build_tx_cmd_basic(struct il_priv *il,
  336. struct il_device_cmd *cmd,
  337. struct ieee80211_tx_info *info,
  338. struct ieee80211_hdr *hdr, u8 std_id)
  339. {
  340. struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
  341. __le32 tx_flags = tx_cmd->tx_flags;
  342. __le16 fc = hdr->frame_control;
  343. tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  344. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  345. tx_flags |= TX_CMD_FLG_ACK_MSK;
  346. if (ieee80211_is_mgmt(fc))
  347. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  348. if (ieee80211_is_probe_resp(fc) &&
  349. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  350. tx_flags |= TX_CMD_FLG_TSF_MSK;
  351. } else {
  352. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  353. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  354. }
  355. tx_cmd->sta_id = std_id;
  356. if (ieee80211_has_morefrags(fc))
  357. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  358. if (ieee80211_is_data_qos(fc)) {
  359. u8 *qc = ieee80211_get_qos_ctl(hdr);
  360. tx_cmd->tid_tspec = qc[0] & 0xf;
  361. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  362. } else {
  363. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  364. }
  365. il_tx_cmd_protection(il, info, fc, &tx_flags);
  366. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  367. if (ieee80211_is_mgmt(fc)) {
  368. if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
  369. tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
  370. else
  371. tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
  372. } else {
  373. tx_cmd->timeout.pm_frame_timeout = 0;
  374. }
  375. tx_cmd->driver_txop = 0;
  376. tx_cmd->tx_flags = tx_flags;
  377. tx_cmd->next_frame_len = 0;
  378. }
  379. /*
  380. * start C_TX command process
  381. */
  382. static int il3945_tx_skb(struct il_priv *il, struct sk_buff *skb)
  383. {
  384. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  385. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  386. struct il3945_tx_cmd *tx_cmd;
  387. struct il_tx_queue *txq = NULL;
  388. struct il_queue *q = NULL;
  389. struct il_device_cmd *out_cmd;
  390. struct il_cmd_meta *out_meta;
  391. dma_addr_t phys_addr;
  392. dma_addr_t txcmd_phys;
  393. int txq_id = skb_get_queue_mapping(skb);
  394. u16 len, idx, hdr_len;
  395. u8 id;
  396. u8 unicast;
  397. u8 sta_id;
  398. u8 tid = 0;
  399. __le16 fc;
  400. u8 wait_write_ptr = 0;
  401. unsigned long flags;
  402. spin_lock_irqsave(&il->lock, flags);
  403. if (il_is_rfkill(il)) {
  404. D_DROP("Dropping - RF KILL\n");
  405. goto drop_unlock;
  406. }
  407. if ((ieee80211_get_tx_rate(il->hw, info)->hw_value & 0xFF) == IL_INVALID_RATE) {
  408. IL_ERR("ERROR: No TX rate available.\n");
  409. goto drop_unlock;
  410. }
  411. unicast = !is_multicast_ether_addr(hdr->addr1);
  412. id = 0;
  413. fc = hdr->frame_control;
  414. #ifdef CONFIG_IWLEGACY_DEBUG
  415. if (ieee80211_is_auth(fc))
  416. D_TX("Sending AUTH frame\n");
  417. else if (ieee80211_is_assoc_req(fc))
  418. D_TX("Sending ASSOC frame\n");
  419. else if (ieee80211_is_reassoc_req(fc))
  420. D_TX("Sending REASSOC frame\n");
  421. #endif
  422. spin_unlock_irqrestore(&il->lock, flags);
  423. hdr_len = ieee80211_hdrlen(fc);
  424. /* Find idx into station table for destination station */
  425. sta_id = il_sta_id_or_broadcast(
  426. il, &il->ctx,
  427. info->control.sta);
  428. if (sta_id == IL_INVALID_STATION) {
  429. D_DROP("Dropping - INVALID STATION: %pM\n",
  430. hdr->addr1);
  431. goto drop;
  432. }
  433. D_RATE("station Id %d\n", sta_id);
  434. if (ieee80211_is_data_qos(fc)) {
  435. u8 *qc = ieee80211_get_qos_ctl(hdr);
  436. tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
  437. if (unlikely(tid >= MAX_TID_COUNT))
  438. goto drop;
  439. }
  440. /* Descriptor for chosen Tx queue */
  441. txq = &il->txq[txq_id];
  442. q = &txq->q;
  443. if ((il_queue_space(q) < q->high_mark))
  444. goto drop;
  445. spin_lock_irqsave(&il->lock, flags);
  446. idx = il_get_cmd_idx(q, q->write_ptr, 0);
  447. /* Set up driver data for this TFD */
  448. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct il_tx_info));
  449. txq->txb[q->write_ptr].skb = skb;
  450. txq->txb[q->write_ptr].ctx = &il->ctx;
  451. /* Init first empty entry in queue's array of Tx/cmd buffers */
  452. out_cmd = txq->cmd[idx];
  453. out_meta = &txq->meta[idx];
  454. tx_cmd = (struct il3945_tx_cmd *)out_cmd->cmd.payload;
  455. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  456. memset(tx_cmd, 0, sizeof(*tx_cmd));
  457. /*
  458. * Set up the Tx-command (not MAC!) header.
  459. * Store the chosen Tx queue and TFD idx within the sequence field;
  460. * after Tx, uCode's Tx response will return this value so driver can
  461. * locate the frame within the tx queue and do post-tx processing.
  462. */
  463. out_cmd->hdr.cmd = C_TX;
  464. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  465. IDX_TO_SEQ(q->write_ptr)));
  466. /* Copy MAC header from skb into command buffer */
  467. memcpy(tx_cmd->hdr, hdr, hdr_len);
  468. if (info->control.hw_key)
  469. il3945_build_tx_cmd_hwcrypto(il, info, out_cmd, skb, sta_id);
  470. /* TODO need this for burst mode later on */
  471. il3945_build_tx_cmd_basic(il, out_cmd, info, hdr, sta_id);
  472. /* set is_hcca to 0; it probably will never be implemented */
  473. il3945_hw_build_tx_cmd_rate(il, out_cmd, info, hdr, sta_id, 0);
  474. /* Total # bytes to be transmitted */
  475. len = (u16)skb->len;
  476. tx_cmd->len = cpu_to_le16(len);
  477. il_dbg_log_tx_data_frame(il, len, hdr);
  478. il_update_stats(il, true, fc, len);
  479. tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  480. tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  481. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  482. txq->need_update = 1;
  483. } else {
  484. wait_write_ptr = 1;
  485. txq->need_update = 0;
  486. }
  487. D_TX("sequence nr = 0X%x\n",
  488. le16_to_cpu(out_cmd->hdr.sequence));
  489. D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
  490. il_print_hex_dump(il, IL_DL_TX, tx_cmd, sizeof(*tx_cmd));
  491. il_print_hex_dump(il, IL_DL_TX, (u8 *)tx_cmd->hdr,
  492. ieee80211_hdrlen(fc));
  493. /*
  494. * Use the first empty entry in this queue's command buffer array
  495. * to contain the Tx command and MAC header concatenated together
  496. * (payload data will be in another buffer).
  497. * Size of this varies, due to varying MAC header length.
  498. * If end is not dword aligned, we'll have 2 extra bytes at the end
  499. * of the MAC header (device reads on dword boundaries).
  500. * We'll tell device about this padding later.
  501. */
  502. len = sizeof(struct il3945_tx_cmd) +
  503. sizeof(struct il_cmd_header) + hdr_len;
  504. len = (len + 3) & ~3;
  505. /* Physical address of this Tx command's header (not MAC header!),
  506. * within command buffer array. */
  507. txcmd_phys = pci_map_single(il->pci_dev, &out_cmd->hdr,
  508. len, PCI_DMA_TODEVICE);
  509. /* we do not map meta data ... so we can safely access address to
  510. * provide to unmap command*/
  511. dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
  512. dma_unmap_len_set(out_meta, len, len);
  513. /* Add buffer containing Tx command and MAC(!) header to TFD's
  514. * first entry */
  515. il->cfg->ops->lib->txq_attach_buf_to_tfd(il, txq,
  516. txcmd_phys, len, 1, 0);
  517. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  518. * if any (802.11 null frames have no payload). */
  519. len = skb->len - hdr_len;
  520. if (len) {
  521. phys_addr = pci_map_single(il->pci_dev, skb->data + hdr_len,
  522. len, PCI_DMA_TODEVICE);
  523. il->cfg->ops->lib->txq_attach_buf_to_tfd(il, txq,
  524. phys_addr, len,
  525. 0, U32_PAD(len));
  526. }
  527. /* Tell device the write idx *just past* this latest filled TFD */
  528. q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
  529. il_txq_update_write_ptr(il, txq);
  530. spin_unlock_irqrestore(&il->lock, flags);
  531. if (il_queue_space(q) < q->high_mark
  532. && il->mac80211_registered) {
  533. if (wait_write_ptr) {
  534. spin_lock_irqsave(&il->lock, flags);
  535. txq->need_update = 1;
  536. il_txq_update_write_ptr(il, txq);
  537. spin_unlock_irqrestore(&il->lock, flags);
  538. }
  539. il_stop_queue(il, txq);
  540. }
  541. return 0;
  542. drop_unlock:
  543. spin_unlock_irqrestore(&il->lock, flags);
  544. drop:
  545. return -1;
  546. }
  547. static int il3945_get_measurement(struct il_priv *il,
  548. struct ieee80211_measurement_params *params,
  549. u8 type)
  550. {
  551. struct il_spectrum_cmd spectrum;
  552. struct il_rx_pkt *pkt;
  553. struct il_host_cmd cmd = {
  554. .id = C_SPECTRUM_MEASUREMENT,
  555. .data = (void *)&spectrum,
  556. .flags = CMD_WANT_SKB,
  557. };
  558. u32 add_time = le64_to_cpu(params->start_time);
  559. int rc;
  560. int spectrum_resp_status;
  561. int duration = le16_to_cpu(params->duration);
  562. struct il_rxon_context *ctx = &il->ctx;
  563. if (il_is_associated(il))
  564. add_time = il_usecs_to_beacons(il,
  565. le64_to_cpu(params->start_time) - il->_3945.last_tsf,
  566. le16_to_cpu(ctx->timing.beacon_interval));
  567. memset(&spectrum, 0, sizeof(spectrum));
  568. spectrum.channel_count = cpu_to_le16(1);
  569. spectrum.flags =
  570. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  571. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  572. cmd.len = sizeof(spectrum);
  573. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  574. if (il_is_associated(il))
  575. spectrum.start_time =
  576. il_add_beacon_time(il,
  577. il->_3945.last_beacon_time, add_time,
  578. le16_to_cpu(ctx->timing.beacon_interval));
  579. else
  580. spectrum.start_time = 0;
  581. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  582. spectrum.channels[0].channel = params->channel;
  583. spectrum.channels[0].type = type;
  584. if (ctx->active.flags & RXON_FLG_BAND_24G_MSK)
  585. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  586. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  587. rc = il_send_cmd_sync(il, &cmd);
  588. if (rc)
  589. return rc;
  590. pkt = (struct il_rx_pkt *)cmd.reply_page;
  591. if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
  592. IL_ERR("Bad return from N_RX_ON_ASSOC command\n");
  593. rc = -EIO;
  594. }
  595. spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status);
  596. switch (spectrum_resp_status) {
  597. case 0: /* Command will be handled */
  598. if (pkt->u.spectrum.id != 0xff) {
  599. D_INFO("Replaced existing measurement: %d\n",
  600. pkt->u.spectrum.id);
  601. il->measurement_status &= ~MEASUREMENT_READY;
  602. }
  603. il->measurement_status |= MEASUREMENT_ACTIVE;
  604. rc = 0;
  605. break;
  606. case 1: /* Command will not be handled */
  607. rc = -EAGAIN;
  608. break;
  609. }
  610. il_free_pages(il, cmd.reply_page);
  611. return rc;
  612. }
  613. static void il3945_rx_reply_alive(struct il_priv *il,
  614. struct il_rx_buf *rxb)
  615. {
  616. struct il_rx_pkt *pkt = rxb_addr(rxb);
  617. struct il_alive_resp *palive;
  618. struct delayed_work *pwork;
  619. palive = &pkt->u.alive_frame;
  620. D_INFO("Alive ucode status 0x%08X revision "
  621. "0x%01X 0x%01X\n",
  622. palive->is_valid, palive->ver_type,
  623. palive->ver_subtype);
  624. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  625. D_INFO("Initialization Alive received.\n");
  626. memcpy(&il->card_alive_init, &pkt->u.alive_frame,
  627. sizeof(struct il_alive_resp));
  628. pwork = &il->init_alive_start;
  629. } else {
  630. D_INFO("Runtime Alive received.\n");
  631. memcpy(&il->card_alive, &pkt->u.alive_frame,
  632. sizeof(struct il_alive_resp));
  633. pwork = &il->alive_start;
  634. il3945_disable_events(il);
  635. }
  636. /* We delay the ALIVE response by 5ms to
  637. * give the HW RF Kill time to activate... */
  638. if (palive->is_valid == UCODE_VALID_OK)
  639. queue_delayed_work(il->workqueue, pwork,
  640. msecs_to_jiffies(5));
  641. else
  642. IL_WARN("uCode did not respond OK.\n");
  643. }
  644. static void il3945_rx_reply_add_sta(struct il_priv *il,
  645. struct il_rx_buf *rxb)
  646. {
  647. #ifdef CONFIG_IWLEGACY_DEBUG
  648. struct il_rx_pkt *pkt = rxb_addr(rxb);
  649. #endif
  650. D_RX("Received C_ADD_STA: 0x%02X\n", pkt->u.status);
  651. }
  652. static void il3945_rx_beacon_notif(struct il_priv *il,
  653. struct il_rx_buf *rxb)
  654. {
  655. struct il_rx_pkt *pkt = rxb_addr(rxb);
  656. struct il3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  657. #ifdef CONFIG_IWLEGACY_DEBUG
  658. u8 rate = beacon->beacon_notify_hdr.rate;
  659. D_RX("beacon status %x retries %d iss %d "
  660. "tsf %d %d rate %d\n",
  661. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  662. beacon->beacon_notify_hdr.failure_frame,
  663. le32_to_cpu(beacon->ibss_mgr_status),
  664. le32_to_cpu(beacon->high_tsf),
  665. le32_to_cpu(beacon->low_tsf), rate);
  666. #endif
  667. il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
  668. }
  669. /* Handle notification from uCode that card's power state is changing
  670. * due to software, hardware, or critical temperature RFKILL */
  671. static void il3945_rx_card_state_notif(struct il_priv *il,
  672. struct il_rx_buf *rxb)
  673. {
  674. struct il_rx_pkt *pkt = rxb_addr(rxb);
  675. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  676. unsigned long status = il->status;
  677. IL_WARN("Card state received: HW:%s SW:%s\n",
  678. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  679. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  680. _il_wr(il, CSR_UCODE_DRV_GP1_SET,
  681. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  682. if (flags & HW_CARD_DISABLED)
  683. set_bit(S_RF_KILL_HW, &il->status);
  684. else
  685. clear_bit(S_RF_KILL_HW, &il->status);
  686. il_scan_cancel(il);
  687. if ((test_bit(S_RF_KILL_HW, &status) !=
  688. test_bit(S_RF_KILL_HW, &il->status)))
  689. wiphy_rfkill_set_hw_state(il->hw->wiphy,
  690. test_bit(S_RF_KILL_HW, &il->status));
  691. else
  692. wake_up(&il->wait_command_queue);
  693. }
  694. /**
  695. * il3945_setup_rx_handlers - Initialize Rx handler callbacks
  696. *
  697. * Setup the RX handlers for each of the reply types sent from the uCode
  698. * to the host.
  699. *
  700. * This function chains into the hardware specific files for them to setup
  701. * any hardware specific handlers as well.
  702. */
  703. static void il3945_setup_rx_handlers(struct il_priv *il)
  704. {
  705. il->rx_handlers[N_ALIVE] = il3945_rx_reply_alive;
  706. il->rx_handlers[C_ADD_STA] = il3945_rx_reply_add_sta;
  707. il->rx_handlers[N_ERROR] = il_rx_reply_error;
  708. il->rx_handlers[N_CHANNEL_SWITCH] = il_rx_csa;
  709. il->rx_handlers[N_SPECTRUM_MEASUREMENT] =
  710. il_rx_spectrum_measure_notif;
  711. il->rx_handlers[N_PM_SLEEP] = il_rx_pm_sleep_notif;
  712. il->rx_handlers[N_PM_DEBUG_STATS] =
  713. il_rx_pm_debug_stats_notif;
  714. il->rx_handlers[N_BEACON] = il3945_rx_beacon_notif;
  715. /*
  716. * The same handler is used for both the REPLY to a discrete
  717. * stats request from the host as well as for the periodic
  718. * stats notifications (after received beacons) from the uCode.
  719. */
  720. il->rx_handlers[C_STATS] = il3945_reply_stats;
  721. il->rx_handlers[N_STATS] = il3945_hw_rx_stats;
  722. il_setup_rx_scan_handlers(il);
  723. il->rx_handlers[N_CARD_STATE] = il3945_rx_card_state_notif;
  724. /* Set up hardware specific Rx handlers */
  725. il3945_hw_rx_handler_setup(il);
  726. }
  727. /************************** RX-FUNCTIONS ****************************/
  728. /*
  729. * Rx theory of operation
  730. *
  731. * The host allocates 32 DMA target addresses and passes the host address
  732. * to the firmware at register IL_RFDS_TBL_LOWER + N * RFD_SIZE where N is
  733. * 0 to 31
  734. *
  735. * Rx Queue Indexes
  736. * The host/firmware share two idx registers for managing the Rx buffers.
  737. *
  738. * The READ idx maps to the first position that the firmware may be writing
  739. * to -- the driver can read up to (but not including) this position and get
  740. * good data.
  741. * The READ idx is managed by the firmware once the card is enabled.
  742. *
  743. * The WRITE idx maps to the last position the driver has read from -- the
  744. * position preceding WRITE is the last slot the firmware can place a packet.
  745. *
  746. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  747. * WRITE = READ.
  748. *
  749. * During initialization, the host sets up the READ queue position to the first
  750. * IDX position, and WRITE to the last (READ - 1 wrapped)
  751. *
  752. * When the firmware places a packet in a buffer, it will advance the READ idx
  753. * and fire the RX interrupt. The driver can then query the READ idx and
  754. * process as many packets as possible, moving the WRITE idx forward as it
  755. * resets the Rx queue buffers with new memory.
  756. *
  757. * The management in the driver is as follows:
  758. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  759. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  760. * to replenish the iwl->rxq->rx_free.
  761. * + In il3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  762. * iwl->rxq is replenished and the READ IDX is updated (updating the
  763. * 'processed' and 'read' driver idxes as well)
  764. * + A received packet is processed and handed to the kernel network stack,
  765. * detached from the iwl->rxq. The driver 'processed' idx is updated.
  766. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  767. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  768. * IDX is not incremented and iwl->status(RX_STALLED) is set. If there
  769. * were enough free buffers and RX_STALLED is set it is cleared.
  770. *
  771. *
  772. * Driver sequence:
  773. *
  774. * il3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  775. * il3945_rx_queue_restock
  776. * il3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  777. * queue, updates firmware pointers, and updates
  778. * the WRITE idx. If insufficient rx_free buffers
  779. * are available, schedules il3945_rx_replenish
  780. *
  781. * -- enable interrupts --
  782. * ISR - il3945_rx() Detach il_rx_bufs from pool up to the
  783. * READ IDX, detaching the SKB from the pool.
  784. * Moves the packet buffer from queue to rx_used.
  785. * Calls il3945_rx_queue_restock to refill any empty
  786. * slots.
  787. * ...
  788. *
  789. */
  790. /**
  791. * il3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  792. */
  793. static inline __le32 il3945_dma_addr2rbd_ptr(struct il_priv *il,
  794. dma_addr_t dma_addr)
  795. {
  796. return cpu_to_le32((u32)dma_addr);
  797. }
  798. /**
  799. * il3945_rx_queue_restock - refill RX queue from pre-allocated pool
  800. *
  801. * If there are slots in the RX queue that need to be restocked,
  802. * and we have free pre-allocated buffers, fill the ranks as much
  803. * as we can, pulling from rx_free.
  804. *
  805. * This moves the 'write' idx forward to catch up with 'processed', and
  806. * also updates the memory address in the firmware to reference the new
  807. * target buffer.
  808. */
  809. static void il3945_rx_queue_restock(struct il_priv *il)
  810. {
  811. struct il_rx_queue *rxq = &il->rxq;
  812. struct list_head *element;
  813. struct il_rx_buf *rxb;
  814. unsigned long flags;
  815. int write;
  816. spin_lock_irqsave(&rxq->lock, flags);
  817. write = rxq->write & ~0x7;
  818. while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
  819. /* Get next free Rx buffer, remove from free list */
  820. element = rxq->rx_free.next;
  821. rxb = list_entry(element, struct il_rx_buf, list);
  822. list_del(element);
  823. /* Point to Rx buffer via next RBD in circular buffer */
  824. rxq->bd[rxq->write] = il3945_dma_addr2rbd_ptr(il, rxb->page_dma);
  825. rxq->queue[rxq->write] = rxb;
  826. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  827. rxq->free_count--;
  828. }
  829. spin_unlock_irqrestore(&rxq->lock, flags);
  830. /* If the pre-allocated buffer pool is dropping low, schedule to
  831. * refill it */
  832. if (rxq->free_count <= RX_LOW_WATERMARK)
  833. queue_work(il->workqueue, &il->rx_replenish);
  834. /* If we've added more space for the firmware to place data, tell it.
  835. * Increment device's write pointer in multiples of 8. */
  836. if (rxq->write_actual != (rxq->write & ~0x7) ||
  837. abs(rxq->write - rxq->read) > 7) {
  838. spin_lock_irqsave(&rxq->lock, flags);
  839. rxq->need_update = 1;
  840. spin_unlock_irqrestore(&rxq->lock, flags);
  841. il_rx_queue_update_write_ptr(il, rxq);
  842. }
  843. }
  844. /**
  845. * il3945_rx_replenish - Move all used packet from rx_used to rx_free
  846. *
  847. * When moving to rx_free an SKB is allocated for the slot.
  848. *
  849. * Also restock the Rx queue via il3945_rx_queue_restock.
  850. * This is called as a scheduled work item (except for during initialization)
  851. */
  852. static void il3945_rx_allocate(struct il_priv *il, gfp_t priority)
  853. {
  854. struct il_rx_queue *rxq = &il->rxq;
  855. struct list_head *element;
  856. struct il_rx_buf *rxb;
  857. struct page *page;
  858. unsigned long flags;
  859. gfp_t gfp_mask = priority;
  860. while (1) {
  861. spin_lock_irqsave(&rxq->lock, flags);
  862. if (list_empty(&rxq->rx_used)) {
  863. spin_unlock_irqrestore(&rxq->lock, flags);
  864. return;
  865. }
  866. spin_unlock_irqrestore(&rxq->lock, flags);
  867. if (rxq->free_count > RX_LOW_WATERMARK)
  868. gfp_mask |= __GFP_NOWARN;
  869. if (il->hw_params.rx_page_order > 0)
  870. gfp_mask |= __GFP_COMP;
  871. /* Alloc a new receive buffer */
  872. page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
  873. if (!page) {
  874. if (net_ratelimit())
  875. D_INFO("Failed to allocate SKB buffer.\n");
  876. if (rxq->free_count <= RX_LOW_WATERMARK &&
  877. net_ratelimit())
  878. IL_ERR("Failed to allocate SKB buffer with %s. Only %u free buffers remaining.\n",
  879. priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
  880. rxq->free_count);
  881. /* We don't reschedule replenish work here -- we will
  882. * call the restock method and if it still needs
  883. * more buffers it will schedule replenish */
  884. break;
  885. }
  886. spin_lock_irqsave(&rxq->lock, flags);
  887. if (list_empty(&rxq->rx_used)) {
  888. spin_unlock_irqrestore(&rxq->lock, flags);
  889. __free_pages(page, il->hw_params.rx_page_order);
  890. return;
  891. }
  892. element = rxq->rx_used.next;
  893. rxb = list_entry(element, struct il_rx_buf, list);
  894. list_del(element);
  895. spin_unlock_irqrestore(&rxq->lock, flags);
  896. rxb->page = page;
  897. /* Get physical address of RB/SKB */
  898. rxb->page_dma = pci_map_page(il->pci_dev, page, 0,
  899. PAGE_SIZE << il->hw_params.rx_page_order,
  900. PCI_DMA_FROMDEVICE);
  901. spin_lock_irqsave(&rxq->lock, flags);
  902. list_add_tail(&rxb->list, &rxq->rx_free);
  903. rxq->free_count++;
  904. il->alloc_rxb_page++;
  905. spin_unlock_irqrestore(&rxq->lock, flags);
  906. }
  907. }
  908. void il3945_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
  909. {
  910. unsigned long flags;
  911. int i;
  912. spin_lock_irqsave(&rxq->lock, flags);
  913. INIT_LIST_HEAD(&rxq->rx_free);
  914. INIT_LIST_HEAD(&rxq->rx_used);
  915. /* Fill the rx_used queue with _all_ of the Rx buffers */
  916. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  917. /* In the reset function, these buffers may have been allocated
  918. * to an SKB, so we need to unmap and free potential storage */
  919. if (rxq->pool[i].page != NULL) {
  920. pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
  921. PAGE_SIZE << il->hw_params.rx_page_order,
  922. PCI_DMA_FROMDEVICE);
  923. __il_free_pages(il, rxq->pool[i].page);
  924. rxq->pool[i].page = NULL;
  925. }
  926. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  927. }
  928. /* Set us so that we have processed and used all buffers, but have
  929. * not restocked the Rx queue with fresh buffers */
  930. rxq->read = rxq->write = 0;
  931. rxq->write_actual = 0;
  932. rxq->free_count = 0;
  933. spin_unlock_irqrestore(&rxq->lock, flags);
  934. }
  935. void il3945_rx_replenish(void *data)
  936. {
  937. struct il_priv *il = data;
  938. unsigned long flags;
  939. il3945_rx_allocate(il, GFP_KERNEL);
  940. spin_lock_irqsave(&il->lock, flags);
  941. il3945_rx_queue_restock(il);
  942. spin_unlock_irqrestore(&il->lock, flags);
  943. }
  944. static void il3945_rx_replenish_now(struct il_priv *il)
  945. {
  946. il3945_rx_allocate(il, GFP_ATOMIC);
  947. il3945_rx_queue_restock(il);
  948. }
  949. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  950. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  951. * This free routine walks the list of POOL entries and if SKB is set to
  952. * non NULL it is unmapped and freed
  953. */
  954. static void il3945_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
  955. {
  956. int i;
  957. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  958. if (rxq->pool[i].page != NULL) {
  959. pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
  960. PAGE_SIZE << il->hw_params.rx_page_order,
  961. PCI_DMA_FROMDEVICE);
  962. __il_free_pages(il, rxq->pool[i].page);
  963. rxq->pool[i].page = NULL;
  964. }
  965. }
  966. dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  967. rxq->bd_dma);
  968. dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
  969. rxq->rb_stts, rxq->rb_stts_dma);
  970. rxq->bd = NULL;
  971. rxq->rb_stts = NULL;
  972. }
  973. /* Convert linear signal-to-noise ratio into dB */
  974. static u8 ratio2dB[100] = {
  975. /* 0 1 2 3 4 5 6 7 8 9 */
  976. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  977. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  978. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  979. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  980. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  981. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  982. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  983. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  984. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  985. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  986. };
  987. /* Calculates a relative dB value from a ratio of linear
  988. * (i.e. not dB) signal levels.
  989. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  990. int il3945_calc_db_from_ratio(int sig_ratio)
  991. {
  992. /* 1000:1 or higher just report as 60 dB */
  993. if (sig_ratio >= 1000)
  994. return 60;
  995. /* 100:1 or higher, divide by 10 and use table,
  996. * add 20 dB to make up for divide by 10 */
  997. if (sig_ratio >= 100)
  998. return 20 + (int)ratio2dB[sig_ratio/10];
  999. /* We shouldn't see this */
  1000. if (sig_ratio < 1)
  1001. return 0;
  1002. /* Use table for ratios 1:1 - 99:1 */
  1003. return (int)ratio2dB[sig_ratio];
  1004. }
  1005. /**
  1006. * il3945_rx_handle - Main entry function for receiving responses from uCode
  1007. *
  1008. * Uses the il->rx_handlers callback function array to invoke
  1009. * the appropriate handlers, including command responses,
  1010. * frame-received notifications, and other notifications.
  1011. */
  1012. static void il3945_rx_handle(struct il_priv *il)
  1013. {
  1014. struct il_rx_buf *rxb;
  1015. struct il_rx_pkt *pkt;
  1016. struct il_rx_queue *rxq = &il->rxq;
  1017. u32 r, i;
  1018. int reclaim;
  1019. unsigned long flags;
  1020. u8 fill_rx = 0;
  1021. u32 count = 8;
  1022. int total_empty = 0;
  1023. /* uCode's read idx (stored in shared DRAM) indicates the last Rx
  1024. * buffer that the driver may process (last buffer filled by ucode). */
  1025. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  1026. i = rxq->read;
  1027. /* calculate total frames need to be restock after handling RX */
  1028. total_empty = r - rxq->write_actual;
  1029. if (total_empty < 0)
  1030. total_empty += RX_QUEUE_SIZE;
  1031. if (total_empty > (RX_QUEUE_SIZE / 2))
  1032. fill_rx = 1;
  1033. /* Rx interrupt, but nothing sent from uCode */
  1034. if (i == r)
  1035. D_RX("r = %d, i = %d\n", r, i);
  1036. while (i != r) {
  1037. int len;
  1038. rxb = rxq->queue[i];
  1039. /* If an RXB doesn't have a Rx queue slot associated with it,
  1040. * then a bug has been introduced in the queue refilling
  1041. * routines -- catch it here */
  1042. BUG_ON(rxb == NULL);
  1043. rxq->queue[i] = NULL;
  1044. pci_unmap_page(il->pci_dev, rxb->page_dma,
  1045. PAGE_SIZE << il->hw_params.rx_page_order,
  1046. PCI_DMA_FROMDEVICE);
  1047. pkt = rxb_addr(rxb);
  1048. len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  1049. len += sizeof(u32); /* account for status word */
  1050. /* Reclaim a command buffer only if this packet is a response
  1051. * to a (driver-originated) command.
  1052. * If the packet (e.g. Rx frame) originated from uCode,
  1053. * there is no command buffer to reclaim.
  1054. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  1055. * but apparently a few don't get set; catch them here. */
  1056. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  1057. pkt->hdr.cmd != N_STATS &&
  1058. pkt->hdr.cmd != C_TX;
  1059. /* Based on type of command response or notification,
  1060. * handle those that need handling via function in
  1061. * rx_handlers table. See il3945_setup_rx_handlers() */
  1062. if (il->rx_handlers[pkt->hdr.cmd]) {
  1063. D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i,
  1064. il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  1065. il->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  1066. il->rx_handlers[pkt->hdr.cmd] (il, rxb);
  1067. } else {
  1068. /* No handling needed */
  1069. D_RX(
  1070. "r %d i %d No handler needed for %s, 0x%02x\n",
  1071. r, i, il_get_cmd_string(pkt->hdr.cmd),
  1072. pkt->hdr.cmd);
  1073. }
  1074. /*
  1075. * XXX: After here, we should always check rxb->page
  1076. * against NULL before touching it or its virtual
  1077. * memory (pkt). Because some rx_handler might have
  1078. * already taken or freed the pages.
  1079. */
  1080. if (reclaim) {
  1081. /* Invoke any callbacks, transfer the buffer to caller,
  1082. * and fire off the (possibly) blocking il_send_cmd()
  1083. * as we reclaim the driver command queue */
  1084. if (rxb->page)
  1085. il_tx_cmd_complete(il, rxb);
  1086. else
  1087. IL_WARN("Claim null rxb?\n");
  1088. }
  1089. /* Reuse the page if possible. For notification packets and
  1090. * SKBs that fail to Rx correctly, add them back into the
  1091. * rx_free list for reuse later. */
  1092. spin_lock_irqsave(&rxq->lock, flags);
  1093. if (rxb->page != NULL) {
  1094. rxb->page_dma = pci_map_page(il->pci_dev, rxb->page,
  1095. 0, PAGE_SIZE << il->hw_params.rx_page_order,
  1096. PCI_DMA_FROMDEVICE);
  1097. list_add_tail(&rxb->list, &rxq->rx_free);
  1098. rxq->free_count++;
  1099. } else
  1100. list_add_tail(&rxb->list, &rxq->rx_used);
  1101. spin_unlock_irqrestore(&rxq->lock, flags);
  1102. i = (i + 1) & RX_QUEUE_MASK;
  1103. /* If there are a lot of unused frames,
  1104. * restock the Rx queue so ucode won't assert. */
  1105. if (fill_rx) {
  1106. count++;
  1107. if (count >= 8) {
  1108. rxq->read = i;
  1109. il3945_rx_replenish_now(il);
  1110. count = 0;
  1111. }
  1112. }
  1113. }
  1114. /* Backtrack one entry */
  1115. rxq->read = i;
  1116. if (fill_rx)
  1117. il3945_rx_replenish_now(il);
  1118. else
  1119. il3945_rx_queue_restock(il);
  1120. }
  1121. /* call this function to flush any scheduled tasklet */
  1122. static inline void il3945_synchronize_irq(struct il_priv *il)
  1123. {
  1124. /* wait to make sure we flush pending tasklet*/
  1125. synchronize_irq(il->pci_dev->irq);
  1126. tasklet_kill(&il->irq_tasklet);
  1127. }
  1128. static const char *il3945_desc_lookup(int i)
  1129. {
  1130. switch (i) {
  1131. case 1:
  1132. return "FAIL";
  1133. case 2:
  1134. return "BAD_PARAM";
  1135. case 3:
  1136. return "BAD_CHECKSUM";
  1137. case 4:
  1138. return "NMI_INTERRUPT";
  1139. case 5:
  1140. return "SYSASSERT";
  1141. case 6:
  1142. return "FATAL_ERROR";
  1143. }
  1144. return "UNKNOWN";
  1145. }
  1146. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1147. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1148. void il3945_dump_nic_error_log(struct il_priv *il)
  1149. {
  1150. u32 i;
  1151. u32 desc, time, count, base, data1;
  1152. u32 blink1, blink2, ilink1, ilink2;
  1153. base = le32_to_cpu(il->card_alive.error_event_table_ptr);
  1154. if (!il3945_hw_valid_rtc_data_addr(base)) {
  1155. IL_ERR("Not valid error log pointer 0x%08X\n", base);
  1156. return;
  1157. }
  1158. count = il_read_targ_mem(il, base);
  1159. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1160. IL_ERR("Start IWL Error Log Dump:\n");
  1161. IL_ERR("Status: 0x%08lX, count: %d\n",
  1162. il->status, count);
  1163. }
  1164. IL_ERR("Desc Time asrtPC blink2 "
  1165. "ilink1 nmiPC Line\n");
  1166. for (i = ERROR_START_OFFSET;
  1167. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  1168. i += ERROR_ELEM_SIZE) {
  1169. desc = il_read_targ_mem(il, base + i);
  1170. time =
  1171. il_read_targ_mem(il, base + i + 1 * sizeof(u32));
  1172. blink1 =
  1173. il_read_targ_mem(il, base + i + 2 * sizeof(u32));
  1174. blink2 =
  1175. il_read_targ_mem(il, base + i + 3 * sizeof(u32));
  1176. ilink1 =
  1177. il_read_targ_mem(il, base + i + 4 * sizeof(u32));
  1178. ilink2 =
  1179. il_read_targ_mem(il, base + i + 5 * sizeof(u32));
  1180. data1 =
  1181. il_read_targ_mem(il, base + i + 6 * sizeof(u32));
  1182. IL_ERR(
  1183. "%-13s (0x%X) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  1184. il3945_desc_lookup(desc), desc, time, blink1, blink2,
  1185. ilink1, ilink2, data1);
  1186. }
  1187. }
  1188. static void il3945_irq_tasklet(struct il_priv *il)
  1189. {
  1190. u32 inta, handled = 0;
  1191. u32 inta_fh;
  1192. unsigned long flags;
  1193. #ifdef CONFIG_IWLEGACY_DEBUG
  1194. u32 inta_mask;
  1195. #endif
  1196. spin_lock_irqsave(&il->lock, flags);
  1197. /* Ack/clear/reset pending uCode interrupts.
  1198. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  1199. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  1200. inta = _il_rd(il, CSR_INT);
  1201. _il_wr(il, CSR_INT, inta);
  1202. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  1203. * Any new interrupts that happen after this, either while we're
  1204. * in this tasklet, or later, will show up in next ISR/tasklet. */
  1205. inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
  1206. _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
  1207. #ifdef CONFIG_IWLEGACY_DEBUG
  1208. if (il_get_debug_level(il) & IL_DL_ISR) {
  1209. /* just for debug */
  1210. inta_mask = _il_rd(il, CSR_INT_MASK);
  1211. D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  1212. inta, inta_mask, inta_fh);
  1213. }
  1214. #endif
  1215. spin_unlock_irqrestore(&il->lock, flags);
  1216. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  1217. * atomic, make sure that inta covers all the interrupts that
  1218. * we've discovered, even if FH interrupt came in just after
  1219. * reading CSR_INT. */
  1220. if (inta_fh & CSR39_FH_INT_RX_MASK)
  1221. inta |= CSR_INT_BIT_FH_RX;
  1222. if (inta_fh & CSR39_FH_INT_TX_MASK)
  1223. inta |= CSR_INT_BIT_FH_TX;
  1224. /* Now service all interrupt bits discovered above. */
  1225. if (inta & CSR_INT_BIT_HW_ERR) {
  1226. IL_ERR("Hardware error detected. Restarting.\n");
  1227. /* Tell the device to stop sending interrupts */
  1228. il_disable_interrupts(il);
  1229. il->isr_stats.hw++;
  1230. il_irq_handle_error(il);
  1231. handled |= CSR_INT_BIT_HW_ERR;
  1232. return;
  1233. }
  1234. #ifdef CONFIG_IWLEGACY_DEBUG
  1235. if (il_get_debug_level(il) & (IL_DL_ISR)) {
  1236. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  1237. if (inta & CSR_INT_BIT_SCD) {
  1238. D_ISR("Scheduler finished to transmit "
  1239. "the frame/frames.\n");
  1240. il->isr_stats.sch++;
  1241. }
  1242. /* Alive notification via Rx interrupt will do the real work */
  1243. if (inta & CSR_INT_BIT_ALIVE) {
  1244. D_ISR("Alive interrupt\n");
  1245. il->isr_stats.alive++;
  1246. }
  1247. }
  1248. #endif
  1249. /* Safely ignore these bits for debug checks below */
  1250. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  1251. /* Error detected by uCode */
  1252. if (inta & CSR_INT_BIT_SW_ERR) {
  1253. IL_ERR("Microcode SW error detected. "
  1254. "Restarting 0x%X.\n", inta);
  1255. il->isr_stats.sw++;
  1256. il_irq_handle_error(il);
  1257. handled |= CSR_INT_BIT_SW_ERR;
  1258. }
  1259. /* uCode wakes up after power-down sleep */
  1260. if (inta & CSR_INT_BIT_WAKEUP) {
  1261. D_ISR("Wakeup interrupt\n");
  1262. il_rx_queue_update_write_ptr(il, &il->rxq);
  1263. il_txq_update_write_ptr(il, &il->txq[0]);
  1264. il_txq_update_write_ptr(il, &il->txq[1]);
  1265. il_txq_update_write_ptr(il, &il->txq[2]);
  1266. il_txq_update_write_ptr(il, &il->txq[3]);
  1267. il_txq_update_write_ptr(il, &il->txq[4]);
  1268. il_txq_update_write_ptr(il, &il->txq[5]);
  1269. il->isr_stats.wakeup++;
  1270. handled |= CSR_INT_BIT_WAKEUP;
  1271. }
  1272. /* All uCode command responses, including Tx command responses,
  1273. * Rx "responses" (frame-received notification), and other
  1274. * notifications from uCode come through here*/
  1275. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1276. il3945_rx_handle(il);
  1277. il->isr_stats.rx++;
  1278. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1279. }
  1280. if (inta & CSR_INT_BIT_FH_TX) {
  1281. D_ISR("Tx interrupt\n");
  1282. il->isr_stats.tx++;
  1283. _il_wr(il, CSR_FH_INT_STATUS, (1 << 6));
  1284. il_wr(il, FH39_TCSR_CREDIT
  1285. (FH39_SRVC_CHNL), 0x0);
  1286. handled |= CSR_INT_BIT_FH_TX;
  1287. }
  1288. if (inta & ~handled) {
  1289. IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1290. il->isr_stats.unhandled++;
  1291. }
  1292. if (inta & ~il->inta_mask) {
  1293. IL_WARN("Disabled INTA bits 0x%08x were pending\n",
  1294. inta & ~il->inta_mask);
  1295. IL_WARN(" with FH_INT = 0x%08x\n", inta_fh);
  1296. }
  1297. /* Re-enable all interrupts */
  1298. /* only Re-enable if disabled by irq */
  1299. if (test_bit(S_INT_ENABLED, &il->status))
  1300. il_enable_interrupts(il);
  1301. #ifdef CONFIG_IWLEGACY_DEBUG
  1302. if (il_get_debug_level(il) & (IL_DL_ISR)) {
  1303. inta = _il_rd(il, CSR_INT);
  1304. inta_mask = _il_rd(il, CSR_INT_MASK);
  1305. inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
  1306. D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  1307. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  1308. }
  1309. #endif
  1310. }
  1311. static int il3945_get_channels_for_scan(struct il_priv *il,
  1312. enum ieee80211_band band,
  1313. u8 is_active, u8 n_probes,
  1314. struct il3945_scan_channel *scan_ch,
  1315. struct ieee80211_vif *vif)
  1316. {
  1317. struct ieee80211_channel *chan;
  1318. const struct ieee80211_supported_band *sband;
  1319. const struct il_channel_info *ch_info;
  1320. u16 passive_dwell = 0;
  1321. u16 active_dwell = 0;
  1322. int added, i;
  1323. sband = il_get_hw_mode(il, band);
  1324. if (!sband)
  1325. return 0;
  1326. active_dwell = il_get_active_dwell_time(il, band, n_probes);
  1327. passive_dwell = il_get_passive_dwell_time(il, band, vif);
  1328. if (passive_dwell <= active_dwell)
  1329. passive_dwell = active_dwell + 1;
  1330. for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
  1331. chan = il->scan_request->channels[i];
  1332. if (chan->band != band)
  1333. continue;
  1334. scan_ch->channel = chan->hw_value;
  1335. ch_info = il_get_channel_info(il, band,
  1336. scan_ch->channel);
  1337. if (!il_is_channel_valid(ch_info)) {
  1338. D_SCAN(
  1339. "Channel %d is INVALID for this band.\n",
  1340. scan_ch->channel);
  1341. continue;
  1342. }
  1343. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  1344. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  1345. /* If passive , set up for auto-switch
  1346. * and use long active_dwell time.
  1347. */
  1348. if (!is_active || il_is_channel_passive(ch_info) ||
  1349. (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
  1350. scan_ch->type = 0; /* passive */
  1351. if (IL_UCODE_API(il->ucode_ver) == 1)
  1352. scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
  1353. } else {
  1354. scan_ch->type = 1; /* active */
  1355. }
  1356. /* Set direct probe bits. These may be used both for active
  1357. * scan channels (probes gets sent right away),
  1358. * or for passive channels (probes get se sent only after
  1359. * hearing clear Rx packet).*/
  1360. if (IL_UCODE_API(il->ucode_ver) >= 2) {
  1361. if (n_probes)
  1362. scan_ch->type |= IL39_SCAN_PROBE_MASK(n_probes);
  1363. } else {
  1364. /* uCode v1 does not allow setting direct probe bits on
  1365. * passive channel. */
  1366. if ((scan_ch->type & 1) && n_probes)
  1367. scan_ch->type |= IL39_SCAN_PROBE_MASK(n_probes);
  1368. }
  1369. /* Set txpower levels to defaults */
  1370. scan_ch->tpc.dsp_atten = 110;
  1371. /* scan_pwr_info->tpc.dsp_atten; */
  1372. /*scan_pwr_info->tpc.tx_gain; */
  1373. if (band == IEEE80211_BAND_5GHZ)
  1374. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  1375. else {
  1376. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  1377. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  1378. * power level:
  1379. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  1380. */
  1381. }
  1382. D_SCAN("Scanning %d [%s %d]\n",
  1383. scan_ch->channel,
  1384. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  1385. (scan_ch->type & 1) ?
  1386. active_dwell : passive_dwell);
  1387. scan_ch++;
  1388. added++;
  1389. }
  1390. D_SCAN("total channels to scan %d\n", added);
  1391. return added;
  1392. }
  1393. static void il3945_init_hw_rates(struct il_priv *il,
  1394. struct ieee80211_rate *rates)
  1395. {
  1396. int i;
  1397. for (i = 0; i < RATE_COUNT_LEGACY; i++) {
  1398. rates[i].bitrate = il3945_rates[i].ieee * 5;
  1399. rates[i].hw_value = i; /* Rate scaling will work on idxes */
  1400. rates[i].hw_value_short = i;
  1401. rates[i].flags = 0;
  1402. if (i > IL39_LAST_OFDM_RATE || i < IL_FIRST_OFDM_RATE) {
  1403. /*
  1404. * If CCK != 1M then set short preamble rate flag.
  1405. */
  1406. rates[i].flags |= (il3945_rates[i].plcp == 10) ?
  1407. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  1408. }
  1409. }
  1410. }
  1411. /******************************************************************************
  1412. *
  1413. * uCode download functions
  1414. *
  1415. ******************************************************************************/
  1416. static void il3945_dealloc_ucode_pci(struct il_priv *il)
  1417. {
  1418. il_free_fw_desc(il->pci_dev, &il->ucode_code);
  1419. il_free_fw_desc(il->pci_dev, &il->ucode_data);
  1420. il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
  1421. il_free_fw_desc(il->pci_dev, &il->ucode_init);
  1422. il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
  1423. il_free_fw_desc(il->pci_dev, &il->ucode_boot);
  1424. }
  1425. /**
  1426. * il3945_verify_inst_full - verify runtime uCode image in card vs. host,
  1427. * looking at all data.
  1428. */
  1429. static int il3945_verify_inst_full(struct il_priv *il, __le32 *image, u32 len)
  1430. {
  1431. u32 val;
  1432. u32 save_len = len;
  1433. int rc = 0;
  1434. u32 errcnt;
  1435. D_INFO("ucode inst image size is %u\n", len);
  1436. il_wr(il, HBUS_TARG_MEM_RADDR,
  1437. IL39_RTC_INST_LOWER_BOUND);
  1438. errcnt = 0;
  1439. for (; len > 0; len -= sizeof(u32), image++) {
  1440. /* read data comes through single port, auto-incr addr */
  1441. /* NOTE: Use the debugless read so we don't flood kernel log
  1442. * if IL_DL_IO is set */
  1443. val = _il_rd(il, HBUS_TARG_MEM_RDAT);
  1444. if (val != le32_to_cpu(*image)) {
  1445. IL_ERR("uCode INST section is invalid at "
  1446. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  1447. save_len - len, val, le32_to_cpu(*image));
  1448. rc = -EIO;
  1449. errcnt++;
  1450. if (errcnt >= 20)
  1451. break;
  1452. }
  1453. }
  1454. if (!errcnt)
  1455. D_INFO(
  1456. "ucode image in INSTRUCTION memory is good\n");
  1457. return rc;
  1458. }
  1459. /**
  1460. * il3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  1461. * using sample data 100 bytes apart. If these sample points are good,
  1462. * it's a pretty good bet that everything between them is good, too.
  1463. */
  1464. static int il3945_verify_inst_sparse(struct il_priv *il, __le32 *image, u32 len)
  1465. {
  1466. u32 val;
  1467. int rc = 0;
  1468. u32 errcnt = 0;
  1469. u32 i;
  1470. D_INFO("ucode inst image size is %u\n", len);
  1471. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  1472. /* read data comes through single port, auto-incr addr */
  1473. /* NOTE: Use the debugless read so we don't flood kernel log
  1474. * if IL_DL_IO is set */
  1475. il_wr(il, HBUS_TARG_MEM_RADDR,
  1476. i + IL39_RTC_INST_LOWER_BOUND);
  1477. val = _il_rd(il, HBUS_TARG_MEM_RDAT);
  1478. if (val != le32_to_cpu(*image)) {
  1479. #if 0 /* Enable this if you want to see details */
  1480. IL_ERR("uCode INST section is invalid at "
  1481. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  1482. i, val, *image);
  1483. #endif
  1484. rc = -EIO;
  1485. errcnt++;
  1486. if (errcnt >= 3)
  1487. break;
  1488. }
  1489. }
  1490. return rc;
  1491. }
  1492. /**
  1493. * il3945_verify_ucode - determine which instruction image is in SRAM,
  1494. * and verify its contents
  1495. */
  1496. static int il3945_verify_ucode(struct il_priv *il)
  1497. {
  1498. __le32 *image;
  1499. u32 len;
  1500. int rc = 0;
  1501. /* Try bootstrap */
  1502. image = (__le32 *)il->ucode_boot.v_addr;
  1503. len = il->ucode_boot.len;
  1504. rc = il3945_verify_inst_sparse(il, image, len);
  1505. if (rc == 0) {
  1506. D_INFO("Bootstrap uCode is good in inst SRAM\n");
  1507. return 0;
  1508. }
  1509. /* Try initialize */
  1510. image = (__le32 *)il->ucode_init.v_addr;
  1511. len = il->ucode_init.len;
  1512. rc = il3945_verify_inst_sparse(il, image, len);
  1513. if (rc == 0) {
  1514. D_INFO("Initialize uCode is good in inst SRAM\n");
  1515. return 0;
  1516. }
  1517. /* Try runtime/protocol */
  1518. image = (__le32 *)il->ucode_code.v_addr;
  1519. len = il->ucode_code.len;
  1520. rc = il3945_verify_inst_sparse(il, image, len);
  1521. if (rc == 0) {
  1522. D_INFO("Runtime uCode is good in inst SRAM\n");
  1523. return 0;
  1524. }
  1525. IL_ERR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  1526. /* Since nothing seems to match, show first several data entries in
  1527. * instruction SRAM, so maybe visual inspection will give a clue.
  1528. * Selection of bootstrap image (vs. other images) is arbitrary. */
  1529. image = (__le32 *)il->ucode_boot.v_addr;
  1530. len = il->ucode_boot.len;
  1531. rc = il3945_verify_inst_full(il, image, len);
  1532. return rc;
  1533. }
  1534. static void il3945_nic_start(struct il_priv *il)
  1535. {
  1536. /* Remove all resets to allow NIC to operate */
  1537. _il_wr(il, CSR_RESET, 0);
  1538. }
  1539. #define IL3945_UCODE_GET(item) \
  1540. static u32 il3945_ucode_get_##item(const struct il_ucode_header *ucode)\
  1541. { \
  1542. return le32_to_cpu(ucode->v1.item); \
  1543. }
  1544. static u32 il3945_ucode_get_header_size(u32 api_ver)
  1545. {
  1546. return 24;
  1547. }
  1548. static u8 *il3945_ucode_get_data(const struct il_ucode_header *ucode)
  1549. {
  1550. return (u8 *) ucode->v1.data;
  1551. }
  1552. IL3945_UCODE_GET(inst_size);
  1553. IL3945_UCODE_GET(data_size);
  1554. IL3945_UCODE_GET(init_size);
  1555. IL3945_UCODE_GET(init_data_size);
  1556. IL3945_UCODE_GET(boot_size);
  1557. /**
  1558. * il3945_read_ucode - Read uCode images from disk file.
  1559. *
  1560. * Copy into buffers for card to fetch via bus-mastering
  1561. */
  1562. static int il3945_read_ucode(struct il_priv *il)
  1563. {
  1564. const struct il_ucode_header *ucode;
  1565. int ret = -EINVAL, idx;
  1566. const struct firmware *ucode_raw;
  1567. /* firmware file name contains uCode/driver compatibility version */
  1568. const char *name_pre = il->cfg->fw_name_pre;
  1569. const unsigned int api_max = il->cfg->ucode_api_max;
  1570. const unsigned int api_min = il->cfg->ucode_api_min;
  1571. char buf[25];
  1572. u8 *src;
  1573. size_t len;
  1574. u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
  1575. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1576. * request_firmware() is synchronous, file is in memory on return. */
  1577. for (idx = api_max; idx >= api_min; idx--) {
  1578. sprintf(buf, "%s%u%s", name_pre, idx, ".ucode");
  1579. ret = request_firmware(&ucode_raw, buf, &il->pci_dev->dev);
  1580. if (ret < 0) {
  1581. IL_ERR("%s firmware file req failed: %d\n",
  1582. buf, ret);
  1583. if (ret == -ENOENT)
  1584. continue;
  1585. else
  1586. goto error;
  1587. } else {
  1588. if (idx < api_max)
  1589. IL_ERR("Loaded firmware %s, "
  1590. "which is deprecated. "
  1591. " Please use API v%u instead.\n",
  1592. buf, api_max);
  1593. D_INFO("Got firmware '%s' file "
  1594. "(%zd bytes) from disk\n",
  1595. buf, ucode_raw->size);
  1596. break;
  1597. }
  1598. }
  1599. if (ret < 0)
  1600. goto error;
  1601. /* Make sure that we got at least our header! */
  1602. if (ucode_raw->size < il3945_ucode_get_header_size(1)) {
  1603. IL_ERR("File size way too small!\n");
  1604. ret = -EINVAL;
  1605. goto err_release;
  1606. }
  1607. /* Data from ucode file: header followed by uCode images */
  1608. ucode = (struct il_ucode_header *)ucode_raw->data;
  1609. il->ucode_ver = le32_to_cpu(ucode->ver);
  1610. api_ver = IL_UCODE_API(il->ucode_ver);
  1611. inst_size = il3945_ucode_get_inst_size(ucode);
  1612. data_size = il3945_ucode_get_data_size(ucode);
  1613. init_size = il3945_ucode_get_init_size(ucode);
  1614. init_data_size = il3945_ucode_get_init_data_size(ucode);
  1615. boot_size = il3945_ucode_get_boot_size(ucode);
  1616. src = il3945_ucode_get_data(ucode);
  1617. /* api_ver should match the api version forming part of the
  1618. * firmware filename ... but we don't check for that and only rely
  1619. * on the API version read from firmware header from here on forward */
  1620. if (api_ver < api_min || api_ver > api_max) {
  1621. IL_ERR("Driver unable to support your firmware API. "
  1622. "Driver supports v%u, firmware is v%u.\n",
  1623. api_max, api_ver);
  1624. il->ucode_ver = 0;
  1625. ret = -EINVAL;
  1626. goto err_release;
  1627. }
  1628. if (api_ver != api_max)
  1629. IL_ERR("Firmware has old API version. Expected %u, "
  1630. "got %u. New firmware can be obtained "
  1631. "from http://www.intellinuxwireless.org.\n",
  1632. api_max, api_ver);
  1633. IL_INFO("loaded firmware version %u.%u.%u.%u\n",
  1634. IL_UCODE_MAJOR(il->ucode_ver),
  1635. IL_UCODE_MINOR(il->ucode_ver),
  1636. IL_UCODE_API(il->ucode_ver),
  1637. IL_UCODE_SERIAL(il->ucode_ver));
  1638. snprintf(il->hw->wiphy->fw_version,
  1639. sizeof(il->hw->wiphy->fw_version),
  1640. "%u.%u.%u.%u",
  1641. IL_UCODE_MAJOR(il->ucode_ver),
  1642. IL_UCODE_MINOR(il->ucode_ver),
  1643. IL_UCODE_API(il->ucode_ver),
  1644. IL_UCODE_SERIAL(il->ucode_ver));
  1645. D_INFO("f/w package hdr ucode version raw = 0x%x\n",
  1646. il->ucode_ver);
  1647. D_INFO("f/w package hdr runtime inst size = %u\n",
  1648. inst_size);
  1649. D_INFO("f/w package hdr runtime data size = %u\n",
  1650. data_size);
  1651. D_INFO("f/w package hdr init inst size = %u\n",
  1652. init_size);
  1653. D_INFO("f/w package hdr init data size = %u\n",
  1654. init_data_size);
  1655. D_INFO("f/w package hdr boot inst size = %u\n",
  1656. boot_size);
  1657. /* Verify size of file vs. image size info in file's header */
  1658. if (ucode_raw->size != il3945_ucode_get_header_size(api_ver) +
  1659. inst_size + data_size + init_size +
  1660. init_data_size + boot_size) {
  1661. D_INFO(
  1662. "uCode file size %zd does not match expected size\n",
  1663. ucode_raw->size);
  1664. ret = -EINVAL;
  1665. goto err_release;
  1666. }
  1667. /* Verify that uCode images will fit in card's SRAM */
  1668. if (inst_size > IL39_MAX_INST_SIZE) {
  1669. D_INFO("uCode instr len %d too large to fit in\n",
  1670. inst_size);
  1671. ret = -EINVAL;
  1672. goto err_release;
  1673. }
  1674. if (data_size > IL39_MAX_DATA_SIZE) {
  1675. D_INFO("uCode data len %d too large to fit in\n",
  1676. data_size);
  1677. ret = -EINVAL;
  1678. goto err_release;
  1679. }
  1680. if (init_size > IL39_MAX_INST_SIZE) {
  1681. D_INFO(
  1682. "uCode init instr len %d too large to fit in\n",
  1683. init_size);
  1684. ret = -EINVAL;
  1685. goto err_release;
  1686. }
  1687. if (init_data_size > IL39_MAX_DATA_SIZE) {
  1688. D_INFO(
  1689. "uCode init data len %d too large to fit in\n",
  1690. init_data_size);
  1691. ret = -EINVAL;
  1692. goto err_release;
  1693. }
  1694. if (boot_size > IL39_MAX_BSM_SIZE) {
  1695. D_INFO(
  1696. "uCode boot instr len %d too large to fit in\n",
  1697. boot_size);
  1698. ret = -EINVAL;
  1699. goto err_release;
  1700. }
  1701. /* Allocate ucode buffers for card's bus-master loading ... */
  1702. /* Runtime instructions and 2 copies of data:
  1703. * 1) unmodified from disk
  1704. * 2) backup cache for save/restore during power-downs */
  1705. il->ucode_code.len = inst_size;
  1706. il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
  1707. il->ucode_data.len = data_size;
  1708. il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
  1709. il->ucode_data_backup.len = data_size;
  1710. il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
  1711. if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
  1712. !il->ucode_data_backup.v_addr)
  1713. goto err_pci_alloc;
  1714. /* Initialization instructions and data */
  1715. if (init_size && init_data_size) {
  1716. il->ucode_init.len = init_size;
  1717. il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
  1718. il->ucode_init_data.len = init_data_size;
  1719. il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
  1720. if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
  1721. goto err_pci_alloc;
  1722. }
  1723. /* Bootstrap (instructions only, no data) */
  1724. if (boot_size) {
  1725. il->ucode_boot.len = boot_size;
  1726. il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
  1727. if (!il->ucode_boot.v_addr)
  1728. goto err_pci_alloc;
  1729. }
  1730. /* Copy images into buffers for card's bus-master reads ... */
  1731. /* Runtime instructions (first block of data in file) */
  1732. len = inst_size;
  1733. D_INFO(
  1734. "Copying (but not loading) uCode instr len %zd\n", len);
  1735. memcpy(il->ucode_code.v_addr, src, len);
  1736. src += len;
  1737. D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1738. il->ucode_code.v_addr, (u32)il->ucode_code.p_addr);
  1739. /* Runtime data (2nd block)
  1740. * NOTE: Copy into backup buffer will be done in il3945_up() */
  1741. len = data_size;
  1742. D_INFO(
  1743. "Copying (but not loading) uCode data len %zd\n", len);
  1744. memcpy(il->ucode_data.v_addr, src, len);
  1745. memcpy(il->ucode_data_backup.v_addr, src, len);
  1746. src += len;
  1747. /* Initialization instructions (3rd block) */
  1748. if (init_size) {
  1749. len = init_size;
  1750. D_INFO(
  1751. "Copying (but not loading) init instr len %zd\n", len);
  1752. memcpy(il->ucode_init.v_addr, src, len);
  1753. src += len;
  1754. }
  1755. /* Initialization data (4th block) */
  1756. if (init_data_size) {
  1757. len = init_data_size;
  1758. D_INFO(
  1759. "Copying (but not loading) init data len %zd\n", len);
  1760. memcpy(il->ucode_init_data.v_addr, src, len);
  1761. src += len;
  1762. }
  1763. /* Bootstrap instructions (5th block) */
  1764. len = boot_size;
  1765. D_INFO(
  1766. "Copying (but not loading) boot instr len %zd\n", len);
  1767. memcpy(il->ucode_boot.v_addr, src, len);
  1768. /* We have our copies now, allow OS release its copies */
  1769. release_firmware(ucode_raw);
  1770. return 0;
  1771. err_pci_alloc:
  1772. IL_ERR("failed to allocate pci memory\n");
  1773. ret = -ENOMEM;
  1774. il3945_dealloc_ucode_pci(il);
  1775. err_release:
  1776. release_firmware(ucode_raw);
  1777. error:
  1778. return ret;
  1779. }
  1780. /**
  1781. * il3945_set_ucode_ptrs - Set uCode address location
  1782. *
  1783. * Tell initialization uCode where to find runtime uCode.
  1784. *
  1785. * BSM registers initially contain pointers to initialization uCode.
  1786. * We need to replace them to load runtime uCode inst and data,
  1787. * and to save runtime data when powering down.
  1788. */
  1789. static int il3945_set_ucode_ptrs(struct il_priv *il)
  1790. {
  1791. dma_addr_t pinst;
  1792. dma_addr_t pdata;
  1793. /* bits 31:0 for 3945 */
  1794. pinst = il->ucode_code.p_addr;
  1795. pdata = il->ucode_data_backup.p_addr;
  1796. /* Tell bootstrap uCode where to find image to load */
  1797. il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
  1798. il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
  1799. il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG,
  1800. il->ucode_data.len);
  1801. /* Inst byte count must be last to set up, bit 31 signals uCode
  1802. * that all new ptr/size info is in place */
  1803. il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG,
  1804. il->ucode_code.len | BSM_DRAM_INST_LOAD);
  1805. D_INFO("Runtime uCode pointers are set.\n");
  1806. return 0;
  1807. }
  1808. /**
  1809. * il3945_init_alive_start - Called after N_ALIVE notification received
  1810. *
  1811. * Called after N_ALIVE notification received from "initialize" uCode.
  1812. *
  1813. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  1814. */
  1815. static void il3945_init_alive_start(struct il_priv *il)
  1816. {
  1817. /* Check alive response for "valid" sign from uCode */
  1818. if (il->card_alive_init.is_valid != UCODE_VALID_OK) {
  1819. /* We had an error bringing up the hardware, so take it
  1820. * all the way back down so we can try again */
  1821. D_INFO("Initialize Alive failed.\n");
  1822. goto restart;
  1823. }
  1824. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  1825. * This is a paranoid check, because we would not have gotten the
  1826. * "initialize" alive if code weren't properly loaded. */
  1827. if (il3945_verify_ucode(il)) {
  1828. /* Runtime instruction load was bad;
  1829. * take it all the way back down so we can try again */
  1830. D_INFO("Bad \"initialize\" uCode load.\n");
  1831. goto restart;
  1832. }
  1833. /* Send pointers to protocol/runtime uCode image ... init code will
  1834. * load and launch runtime uCode, which will send us another "Alive"
  1835. * notification. */
  1836. D_INFO("Initialization Alive received.\n");
  1837. if (il3945_set_ucode_ptrs(il)) {
  1838. /* Runtime instruction load won't happen;
  1839. * take it all the way back down so we can try again */
  1840. D_INFO("Couldn't set up uCode pointers.\n");
  1841. goto restart;
  1842. }
  1843. return;
  1844. restart:
  1845. queue_work(il->workqueue, &il->restart);
  1846. }
  1847. /**
  1848. * il3945_alive_start - called after N_ALIVE notification received
  1849. * from protocol/runtime uCode (initialization uCode's
  1850. * Alive gets handled by il3945_init_alive_start()).
  1851. */
  1852. static void il3945_alive_start(struct il_priv *il)
  1853. {
  1854. int thermal_spin = 0;
  1855. u32 rfkill;
  1856. struct il_rxon_context *ctx = &il->ctx;
  1857. D_INFO("Runtime Alive received.\n");
  1858. if (il->card_alive.is_valid != UCODE_VALID_OK) {
  1859. /* We had an error bringing up the hardware, so take it
  1860. * all the way back down so we can try again */
  1861. D_INFO("Alive failed.\n");
  1862. goto restart;
  1863. }
  1864. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1865. * This is a paranoid check, because we would not have gotten the
  1866. * "runtime" alive if code weren't properly loaded. */
  1867. if (il3945_verify_ucode(il)) {
  1868. /* Runtime instruction load was bad;
  1869. * take it all the way back down so we can try again */
  1870. D_INFO("Bad runtime uCode load.\n");
  1871. goto restart;
  1872. }
  1873. rfkill = il_rd_prph(il, APMG_RFKILL_REG);
  1874. D_INFO("RFKILL status: 0x%x\n", rfkill);
  1875. if (rfkill & 0x1) {
  1876. clear_bit(S_RF_KILL_HW, &il->status);
  1877. /* if RFKILL is not on, then wait for thermal
  1878. * sensor in adapter to kick in */
  1879. while (il3945_hw_get_temperature(il) == 0) {
  1880. thermal_spin++;
  1881. udelay(10);
  1882. }
  1883. if (thermal_spin)
  1884. D_INFO("Thermal calibration took %dus\n",
  1885. thermal_spin * 10);
  1886. } else
  1887. set_bit(S_RF_KILL_HW, &il->status);
  1888. /* After the ALIVE response, we can send commands to 3945 uCode */
  1889. set_bit(S_ALIVE, &il->status);
  1890. /* Enable watchdog to monitor the driver tx queues */
  1891. il_setup_watchdog(il);
  1892. if (il_is_rfkill(il))
  1893. return;
  1894. ieee80211_wake_queues(il->hw);
  1895. il->active_rate = RATES_MASK_3945;
  1896. il_power_update_mode(il, true);
  1897. if (il_is_associated(il)) {
  1898. struct il3945_rxon_cmd *active_rxon =
  1899. (struct il3945_rxon_cmd *)(&ctx->active);
  1900. ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1901. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1902. } else {
  1903. /* Initialize our rx_config data */
  1904. il_connection_init_rx_config(il, ctx);
  1905. }
  1906. /* Configure Bluetooth device coexistence support */
  1907. il_send_bt_config(il);
  1908. set_bit(S_READY, &il->status);
  1909. /* Configure the adapter for unassociated operation */
  1910. il3945_commit_rxon(il, ctx);
  1911. il3945_reg_txpower_periodic(il);
  1912. D_INFO("ALIVE processing complete.\n");
  1913. wake_up(&il->wait_command_queue);
  1914. return;
  1915. restart:
  1916. queue_work(il->workqueue, &il->restart);
  1917. }
  1918. static void il3945_cancel_deferred_work(struct il_priv *il);
  1919. static void __il3945_down(struct il_priv *il)
  1920. {
  1921. unsigned long flags;
  1922. int exit_pending;
  1923. D_INFO(DRV_NAME " is going down\n");
  1924. il_scan_cancel_timeout(il, 200);
  1925. exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status);
  1926. /* Stop TX queues watchdog. We need to have S_EXIT_PENDING bit set
  1927. * to prevent rearm timer */
  1928. del_timer_sync(&il->watchdog);
  1929. /* Station information will now be cleared in device */
  1930. il_clear_ucode_stations(il, NULL);
  1931. il_dealloc_bcast_stations(il);
  1932. il_clear_driver_stations(il);
  1933. /* Unblock any waiting calls */
  1934. wake_up_all(&il->wait_command_queue);
  1935. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1936. * exiting the module */
  1937. if (!exit_pending)
  1938. clear_bit(S_EXIT_PENDING, &il->status);
  1939. /* stop and reset the on-board processor */
  1940. _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1941. /* tell the device to stop sending interrupts */
  1942. spin_lock_irqsave(&il->lock, flags);
  1943. il_disable_interrupts(il);
  1944. spin_unlock_irqrestore(&il->lock, flags);
  1945. il3945_synchronize_irq(il);
  1946. if (il->mac80211_registered)
  1947. ieee80211_stop_queues(il->hw);
  1948. /* If we have not previously called il3945_init() then
  1949. * clear all bits but the RF Kill bits and return */
  1950. if (!il_is_init(il)) {
  1951. il->status = test_bit(S_RF_KILL_HW, &il->status) <<
  1952. S_RF_KILL_HW |
  1953. test_bit(S_GEO_CONFIGURED, &il->status) <<
  1954. S_GEO_CONFIGURED |
  1955. test_bit(S_EXIT_PENDING, &il->status) <<
  1956. S_EXIT_PENDING;
  1957. goto exit;
  1958. }
  1959. /* ...otherwise clear out all the status bits but the RF Kill
  1960. * bit and continue taking the NIC down. */
  1961. il->status &= test_bit(S_RF_KILL_HW, &il->status) <<
  1962. S_RF_KILL_HW |
  1963. test_bit(S_GEO_CONFIGURED, &il->status) <<
  1964. S_GEO_CONFIGURED |
  1965. test_bit(S_FW_ERROR, &il->status) <<
  1966. S_FW_ERROR |
  1967. test_bit(S_EXIT_PENDING, &il->status) <<
  1968. S_EXIT_PENDING;
  1969. il3945_hw_txq_ctx_stop(il);
  1970. il3945_hw_rxq_stop(il);
  1971. /* Power-down device's busmaster DMA clocks */
  1972. il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  1973. udelay(5);
  1974. /* Stop the device, and put it in low power state */
  1975. il_apm_stop(il);
  1976. exit:
  1977. memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
  1978. if (il->beacon_skb)
  1979. dev_kfree_skb(il->beacon_skb);
  1980. il->beacon_skb = NULL;
  1981. /* clear out any free frames */
  1982. il3945_clear_free_frames(il);
  1983. }
  1984. static void il3945_down(struct il_priv *il)
  1985. {
  1986. mutex_lock(&il->mutex);
  1987. __il3945_down(il);
  1988. mutex_unlock(&il->mutex);
  1989. il3945_cancel_deferred_work(il);
  1990. }
  1991. #define MAX_HW_RESTARTS 5
  1992. static int il3945_alloc_bcast_station(struct il_priv *il)
  1993. {
  1994. struct il_rxon_context *ctx = &il->ctx;
  1995. unsigned long flags;
  1996. u8 sta_id;
  1997. spin_lock_irqsave(&il->sta_lock, flags);
  1998. sta_id = il_prep_station(il, ctx,
  1999. il_bcast_addr, false, NULL);
  2000. if (sta_id == IL_INVALID_STATION) {
  2001. IL_ERR("Unable to prepare broadcast station\n");
  2002. spin_unlock_irqrestore(&il->sta_lock, flags);
  2003. return -EINVAL;
  2004. }
  2005. il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
  2006. il->stations[sta_id].used |= IL_STA_BCAST;
  2007. spin_unlock_irqrestore(&il->sta_lock, flags);
  2008. return 0;
  2009. }
  2010. static int __il3945_up(struct il_priv *il)
  2011. {
  2012. int rc, i;
  2013. rc = il3945_alloc_bcast_station(il);
  2014. if (rc)
  2015. return rc;
  2016. if (test_bit(S_EXIT_PENDING, &il->status)) {
  2017. IL_WARN("Exit pending; will not bring the NIC up\n");
  2018. return -EIO;
  2019. }
  2020. if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
  2021. IL_ERR("ucode not available for device bring up\n");
  2022. return -EIO;
  2023. }
  2024. /* If platform's RF_KILL switch is NOT set to KILL */
  2025. if (_il_rd(il, CSR_GP_CNTRL) &
  2026. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2027. clear_bit(S_RF_KILL_HW, &il->status);
  2028. else {
  2029. set_bit(S_RF_KILL_HW, &il->status);
  2030. IL_WARN("Radio disabled by HW RF Kill switch\n");
  2031. return -ENODEV;
  2032. }
  2033. _il_wr(il, CSR_INT, 0xFFFFFFFF);
  2034. rc = il3945_hw_nic_init(il);
  2035. if (rc) {
  2036. IL_ERR("Unable to int nic\n");
  2037. return rc;
  2038. }
  2039. /* make sure rfkill handshake bits are cleared */
  2040. _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2041. _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
  2042. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2043. /* clear (again), then enable host interrupts */
  2044. _il_wr(il, CSR_INT, 0xFFFFFFFF);
  2045. il_enable_interrupts(il);
  2046. /* really make sure rfkill handshake bits are cleared */
  2047. _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2048. _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2049. /* Copy original ucode data image from disk into backup cache.
  2050. * This will be used to initialize the on-board processor's
  2051. * data SRAM for a clean start when the runtime program first loads. */
  2052. memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
  2053. il->ucode_data.len);
  2054. /* We return success when we resume from suspend and rf_kill is on. */
  2055. if (test_bit(S_RF_KILL_HW, &il->status))
  2056. return 0;
  2057. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  2058. /* load bootstrap state machine,
  2059. * load bootstrap program into processor's memory,
  2060. * prepare to load the "initialize" uCode */
  2061. rc = il->cfg->ops->lib->load_ucode(il);
  2062. if (rc) {
  2063. IL_ERR(
  2064. "Unable to set up bootstrap uCode: %d\n", rc);
  2065. continue;
  2066. }
  2067. /* start card; "initialize" will load runtime ucode */
  2068. il3945_nic_start(il);
  2069. D_INFO(DRV_NAME " is coming up\n");
  2070. return 0;
  2071. }
  2072. set_bit(S_EXIT_PENDING, &il->status);
  2073. __il3945_down(il);
  2074. clear_bit(S_EXIT_PENDING, &il->status);
  2075. /* tried to restart and config the device for as long as our
  2076. * patience could withstand */
  2077. IL_ERR("Unable to initialize device after %d attempts.\n", i);
  2078. return -EIO;
  2079. }
  2080. /*****************************************************************************
  2081. *
  2082. * Workqueue callbacks
  2083. *
  2084. *****************************************************************************/
  2085. static void il3945_bg_init_alive_start(struct work_struct *data)
  2086. {
  2087. struct il_priv *il =
  2088. container_of(data, struct il_priv, init_alive_start.work);
  2089. mutex_lock(&il->mutex);
  2090. if (test_bit(S_EXIT_PENDING, &il->status))
  2091. goto out;
  2092. il3945_init_alive_start(il);
  2093. out:
  2094. mutex_unlock(&il->mutex);
  2095. }
  2096. static void il3945_bg_alive_start(struct work_struct *data)
  2097. {
  2098. struct il_priv *il =
  2099. container_of(data, struct il_priv, alive_start.work);
  2100. mutex_lock(&il->mutex);
  2101. if (test_bit(S_EXIT_PENDING, &il->status))
  2102. goto out;
  2103. il3945_alive_start(il);
  2104. out:
  2105. mutex_unlock(&il->mutex);
  2106. }
  2107. /*
  2108. * 3945 cannot interrupt driver when hardware rf kill switch toggles;
  2109. * driver must poll CSR_GP_CNTRL_REG register for change. This register
  2110. * *is* readable even when device has been SW_RESET into low power mode
  2111. * (e.g. during RF KILL).
  2112. */
  2113. static void il3945_rfkill_poll(struct work_struct *data)
  2114. {
  2115. struct il_priv *il =
  2116. container_of(data, struct il_priv, _3945.rfkill_poll.work);
  2117. bool old_rfkill = test_bit(S_RF_KILL_HW, &il->status);
  2118. bool new_rfkill = !(_il_rd(il, CSR_GP_CNTRL)
  2119. & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
  2120. if (new_rfkill != old_rfkill) {
  2121. if (new_rfkill)
  2122. set_bit(S_RF_KILL_HW, &il->status);
  2123. else
  2124. clear_bit(S_RF_KILL_HW, &il->status);
  2125. wiphy_rfkill_set_hw_state(il->hw->wiphy, new_rfkill);
  2126. D_RF_KILL("RF_KILL bit toggled to %s.\n",
  2127. new_rfkill ? "disable radio" : "enable radio");
  2128. }
  2129. /* Keep this running, even if radio now enabled. This will be
  2130. * cancelled in mac_start() if system decides to start again */
  2131. queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
  2132. round_jiffies_relative(2 * HZ));
  2133. }
  2134. int il3945_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
  2135. {
  2136. struct il_host_cmd cmd = {
  2137. .id = C_SCAN,
  2138. .len = sizeof(struct il3945_scan_cmd),
  2139. .flags = CMD_SIZE_HUGE,
  2140. };
  2141. struct il3945_scan_cmd *scan;
  2142. u8 n_probes = 0;
  2143. enum ieee80211_band band;
  2144. bool is_active = false;
  2145. int ret;
  2146. u16 len;
  2147. lockdep_assert_held(&il->mutex);
  2148. if (!il->scan_cmd) {
  2149. il->scan_cmd = kmalloc(sizeof(struct il3945_scan_cmd) +
  2150. IL_MAX_SCAN_SIZE, GFP_KERNEL);
  2151. if (!il->scan_cmd) {
  2152. D_SCAN("Fail to allocate scan memory\n");
  2153. return -ENOMEM;
  2154. }
  2155. }
  2156. scan = il->scan_cmd;
  2157. memset(scan, 0, sizeof(struct il3945_scan_cmd) + IL_MAX_SCAN_SIZE);
  2158. scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
  2159. scan->quiet_time = IL_ACTIVE_QUIET_TIME;
  2160. if (il_is_associated(il)) {
  2161. u16 interval;
  2162. u32 extra;
  2163. u32 suspend_time = 100;
  2164. u32 scan_suspend_time = 100;
  2165. D_INFO("Scanning while associated...\n");
  2166. interval = vif->bss_conf.beacon_int;
  2167. scan->suspend_time = 0;
  2168. scan->max_out_time = cpu_to_le32(200 * 1024);
  2169. if (!interval)
  2170. interval = suspend_time;
  2171. /*
  2172. * suspend time format:
  2173. * 0-19: beacon interval in usec (time before exec.)
  2174. * 20-23: 0
  2175. * 24-31: number of beacons (suspend between channels)
  2176. */
  2177. extra = (suspend_time / interval) << 24;
  2178. scan_suspend_time = 0xFF0FFFFF &
  2179. (extra | ((suspend_time % interval) * 1024));
  2180. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  2181. D_SCAN("suspend_time 0x%X beacon interval %d\n",
  2182. scan_suspend_time, interval);
  2183. }
  2184. if (il->scan_request->n_ssids) {
  2185. int i, p = 0;
  2186. D_SCAN("Kicking off active scan\n");
  2187. for (i = 0; i < il->scan_request->n_ssids; i++) {
  2188. /* always does wildcard anyway */
  2189. if (!il->scan_request->ssids[i].ssid_len)
  2190. continue;
  2191. scan->direct_scan[p].id = WLAN_EID_SSID;
  2192. scan->direct_scan[p].len =
  2193. il->scan_request->ssids[i].ssid_len;
  2194. memcpy(scan->direct_scan[p].ssid,
  2195. il->scan_request->ssids[i].ssid,
  2196. il->scan_request->ssids[i].ssid_len);
  2197. n_probes++;
  2198. p++;
  2199. }
  2200. is_active = true;
  2201. } else
  2202. D_SCAN("Kicking off passive scan.\n");
  2203. /* We don't build a direct scan probe request; the uCode will do
  2204. * that based on the direct_mask added to each channel entry */
  2205. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  2206. scan->tx_cmd.sta_id = il->ctx.bcast_sta_id;
  2207. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2208. /* flags + rate selection */
  2209. switch (il->scan_band) {
  2210. case IEEE80211_BAND_2GHZ:
  2211. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  2212. scan->tx_cmd.rate = RATE_1M_PLCP;
  2213. band = IEEE80211_BAND_2GHZ;
  2214. break;
  2215. case IEEE80211_BAND_5GHZ:
  2216. scan->tx_cmd.rate = RATE_6M_PLCP;
  2217. band = IEEE80211_BAND_5GHZ;
  2218. break;
  2219. default:
  2220. IL_WARN("Invalid scan band\n");
  2221. return -EIO;
  2222. }
  2223. /*
  2224. * If active scaning is requested but a certain channel
  2225. * is marked passive, we can do active scanning if we
  2226. * detect transmissions.
  2227. */
  2228. scan->good_CRC_th = is_active ? IL_GOOD_CRC_TH_DEFAULT :
  2229. IL_GOOD_CRC_TH_DISABLED;
  2230. len = il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data,
  2231. vif->addr, il->scan_request->ie,
  2232. il->scan_request->ie_len,
  2233. IL_MAX_SCAN_SIZE - sizeof(*scan));
  2234. scan->tx_cmd.len = cpu_to_le16(len);
  2235. /* select Rx antennas */
  2236. scan->flags |= il3945_get_antenna_flags(il);
  2237. scan->channel_count = il3945_get_channels_for_scan(il, band, is_active, n_probes,
  2238. (void *)&scan->data[len], vif);
  2239. if (scan->channel_count == 0) {
  2240. D_SCAN("channel count %d\n", scan->channel_count);
  2241. return -EIO;
  2242. }
  2243. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  2244. scan->channel_count * sizeof(struct il3945_scan_channel);
  2245. cmd.data = scan;
  2246. scan->len = cpu_to_le16(cmd.len);
  2247. set_bit(S_SCAN_HW, &il->status);
  2248. ret = il_send_cmd_sync(il, &cmd);
  2249. if (ret)
  2250. clear_bit(S_SCAN_HW, &il->status);
  2251. return ret;
  2252. }
  2253. void il3945_post_scan(struct il_priv *il)
  2254. {
  2255. struct il_rxon_context *ctx = &il->ctx;
  2256. /*
  2257. * Since setting the RXON may have been deferred while
  2258. * performing the scan, fire one off if needed
  2259. */
  2260. if (memcmp(&ctx->staging, &ctx->active, sizeof(ctx->staging)))
  2261. il3945_commit_rxon(il, ctx);
  2262. }
  2263. static void il3945_bg_restart(struct work_struct *data)
  2264. {
  2265. struct il_priv *il = container_of(data, struct il_priv, restart);
  2266. if (test_bit(S_EXIT_PENDING, &il->status))
  2267. return;
  2268. if (test_and_clear_bit(S_FW_ERROR, &il->status)) {
  2269. mutex_lock(&il->mutex);
  2270. il->ctx.vif = NULL;
  2271. il->is_open = 0;
  2272. mutex_unlock(&il->mutex);
  2273. il3945_down(il);
  2274. ieee80211_restart_hw(il->hw);
  2275. } else {
  2276. il3945_down(il);
  2277. mutex_lock(&il->mutex);
  2278. if (test_bit(S_EXIT_PENDING, &il->status)) {
  2279. mutex_unlock(&il->mutex);
  2280. return;
  2281. }
  2282. __il3945_up(il);
  2283. mutex_unlock(&il->mutex);
  2284. }
  2285. }
  2286. static void il3945_bg_rx_replenish(struct work_struct *data)
  2287. {
  2288. struct il_priv *il =
  2289. container_of(data, struct il_priv, rx_replenish);
  2290. mutex_lock(&il->mutex);
  2291. if (test_bit(S_EXIT_PENDING, &il->status))
  2292. goto out;
  2293. il3945_rx_replenish(il);
  2294. out:
  2295. mutex_unlock(&il->mutex);
  2296. }
  2297. void il3945_post_associate(struct il_priv *il)
  2298. {
  2299. int rc = 0;
  2300. struct ieee80211_conf *conf = NULL;
  2301. struct il_rxon_context *ctx = &il->ctx;
  2302. if (!ctx->vif || !il->is_open)
  2303. return;
  2304. D_ASSOC("Associated as %d to: %pM\n",
  2305. ctx->vif->bss_conf.aid, ctx->active.bssid_addr);
  2306. if (test_bit(S_EXIT_PENDING, &il->status))
  2307. return;
  2308. il_scan_cancel_timeout(il, 200);
  2309. conf = il_ieee80211_get_hw_conf(il->hw);
  2310. ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2311. il3945_commit_rxon(il, ctx);
  2312. rc = il_send_rxon_timing(il, ctx);
  2313. if (rc)
  2314. IL_WARN("C_RXON_TIMING failed - "
  2315. "Attempting to continue.\n");
  2316. ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2317. ctx->staging.assoc_id = cpu_to_le16(ctx->vif->bss_conf.aid);
  2318. D_ASSOC("assoc id %d beacon interval %d\n",
  2319. ctx->vif->bss_conf.aid, ctx->vif->bss_conf.beacon_int);
  2320. if (ctx->vif->bss_conf.use_short_preamble)
  2321. ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2322. else
  2323. ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2324. if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
  2325. if (ctx->vif->bss_conf.use_short_slot)
  2326. ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2327. else
  2328. ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2329. }
  2330. il3945_commit_rxon(il, ctx);
  2331. switch (ctx->vif->type) {
  2332. case NL80211_IFTYPE_STATION:
  2333. il3945_rate_scale_init(il->hw, IL_AP_ID);
  2334. break;
  2335. case NL80211_IFTYPE_ADHOC:
  2336. il3945_send_beacon_cmd(il);
  2337. break;
  2338. default:
  2339. IL_ERR("%s Should not be called in %d mode\n",
  2340. __func__, ctx->vif->type);
  2341. break;
  2342. }
  2343. }
  2344. /*****************************************************************************
  2345. *
  2346. * mac80211 entry point functions
  2347. *
  2348. *****************************************************************************/
  2349. #define UCODE_READY_TIMEOUT (2 * HZ)
  2350. static int il3945_mac_start(struct ieee80211_hw *hw)
  2351. {
  2352. struct il_priv *il = hw->priv;
  2353. int ret;
  2354. D_MAC80211("enter\n");
  2355. /* we should be verifying the device is ready to be opened */
  2356. mutex_lock(&il->mutex);
  2357. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  2358. * ucode filename and max sizes are card-specific. */
  2359. if (!il->ucode_code.len) {
  2360. ret = il3945_read_ucode(il);
  2361. if (ret) {
  2362. IL_ERR("Could not read microcode: %d\n", ret);
  2363. mutex_unlock(&il->mutex);
  2364. goto out_release_irq;
  2365. }
  2366. }
  2367. ret = __il3945_up(il);
  2368. mutex_unlock(&il->mutex);
  2369. if (ret)
  2370. goto out_release_irq;
  2371. D_INFO("Start UP work.\n");
  2372. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  2373. * mac80211 will not be run successfully. */
  2374. ret = wait_event_timeout(il->wait_command_queue,
  2375. test_bit(S_READY, &il->status),
  2376. UCODE_READY_TIMEOUT);
  2377. if (!ret) {
  2378. if (!test_bit(S_READY, &il->status)) {
  2379. IL_ERR(
  2380. "Wait for START_ALIVE timeout after %dms.\n",
  2381. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2382. ret = -ETIMEDOUT;
  2383. goto out_release_irq;
  2384. }
  2385. }
  2386. /* ucode is running and will send rfkill notifications,
  2387. * no need to poll the killswitch state anymore */
  2388. cancel_delayed_work(&il->_3945.rfkill_poll);
  2389. il->is_open = 1;
  2390. D_MAC80211("leave\n");
  2391. return 0;
  2392. out_release_irq:
  2393. il->is_open = 0;
  2394. D_MAC80211("leave - failed\n");
  2395. return ret;
  2396. }
  2397. static void il3945_mac_stop(struct ieee80211_hw *hw)
  2398. {
  2399. struct il_priv *il = hw->priv;
  2400. D_MAC80211("enter\n");
  2401. if (!il->is_open) {
  2402. D_MAC80211("leave - skip\n");
  2403. return;
  2404. }
  2405. il->is_open = 0;
  2406. il3945_down(il);
  2407. flush_workqueue(il->workqueue);
  2408. /* start polling the killswitch state again */
  2409. queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
  2410. round_jiffies_relative(2 * HZ));
  2411. D_MAC80211("leave\n");
  2412. }
  2413. static void il3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2414. {
  2415. struct il_priv *il = hw->priv;
  2416. D_MAC80211("enter\n");
  2417. D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2418. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2419. if (il3945_tx_skb(il, skb))
  2420. dev_kfree_skb_any(skb);
  2421. D_MAC80211("leave\n");
  2422. }
  2423. void il3945_config_ap(struct il_priv *il)
  2424. {
  2425. struct il_rxon_context *ctx = &il->ctx;
  2426. struct ieee80211_vif *vif = ctx->vif;
  2427. int rc = 0;
  2428. if (test_bit(S_EXIT_PENDING, &il->status))
  2429. return;
  2430. /* The following should be done only at AP bring up */
  2431. if (!(il_is_associated(il))) {
  2432. /* RXON - unassoc (to set timing command) */
  2433. ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2434. il3945_commit_rxon(il, ctx);
  2435. /* RXON Timing */
  2436. rc = il_send_rxon_timing(il, ctx);
  2437. if (rc)
  2438. IL_WARN("C_RXON_TIMING failed - "
  2439. "Attempting to continue.\n");
  2440. ctx->staging.assoc_id = 0;
  2441. if (vif->bss_conf.use_short_preamble)
  2442. ctx->staging.flags |=
  2443. RXON_FLG_SHORT_PREAMBLE_MSK;
  2444. else
  2445. ctx->staging.flags &=
  2446. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2447. if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
  2448. if (vif->bss_conf.use_short_slot)
  2449. ctx->staging.flags |=
  2450. RXON_FLG_SHORT_SLOT_MSK;
  2451. else
  2452. ctx->staging.flags &=
  2453. ~RXON_FLG_SHORT_SLOT_MSK;
  2454. }
  2455. /* restore RXON assoc */
  2456. ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2457. il3945_commit_rxon(il, ctx);
  2458. }
  2459. il3945_send_beacon_cmd(il);
  2460. }
  2461. static int il3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2462. struct ieee80211_vif *vif,
  2463. struct ieee80211_sta *sta,
  2464. struct ieee80211_key_conf *key)
  2465. {
  2466. struct il_priv *il = hw->priv;
  2467. int ret = 0;
  2468. u8 sta_id = IL_INVALID_STATION;
  2469. u8 static_key;
  2470. D_MAC80211("enter\n");
  2471. if (il3945_mod_params.sw_crypto) {
  2472. D_MAC80211("leave - hwcrypto disabled\n");
  2473. return -EOPNOTSUPP;
  2474. }
  2475. /*
  2476. * To support IBSS RSN, don't program group keys in IBSS, the
  2477. * hardware will then not attempt to decrypt the frames.
  2478. */
  2479. if (vif->type == NL80211_IFTYPE_ADHOC &&
  2480. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
  2481. return -EOPNOTSUPP;
  2482. static_key = !il_is_associated(il);
  2483. if (!static_key) {
  2484. sta_id = il_sta_id_or_broadcast(
  2485. il, &il->ctx, sta);
  2486. if (sta_id == IL_INVALID_STATION)
  2487. return -EINVAL;
  2488. }
  2489. mutex_lock(&il->mutex);
  2490. il_scan_cancel_timeout(il, 100);
  2491. switch (cmd) {
  2492. case SET_KEY:
  2493. if (static_key)
  2494. ret = il3945_set_static_key(il, key);
  2495. else
  2496. ret = il3945_set_dynamic_key(il, key, sta_id);
  2497. D_MAC80211("enable hwcrypto key\n");
  2498. break;
  2499. case DISABLE_KEY:
  2500. if (static_key)
  2501. ret = il3945_remove_static_key(il);
  2502. else
  2503. ret = il3945_clear_sta_key_info(il, sta_id);
  2504. D_MAC80211("disable hwcrypto key\n");
  2505. break;
  2506. default:
  2507. ret = -EINVAL;
  2508. }
  2509. mutex_unlock(&il->mutex);
  2510. D_MAC80211("leave\n");
  2511. return ret;
  2512. }
  2513. static int il3945_mac_sta_add(struct ieee80211_hw *hw,
  2514. struct ieee80211_vif *vif,
  2515. struct ieee80211_sta *sta)
  2516. {
  2517. struct il_priv *il = hw->priv;
  2518. struct il3945_sta_priv *sta_priv = (void *)sta->drv_priv;
  2519. int ret;
  2520. bool is_ap = vif->type == NL80211_IFTYPE_STATION;
  2521. u8 sta_id;
  2522. D_INFO("received request to add station %pM\n",
  2523. sta->addr);
  2524. mutex_lock(&il->mutex);
  2525. D_INFO("proceeding to add station %pM\n",
  2526. sta->addr);
  2527. sta_priv->common.sta_id = IL_INVALID_STATION;
  2528. ret = il_add_station_common(il,
  2529. &il->ctx,
  2530. sta->addr, is_ap, sta, &sta_id);
  2531. if (ret) {
  2532. IL_ERR("Unable to add station %pM (%d)\n",
  2533. sta->addr, ret);
  2534. /* Should we return success if return code is EEXIST ? */
  2535. mutex_unlock(&il->mutex);
  2536. return ret;
  2537. }
  2538. sta_priv->common.sta_id = sta_id;
  2539. /* Initialize rate scaling */
  2540. D_INFO("Initializing rate scaling for station %pM\n",
  2541. sta->addr);
  2542. il3945_rs_rate_init(il, sta, sta_id);
  2543. mutex_unlock(&il->mutex);
  2544. return 0;
  2545. }
  2546. static void il3945_configure_filter(struct ieee80211_hw *hw,
  2547. unsigned int changed_flags,
  2548. unsigned int *total_flags,
  2549. u64 multicast)
  2550. {
  2551. struct il_priv *il = hw->priv;
  2552. __le32 filter_or = 0, filter_nand = 0;
  2553. struct il_rxon_context *ctx = &il->ctx;
  2554. #define CHK(test, flag) do { \
  2555. if (*total_flags & (test)) \
  2556. filter_or |= (flag); \
  2557. else \
  2558. filter_nand |= (flag); \
  2559. } while (0)
  2560. D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n",
  2561. changed_flags, *total_flags);
  2562. CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
  2563. CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
  2564. CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
  2565. #undef CHK
  2566. mutex_lock(&il->mutex);
  2567. ctx->staging.filter_flags &= ~filter_nand;
  2568. ctx->staging.filter_flags |= filter_or;
  2569. /*
  2570. * Not committing directly because hardware can perform a scan,
  2571. * but even if hw is ready, committing here breaks for some reason,
  2572. * we'll eventually commit the filter flags change anyway.
  2573. */
  2574. mutex_unlock(&il->mutex);
  2575. /*
  2576. * Receiving all multicast frames is always enabled by the
  2577. * default flags setup in il_connection_init_rx_config()
  2578. * since we currently do not support programming multicast
  2579. * filters into the device.
  2580. */
  2581. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  2582. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  2583. }
  2584. /*****************************************************************************
  2585. *
  2586. * sysfs attributes
  2587. *
  2588. *****************************************************************************/
  2589. #ifdef CONFIG_IWLEGACY_DEBUG
  2590. /*
  2591. * The following adds a new attribute to the sysfs representation
  2592. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  2593. * used for controlling the debug level.
  2594. *
  2595. * See the level definitions in iwl for details.
  2596. *
  2597. * The debug_level being managed using sysfs below is a per device debug
  2598. * level that is used instead of the global debug level if it (the per
  2599. * device debug level) is set.
  2600. */
  2601. static ssize_t il3945_show_debug_level(struct device *d,
  2602. struct device_attribute *attr, char *buf)
  2603. {
  2604. struct il_priv *il = dev_get_drvdata(d);
  2605. return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
  2606. }
  2607. static ssize_t il3945_store_debug_level(struct device *d,
  2608. struct device_attribute *attr,
  2609. const char *buf, size_t count)
  2610. {
  2611. struct il_priv *il = dev_get_drvdata(d);
  2612. unsigned long val;
  2613. int ret;
  2614. ret = strict_strtoul(buf, 0, &val);
  2615. if (ret)
  2616. IL_INFO("%s is not in hex or decimal form.\n", buf);
  2617. else {
  2618. il->debug_level = val;
  2619. if (il_alloc_traffic_mem(il))
  2620. IL_ERR(
  2621. "Not enough memory to generate traffic log\n");
  2622. }
  2623. return strnlen(buf, count);
  2624. }
  2625. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2626. il3945_show_debug_level, il3945_store_debug_level);
  2627. #endif /* CONFIG_IWLEGACY_DEBUG */
  2628. static ssize_t il3945_show_temperature(struct device *d,
  2629. struct device_attribute *attr, char *buf)
  2630. {
  2631. struct il_priv *il = dev_get_drvdata(d);
  2632. if (!il_is_alive(il))
  2633. return -EAGAIN;
  2634. return sprintf(buf, "%d\n", il3945_hw_get_temperature(il));
  2635. }
  2636. static DEVICE_ATTR(temperature, S_IRUGO, il3945_show_temperature, NULL);
  2637. static ssize_t il3945_show_tx_power(struct device *d,
  2638. struct device_attribute *attr, char *buf)
  2639. {
  2640. struct il_priv *il = dev_get_drvdata(d);
  2641. return sprintf(buf, "%d\n", il->tx_power_user_lmt);
  2642. }
  2643. static ssize_t il3945_store_tx_power(struct device *d,
  2644. struct device_attribute *attr,
  2645. const char *buf, size_t count)
  2646. {
  2647. struct il_priv *il = dev_get_drvdata(d);
  2648. char *p = (char *)buf;
  2649. u32 val;
  2650. val = simple_strtoul(p, &p, 10);
  2651. if (p == buf)
  2652. IL_INFO(": %s is not in decimal form.\n", buf);
  2653. else
  2654. il3945_hw_reg_set_txpower(il, val);
  2655. return count;
  2656. }
  2657. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, il3945_show_tx_power, il3945_store_tx_power);
  2658. static ssize_t il3945_show_flags(struct device *d,
  2659. struct device_attribute *attr, char *buf)
  2660. {
  2661. struct il_priv *il = dev_get_drvdata(d);
  2662. struct il_rxon_context *ctx = &il->ctx;
  2663. return sprintf(buf, "0x%04X\n", ctx->active.flags);
  2664. }
  2665. static ssize_t il3945_store_flags(struct device *d,
  2666. struct device_attribute *attr,
  2667. const char *buf, size_t count)
  2668. {
  2669. struct il_priv *il = dev_get_drvdata(d);
  2670. u32 flags = simple_strtoul(buf, NULL, 0);
  2671. struct il_rxon_context *ctx = &il->ctx;
  2672. mutex_lock(&il->mutex);
  2673. if (le32_to_cpu(ctx->staging.flags) != flags) {
  2674. /* Cancel any currently running scans... */
  2675. if (il_scan_cancel_timeout(il, 100))
  2676. IL_WARN("Could not cancel scan.\n");
  2677. else {
  2678. D_INFO("Committing rxon.flags = 0x%04X\n",
  2679. flags);
  2680. ctx->staging.flags = cpu_to_le32(flags);
  2681. il3945_commit_rxon(il, ctx);
  2682. }
  2683. }
  2684. mutex_unlock(&il->mutex);
  2685. return count;
  2686. }
  2687. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, il3945_show_flags, il3945_store_flags);
  2688. static ssize_t il3945_show_filter_flags(struct device *d,
  2689. struct device_attribute *attr, char *buf)
  2690. {
  2691. struct il_priv *il = dev_get_drvdata(d);
  2692. struct il_rxon_context *ctx = &il->ctx;
  2693. return sprintf(buf, "0x%04X\n",
  2694. le32_to_cpu(ctx->active.filter_flags));
  2695. }
  2696. static ssize_t il3945_store_filter_flags(struct device *d,
  2697. struct device_attribute *attr,
  2698. const char *buf, size_t count)
  2699. {
  2700. struct il_priv *il = dev_get_drvdata(d);
  2701. struct il_rxon_context *ctx = &il->ctx;
  2702. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  2703. mutex_lock(&il->mutex);
  2704. if (le32_to_cpu(ctx->staging.filter_flags) != filter_flags) {
  2705. /* Cancel any currently running scans... */
  2706. if (il_scan_cancel_timeout(il, 100))
  2707. IL_WARN("Could not cancel scan.\n");
  2708. else {
  2709. D_INFO("Committing rxon.filter_flags = "
  2710. "0x%04X\n", filter_flags);
  2711. ctx->staging.filter_flags =
  2712. cpu_to_le32(filter_flags);
  2713. il3945_commit_rxon(il, ctx);
  2714. }
  2715. }
  2716. mutex_unlock(&il->mutex);
  2717. return count;
  2718. }
  2719. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, il3945_show_filter_flags,
  2720. il3945_store_filter_flags);
  2721. static ssize_t il3945_show_measurement(struct device *d,
  2722. struct device_attribute *attr, char *buf)
  2723. {
  2724. struct il_priv *il = dev_get_drvdata(d);
  2725. struct il_spectrum_notification measure_report;
  2726. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  2727. u8 *data = (u8 *)&measure_report;
  2728. unsigned long flags;
  2729. spin_lock_irqsave(&il->lock, flags);
  2730. if (!(il->measurement_status & MEASUREMENT_READY)) {
  2731. spin_unlock_irqrestore(&il->lock, flags);
  2732. return 0;
  2733. }
  2734. memcpy(&measure_report, &il->measure_report, size);
  2735. il->measurement_status = 0;
  2736. spin_unlock_irqrestore(&il->lock, flags);
  2737. while (size && PAGE_SIZE - len) {
  2738. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2739. PAGE_SIZE - len, 1);
  2740. len = strlen(buf);
  2741. if (PAGE_SIZE - len)
  2742. buf[len++] = '\n';
  2743. ofs += 16;
  2744. size -= min(size, 16U);
  2745. }
  2746. return len;
  2747. }
  2748. static ssize_t il3945_store_measurement(struct device *d,
  2749. struct device_attribute *attr,
  2750. const char *buf, size_t count)
  2751. {
  2752. struct il_priv *il = dev_get_drvdata(d);
  2753. struct il_rxon_context *ctx = &il->ctx;
  2754. struct ieee80211_measurement_params params = {
  2755. .channel = le16_to_cpu(ctx->active.channel),
  2756. .start_time = cpu_to_le64(il->_3945.last_tsf),
  2757. .duration = cpu_to_le16(1),
  2758. };
  2759. u8 type = IL_MEASURE_BASIC;
  2760. u8 buffer[32];
  2761. u8 channel;
  2762. if (count) {
  2763. char *p = buffer;
  2764. strncpy(buffer, buf, min(sizeof(buffer), count));
  2765. channel = simple_strtoul(p, NULL, 0);
  2766. if (channel)
  2767. params.channel = channel;
  2768. p = buffer;
  2769. while (*p && *p != ' ')
  2770. p++;
  2771. if (*p)
  2772. type = simple_strtoul(p + 1, NULL, 0);
  2773. }
  2774. D_INFO("Invoking measurement of type %d on "
  2775. "channel %d (for '%s')\n", type, params.channel, buf);
  2776. il3945_get_measurement(il, &params, type);
  2777. return count;
  2778. }
  2779. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  2780. il3945_show_measurement, il3945_store_measurement);
  2781. static ssize_t il3945_store_retry_rate(struct device *d,
  2782. struct device_attribute *attr,
  2783. const char *buf, size_t count)
  2784. {
  2785. struct il_priv *il = dev_get_drvdata(d);
  2786. il->retry_rate = simple_strtoul(buf, NULL, 0);
  2787. if (il->retry_rate <= 0)
  2788. il->retry_rate = 1;
  2789. return count;
  2790. }
  2791. static ssize_t il3945_show_retry_rate(struct device *d,
  2792. struct device_attribute *attr, char *buf)
  2793. {
  2794. struct il_priv *il = dev_get_drvdata(d);
  2795. return sprintf(buf, "%d", il->retry_rate);
  2796. }
  2797. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, il3945_show_retry_rate,
  2798. il3945_store_retry_rate);
  2799. static ssize_t il3945_show_channels(struct device *d,
  2800. struct device_attribute *attr, char *buf)
  2801. {
  2802. /* all this shit doesn't belong into sysfs anyway */
  2803. return 0;
  2804. }
  2805. static DEVICE_ATTR(channels, S_IRUSR, il3945_show_channels, NULL);
  2806. static ssize_t il3945_show_antenna(struct device *d,
  2807. struct device_attribute *attr, char *buf)
  2808. {
  2809. struct il_priv *il = dev_get_drvdata(d);
  2810. if (!il_is_alive(il))
  2811. return -EAGAIN;
  2812. return sprintf(buf, "%d\n", il3945_mod_params.antenna);
  2813. }
  2814. static ssize_t il3945_store_antenna(struct device *d,
  2815. struct device_attribute *attr,
  2816. const char *buf, size_t count)
  2817. {
  2818. struct il_priv *il __maybe_unused = dev_get_drvdata(d);
  2819. int ant;
  2820. if (count == 0)
  2821. return 0;
  2822. if (sscanf(buf, "%1i", &ant) != 1) {
  2823. D_INFO("not in hex or decimal form.\n");
  2824. return count;
  2825. }
  2826. if (ant >= 0 && ant <= 2) {
  2827. D_INFO("Setting antenna select to %d.\n", ant);
  2828. il3945_mod_params.antenna = (enum il3945_antenna)ant;
  2829. } else
  2830. D_INFO("Bad antenna select value %d.\n", ant);
  2831. return count;
  2832. }
  2833. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, il3945_show_antenna, il3945_store_antenna);
  2834. static ssize_t il3945_show_status(struct device *d,
  2835. struct device_attribute *attr, char *buf)
  2836. {
  2837. struct il_priv *il = dev_get_drvdata(d);
  2838. if (!il_is_alive(il))
  2839. return -EAGAIN;
  2840. return sprintf(buf, "0x%08x\n", (int)il->status);
  2841. }
  2842. static DEVICE_ATTR(status, S_IRUGO, il3945_show_status, NULL);
  2843. static ssize_t il3945_dump_error_log(struct device *d,
  2844. struct device_attribute *attr,
  2845. const char *buf, size_t count)
  2846. {
  2847. struct il_priv *il = dev_get_drvdata(d);
  2848. char *p = (char *)buf;
  2849. if (p[0] == '1')
  2850. il3945_dump_nic_error_log(il);
  2851. return strnlen(buf, count);
  2852. }
  2853. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, il3945_dump_error_log);
  2854. /*****************************************************************************
  2855. *
  2856. * driver setup and tear down
  2857. *
  2858. *****************************************************************************/
  2859. static void il3945_setup_deferred_work(struct il_priv *il)
  2860. {
  2861. il->workqueue = create_singlethread_workqueue(DRV_NAME);
  2862. init_waitqueue_head(&il->wait_command_queue);
  2863. INIT_WORK(&il->restart, il3945_bg_restart);
  2864. INIT_WORK(&il->rx_replenish, il3945_bg_rx_replenish);
  2865. INIT_DELAYED_WORK(&il->init_alive_start, il3945_bg_init_alive_start);
  2866. INIT_DELAYED_WORK(&il->alive_start, il3945_bg_alive_start);
  2867. INIT_DELAYED_WORK(&il->_3945.rfkill_poll, il3945_rfkill_poll);
  2868. il_setup_scan_deferred_work(il);
  2869. il3945_hw_setup_deferred_work(il);
  2870. init_timer(&il->watchdog);
  2871. il->watchdog.data = (unsigned long)il;
  2872. il->watchdog.function = il_bg_watchdog;
  2873. tasklet_init(&il->irq_tasklet, (void (*)(unsigned long))
  2874. il3945_irq_tasklet, (unsigned long)il);
  2875. }
  2876. static void il3945_cancel_deferred_work(struct il_priv *il)
  2877. {
  2878. il3945_hw_cancel_deferred_work(il);
  2879. cancel_delayed_work_sync(&il->init_alive_start);
  2880. cancel_delayed_work(&il->alive_start);
  2881. il_cancel_scan_deferred_work(il);
  2882. }
  2883. static struct attribute *il3945_sysfs_entries[] = {
  2884. &dev_attr_antenna.attr,
  2885. &dev_attr_channels.attr,
  2886. &dev_attr_dump_errors.attr,
  2887. &dev_attr_flags.attr,
  2888. &dev_attr_filter_flags.attr,
  2889. &dev_attr_measurement.attr,
  2890. &dev_attr_retry_rate.attr,
  2891. &dev_attr_status.attr,
  2892. &dev_attr_temperature.attr,
  2893. &dev_attr_tx_power.attr,
  2894. #ifdef CONFIG_IWLEGACY_DEBUG
  2895. &dev_attr_debug_level.attr,
  2896. #endif
  2897. NULL
  2898. };
  2899. static struct attribute_group il3945_attribute_group = {
  2900. .name = NULL, /* put in device directory */
  2901. .attrs = il3945_sysfs_entries,
  2902. };
  2903. struct ieee80211_ops il3945_hw_ops = {
  2904. .tx = il3945_mac_tx,
  2905. .start = il3945_mac_start,
  2906. .stop = il3945_mac_stop,
  2907. .add_interface = il_mac_add_interface,
  2908. .remove_interface = il_mac_remove_interface,
  2909. .change_interface = il_mac_change_interface,
  2910. .config = il_mac_config,
  2911. .configure_filter = il3945_configure_filter,
  2912. .set_key = il3945_mac_set_key,
  2913. .conf_tx = il_mac_conf_tx,
  2914. .reset_tsf = il_mac_reset_tsf,
  2915. .bss_info_changed = il_mac_bss_info_changed,
  2916. .hw_scan = il_mac_hw_scan,
  2917. .sta_add = il3945_mac_sta_add,
  2918. .sta_remove = il_mac_sta_remove,
  2919. .tx_last_beacon = il_mac_tx_last_beacon,
  2920. };
  2921. static int il3945_init_drv(struct il_priv *il)
  2922. {
  2923. int ret;
  2924. struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
  2925. il->retry_rate = 1;
  2926. il->beacon_skb = NULL;
  2927. spin_lock_init(&il->sta_lock);
  2928. spin_lock_init(&il->hcmd_lock);
  2929. INIT_LIST_HEAD(&il->free_frames);
  2930. mutex_init(&il->mutex);
  2931. il->ieee_channels = NULL;
  2932. il->ieee_rates = NULL;
  2933. il->band = IEEE80211_BAND_2GHZ;
  2934. il->iw_mode = NL80211_IFTYPE_STATION;
  2935. il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
  2936. /* initialize force reset */
  2937. il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
  2938. if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
  2939. IL_WARN("Unsupported EEPROM version: 0x%04X\n",
  2940. eeprom->version);
  2941. ret = -EINVAL;
  2942. goto err;
  2943. }
  2944. ret = il_init_channel_map(il);
  2945. if (ret) {
  2946. IL_ERR("initializing regulatory failed: %d\n", ret);
  2947. goto err;
  2948. }
  2949. /* Set up txpower settings in driver for all channels */
  2950. if (il3945_txpower_set_from_eeprom(il)) {
  2951. ret = -EIO;
  2952. goto err_free_channel_map;
  2953. }
  2954. ret = il_init_geos(il);
  2955. if (ret) {
  2956. IL_ERR("initializing geos failed: %d\n", ret);
  2957. goto err_free_channel_map;
  2958. }
  2959. il3945_init_hw_rates(il, il->ieee_rates);
  2960. return 0;
  2961. err_free_channel_map:
  2962. il_free_channel_map(il);
  2963. err:
  2964. return ret;
  2965. }
  2966. #define IL3945_MAX_PROBE_REQUEST 200
  2967. static int il3945_setup_mac(struct il_priv *il)
  2968. {
  2969. int ret;
  2970. struct ieee80211_hw *hw = il->hw;
  2971. hw->rate_control_algorithm = "iwl-3945-rs";
  2972. hw->sta_data_size = sizeof(struct il3945_sta_priv);
  2973. hw->vif_data_size = sizeof(struct il_vif_priv);
  2974. /* Tell mac80211 our characteristics */
  2975. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  2976. IEEE80211_HW_SPECTRUM_MGMT;
  2977. hw->wiphy->interface_modes =
  2978. il->ctx.interface_modes;
  2979. hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
  2980. WIPHY_FLAG_DISABLE_BEACON_HINTS |
  2981. WIPHY_FLAG_IBSS_RSN;
  2982. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
  2983. /* we create the 802.11 header and a zero-length SSID element */
  2984. hw->wiphy->max_scan_ie_len = IL3945_MAX_PROBE_REQUEST - 24 - 2;
  2985. /* Default value; 4 EDCA QOS priorities */
  2986. hw->queues = 4;
  2987. if (il->bands[IEEE80211_BAND_2GHZ].n_channels)
  2988. il->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  2989. &il->bands[IEEE80211_BAND_2GHZ];
  2990. if (il->bands[IEEE80211_BAND_5GHZ].n_channels)
  2991. il->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  2992. &il->bands[IEEE80211_BAND_5GHZ];
  2993. il_leds_init(il);
  2994. ret = ieee80211_register_hw(il->hw);
  2995. if (ret) {
  2996. IL_ERR("Failed to register hw (error %d)\n", ret);
  2997. return ret;
  2998. }
  2999. il->mac80211_registered = 1;
  3000. return 0;
  3001. }
  3002. static int il3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  3003. {
  3004. int err = 0;
  3005. struct il_priv *il;
  3006. struct ieee80211_hw *hw;
  3007. struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
  3008. struct il3945_eeprom *eeprom;
  3009. unsigned long flags;
  3010. /***********************
  3011. * 1. Allocating HW data
  3012. * ********************/
  3013. /* mac80211 allocates memory for this device instance, including
  3014. * space for this driver's ilate structure */
  3015. hw = il_alloc_all(cfg);
  3016. if (hw == NULL) {
  3017. pr_err("Can not allocate network device\n");
  3018. err = -ENOMEM;
  3019. goto out;
  3020. }
  3021. il = hw->priv;
  3022. SET_IEEE80211_DEV(hw, &pdev->dev);
  3023. il->cmd_queue = IL39_CMD_QUEUE_NUM;
  3024. il->ctx.ctxid = 0;
  3025. il->ctx.rxon_cmd = C_RXON;
  3026. il->ctx.rxon_timing_cmd = C_RXON_TIMING;
  3027. il->ctx.rxon_assoc_cmd = C_RXON_ASSOC;
  3028. il->ctx.qos_cmd = C_QOS_PARAM;
  3029. il->ctx.ap_sta_id = IL_AP_ID;
  3030. il->ctx.wep_key_cmd = C_WEPKEY;
  3031. il->ctx.interface_modes =
  3032. BIT(NL80211_IFTYPE_STATION) |
  3033. BIT(NL80211_IFTYPE_ADHOC);
  3034. il->ctx.ibss_devtype = RXON_DEV_TYPE_IBSS;
  3035. il->ctx.station_devtype = RXON_DEV_TYPE_ESS;
  3036. il->ctx.unused_devtype = RXON_DEV_TYPE_ESS;
  3037. /*
  3038. * Disabling hardware scan means that mac80211 will perform scans
  3039. * "the hard way", rather than using device's scan.
  3040. */
  3041. if (il3945_mod_params.disable_hw_scan) {
  3042. D_INFO("Disabling hw_scan\n");
  3043. il3945_hw_ops.hw_scan = NULL;
  3044. }
  3045. D_INFO("*** LOAD DRIVER ***\n");
  3046. il->cfg = cfg;
  3047. il->pci_dev = pdev;
  3048. il->inta_mask = CSR_INI_SET_MASK;
  3049. if (il_alloc_traffic_mem(il))
  3050. IL_ERR("Not enough memory to generate traffic log\n");
  3051. /***************************
  3052. * 2. Initializing PCI bus
  3053. * *************************/
  3054. pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
  3055. PCIE_LINK_STATE_CLKPM);
  3056. if (pci_enable_device(pdev)) {
  3057. err = -ENODEV;
  3058. goto out_ieee80211_free_hw;
  3059. }
  3060. pci_set_master(pdev);
  3061. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  3062. if (!err)
  3063. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  3064. if (err) {
  3065. IL_WARN("No suitable DMA available.\n");
  3066. goto out_pci_disable_device;
  3067. }
  3068. pci_set_drvdata(pdev, il);
  3069. err = pci_request_regions(pdev, DRV_NAME);
  3070. if (err)
  3071. goto out_pci_disable_device;
  3072. /***********************
  3073. * 3. Read REV Register
  3074. * ********************/
  3075. il->hw_base = pci_iomap(pdev, 0, 0);
  3076. if (!il->hw_base) {
  3077. err = -ENODEV;
  3078. goto out_pci_release_regions;
  3079. }
  3080. D_INFO("pci_resource_len = 0x%08llx\n",
  3081. (unsigned long long) pci_resource_len(pdev, 0));
  3082. D_INFO("pci_resource_base = %p\n", il->hw_base);
  3083. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  3084. * PCI Tx retries from interfering with C3 CPU state */
  3085. pci_write_config_byte(pdev, 0x41, 0x00);
  3086. /* these spin locks will be used in apm_ops.init and EEPROM access
  3087. * we should init now
  3088. */
  3089. spin_lock_init(&il->reg_lock);
  3090. spin_lock_init(&il->lock);
  3091. /*
  3092. * stop and reset the on-board processor just in case it is in a
  3093. * strange state ... like being left stranded by a primary kernel
  3094. * and this is now the kdump kernel trying to start up
  3095. */
  3096. _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  3097. /***********************
  3098. * 4. Read EEPROM
  3099. * ********************/
  3100. /* Read the EEPROM */
  3101. err = il_eeprom_init(il);
  3102. if (err) {
  3103. IL_ERR("Unable to init EEPROM\n");
  3104. goto out_iounmap;
  3105. }
  3106. /* MAC Address location in EEPROM same for 3945/4965 */
  3107. eeprom = (struct il3945_eeprom *)il->eeprom;
  3108. D_INFO("MAC address: %pM\n", eeprom->mac_address);
  3109. SET_IEEE80211_PERM_ADDR(il->hw, eeprom->mac_address);
  3110. /***********************
  3111. * 5. Setup HW Constants
  3112. * ********************/
  3113. /* Device-specific setup */
  3114. if (il3945_hw_set_hw_params(il)) {
  3115. IL_ERR("failed to set hw settings\n");
  3116. goto out_eeprom_free;
  3117. }
  3118. /***********************
  3119. * 6. Setup il
  3120. * ********************/
  3121. err = il3945_init_drv(il);
  3122. if (err) {
  3123. IL_ERR("initializing driver failed\n");
  3124. goto out_unset_hw_params;
  3125. }
  3126. IL_INFO("Detected Intel Wireless WiFi Link %s\n",
  3127. il->cfg->name);
  3128. /***********************
  3129. * 7. Setup Services
  3130. * ********************/
  3131. spin_lock_irqsave(&il->lock, flags);
  3132. il_disable_interrupts(il);
  3133. spin_unlock_irqrestore(&il->lock, flags);
  3134. pci_enable_msi(il->pci_dev);
  3135. err = request_irq(il->pci_dev->irq, il_isr,
  3136. IRQF_SHARED, DRV_NAME, il);
  3137. if (err) {
  3138. IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
  3139. goto out_disable_msi;
  3140. }
  3141. err = sysfs_create_group(&pdev->dev.kobj, &il3945_attribute_group);
  3142. if (err) {
  3143. IL_ERR("failed to create sysfs device attributes\n");
  3144. goto out_release_irq;
  3145. }
  3146. il_set_rxon_channel(il,
  3147. &il->bands[IEEE80211_BAND_2GHZ].channels[5],
  3148. &il->ctx);
  3149. il3945_setup_deferred_work(il);
  3150. il3945_setup_rx_handlers(il);
  3151. il_power_initialize(il);
  3152. /*********************************
  3153. * 8. Setup and Register mac80211
  3154. * *******************************/
  3155. il_enable_interrupts(il);
  3156. err = il3945_setup_mac(il);
  3157. if (err)
  3158. goto out_remove_sysfs;
  3159. err = il_dbgfs_register(il, DRV_NAME);
  3160. if (err)
  3161. IL_ERR("failed to create debugfs files. Ignoring error: %d\n", err);
  3162. /* Start monitoring the killswitch */
  3163. queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
  3164. 2 * HZ);
  3165. return 0;
  3166. out_remove_sysfs:
  3167. destroy_workqueue(il->workqueue);
  3168. il->workqueue = NULL;
  3169. sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group);
  3170. out_release_irq:
  3171. free_irq(il->pci_dev->irq, il);
  3172. out_disable_msi:
  3173. pci_disable_msi(il->pci_dev);
  3174. il_free_geos(il);
  3175. il_free_channel_map(il);
  3176. out_unset_hw_params:
  3177. il3945_unset_hw_params(il);
  3178. out_eeprom_free:
  3179. il_eeprom_free(il);
  3180. out_iounmap:
  3181. pci_iounmap(pdev, il->hw_base);
  3182. out_pci_release_regions:
  3183. pci_release_regions(pdev);
  3184. out_pci_disable_device:
  3185. pci_set_drvdata(pdev, NULL);
  3186. pci_disable_device(pdev);
  3187. out_ieee80211_free_hw:
  3188. il_free_traffic_mem(il);
  3189. ieee80211_free_hw(il->hw);
  3190. out:
  3191. return err;
  3192. }
  3193. static void __devexit il3945_pci_remove(struct pci_dev *pdev)
  3194. {
  3195. struct il_priv *il = pci_get_drvdata(pdev);
  3196. unsigned long flags;
  3197. if (!il)
  3198. return;
  3199. D_INFO("*** UNLOAD DRIVER ***\n");
  3200. il_dbgfs_unregister(il);
  3201. set_bit(S_EXIT_PENDING, &il->status);
  3202. il_leds_exit(il);
  3203. if (il->mac80211_registered) {
  3204. ieee80211_unregister_hw(il->hw);
  3205. il->mac80211_registered = 0;
  3206. } else {
  3207. il3945_down(il);
  3208. }
  3209. /*
  3210. * Make sure device is reset to low power before unloading driver.
  3211. * This may be redundant with il_down(), but there are paths to
  3212. * run il_down() without calling apm_ops.stop(), and there are
  3213. * paths to avoid running il_down() at all before leaving driver.
  3214. * This (inexpensive) call *makes sure* device is reset.
  3215. */
  3216. il_apm_stop(il);
  3217. /* make sure we flush any pending irq or
  3218. * tasklet for the driver
  3219. */
  3220. spin_lock_irqsave(&il->lock, flags);
  3221. il_disable_interrupts(il);
  3222. spin_unlock_irqrestore(&il->lock, flags);
  3223. il3945_synchronize_irq(il);
  3224. sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group);
  3225. cancel_delayed_work_sync(&il->_3945.rfkill_poll);
  3226. il3945_dealloc_ucode_pci(il);
  3227. if (il->rxq.bd)
  3228. il3945_rx_queue_free(il, &il->rxq);
  3229. il3945_hw_txq_ctx_free(il);
  3230. il3945_unset_hw_params(il);
  3231. /*netif_stop_queue(dev); */
  3232. flush_workqueue(il->workqueue);
  3233. /* ieee80211_unregister_hw calls il3945_mac_stop, which flushes
  3234. * il->workqueue... so we can't take down the workqueue
  3235. * until now... */
  3236. destroy_workqueue(il->workqueue);
  3237. il->workqueue = NULL;
  3238. il_free_traffic_mem(il);
  3239. free_irq(pdev->irq, il);
  3240. pci_disable_msi(pdev);
  3241. pci_iounmap(pdev, il->hw_base);
  3242. pci_release_regions(pdev);
  3243. pci_disable_device(pdev);
  3244. pci_set_drvdata(pdev, NULL);
  3245. il_free_channel_map(il);
  3246. il_free_geos(il);
  3247. kfree(il->scan_cmd);
  3248. if (il->beacon_skb)
  3249. dev_kfree_skb(il->beacon_skb);
  3250. ieee80211_free_hw(il->hw);
  3251. }
  3252. /*****************************************************************************
  3253. *
  3254. * driver and module entry point
  3255. *
  3256. *****************************************************************************/
  3257. static struct pci_driver il3945_driver = {
  3258. .name = DRV_NAME,
  3259. .id_table = il3945_hw_card_ids,
  3260. .probe = il3945_pci_probe,
  3261. .remove = __devexit_p(il3945_pci_remove),
  3262. .driver.pm = IL_LEGACY_PM_OPS,
  3263. };
  3264. static int __init il3945_init(void)
  3265. {
  3266. int ret;
  3267. pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3268. pr_info(DRV_COPYRIGHT "\n");
  3269. ret = il3945_rate_control_register();
  3270. if (ret) {
  3271. pr_err("Unable to register rate control algorithm: %d\n", ret);
  3272. return ret;
  3273. }
  3274. ret = pci_register_driver(&il3945_driver);
  3275. if (ret) {
  3276. pr_err("Unable to initialize PCI module\n");
  3277. goto error_register;
  3278. }
  3279. return ret;
  3280. error_register:
  3281. il3945_rate_control_unregister();
  3282. return ret;
  3283. }
  3284. static void __exit il3945_exit(void)
  3285. {
  3286. pci_unregister_driver(&il3945_driver);
  3287. il3945_rate_control_unregister();
  3288. }
  3289. MODULE_FIRMWARE(IL3945_MODULE_FIRMWARE(IL3945_UCODE_API_MAX));
  3290. module_param_named(antenna, il3945_mod_params.antenna, int, S_IRUGO);
  3291. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  3292. module_param_named(swcrypto, il3945_mod_params.sw_crypto, int, S_IRUGO);
  3293. MODULE_PARM_DESC(swcrypto,
  3294. "using software crypto (default 1 [software])");
  3295. module_param_named(disable_hw_scan, il3945_mod_params.disable_hw_scan,
  3296. int, S_IRUGO);
  3297. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 1)");
  3298. #ifdef CONFIG_IWLEGACY_DEBUG
  3299. module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR);
  3300. MODULE_PARM_DESC(debug, "debug output mask");
  3301. #endif
  3302. module_param_named(fw_restart, il3945_mod_params.restart_fw, int, S_IRUGO);
  3303. MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
  3304. module_exit(il3945_exit);
  3305. module_init(il3945_init);