fsi.c 39 KB

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  1. /*
  2. * Fifo-attached Serial Interface (FSI) support for SH7724
  3. *
  4. * Copyright (C) 2009 Renesas Solutions Corp.
  5. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  6. *
  7. * Based on ssi.c
  8. * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/delay.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/io.h>
  18. #include <linux/scatterlist.h>
  19. #include <linux/sh_dma.h>
  20. #include <linux/slab.h>
  21. #include <linux/module.h>
  22. #include <sound/soc.h>
  23. #include <sound/sh_fsi.h>
  24. /* PortA/PortB register */
  25. #define REG_DO_FMT 0x0000
  26. #define REG_DOFF_CTL 0x0004
  27. #define REG_DOFF_ST 0x0008
  28. #define REG_DI_FMT 0x000C
  29. #define REG_DIFF_CTL 0x0010
  30. #define REG_DIFF_ST 0x0014
  31. #define REG_CKG1 0x0018
  32. #define REG_CKG2 0x001C
  33. #define REG_DIDT 0x0020
  34. #define REG_DODT 0x0024
  35. #define REG_MUTE_ST 0x0028
  36. #define REG_OUT_DMAC 0x002C
  37. #define REG_OUT_SEL 0x0030
  38. #define REG_IN_DMAC 0x0038
  39. /* master register */
  40. #define MST_CLK_RST 0x0210
  41. #define MST_SOFT_RST 0x0214
  42. #define MST_FIFO_SZ 0x0218
  43. /* core register (depend on FSI version) */
  44. #define A_MST_CTLR 0x0180
  45. #define B_MST_CTLR 0x01A0
  46. #define CPU_INT_ST 0x01F4
  47. #define CPU_IEMSK 0x01F8
  48. #define CPU_IMSK 0x01FC
  49. #define INT_ST 0x0200
  50. #define IEMSK 0x0204
  51. #define IMSK 0x0208
  52. /* DO_FMT */
  53. /* DI_FMT */
  54. #define CR_BWS_MASK (0x3 << 20) /* FSI2 */
  55. #define CR_BWS_24 (0x0 << 20) /* FSI2 */
  56. #define CR_BWS_16 (0x1 << 20) /* FSI2 */
  57. #define CR_BWS_20 (0x2 << 20) /* FSI2 */
  58. #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
  59. #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
  60. #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
  61. #define CR_MONO (0x0 << 4)
  62. #define CR_MONO_D (0x1 << 4)
  63. #define CR_PCM (0x2 << 4)
  64. #define CR_I2S (0x3 << 4)
  65. #define CR_TDM (0x4 << 4)
  66. #define CR_TDM_D (0x5 << 4)
  67. /* OUT_DMAC */
  68. /* IN_DMAC */
  69. #define VDMD_MASK (0x3 << 4)
  70. #define VDMD_FRONT (0x0 << 4) /* Package in front */
  71. #define VDMD_BACK (0x1 << 4) /* Package in back */
  72. #define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */
  73. #define DMA_ON (0x1 << 0)
  74. /* DOFF_CTL */
  75. /* DIFF_CTL */
  76. #define IRQ_HALF 0x00100000
  77. #define FIFO_CLR 0x00000001
  78. /* DOFF_ST */
  79. #define ERR_OVER 0x00000010
  80. #define ERR_UNDER 0x00000001
  81. #define ST_ERR (ERR_OVER | ERR_UNDER)
  82. /* CKG1 */
  83. #define ACKMD_MASK 0x00007000
  84. #define BPFMD_MASK 0x00000700
  85. #define DIMD (1 << 4)
  86. #define DOMD (1 << 0)
  87. /* A/B MST_CTLR */
  88. #define BP (1 << 4) /* Fix the signal of Biphase output */
  89. #define SE (1 << 0) /* Fix the master clock */
  90. /* CLK_RST */
  91. #define CRB (1 << 4)
  92. #define CRA (1 << 0)
  93. /* IO SHIFT / MACRO */
  94. #define BI_SHIFT 12
  95. #define BO_SHIFT 8
  96. #define AI_SHIFT 4
  97. #define AO_SHIFT 0
  98. #define AB_IO(param, shift) (param << shift)
  99. /* SOFT_RST */
  100. #define PBSR (1 << 12) /* Port B Software Reset */
  101. #define PASR (1 << 8) /* Port A Software Reset */
  102. #define IR (1 << 4) /* Interrupt Reset */
  103. #define FSISR (1 << 0) /* Software Reset */
  104. /* OUT_SEL (FSI2) */
  105. #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
  106. /* 1: Biphase and serial */
  107. /* FIFO_SZ */
  108. #define FIFO_SZ_MASK 0x7
  109. #define FSI_RATES SNDRV_PCM_RATE_8000_96000
  110. #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
  111. typedef int (*set_rate_func)(struct device *dev, int rate, int enable);
  112. /*
  113. * FSI driver use below type name for variable
  114. *
  115. * xxx_num : number of data
  116. * xxx_pos : position of data
  117. * xxx_capa : capacity of data
  118. */
  119. /*
  120. * period/frame/sample image
  121. *
  122. * ex) PCM (2ch)
  123. *
  124. * period pos period pos
  125. * [n] [n + 1]
  126. * |<-------------------- period--------------------->|
  127. * ==|============================================ ... =|==
  128. * | |
  129. * ||<----- frame ----->|<------ frame ----->| ... |
  130. * |+--------------------+--------------------+- ... |
  131. * ||[ sample ][ sample ]|[ sample ][ sample ]| ... |
  132. * |+--------------------+--------------------+- ... |
  133. * ==|============================================ ... =|==
  134. */
  135. /*
  136. * FSI FIFO image
  137. *
  138. * | |
  139. * | |
  140. * | [ sample ] |
  141. * | [ sample ] |
  142. * | [ sample ] |
  143. * | [ sample ] |
  144. * --> go to codecs
  145. */
  146. /*
  147. * struct
  148. */
  149. struct fsi_stream_handler;
  150. struct fsi_stream {
  151. /*
  152. * these are initialized by fsi_stream_init()
  153. */
  154. struct snd_pcm_substream *substream;
  155. int fifo_sample_capa; /* sample capacity of FSI FIFO */
  156. int buff_sample_capa; /* sample capacity of ALSA buffer */
  157. int buff_sample_pos; /* sample position of ALSA buffer */
  158. int period_samples; /* sample number / 1 period */
  159. int period_pos; /* current period position */
  160. int sample_width; /* sample width */
  161. int uerr_num;
  162. int oerr_num;
  163. /*
  164. * thse are initialized by fsi_handler_init()
  165. */
  166. struct fsi_stream_handler *handler;
  167. struct fsi_priv *priv;
  168. /*
  169. * these are for DMAEngine
  170. */
  171. struct dma_chan *chan;
  172. struct sh_dmae_slave slave; /* see fsi_handler_init() */
  173. struct tasklet_struct tasklet;
  174. dma_addr_t dma;
  175. };
  176. struct fsi_priv {
  177. void __iomem *base;
  178. struct fsi_master *master;
  179. struct sh_fsi_port_info *info;
  180. struct fsi_stream playback;
  181. struct fsi_stream capture;
  182. u32 do_fmt;
  183. u32 di_fmt;
  184. int chan_num:16;
  185. int clk_master:1;
  186. int spdif:1;
  187. long rate;
  188. };
  189. struct fsi_stream_handler {
  190. int (*init)(struct fsi_priv *fsi, struct fsi_stream *io);
  191. int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io);
  192. int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io);
  193. int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io);
  194. int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io);
  195. void (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io,
  196. int enable);
  197. };
  198. #define fsi_stream_handler_call(io, func, args...) \
  199. (!(io) ? -ENODEV : \
  200. !((io)->handler->func) ? 0 : \
  201. (io)->handler->func(args))
  202. struct fsi_core {
  203. int ver;
  204. u32 int_st;
  205. u32 iemsk;
  206. u32 imsk;
  207. u32 a_mclk;
  208. u32 b_mclk;
  209. };
  210. struct fsi_master {
  211. void __iomem *base;
  212. int irq;
  213. struct fsi_priv fsia;
  214. struct fsi_priv fsib;
  215. struct fsi_core *core;
  216. spinlock_t lock;
  217. };
  218. static int fsi_stream_is_play(struct fsi_priv *fsi, struct fsi_stream *io);
  219. /*
  220. * basic read write function
  221. */
  222. static void __fsi_reg_write(u32 __iomem *reg, u32 data)
  223. {
  224. /* valid data area is 24bit */
  225. data &= 0x00ffffff;
  226. __raw_writel(data, reg);
  227. }
  228. static u32 __fsi_reg_read(u32 __iomem *reg)
  229. {
  230. return __raw_readl(reg);
  231. }
  232. static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data)
  233. {
  234. u32 val = __fsi_reg_read(reg);
  235. val &= ~mask;
  236. val |= data & mask;
  237. __fsi_reg_write(reg, val);
  238. }
  239. #define fsi_reg_write(p, r, d)\
  240. __fsi_reg_write((p->base + REG_##r), d)
  241. #define fsi_reg_read(p, r)\
  242. __fsi_reg_read((p->base + REG_##r))
  243. #define fsi_reg_mask_set(p, r, m, d)\
  244. __fsi_reg_mask_set((p->base + REG_##r), m, d)
  245. #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
  246. #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
  247. static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
  248. {
  249. u32 ret;
  250. unsigned long flags;
  251. spin_lock_irqsave(&master->lock, flags);
  252. ret = __fsi_reg_read(master->base + reg);
  253. spin_unlock_irqrestore(&master->lock, flags);
  254. return ret;
  255. }
  256. #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
  257. #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
  258. static void _fsi_master_mask_set(struct fsi_master *master,
  259. u32 reg, u32 mask, u32 data)
  260. {
  261. unsigned long flags;
  262. spin_lock_irqsave(&master->lock, flags);
  263. __fsi_reg_mask_set(master->base + reg, mask, data);
  264. spin_unlock_irqrestore(&master->lock, flags);
  265. }
  266. /*
  267. * basic function
  268. */
  269. static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
  270. {
  271. return fsi->master;
  272. }
  273. static int fsi_is_clk_master(struct fsi_priv *fsi)
  274. {
  275. return fsi->clk_master;
  276. }
  277. static int fsi_is_port_a(struct fsi_priv *fsi)
  278. {
  279. return fsi->master->base == fsi->base;
  280. }
  281. static int fsi_is_spdif(struct fsi_priv *fsi)
  282. {
  283. return fsi->spdif;
  284. }
  285. static int fsi_is_play(struct snd_pcm_substream *substream)
  286. {
  287. return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  288. }
  289. static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
  290. {
  291. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  292. return rtd->cpu_dai;
  293. }
  294. static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
  295. {
  296. struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
  297. if (dai->id == 0)
  298. return &master->fsia;
  299. else
  300. return &master->fsib;
  301. }
  302. static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
  303. {
  304. return fsi_get_priv_frm_dai(fsi_get_dai(substream));
  305. }
  306. static set_rate_func fsi_get_info_set_rate(struct fsi_priv *fsi)
  307. {
  308. if (!fsi->info)
  309. return NULL;
  310. return fsi->info->set_rate;
  311. }
  312. static u32 fsi_get_info_flags(struct fsi_priv *fsi)
  313. {
  314. if (!fsi->info)
  315. return 0;
  316. return fsi->info->flags;
  317. }
  318. static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io)
  319. {
  320. int is_play = fsi_stream_is_play(fsi, io);
  321. int is_porta = fsi_is_port_a(fsi);
  322. u32 shift;
  323. if (is_porta)
  324. shift = is_play ? AO_SHIFT : AI_SHIFT;
  325. else
  326. shift = is_play ? BO_SHIFT : BI_SHIFT;
  327. return shift;
  328. }
  329. static int fsi_frame2sample(struct fsi_priv *fsi, int frames)
  330. {
  331. return frames * fsi->chan_num;
  332. }
  333. static int fsi_sample2frame(struct fsi_priv *fsi, int samples)
  334. {
  335. return samples / fsi->chan_num;
  336. }
  337. static int fsi_get_current_fifo_samples(struct fsi_priv *fsi,
  338. struct fsi_stream *io)
  339. {
  340. int is_play = fsi_stream_is_play(fsi, io);
  341. u32 status;
  342. int frames;
  343. status = is_play ?
  344. fsi_reg_read(fsi, DOFF_ST) :
  345. fsi_reg_read(fsi, DIFF_ST);
  346. frames = 0x1ff & (status >> 8);
  347. return fsi_frame2sample(fsi, frames);
  348. }
  349. static void fsi_count_fifo_err(struct fsi_priv *fsi)
  350. {
  351. u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
  352. u32 istatus = fsi_reg_read(fsi, DIFF_ST);
  353. if (ostatus & ERR_OVER)
  354. fsi->playback.oerr_num++;
  355. if (ostatus & ERR_UNDER)
  356. fsi->playback.uerr_num++;
  357. if (istatus & ERR_OVER)
  358. fsi->capture.oerr_num++;
  359. if (istatus & ERR_UNDER)
  360. fsi->capture.uerr_num++;
  361. fsi_reg_write(fsi, DOFF_ST, 0);
  362. fsi_reg_write(fsi, DIFF_ST, 0);
  363. }
  364. /*
  365. * fsi_stream_xx() function
  366. */
  367. static inline int fsi_stream_is_play(struct fsi_priv *fsi,
  368. struct fsi_stream *io)
  369. {
  370. return &fsi->playback == io;
  371. }
  372. static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi,
  373. struct snd_pcm_substream *substream)
  374. {
  375. return fsi_is_play(substream) ? &fsi->playback : &fsi->capture;
  376. }
  377. static int fsi_stream_is_working(struct fsi_priv *fsi,
  378. struct fsi_stream *io)
  379. {
  380. struct fsi_master *master = fsi_get_master(fsi);
  381. unsigned long flags;
  382. int ret;
  383. spin_lock_irqsave(&master->lock, flags);
  384. ret = !!(io->substream && io->substream->runtime);
  385. spin_unlock_irqrestore(&master->lock, flags);
  386. return ret;
  387. }
  388. static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io)
  389. {
  390. return io->priv;
  391. }
  392. static void fsi_stream_init(struct fsi_priv *fsi,
  393. struct fsi_stream *io,
  394. struct snd_pcm_substream *substream)
  395. {
  396. struct snd_pcm_runtime *runtime = substream->runtime;
  397. struct fsi_master *master = fsi_get_master(fsi);
  398. unsigned long flags;
  399. spin_lock_irqsave(&master->lock, flags);
  400. io->substream = substream;
  401. io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size);
  402. io->buff_sample_pos = 0;
  403. io->period_samples = fsi_frame2sample(fsi, runtime->period_size);
  404. io->period_pos = 0;
  405. io->sample_width = samples_to_bytes(runtime, 1);
  406. io->oerr_num = -1; /* ignore 1st err */
  407. io->uerr_num = -1; /* ignore 1st err */
  408. fsi_stream_handler_call(io, init, fsi, io);
  409. spin_unlock_irqrestore(&master->lock, flags);
  410. }
  411. static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io)
  412. {
  413. struct snd_soc_dai *dai = fsi_get_dai(io->substream);
  414. struct fsi_master *master = fsi_get_master(fsi);
  415. unsigned long flags;
  416. spin_lock_irqsave(&master->lock, flags);
  417. if (io->oerr_num > 0)
  418. dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
  419. if (io->uerr_num > 0)
  420. dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
  421. fsi_stream_handler_call(io, quit, fsi, io);
  422. io->substream = NULL;
  423. io->buff_sample_capa = 0;
  424. io->buff_sample_pos = 0;
  425. io->period_samples = 0;
  426. io->period_pos = 0;
  427. io->sample_width = 0;
  428. io->oerr_num = 0;
  429. io->uerr_num = 0;
  430. spin_unlock_irqrestore(&master->lock, flags);
  431. }
  432. static int fsi_stream_transfer(struct fsi_stream *io)
  433. {
  434. struct fsi_priv *fsi = fsi_stream_to_priv(io);
  435. if (!fsi)
  436. return -EIO;
  437. return fsi_stream_handler_call(io, transfer, fsi, io);
  438. }
  439. #define fsi_stream_start(fsi, io)\
  440. fsi_stream_handler_call(io, start_stop, fsi, io, 1)
  441. #define fsi_stream_stop(fsi, io)\
  442. fsi_stream_handler_call(io, start_stop, fsi, io, 0)
  443. static int fsi_stream_probe(struct fsi_priv *fsi)
  444. {
  445. struct fsi_stream *io;
  446. int ret1, ret2;
  447. io = &fsi->playback;
  448. ret1 = fsi_stream_handler_call(io, probe, fsi, io);
  449. io = &fsi->capture;
  450. ret2 = fsi_stream_handler_call(io, probe, fsi, io);
  451. if (ret1 < 0)
  452. return ret1;
  453. if (ret2 < 0)
  454. return ret2;
  455. return 0;
  456. }
  457. static int fsi_stream_remove(struct fsi_priv *fsi)
  458. {
  459. struct fsi_stream *io;
  460. int ret1, ret2;
  461. io = &fsi->playback;
  462. ret1 = fsi_stream_handler_call(io, remove, fsi, io);
  463. io = &fsi->capture;
  464. ret2 = fsi_stream_handler_call(io, remove, fsi, io);
  465. if (ret1 < 0)
  466. return ret1;
  467. if (ret2 < 0)
  468. return ret2;
  469. return 0;
  470. }
  471. /*
  472. * irq function
  473. */
  474. static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io)
  475. {
  476. u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
  477. struct fsi_master *master = fsi_get_master(fsi);
  478. fsi_core_mask_set(master, imsk, data, data);
  479. fsi_core_mask_set(master, iemsk, data, data);
  480. }
  481. static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io)
  482. {
  483. u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
  484. struct fsi_master *master = fsi_get_master(fsi);
  485. fsi_core_mask_set(master, imsk, data, 0);
  486. fsi_core_mask_set(master, iemsk, data, 0);
  487. }
  488. static u32 fsi_irq_get_status(struct fsi_master *master)
  489. {
  490. return fsi_core_read(master, int_st);
  491. }
  492. static void fsi_irq_clear_status(struct fsi_priv *fsi)
  493. {
  494. u32 data = 0;
  495. struct fsi_master *master = fsi_get_master(fsi);
  496. data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback));
  497. data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture));
  498. /* clear interrupt factor */
  499. fsi_core_mask_set(master, int_st, data, 0);
  500. }
  501. /*
  502. * SPDIF master clock function
  503. *
  504. * These functions are used later FSI2
  505. */
  506. static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
  507. {
  508. struct fsi_master *master = fsi_get_master(fsi);
  509. u32 mask, val;
  510. if (master->core->ver < 2) {
  511. pr_err("fsi: register access err (%s)\n", __func__);
  512. return;
  513. }
  514. mask = BP | SE;
  515. val = enable ? mask : 0;
  516. fsi_is_port_a(fsi) ?
  517. fsi_core_mask_set(master, a_mclk, mask, val) :
  518. fsi_core_mask_set(master, b_mclk, mask, val);
  519. }
  520. /*
  521. * clock function
  522. */
  523. static int fsi_set_master_clk(struct device *dev, struct fsi_priv *fsi,
  524. long rate, int enable)
  525. {
  526. struct fsi_master *master = fsi_get_master(fsi);
  527. set_rate_func set_rate = fsi_get_info_set_rate(fsi);
  528. int fsi_ver = master->core->ver;
  529. int ret;
  530. if (!set_rate)
  531. return 0;
  532. ret = set_rate(dev, rate, enable);
  533. if (ret < 0) /* error */
  534. return ret;
  535. if (!enable)
  536. return 0;
  537. if (ret > 0) {
  538. u32 data = 0;
  539. switch (ret & SH_FSI_ACKMD_MASK) {
  540. default:
  541. /* FALL THROUGH */
  542. case SH_FSI_ACKMD_512:
  543. data |= (0x0 << 12);
  544. break;
  545. case SH_FSI_ACKMD_256:
  546. data |= (0x1 << 12);
  547. break;
  548. case SH_FSI_ACKMD_128:
  549. data |= (0x2 << 12);
  550. break;
  551. case SH_FSI_ACKMD_64:
  552. data |= (0x3 << 12);
  553. break;
  554. case SH_FSI_ACKMD_32:
  555. if (fsi_ver < 2)
  556. dev_err(dev, "unsupported ACKMD\n");
  557. else
  558. data |= (0x4 << 12);
  559. break;
  560. }
  561. switch (ret & SH_FSI_BPFMD_MASK) {
  562. default:
  563. /* FALL THROUGH */
  564. case SH_FSI_BPFMD_32:
  565. data |= (0x0 << 8);
  566. break;
  567. case SH_FSI_BPFMD_64:
  568. data |= (0x1 << 8);
  569. break;
  570. case SH_FSI_BPFMD_128:
  571. data |= (0x2 << 8);
  572. break;
  573. case SH_FSI_BPFMD_256:
  574. data |= (0x3 << 8);
  575. break;
  576. case SH_FSI_BPFMD_512:
  577. data |= (0x4 << 8);
  578. break;
  579. case SH_FSI_BPFMD_16:
  580. if (fsi_ver < 2)
  581. dev_err(dev, "unsupported ACKMD\n");
  582. else
  583. data |= (0x7 << 8);
  584. break;
  585. }
  586. fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
  587. udelay(10);
  588. ret = 0;
  589. }
  590. return ret;
  591. }
  592. /*
  593. * pio data transfer handler
  594. */
  595. static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples)
  596. {
  597. u16 *buf = (u16 *)_buf;
  598. int i;
  599. for (i = 0; i < samples; i++)
  600. fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8));
  601. }
  602. static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples)
  603. {
  604. u16 *buf = (u16 *)_buf;
  605. int i;
  606. for (i = 0; i < samples; i++)
  607. *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
  608. }
  609. static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples)
  610. {
  611. u32 *buf = (u32 *)_buf;
  612. int i;
  613. for (i = 0; i < samples; i++)
  614. fsi_reg_write(fsi, DODT, *(buf + i));
  615. }
  616. static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples)
  617. {
  618. u32 *buf = (u32 *)_buf;
  619. int i;
  620. for (i = 0; i < samples; i++)
  621. *(buf + i) = fsi_reg_read(fsi, DIDT);
  622. }
  623. static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io)
  624. {
  625. struct snd_pcm_runtime *runtime = io->substream->runtime;
  626. return runtime->dma_area +
  627. samples_to_bytes(runtime, io->buff_sample_pos);
  628. }
  629. static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io,
  630. void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples),
  631. void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples),
  632. int samples)
  633. {
  634. struct snd_pcm_runtime *runtime;
  635. struct snd_pcm_substream *substream;
  636. u8 *buf;
  637. int over_period;
  638. if (!fsi_stream_is_working(fsi, io))
  639. return -EINVAL;
  640. over_period = 0;
  641. substream = io->substream;
  642. runtime = substream->runtime;
  643. /* FSI FIFO has limit.
  644. * So, this driver can not send periods data at a time
  645. */
  646. if (io->buff_sample_pos >=
  647. io->period_samples * (io->period_pos + 1)) {
  648. over_period = 1;
  649. io->period_pos = (io->period_pos + 1) % runtime->periods;
  650. if (0 == io->period_pos)
  651. io->buff_sample_pos = 0;
  652. }
  653. buf = fsi_pio_get_area(fsi, io);
  654. switch (io->sample_width) {
  655. case 2:
  656. run16(fsi, buf, samples);
  657. break;
  658. case 4:
  659. run32(fsi, buf, samples);
  660. break;
  661. default:
  662. return -EINVAL;
  663. }
  664. /* update buff_sample_pos */
  665. io->buff_sample_pos += samples;
  666. if (over_period)
  667. snd_pcm_period_elapsed(substream);
  668. return 0;
  669. }
  670. static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io)
  671. {
  672. int sample_residues; /* samples in FSI fifo */
  673. int sample_space; /* ALSA free samples space */
  674. int samples;
  675. sample_residues = fsi_get_current_fifo_samples(fsi, io);
  676. sample_space = io->buff_sample_capa - io->buff_sample_pos;
  677. samples = min(sample_residues, sample_space);
  678. return fsi_pio_transfer(fsi, io,
  679. fsi_pio_pop16,
  680. fsi_pio_pop32,
  681. samples);
  682. }
  683. static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io)
  684. {
  685. int sample_residues; /* ALSA residue samples */
  686. int sample_space; /* FSI fifo free samples space */
  687. int samples;
  688. sample_residues = io->buff_sample_capa - io->buff_sample_pos;
  689. sample_space = io->fifo_sample_capa -
  690. fsi_get_current_fifo_samples(fsi, io);
  691. samples = min(sample_residues, sample_space);
  692. return fsi_pio_transfer(fsi, io,
  693. fsi_pio_push16,
  694. fsi_pio_push32,
  695. samples);
  696. }
  697. static void fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
  698. int enable)
  699. {
  700. struct fsi_master *master = fsi_get_master(fsi);
  701. u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
  702. if (enable)
  703. fsi_irq_enable(fsi, io);
  704. else
  705. fsi_irq_disable(fsi, io);
  706. if (fsi_is_clk_master(fsi))
  707. fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
  708. }
  709. static struct fsi_stream_handler fsi_pio_push_handler = {
  710. .transfer = fsi_pio_push,
  711. .start_stop = fsi_pio_start_stop,
  712. };
  713. static struct fsi_stream_handler fsi_pio_pop_handler = {
  714. .transfer = fsi_pio_pop,
  715. .start_stop = fsi_pio_start_stop,
  716. };
  717. static irqreturn_t fsi_interrupt(int irq, void *data)
  718. {
  719. struct fsi_master *master = data;
  720. u32 int_st = fsi_irq_get_status(master);
  721. /* clear irq status */
  722. fsi_master_mask_set(master, SOFT_RST, IR, 0);
  723. fsi_master_mask_set(master, SOFT_RST, IR, IR);
  724. if (int_st & AB_IO(1, AO_SHIFT))
  725. fsi_stream_transfer(&master->fsia.playback);
  726. if (int_st & AB_IO(1, BO_SHIFT))
  727. fsi_stream_transfer(&master->fsib.playback);
  728. if (int_st & AB_IO(1, AI_SHIFT))
  729. fsi_stream_transfer(&master->fsia.capture);
  730. if (int_st & AB_IO(1, BI_SHIFT))
  731. fsi_stream_transfer(&master->fsib.capture);
  732. fsi_count_fifo_err(&master->fsia);
  733. fsi_count_fifo_err(&master->fsib);
  734. fsi_irq_clear_status(&master->fsia);
  735. fsi_irq_clear_status(&master->fsib);
  736. return IRQ_HANDLED;
  737. }
  738. /*
  739. * dma data transfer handler
  740. */
  741. static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io)
  742. {
  743. struct snd_pcm_runtime *runtime = io->substream->runtime;
  744. struct snd_soc_dai *dai = fsi_get_dai(io->substream);
  745. enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ?
  746. DMA_TO_DEVICE : DMA_FROM_DEVICE;
  747. io->dma = dma_map_single(dai->dev, runtime->dma_area,
  748. snd_pcm_lib_buffer_bytes(io->substream), dir);
  749. return 0;
  750. }
  751. static int fsi_dma_quit(struct fsi_priv *fsi, struct fsi_stream *io)
  752. {
  753. struct snd_soc_dai *dai = fsi_get_dai(io->substream);
  754. enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ?
  755. DMA_TO_DEVICE : DMA_FROM_DEVICE;
  756. dma_unmap_single(dai->dev, io->dma,
  757. snd_pcm_lib_buffer_bytes(io->substream), dir);
  758. return 0;
  759. }
  760. static void fsi_dma_complete(void *data)
  761. {
  762. struct fsi_stream *io = (struct fsi_stream *)data;
  763. struct fsi_priv *fsi = fsi_stream_to_priv(io);
  764. struct snd_pcm_runtime *runtime = io->substream->runtime;
  765. struct snd_soc_dai *dai = fsi_get_dai(io->substream);
  766. enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ?
  767. DMA_TO_DEVICE : DMA_FROM_DEVICE;
  768. dma_sync_single_for_cpu(dai->dev, io->dma,
  769. samples_to_bytes(runtime, io->period_samples), dir);
  770. io->buff_sample_pos += io->period_samples;
  771. io->period_pos++;
  772. if (io->period_pos >= runtime->periods) {
  773. io->period_pos = 0;
  774. io->buff_sample_pos = 0;
  775. }
  776. fsi_count_fifo_err(fsi);
  777. fsi_stream_transfer(io);
  778. snd_pcm_period_elapsed(io->substream);
  779. }
  780. static dma_addr_t fsi_dma_get_area(struct fsi_stream *io)
  781. {
  782. struct snd_pcm_runtime *runtime = io->substream->runtime;
  783. return io->dma + samples_to_bytes(runtime, io->buff_sample_pos);
  784. }
  785. static void fsi_dma_do_tasklet(unsigned long data)
  786. {
  787. struct fsi_stream *io = (struct fsi_stream *)data;
  788. struct fsi_priv *fsi = fsi_stream_to_priv(io);
  789. struct dma_chan *chan;
  790. struct snd_soc_dai *dai;
  791. struct dma_async_tx_descriptor *desc;
  792. struct scatterlist sg;
  793. struct snd_pcm_runtime *runtime;
  794. enum dma_data_direction dir;
  795. dma_cookie_t cookie;
  796. int is_play = fsi_stream_is_play(fsi, io);
  797. int len;
  798. dma_addr_t buf;
  799. if (!fsi_stream_is_working(fsi, io))
  800. return;
  801. dai = fsi_get_dai(io->substream);
  802. chan = io->chan;
  803. runtime = io->substream->runtime;
  804. dir = is_play ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
  805. len = samples_to_bytes(runtime, io->period_samples);
  806. buf = fsi_dma_get_area(io);
  807. dma_sync_single_for_device(dai->dev, io->dma, len, dir);
  808. sg_init_table(&sg, 1);
  809. sg_set_page(&sg, pfn_to_page(PFN_DOWN(buf)),
  810. len , offset_in_page(buf));
  811. sg_dma_address(&sg) = buf;
  812. sg_dma_len(&sg) = len;
  813. desc = dmaengine_prep_slave_sg(chan, &sg, 1, dir,
  814. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  815. if (!desc) {
  816. dev_err(dai->dev, "dmaengine_prep_slave_sg() fail\n");
  817. return;
  818. }
  819. desc->callback = fsi_dma_complete;
  820. desc->callback_param = io;
  821. cookie = desc->tx_submit(desc);
  822. if (cookie < 0) {
  823. dev_err(dai->dev, "tx_submit() fail\n");
  824. return;
  825. }
  826. dma_async_issue_pending(chan);
  827. /*
  828. * FIXME
  829. *
  830. * In DMAEngine case, codec and FSI cannot be started simultaneously
  831. * since FSI is using tasklet.
  832. * Therefore, in capture case, probably FSI FIFO will have got
  833. * overflow error in this point.
  834. * in that case, DMA cannot start transfer until error was cleared.
  835. */
  836. if (!is_play) {
  837. if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) {
  838. fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
  839. fsi_reg_write(fsi, DIFF_ST, 0);
  840. }
  841. }
  842. }
  843. static bool fsi_dma_filter(struct dma_chan *chan, void *param)
  844. {
  845. struct sh_dmae_slave *slave = param;
  846. chan->private = slave;
  847. return true;
  848. }
  849. static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io)
  850. {
  851. tasklet_schedule(&io->tasklet);
  852. return 0;
  853. }
  854. static void fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
  855. int start)
  856. {
  857. u32 bws;
  858. u32 dma;
  859. switch (io->sample_width * start) {
  860. case 2:
  861. bws = CR_BWS_16;
  862. dma = VDMD_STREAM | DMA_ON;
  863. break;
  864. case 4:
  865. bws = CR_BWS_24;
  866. dma = VDMD_BACK | DMA_ON;
  867. break;
  868. default:
  869. bws = 0;
  870. dma = 0;
  871. }
  872. fsi_reg_mask_set(fsi, DO_FMT, CR_BWS_MASK, bws);
  873. fsi_reg_write(fsi, OUT_DMAC, dma);
  874. }
  875. static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io)
  876. {
  877. dma_cap_mask_t mask;
  878. dma_cap_zero(mask);
  879. dma_cap_set(DMA_SLAVE, mask);
  880. io->chan = dma_request_channel(mask, fsi_dma_filter, &io->slave);
  881. if (!io->chan)
  882. return -EIO;
  883. tasklet_init(&io->tasklet, fsi_dma_do_tasklet, (unsigned long)io);
  884. return 0;
  885. }
  886. static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io)
  887. {
  888. tasklet_kill(&io->tasklet);
  889. fsi_stream_stop(fsi, io);
  890. if (io->chan)
  891. dma_release_channel(io->chan);
  892. io->chan = NULL;
  893. return 0;
  894. }
  895. static struct fsi_stream_handler fsi_dma_push_handler = {
  896. .init = fsi_dma_init,
  897. .quit = fsi_dma_quit,
  898. .probe = fsi_dma_probe,
  899. .transfer = fsi_dma_transfer,
  900. .remove = fsi_dma_remove,
  901. .start_stop = fsi_dma_push_start_stop,
  902. };
  903. /*
  904. * dai ops
  905. */
  906. static void fsi_fifo_init(struct fsi_priv *fsi,
  907. struct fsi_stream *io,
  908. struct device *dev)
  909. {
  910. struct fsi_master *master = fsi_get_master(fsi);
  911. int is_play = fsi_stream_is_play(fsi, io);
  912. u32 shift, i;
  913. int frame_capa;
  914. /* get on-chip RAM capacity */
  915. shift = fsi_master_read(master, FIFO_SZ);
  916. shift >>= fsi_get_port_shift(fsi, io);
  917. shift &= FIFO_SZ_MASK;
  918. frame_capa = 256 << shift;
  919. dev_dbg(dev, "fifo = %d words\n", frame_capa);
  920. /*
  921. * The maximum number of sample data varies depending
  922. * on the number of channels selected for the format.
  923. *
  924. * FIFOs are used in 4-channel units in 3-channel mode
  925. * and in 8-channel units in 5- to 7-channel mode
  926. * meaning that more FIFOs than the required size of DPRAM
  927. * are used.
  928. *
  929. * ex) if 256 words of DP-RAM is connected
  930. * 1 channel: 256 (256 x 1 = 256)
  931. * 2 channels: 128 (128 x 2 = 256)
  932. * 3 channels: 64 ( 64 x 3 = 192)
  933. * 4 channels: 64 ( 64 x 4 = 256)
  934. * 5 channels: 32 ( 32 x 5 = 160)
  935. * 6 channels: 32 ( 32 x 6 = 192)
  936. * 7 channels: 32 ( 32 x 7 = 224)
  937. * 8 channels: 32 ( 32 x 8 = 256)
  938. */
  939. for (i = 1; i < fsi->chan_num; i <<= 1)
  940. frame_capa >>= 1;
  941. dev_dbg(dev, "%d channel %d store\n",
  942. fsi->chan_num, frame_capa);
  943. io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
  944. /*
  945. * set interrupt generation factor
  946. * clear FIFO
  947. */
  948. if (is_play) {
  949. fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
  950. fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
  951. } else {
  952. fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
  953. fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
  954. }
  955. }
  956. static int fsi_hw_startup(struct fsi_priv *fsi,
  957. struct fsi_stream *io,
  958. struct device *dev)
  959. {
  960. struct fsi_master *master = fsi_get_master(fsi);
  961. int fsi_ver = master->core->ver;
  962. u32 flags = fsi_get_info_flags(fsi);
  963. u32 data = 0;
  964. /* clock setting */
  965. if (fsi_is_clk_master(fsi))
  966. data = DIMD | DOMD;
  967. fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
  968. /* clock inversion (CKG2) */
  969. data = 0;
  970. if (SH_FSI_LRM_INV & flags)
  971. data |= 1 << 12;
  972. if (SH_FSI_BRM_INV & flags)
  973. data |= 1 << 8;
  974. if (SH_FSI_LRS_INV & flags)
  975. data |= 1 << 4;
  976. if (SH_FSI_BRS_INV & flags)
  977. data |= 1 << 0;
  978. fsi_reg_write(fsi, CKG2, data);
  979. /* set format */
  980. fsi_reg_write(fsi, DO_FMT, fsi->do_fmt);
  981. fsi_reg_write(fsi, DI_FMT, fsi->di_fmt);
  982. /* spdif ? */
  983. if (fsi_is_spdif(fsi)) {
  984. fsi_spdif_clk_ctrl(fsi, 1);
  985. fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
  986. }
  987. /*
  988. * FIXME
  989. *
  990. * FSI driver assumed that data package is in-back.
  991. * FSI2 chip can select it.
  992. */
  993. if (fsi_ver >= 2) {
  994. fsi_reg_write(fsi, OUT_DMAC, VDMD_BACK);
  995. fsi_reg_write(fsi, IN_DMAC, VDMD_BACK);
  996. }
  997. /* irq clear */
  998. fsi_irq_disable(fsi, io);
  999. fsi_irq_clear_status(fsi);
  1000. /* fifo init */
  1001. fsi_fifo_init(fsi, io, dev);
  1002. return 0;
  1003. }
  1004. static void fsi_hw_shutdown(struct fsi_priv *fsi,
  1005. struct device *dev)
  1006. {
  1007. if (fsi_is_clk_master(fsi))
  1008. fsi_set_master_clk(dev, fsi, fsi->rate, 0);
  1009. }
  1010. static int fsi_dai_startup(struct snd_pcm_substream *substream,
  1011. struct snd_soc_dai *dai)
  1012. {
  1013. struct fsi_priv *fsi = fsi_get_priv(substream);
  1014. return fsi_hw_startup(fsi, fsi_stream_get(fsi, substream), dai->dev);
  1015. }
  1016. static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
  1017. struct snd_soc_dai *dai)
  1018. {
  1019. struct fsi_priv *fsi = fsi_get_priv(substream);
  1020. fsi_hw_shutdown(fsi, dai->dev);
  1021. fsi->rate = 0;
  1022. }
  1023. static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
  1024. struct snd_soc_dai *dai)
  1025. {
  1026. struct fsi_priv *fsi = fsi_get_priv(substream);
  1027. struct fsi_stream *io = fsi_stream_get(fsi, substream);
  1028. int ret = 0;
  1029. switch (cmd) {
  1030. case SNDRV_PCM_TRIGGER_START:
  1031. fsi_stream_init(fsi, io, substream);
  1032. ret = fsi_stream_transfer(io);
  1033. if (0 == ret)
  1034. fsi_stream_start(fsi, io);
  1035. break;
  1036. case SNDRV_PCM_TRIGGER_STOP:
  1037. fsi_stream_stop(fsi, io);
  1038. fsi_stream_quit(fsi, io);
  1039. break;
  1040. }
  1041. return ret;
  1042. }
  1043. static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
  1044. {
  1045. u32 data = 0;
  1046. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1047. case SND_SOC_DAIFMT_I2S:
  1048. data = CR_I2S;
  1049. fsi->chan_num = 2;
  1050. break;
  1051. case SND_SOC_DAIFMT_LEFT_J:
  1052. data = CR_PCM;
  1053. fsi->chan_num = 2;
  1054. break;
  1055. default:
  1056. return -EINVAL;
  1057. }
  1058. fsi->do_fmt = data;
  1059. fsi->di_fmt = data;
  1060. return 0;
  1061. }
  1062. static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
  1063. {
  1064. struct fsi_master *master = fsi_get_master(fsi);
  1065. u32 data = 0;
  1066. if (master->core->ver < 2)
  1067. return -EINVAL;
  1068. data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM;
  1069. fsi->chan_num = 2;
  1070. fsi->spdif = 1;
  1071. fsi->do_fmt = data;
  1072. fsi->di_fmt = data;
  1073. return 0;
  1074. }
  1075. static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  1076. {
  1077. struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
  1078. set_rate_func set_rate = fsi_get_info_set_rate(fsi);
  1079. u32 flags = fsi_get_info_flags(fsi);
  1080. int ret;
  1081. /* set master/slave audio interface */
  1082. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1083. case SND_SOC_DAIFMT_CBM_CFM:
  1084. fsi->clk_master = 1;
  1085. break;
  1086. case SND_SOC_DAIFMT_CBS_CFS:
  1087. break;
  1088. default:
  1089. return -EINVAL;
  1090. }
  1091. if (fsi_is_clk_master(fsi) && !set_rate) {
  1092. dev_err(dai->dev, "platform doesn't have set_rate\n");
  1093. return -EINVAL;
  1094. }
  1095. /* set format */
  1096. switch (flags & SH_FSI_FMT_MASK) {
  1097. case SH_FSI_FMT_DAI:
  1098. ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
  1099. break;
  1100. case SH_FSI_FMT_SPDIF:
  1101. ret = fsi_set_fmt_spdif(fsi);
  1102. break;
  1103. default:
  1104. ret = -EINVAL;
  1105. }
  1106. return ret;
  1107. }
  1108. static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
  1109. struct snd_pcm_hw_params *params,
  1110. struct snd_soc_dai *dai)
  1111. {
  1112. struct fsi_priv *fsi = fsi_get_priv(substream);
  1113. long rate = params_rate(params);
  1114. int ret;
  1115. if (!fsi_is_clk_master(fsi))
  1116. return 0;
  1117. ret = fsi_set_master_clk(dai->dev, fsi, rate, 1);
  1118. if (ret < 0)
  1119. return ret;
  1120. fsi->rate = rate;
  1121. return ret;
  1122. }
  1123. static const struct snd_soc_dai_ops fsi_dai_ops = {
  1124. .startup = fsi_dai_startup,
  1125. .shutdown = fsi_dai_shutdown,
  1126. .trigger = fsi_dai_trigger,
  1127. .set_fmt = fsi_dai_set_fmt,
  1128. .hw_params = fsi_dai_hw_params,
  1129. };
  1130. /*
  1131. * pcm ops
  1132. */
  1133. static struct snd_pcm_hardware fsi_pcm_hardware = {
  1134. .info = SNDRV_PCM_INFO_INTERLEAVED |
  1135. SNDRV_PCM_INFO_MMAP |
  1136. SNDRV_PCM_INFO_MMAP_VALID |
  1137. SNDRV_PCM_INFO_PAUSE,
  1138. .formats = FSI_FMTS,
  1139. .rates = FSI_RATES,
  1140. .rate_min = 8000,
  1141. .rate_max = 192000,
  1142. .channels_min = 1,
  1143. .channels_max = 2,
  1144. .buffer_bytes_max = 64 * 1024,
  1145. .period_bytes_min = 32,
  1146. .period_bytes_max = 8192,
  1147. .periods_min = 1,
  1148. .periods_max = 32,
  1149. .fifo_size = 256,
  1150. };
  1151. static int fsi_pcm_open(struct snd_pcm_substream *substream)
  1152. {
  1153. struct snd_pcm_runtime *runtime = substream->runtime;
  1154. int ret = 0;
  1155. snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
  1156. ret = snd_pcm_hw_constraint_integer(runtime,
  1157. SNDRV_PCM_HW_PARAM_PERIODS);
  1158. return ret;
  1159. }
  1160. static int fsi_hw_params(struct snd_pcm_substream *substream,
  1161. struct snd_pcm_hw_params *hw_params)
  1162. {
  1163. return snd_pcm_lib_malloc_pages(substream,
  1164. params_buffer_bytes(hw_params));
  1165. }
  1166. static int fsi_hw_free(struct snd_pcm_substream *substream)
  1167. {
  1168. return snd_pcm_lib_free_pages(substream);
  1169. }
  1170. static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
  1171. {
  1172. struct fsi_priv *fsi = fsi_get_priv(substream);
  1173. struct fsi_stream *io = fsi_stream_get(fsi, substream);
  1174. return fsi_sample2frame(fsi, io->buff_sample_pos);
  1175. }
  1176. static struct snd_pcm_ops fsi_pcm_ops = {
  1177. .open = fsi_pcm_open,
  1178. .ioctl = snd_pcm_lib_ioctl,
  1179. .hw_params = fsi_hw_params,
  1180. .hw_free = fsi_hw_free,
  1181. .pointer = fsi_pointer,
  1182. };
  1183. /*
  1184. * snd_soc_platform
  1185. */
  1186. #define PREALLOC_BUFFER (32 * 1024)
  1187. #define PREALLOC_BUFFER_MAX (32 * 1024)
  1188. static void fsi_pcm_free(struct snd_pcm *pcm)
  1189. {
  1190. snd_pcm_lib_preallocate_free_for_all(pcm);
  1191. }
  1192. static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd)
  1193. {
  1194. struct snd_pcm *pcm = rtd->pcm;
  1195. /*
  1196. * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
  1197. * in MMAP mode (i.e. aplay -M)
  1198. */
  1199. return snd_pcm_lib_preallocate_pages_for_all(
  1200. pcm,
  1201. SNDRV_DMA_TYPE_CONTINUOUS,
  1202. snd_dma_continuous_data(GFP_KERNEL),
  1203. PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
  1204. }
  1205. /*
  1206. * alsa struct
  1207. */
  1208. static struct snd_soc_dai_driver fsi_soc_dai[] = {
  1209. {
  1210. .name = "fsia-dai",
  1211. .playback = {
  1212. .rates = FSI_RATES,
  1213. .formats = FSI_FMTS,
  1214. .channels_min = 1,
  1215. .channels_max = 8,
  1216. },
  1217. .capture = {
  1218. .rates = FSI_RATES,
  1219. .formats = FSI_FMTS,
  1220. .channels_min = 1,
  1221. .channels_max = 8,
  1222. },
  1223. .ops = &fsi_dai_ops,
  1224. },
  1225. {
  1226. .name = "fsib-dai",
  1227. .playback = {
  1228. .rates = FSI_RATES,
  1229. .formats = FSI_FMTS,
  1230. .channels_min = 1,
  1231. .channels_max = 8,
  1232. },
  1233. .capture = {
  1234. .rates = FSI_RATES,
  1235. .formats = FSI_FMTS,
  1236. .channels_min = 1,
  1237. .channels_max = 8,
  1238. },
  1239. .ops = &fsi_dai_ops,
  1240. },
  1241. };
  1242. static struct snd_soc_platform_driver fsi_soc_platform = {
  1243. .ops = &fsi_pcm_ops,
  1244. .pcm_new = fsi_pcm_new,
  1245. .pcm_free = fsi_pcm_free,
  1246. };
  1247. /*
  1248. * platform function
  1249. */
  1250. static void fsi_handler_init(struct fsi_priv *fsi)
  1251. {
  1252. fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */
  1253. fsi->playback.priv = fsi;
  1254. fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */
  1255. fsi->capture.priv = fsi;
  1256. if (fsi->info->tx_id) {
  1257. fsi->playback.slave.slave_id = fsi->info->tx_id;
  1258. fsi->playback.handler = &fsi_dma_push_handler;
  1259. }
  1260. }
  1261. static int fsi_probe(struct platform_device *pdev)
  1262. {
  1263. struct fsi_master *master;
  1264. const struct platform_device_id *id_entry;
  1265. struct sh_fsi_platform_info *info = pdev->dev.platform_data;
  1266. struct resource *res;
  1267. unsigned int irq;
  1268. int ret;
  1269. id_entry = pdev->id_entry;
  1270. if (!id_entry) {
  1271. dev_err(&pdev->dev, "unknown fsi device\n");
  1272. return -ENODEV;
  1273. }
  1274. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1275. irq = platform_get_irq(pdev, 0);
  1276. if (!res || (int)irq <= 0) {
  1277. dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
  1278. ret = -ENODEV;
  1279. goto exit;
  1280. }
  1281. master = kzalloc(sizeof(*master), GFP_KERNEL);
  1282. if (!master) {
  1283. dev_err(&pdev->dev, "Could not allocate master\n");
  1284. ret = -ENOMEM;
  1285. goto exit;
  1286. }
  1287. master->base = ioremap_nocache(res->start, resource_size(res));
  1288. if (!master->base) {
  1289. ret = -ENXIO;
  1290. dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
  1291. goto exit_kfree;
  1292. }
  1293. /* master setting */
  1294. master->irq = irq;
  1295. master->core = (struct fsi_core *)id_entry->driver_data;
  1296. spin_lock_init(&master->lock);
  1297. /* FSI A setting */
  1298. master->fsia.base = master->base;
  1299. master->fsia.master = master;
  1300. master->fsia.info = &info->port_a;
  1301. fsi_handler_init(&master->fsia);
  1302. ret = fsi_stream_probe(&master->fsia);
  1303. if (ret < 0) {
  1304. dev_err(&pdev->dev, "FSIA stream probe failed\n");
  1305. goto exit_iounmap;
  1306. }
  1307. /* FSI B setting */
  1308. master->fsib.base = master->base + 0x40;
  1309. master->fsib.master = master;
  1310. master->fsib.info = &info->port_b;
  1311. fsi_handler_init(&master->fsib);
  1312. ret = fsi_stream_probe(&master->fsib);
  1313. if (ret < 0) {
  1314. dev_err(&pdev->dev, "FSIB stream probe failed\n");
  1315. goto exit_fsia;
  1316. }
  1317. pm_runtime_enable(&pdev->dev);
  1318. dev_set_drvdata(&pdev->dev, master);
  1319. ret = request_irq(irq, &fsi_interrupt, 0,
  1320. id_entry->name, master);
  1321. if (ret) {
  1322. dev_err(&pdev->dev, "irq request err\n");
  1323. goto exit_fsib;
  1324. }
  1325. ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
  1326. if (ret < 0) {
  1327. dev_err(&pdev->dev, "cannot snd soc register\n");
  1328. goto exit_free_irq;
  1329. }
  1330. ret = snd_soc_register_dais(&pdev->dev, fsi_soc_dai,
  1331. ARRAY_SIZE(fsi_soc_dai));
  1332. if (ret < 0) {
  1333. dev_err(&pdev->dev, "cannot snd dai register\n");
  1334. goto exit_snd_soc;
  1335. }
  1336. return ret;
  1337. exit_snd_soc:
  1338. snd_soc_unregister_platform(&pdev->dev);
  1339. exit_free_irq:
  1340. free_irq(irq, master);
  1341. exit_fsib:
  1342. fsi_stream_remove(&master->fsib);
  1343. exit_fsia:
  1344. fsi_stream_remove(&master->fsia);
  1345. exit_iounmap:
  1346. iounmap(master->base);
  1347. pm_runtime_disable(&pdev->dev);
  1348. exit_kfree:
  1349. kfree(master);
  1350. master = NULL;
  1351. exit:
  1352. return ret;
  1353. }
  1354. static int fsi_remove(struct platform_device *pdev)
  1355. {
  1356. struct fsi_master *master;
  1357. master = dev_get_drvdata(&pdev->dev);
  1358. free_irq(master->irq, master);
  1359. pm_runtime_disable(&pdev->dev);
  1360. snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai));
  1361. snd_soc_unregister_platform(&pdev->dev);
  1362. fsi_stream_remove(&master->fsia);
  1363. fsi_stream_remove(&master->fsib);
  1364. iounmap(master->base);
  1365. kfree(master);
  1366. return 0;
  1367. }
  1368. static void __fsi_suspend(struct fsi_priv *fsi,
  1369. struct fsi_stream *io,
  1370. struct device *dev)
  1371. {
  1372. if (!fsi_stream_is_working(fsi, io))
  1373. return;
  1374. fsi_stream_stop(fsi, io);
  1375. fsi_hw_shutdown(fsi, dev);
  1376. }
  1377. static void __fsi_resume(struct fsi_priv *fsi,
  1378. struct fsi_stream *io,
  1379. struct device *dev)
  1380. {
  1381. if (!fsi_stream_is_working(fsi, io))
  1382. return;
  1383. fsi_hw_startup(fsi, io, dev);
  1384. if (fsi_is_clk_master(fsi) && fsi->rate)
  1385. fsi_set_master_clk(dev, fsi, fsi->rate, 1);
  1386. fsi_stream_start(fsi, io);
  1387. }
  1388. static int fsi_suspend(struct device *dev)
  1389. {
  1390. struct fsi_master *master = dev_get_drvdata(dev);
  1391. struct fsi_priv *fsia = &master->fsia;
  1392. struct fsi_priv *fsib = &master->fsib;
  1393. __fsi_suspend(fsia, &fsia->playback, dev);
  1394. __fsi_suspend(fsia, &fsia->capture, dev);
  1395. __fsi_suspend(fsib, &fsib->playback, dev);
  1396. __fsi_suspend(fsib, &fsib->capture, dev);
  1397. return 0;
  1398. }
  1399. static int fsi_resume(struct device *dev)
  1400. {
  1401. struct fsi_master *master = dev_get_drvdata(dev);
  1402. struct fsi_priv *fsia = &master->fsia;
  1403. struct fsi_priv *fsib = &master->fsib;
  1404. __fsi_resume(fsia, &fsia->playback, dev);
  1405. __fsi_resume(fsia, &fsia->capture, dev);
  1406. __fsi_resume(fsib, &fsib->playback, dev);
  1407. __fsi_resume(fsib, &fsib->capture, dev);
  1408. return 0;
  1409. }
  1410. static struct dev_pm_ops fsi_pm_ops = {
  1411. .suspend = fsi_suspend,
  1412. .resume = fsi_resume,
  1413. };
  1414. static struct fsi_core fsi1_core = {
  1415. .ver = 1,
  1416. /* Interrupt */
  1417. .int_st = INT_ST,
  1418. .iemsk = IEMSK,
  1419. .imsk = IMSK,
  1420. };
  1421. static struct fsi_core fsi2_core = {
  1422. .ver = 2,
  1423. /* Interrupt */
  1424. .int_st = CPU_INT_ST,
  1425. .iemsk = CPU_IEMSK,
  1426. .imsk = CPU_IMSK,
  1427. .a_mclk = A_MST_CTLR,
  1428. .b_mclk = B_MST_CTLR,
  1429. };
  1430. static struct platform_device_id fsi_id_table[] = {
  1431. { "sh_fsi", (kernel_ulong_t)&fsi1_core },
  1432. { "sh_fsi2", (kernel_ulong_t)&fsi2_core },
  1433. {},
  1434. };
  1435. MODULE_DEVICE_TABLE(platform, fsi_id_table);
  1436. static struct platform_driver fsi_driver = {
  1437. .driver = {
  1438. .name = "fsi-pcm-audio",
  1439. .pm = &fsi_pm_ops,
  1440. },
  1441. .probe = fsi_probe,
  1442. .remove = fsi_remove,
  1443. .id_table = fsi_id_table,
  1444. };
  1445. module_platform_driver(fsi_driver);
  1446. MODULE_LICENSE("GPL");
  1447. MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
  1448. MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
  1449. MODULE_ALIAS("platform:fsi-pcm-audio");