fsl_udc_core.c 73 KB

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  1. /*
  2. * Copyright (C) 2004-2007,2011 Freescale Semiconductor, Inc.
  3. * All rights reserved.
  4. *
  5. * Author: Li Yang <leoli@freescale.com>
  6. * Jiang Bo <tanya.jiang@freescale.com>
  7. *
  8. * Description:
  9. * Freescale high-speed USB SOC DR module device controller driver.
  10. * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
  11. * The driver is previously named as mpc_udc. Based on bare board
  12. * code from Dave Liu and Shlomi Gridish.
  13. *
  14. * This program is free software; you can redistribute it and/or modify it
  15. * under the terms of the GNU General Public License as published by the
  16. * Free Software Foundation; either version 2 of the License, or (at your
  17. * option) any later version.
  18. */
  19. #undef VERBOSE
  20. #include <linux/module.h>
  21. #include <linux/kernel.h>
  22. #include <linux/ioport.h>
  23. #include <linux/types.h>
  24. #include <linux/errno.h>
  25. #include <linux/slab.h>
  26. #include <linux/init.h>
  27. #include <linux/list.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/proc_fs.h>
  30. #include <linux/mm.h>
  31. #include <linux/moduleparam.h>
  32. #include <linux/device.h>
  33. #include <linux/usb/ch9.h>
  34. #include <linux/usb/gadget.h>
  35. #include <linux/usb/otg.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/platform_device.h>
  38. #include <linux/fsl_devices.h>
  39. #include <linux/dmapool.h>
  40. #include <linux/delay.h>
  41. #include <asm/byteorder.h>
  42. #include <asm/io.h>
  43. #include <asm/unaligned.h>
  44. #include <asm/dma.h>
  45. #include "fsl_usb2_udc.h"
  46. #define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver"
  47. #define DRIVER_AUTHOR "Li Yang/Jiang Bo"
  48. #define DRIVER_VERSION "Apr 20, 2007"
  49. #define DMA_ADDR_INVALID (~(dma_addr_t)0)
  50. static const char driver_name[] = "fsl-usb2-udc";
  51. static const char driver_desc[] = DRIVER_DESC;
  52. static struct usb_dr_device *dr_regs;
  53. #ifndef CONFIG_ARCH_MXC
  54. static struct usb_sys_interface *usb_sys_regs;
  55. #endif
  56. /* it is initialized in probe() */
  57. static struct fsl_udc *udc_controller = NULL;
  58. static const struct usb_endpoint_descriptor
  59. fsl_ep0_desc = {
  60. .bLength = USB_DT_ENDPOINT_SIZE,
  61. .bDescriptorType = USB_DT_ENDPOINT,
  62. .bEndpointAddress = 0,
  63. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  64. .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD,
  65. };
  66. static void fsl_ep_fifo_flush(struct usb_ep *_ep);
  67. #ifdef CONFIG_PPC32
  68. /*
  69. * On some SoCs, the USB controller registers can be big or little endian,
  70. * depending on the version of the chip. In order to be able to run the
  71. * same kernel binary on 2 different versions of an SoC, the BE/LE decision
  72. * must be made at run time. _fsl_readl and fsl_writel are pointers to the
  73. * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
  74. * call through those pointers. Platform code for SoCs that have BE USB
  75. * registers should set pdata->big_endian_mmio flag.
  76. *
  77. * This also applies to controller-to-cpu accessors for the USB descriptors,
  78. * since their endianness is also SoC dependant. Platform code for SoCs that
  79. * have BE USB descriptors should set pdata->big_endian_desc flag.
  80. */
  81. static u32 _fsl_readl_be(const unsigned __iomem *p)
  82. {
  83. return in_be32(p);
  84. }
  85. static u32 _fsl_readl_le(const unsigned __iomem *p)
  86. {
  87. return in_le32(p);
  88. }
  89. static void _fsl_writel_be(u32 v, unsigned __iomem *p)
  90. {
  91. out_be32(p, v);
  92. }
  93. static void _fsl_writel_le(u32 v, unsigned __iomem *p)
  94. {
  95. out_le32(p, v);
  96. }
  97. static u32 (*_fsl_readl)(const unsigned __iomem *p);
  98. static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
  99. #define fsl_readl(p) (*_fsl_readl)((p))
  100. #define fsl_writel(v, p) (*_fsl_writel)((v), (p))
  101. static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
  102. {
  103. if (pdata->big_endian_mmio) {
  104. _fsl_readl = _fsl_readl_be;
  105. _fsl_writel = _fsl_writel_be;
  106. } else {
  107. _fsl_readl = _fsl_readl_le;
  108. _fsl_writel = _fsl_writel_le;
  109. }
  110. }
  111. static inline u32 cpu_to_hc32(const u32 x)
  112. {
  113. return udc_controller->pdata->big_endian_desc
  114. ? (__force u32)cpu_to_be32(x)
  115. : (__force u32)cpu_to_le32(x);
  116. }
  117. static inline u32 hc32_to_cpu(const u32 x)
  118. {
  119. return udc_controller->pdata->big_endian_desc
  120. ? be32_to_cpu((__force __be32)x)
  121. : le32_to_cpu((__force __le32)x);
  122. }
  123. #else /* !CONFIG_PPC32 */
  124. static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
  125. #define fsl_readl(addr) readl(addr)
  126. #define fsl_writel(val32, addr) writel(val32, addr)
  127. #define cpu_to_hc32(x) cpu_to_le32(x)
  128. #define hc32_to_cpu(x) le32_to_cpu(x)
  129. #endif /* CONFIG_PPC32 */
  130. /********************************************************************
  131. * Internal Used Function
  132. ********************************************************************/
  133. /*-----------------------------------------------------------------
  134. * done() - retire a request; caller blocked irqs
  135. * @status : request status to be set, only works when
  136. * request is still in progress.
  137. *--------------------------------------------------------------*/
  138. static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
  139. {
  140. struct fsl_udc *udc = NULL;
  141. unsigned char stopped = ep->stopped;
  142. struct ep_td_struct *curr_td, *next_td;
  143. int j;
  144. udc = (struct fsl_udc *)ep->udc;
  145. /* Removed the req from fsl_ep->queue */
  146. list_del_init(&req->queue);
  147. /* req.status should be set as -EINPROGRESS in ep_queue() */
  148. if (req->req.status == -EINPROGRESS)
  149. req->req.status = status;
  150. else
  151. status = req->req.status;
  152. /* Free dtd for the request */
  153. next_td = req->head;
  154. for (j = 0; j < req->dtd_count; j++) {
  155. curr_td = next_td;
  156. if (j != req->dtd_count - 1) {
  157. next_td = curr_td->next_td_virt;
  158. }
  159. dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
  160. }
  161. if (req->mapped) {
  162. dma_unmap_single(ep->udc->gadget.dev.parent,
  163. req->req.dma, req->req.length,
  164. ep_is_in(ep)
  165. ? DMA_TO_DEVICE
  166. : DMA_FROM_DEVICE);
  167. req->req.dma = DMA_ADDR_INVALID;
  168. req->mapped = 0;
  169. } else
  170. dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
  171. req->req.dma, req->req.length,
  172. ep_is_in(ep)
  173. ? DMA_TO_DEVICE
  174. : DMA_FROM_DEVICE);
  175. if (status && (status != -ESHUTDOWN))
  176. VDBG("complete %s req %p stat %d len %u/%u",
  177. ep->ep.name, &req->req, status,
  178. req->req.actual, req->req.length);
  179. ep->stopped = 1;
  180. spin_unlock(&ep->udc->lock);
  181. /* complete() is from gadget layer,
  182. * eg fsg->bulk_in_complete() */
  183. if (req->req.complete)
  184. req->req.complete(&ep->ep, &req->req);
  185. spin_lock(&ep->udc->lock);
  186. ep->stopped = stopped;
  187. }
  188. /*-----------------------------------------------------------------
  189. * nuke(): delete all requests related to this ep
  190. * called with spinlock held
  191. *--------------------------------------------------------------*/
  192. static void nuke(struct fsl_ep *ep, int status)
  193. {
  194. ep->stopped = 1;
  195. /* Flush fifo */
  196. fsl_ep_fifo_flush(&ep->ep);
  197. /* Whether this eq has request linked */
  198. while (!list_empty(&ep->queue)) {
  199. struct fsl_req *req = NULL;
  200. req = list_entry(ep->queue.next, struct fsl_req, queue);
  201. done(ep, req, status);
  202. }
  203. }
  204. /*------------------------------------------------------------------
  205. Internal Hardware related function
  206. ------------------------------------------------------------------*/
  207. static int dr_controller_setup(struct fsl_udc *udc)
  208. {
  209. unsigned int tmp, portctrl, ep_num;
  210. unsigned int max_no_of_ep;
  211. #ifndef CONFIG_ARCH_MXC
  212. unsigned int ctrl;
  213. #endif
  214. unsigned long timeout;
  215. #define FSL_UDC_RESET_TIMEOUT 1000
  216. /* Config PHY interface */
  217. portctrl = fsl_readl(&dr_regs->portsc1);
  218. portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
  219. switch (udc->phy_mode) {
  220. case FSL_USB2_PHY_ULPI:
  221. portctrl |= PORTSCX_PTS_ULPI;
  222. break;
  223. case FSL_USB2_PHY_UTMI_WIDE:
  224. portctrl |= PORTSCX_PTW_16BIT;
  225. /* fall through */
  226. case FSL_USB2_PHY_UTMI:
  227. portctrl |= PORTSCX_PTS_UTMI;
  228. break;
  229. case FSL_USB2_PHY_SERIAL:
  230. portctrl |= PORTSCX_PTS_FSLS;
  231. break;
  232. default:
  233. return -EINVAL;
  234. }
  235. fsl_writel(portctrl, &dr_regs->portsc1);
  236. /* Stop and reset the usb controller */
  237. tmp = fsl_readl(&dr_regs->usbcmd);
  238. tmp &= ~USB_CMD_RUN_STOP;
  239. fsl_writel(tmp, &dr_regs->usbcmd);
  240. tmp = fsl_readl(&dr_regs->usbcmd);
  241. tmp |= USB_CMD_CTRL_RESET;
  242. fsl_writel(tmp, &dr_regs->usbcmd);
  243. /* Wait for reset to complete */
  244. timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
  245. while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
  246. if (time_after(jiffies, timeout)) {
  247. ERR("udc reset timeout!\n");
  248. return -ETIMEDOUT;
  249. }
  250. cpu_relax();
  251. }
  252. /* Set the controller as device mode */
  253. tmp = fsl_readl(&dr_regs->usbmode);
  254. tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */
  255. tmp |= USB_MODE_CTRL_MODE_DEVICE;
  256. /* Disable Setup Lockout */
  257. tmp |= USB_MODE_SETUP_LOCK_OFF;
  258. if (udc->pdata->es)
  259. tmp |= USB_MODE_ES;
  260. fsl_writel(tmp, &dr_regs->usbmode);
  261. /* Clear the setup status */
  262. fsl_writel(0, &dr_regs->usbsts);
  263. tmp = udc->ep_qh_dma;
  264. tmp &= USB_EP_LIST_ADDRESS_MASK;
  265. fsl_writel(tmp, &dr_regs->endpointlistaddr);
  266. VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
  267. udc->ep_qh, (int)tmp,
  268. fsl_readl(&dr_regs->endpointlistaddr));
  269. max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
  270. for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
  271. tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
  272. tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
  273. tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
  274. | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
  275. fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
  276. }
  277. /* Config control enable i/o output, cpu endian register */
  278. #ifndef CONFIG_ARCH_MXC
  279. if (udc->pdata->have_sysif_regs) {
  280. ctrl = __raw_readl(&usb_sys_regs->control);
  281. ctrl |= USB_CTRL_IOENB;
  282. __raw_writel(ctrl, &usb_sys_regs->control);
  283. }
  284. #endif
  285. #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
  286. /* Turn on cache snooping hardware, since some PowerPC platforms
  287. * wholly rely on hardware to deal with cache coherent. */
  288. if (udc->pdata->have_sysif_regs) {
  289. /* Setup Snooping for all the 4GB space */
  290. tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
  291. __raw_writel(tmp, &usb_sys_regs->snoop1);
  292. tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
  293. __raw_writel(tmp, &usb_sys_regs->snoop2);
  294. }
  295. #endif
  296. return 0;
  297. }
  298. /* Enable DR irq and set controller to run state */
  299. static void dr_controller_run(struct fsl_udc *udc)
  300. {
  301. u32 temp;
  302. /* Enable DR irq reg */
  303. temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
  304. | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
  305. | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
  306. fsl_writel(temp, &dr_regs->usbintr);
  307. /* Clear stopped bit */
  308. udc->stopped = 0;
  309. /* Set the controller as device mode */
  310. temp = fsl_readl(&dr_regs->usbmode);
  311. temp |= USB_MODE_CTRL_MODE_DEVICE;
  312. fsl_writel(temp, &dr_regs->usbmode);
  313. /* Set controller to Run */
  314. temp = fsl_readl(&dr_regs->usbcmd);
  315. temp |= USB_CMD_RUN_STOP;
  316. fsl_writel(temp, &dr_regs->usbcmd);
  317. }
  318. static void dr_controller_stop(struct fsl_udc *udc)
  319. {
  320. unsigned int tmp;
  321. pr_debug("%s\n", __func__);
  322. /* if we're in OTG mode, and the Host is currently using the port,
  323. * stop now and don't rip the controller out from under the
  324. * ehci driver
  325. */
  326. if (udc->gadget.is_otg) {
  327. if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
  328. pr_debug("udc: Leaving early\n");
  329. return;
  330. }
  331. }
  332. /* disable all INTR */
  333. fsl_writel(0, &dr_regs->usbintr);
  334. /* Set stopped bit for isr */
  335. udc->stopped = 1;
  336. /* disable IO output */
  337. /* usb_sys_regs->control = 0; */
  338. /* set controller to Stop */
  339. tmp = fsl_readl(&dr_regs->usbcmd);
  340. tmp &= ~USB_CMD_RUN_STOP;
  341. fsl_writel(tmp, &dr_regs->usbcmd);
  342. }
  343. static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
  344. unsigned char ep_type)
  345. {
  346. unsigned int tmp_epctrl = 0;
  347. tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
  348. if (dir) {
  349. if (ep_num)
  350. tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
  351. tmp_epctrl |= EPCTRL_TX_ENABLE;
  352. tmp_epctrl &= ~EPCTRL_TX_TYPE;
  353. tmp_epctrl |= ((unsigned int)(ep_type)
  354. << EPCTRL_TX_EP_TYPE_SHIFT);
  355. } else {
  356. if (ep_num)
  357. tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
  358. tmp_epctrl |= EPCTRL_RX_ENABLE;
  359. tmp_epctrl &= ~EPCTRL_RX_TYPE;
  360. tmp_epctrl |= ((unsigned int)(ep_type)
  361. << EPCTRL_RX_EP_TYPE_SHIFT);
  362. }
  363. fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
  364. }
  365. static void
  366. dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
  367. {
  368. u32 tmp_epctrl = 0;
  369. tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
  370. if (value) {
  371. /* set the stall bit */
  372. if (dir)
  373. tmp_epctrl |= EPCTRL_TX_EP_STALL;
  374. else
  375. tmp_epctrl |= EPCTRL_RX_EP_STALL;
  376. } else {
  377. /* clear the stall bit and reset data toggle */
  378. if (dir) {
  379. tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
  380. tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
  381. } else {
  382. tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
  383. tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
  384. }
  385. }
  386. fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
  387. }
  388. /* Get stall status of a specific ep
  389. Return: 0: not stalled; 1:stalled */
  390. static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
  391. {
  392. u32 epctrl;
  393. epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
  394. if (dir)
  395. return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
  396. else
  397. return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
  398. }
  399. /********************************************************************
  400. Internal Structure Build up functions
  401. ********************************************************************/
  402. /*------------------------------------------------------------------
  403. * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
  404. * @zlt: Zero Length Termination Select (1: disable; 0: enable)
  405. * @mult: Mult field
  406. ------------------------------------------------------------------*/
  407. static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
  408. unsigned char dir, unsigned char ep_type,
  409. unsigned int max_pkt_len,
  410. unsigned int zlt, unsigned char mult)
  411. {
  412. struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
  413. unsigned int tmp = 0;
  414. /* set the Endpoint Capabilites in QH */
  415. switch (ep_type) {
  416. case USB_ENDPOINT_XFER_CONTROL:
  417. /* Interrupt On Setup (IOS). for control ep */
  418. tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
  419. | EP_QUEUE_HEAD_IOS;
  420. break;
  421. case USB_ENDPOINT_XFER_ISOC:
  422. tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
  423. | (mult << EP_QUEUE_HEAD_MULT_POS);
  424. break;
  425. case USB_ENDPOINT_XFER_BULK:
  426. case USB_ENDPOINT_XFER_INT:
  427. tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
  428. break;
  429. default:
  430. VDBG("error ep type is %d", ep_type);
  431. return;
  432. }
  433. if (zlt)
  434. tmp |= EP_QUEUE_HEAD_ZLT_SEL;
  435. p_QH->max_pkt_length = cpu_to_hc32(tmp);
  436. p_QH->next_dtd_ptr = 1;
  437. p_QH->size_ioc_int_sts = 0;
  438. }
  439. /* Setup qh structure and ep register for ep0. */
  440. static void ep0_setup(struct fsl_udc *udc)
  441. {
  442. /* the intialization of an ep includes: fields in QH, Regs,
  443. * fsl_ep struct */
  444. struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
  445. USB_MAX_CTRL_PAYLOAD, 0, 0);
  446. struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
  447. USB_MAX_CTRL_PAYLOAD, 0, 0);
  448. dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
  449. dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
  450. return;
  451. }
  452. /***********************************************************************
  453. Endpoint Management Functions
  454. ***********************************************************************/
  455. /*-------------------------------------------------------------------------
  456. * when configurations are set, or when interface settings change
  457. * for example the do_set_interface() in gadget layer,
  458. * the driver will enable or disable the relevant endpoints
  459. * ep0 doesn't use this routine. It is always enabled.
  460. -------------------------------------------------------------------------*/
  461. static int fsl_ep_enable(struct usb_ep *_ep,
  462. const struct usb_endpoint_descriptor *desc)
  463. {
  464. struct fsl_udc *udc = NULL;
  465. struct fsl_ep *ep = NULL;
  466. unsigned short max = 0;
  467. unsigned char mult = 0, zlt;
  468. int retval = -EINVAL;
  469. unsigned long flags = 0;
  470. ep = container_of(_ep, struct fsl_ep, ep);
  471. /* catch various bogus parameters */
  472. if (!_ep || !desc || ep->ep.desc
  473. || (desc->bDescriptorType != USB_DT_ENDPOINT))
  474. return -EINVAL;
  475. udc = ep->udc;
  476. if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
  477. return -ESHUTDOWN;
  478. max = usb_endpoint_maxp(desc);
  479. /* Disable automatic zlp generation. Driver is responsible to indicate
  480. * explicitly through req->req.zero. This is needed to enable multi-td
  481. * request. */
  482. zlt = 1;
  483. /* Assume the max packet size from gadget is always correct */
  484. switch (desc->bmAttributes & 0x03) {
  485. case USB_ENDPOINT_XFER_CONTROL:
  486. case USB_ENDPOINT_XFER_BULK:
  487. case USB_ENDPOINT_XFER_INT:
  488. /* mult = 0. Execute N Transactions as demonstrated by
  489. * the USB variable length packet protocol where N is
  490. * computed using the Maximum Packet Length (dQH) and
  491. * the Total Bytes field (dTD) */
  492. mult = 0;
  493. break;
  494. case USB_ENDPOINT_XFER_ISOC:
  495. /* Calculate transactions needed for high bandwidth iso */
  496. mult = (unsigned char)(1 + ((max >> 11) & 0x03));
  497. max = max & 0x7ff; /* bit 0~10 */
  498. /* 3 transactions at most */
  499. if (mult > 3)
  500. goto en_done;
  501. break;
  502. default:
  503. goto en_done;
  504. }
  505. spin_lock_irqsave(&udc->lock, flags);
  506. ep->ep.maxpacket = max;
  507. ep->ep.desc = desc;
  508. ep->stopped = 0;
  509. /* Controller related setup */
  510. /* Init EPx Queue Head (Ep Capabilites field in QH
  511. * according to max, zlt, mult) */
  512. struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
  513. (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
  514. ? USB_SEND : USB_RECV),
  515. (unsigned char) (desc->bmAttributes
  516. & USB_ENDPOINT_XFERTYPE_MASK),
  517. max, zlt, mult);
  518. /* Init endpoint ctrl register */
  519. dr_ep_setup((unsigned char) ep_index(ep),
  520. (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
  521. ? USB_SEND : USB_RECV),
  522. (unsigned char) (desc->bmAttributes
  523. & USB_ENDPOINT_XFERTYPE_MASK));
  524. spin_unlock_irqrestore(&udc->lock, flags);
  525. retval = 0;
  526. VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
  527. ep->ep.desc->bEndpointAddress & 0x0f,
  528. (desc->bEndpointAddress & USB_DIR_IN)
  529. ? "in" : "out", max);
  530. en_done:
  531. return retval;
  532. }
  533. /*---------------------------------------------------------------------
  534. * @ep : the ep being unconfigured. May not be ep0
  535. * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
  536. *---------------------------------------------------------------------*/
  537. static int fsl_ep_disable(struct usb_ep *_ep)
  538. {
  539. struct fsl_udc *udc = NULL;
  540. struct fsl_ep *ep = NULL;
  541. unsigned long flags = 0;
  542. u32 epctrl;
  543. int ep_num;
  544. ep = container_of(_ep, struct fsl_ep, ep);
  545. if (!_ep || !ep->ep.desc) {
  546. VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
  547. return -EINVAL;
  548. }
  549. /* disable ep on controller */
  550. ep_num = ep_index(ep);
  551. epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
  552. if (ep_is_in(ep)) {
  553. epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
  554. epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
  555. } else {
  556. epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
  557. epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
  558. }
  559. fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
  560. udc = (struct fsl_udc *)ep->udc;
  561. spin_lock_irqsave(&udc->lock, flags);
  562. /* nuke all pending requests (does flush) */
  563. nuke(ep, -ESHUTDOWN);
  564. ep->ep.desc = NULL;
  565. ep->stopped = 1;
  566. spin_unlock_irqrestore(&udc->lock, flags);
  567. VDBG("disabled %s OK", _ep->name);
  568. return 0;
  569. }
  570. /*---------------------------------------------------------------------
  571. * allocate a request object used by this endpoint
  572. * the main operation is to insert the req->queue to the eq->queue
  573. * Returns the request, or null if one could not be allocated
  574. *---------------------------------------------------------------------*/
  575. static struct usb_request *
  576. fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
  577. {
  578. struct fsl_req *req = NULL;
  579. req = kzalloc(sizeof *req, gfp_flags);
  580. if (!req)
  581. return NULL;
  582. req->req.dma = DMA_ADDR_INVALID;
  583. INIT_LIST_HEAD(&req->queue);
  584. return &req->req;
  585. }
  586. static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
  587. {
  588. struct fsl_req *req = NULL;
  589. req = container_of(_req, struct fsl_req, req);
  590. if (_req)
  591. kfree(req);
  592. }
  593. /* Actually add a dTD chain to an empty dQH and let go */
  594. static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
  595. {
  596. struct ep_queue_head *qh = get_qh_by_ep(ep);
  597. /* Write dQH next pointer and terminate bit to 0 */
  598. qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
  599. & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
  600. /* Clear active and halt bit */
  601. qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
  602. | EP_QUEUE_HEAD_STATUS_HALT));
  603. /* Ensure that updates to the QH will occur before priming. */
  604. wmb();
  605. /* Prime endpoint by writing correct bit to ENDPTPRIME */
  606. fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
  607. : (1 << (ep_index(ep))), &dr_regs->endpointprime);
  608. }
  609. /* Add dTD chain to the dQH of an EP */
  610. static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
  611. {
  612. u32 temp, bitmask, tmp_stat;
  613. /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
  614. VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
  615. bitmask = ep_is_in(ep)
  616. ? (1 << (ep_index(ep) + 16))
  617. : (1 << (ep_index(ep)));
  618. /* check if the pipe is empty */
  619. if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) {
  620. /* Add td to the end */
  621. struct fsl_req *lastreq;
  622. lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
  623. lastreq->tail->next_td_ptr =
  624. cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
  625. /* Ensure dTD's next dtd pointer to be updated */
  626. wmb();
  627. /* Read prime bit, if 1 goto done */
  628. if (fsl_readl(&dr_regs->endpointprime) & bitmask)
  629. return;
  630. do {
  631. /* Set ATDTW bit in USBCMD */
  632. temp = fsl_readl(&dr_regs->usbcmd);
  633. fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
  634. /* Read correct status bit */
  635. tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
  636. } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
  637. /* Write ATDTW bit to 0 */
  638. temp = fsl_readl(&dr_regs->usbcmd);
  639. fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
  640. if (tmp_stat)
  641. return;
  642. }
  643. fsl_prime_ep(ep, req->head);
  644. }
  645. /* Fill in the dTD structure
  646. * @req: request that the transfer belongs to
  647. * @length: return actually data length of the dTD
  648. * @dma: return dma address of the dTD
  649. * @is_last: return flag if it is the last dTD of the request
  650. * return: pointer to the built dTD */
  651. static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
  652. dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
  653. {
  654. u32 swap_temp;
  655. struct ep_td_struct *dtd;
  656. /* how big will this transfer be? */
  657. *length = min(req->req.length - req->req.actual,
  658. (unsigned)EP_MAX_LENGTH_TRANSFER);
  659. dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
  660. if (dtd == NULL)
  661. return dtd;
  662. dtd->td_dma = *dma;
  663. /* Clear reserved field */
  664. swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
  665. swap_temp &= ~DTD_RESERVED_FIELDS;
  666. dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
  667. /* Init all of buffer page pointers */
  668. swap_temp = (u32) (req->req.dma + req->req.actual);
  669. dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
  670. dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
  671. dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
  672. dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
  673. dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
  674. req->req.actual += *length;
  675. /* zlp is needed if req->req.zero is set */
  676. if (req->req.zero) {
  677. if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
  678. *is_last = 1;
  679. else
  680. *is_last = 0;
  681. } else if (req->req.length == req->req.actual)
  682. *is_last = 1;
  683. else
  684. *is_last = 0;
  685. if ((*is_last) == 0)
  686. VDBG("multi-dtd request!");
  687. /* Fill in the transfer size; set active bit */
  688. swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
  689. /* Enable interrupt for the last dtd of a request */
  690. if (*is_last && !req->req.no_interrupt)
  691. swap_temp |= DTD_IOC;
  692. dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
  693. mb();
  694. VDBG("length = %d address= 0x%x", *length, (int)*dma);
  695. return dtd;
  696. }
  697. /* Generate dtd chain for a request */
  698. static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
  699. {
  700. unsigned count;
  701. int is_last;
  702. int is_first =1;
  703. struct ep_td_struct *last_dtd = NULL, *dtd;
  704. dma_addr_t dma;
  705. do {
  706. dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
  707. if (dtd == NULL)
  708. return -ENOMEM;
  709. if (is_first) {
  710. is_first = 0;
  711. req->head = dtd;
  712. } else {
  713. last_dtd->next_td_ptr = cpu_to_hc32(dma);
  714. last_dtd->next_td_virt = dtd;
  715. }
  716. last_dtd = dtd;
  717. req->dtd_count++;
  718. } while (!is_last);
  719. dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
  720. req->tail = dtd;
  721. return 0;
  722. }
  723. /* queues (submits) an I/O request to an endpoint */
  724. static int
  725. fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
  726. {
  727. struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
  728. struct fsl_req *req = container_of(_req, struct fsl_req, req);
  729. struct fsl_udc *udc;
  730. unsigned long flags;
  731. /* catch various bogus parameters */
  732. if (!_req || !req->req.complete || !req->req.buf
  733. || !list_empty(&req->queue)) {
  734. VDBG("%s, bad params", __func__);
  735. return -EINVAL;
  736. }
  737. if (unlikely(!_ep || !ep->ep.desc)) {
  738. VDBG("%s, bad ep", __func__);
  739. return -EINVAL;
  740. }
  741. if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
  742. if (req->req.length > ep->ep.maxpacket)
  743. return -EMSGSIZE;
  744. }
  745. udc = ep->udc;
  746. if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
  747. return -ESHUTDOWN;
  748. req->ep = ep;
  749. /* map virtual address to hardware */
  750. if (req->req.dma == DMA_ADDR_INVALID) {
  751. req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
  752. req->req.buf,
  753. req->req.length, ep_is_in(ep)
  754. ? DMA_TO_DEVICE
  755. : DMA_FROM_DEVICE);
  756. req->mapped = 1;
  757. } else {
  758. dma_sync_single_for_device(ep->udc->gadget.dev.parent,
  759. req->req.dma, req->req.length,
  760. ep_is_in(ep)
  761. ? DMA_TO_DEVICE
  762. : DMA_FROM_DEVICE);
  763. req->mapped = 0;
  764. }
  765. req->req.status = -EINPROGRESS;
  766. req->req.actual = 0;
  767. req->dtd_count = 0;
  768. /* build dtds and push them to device queue */
  769. if (!fsl_req_to_dtd(req, gfp_flags)) {
  770. spin_lock_irqsave(&udc->lock, flags);
  771. fsl_queue_td(ep, req);
  772. } else {
  773. return -ENOMEM;
  774. }
  775. /* irq handler advances the queue */
  776. if (req != NULL)
  777. list_add_tail(&req->queue, &ep->queue);
  778. spin_unlock_irqrestore(&udc->lock, flags);
  779. return 0;
  780. }
  781. /* dequeues (cancels, unlinks) an I/O request from an endpoint */
  782. static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  783. {
  784. struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
  785. struct fsl_req *req;
  786. unsigned long flags;
  787. int ep_num, stopped, ret = 0;
  788. u32 epctrl;
  789. if (!_ep || !_req)
  790. return -EINVAL;
  791. spin_lock_irqsave(&ep->udc->lock, flags);
  792. stopped = ep->stopped;
  793. /* Stop the ep before we deal with the queue */
  794. ep->stopped = 1;
  795. ep_num = ep_index(ep);
  796. epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
  797. if (ep_is_in(ep))
  798. epctrl &= ~EPCTRL_TX_ENABLE;
  799. else
  800. epctrl &= ~EPCTRL_RX_ENABLE;
  801. fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
  802. /* make sure it's actually queued on this endpoint */
  803. list_for_each_entry(req, &ep->queue, queue) {
  804. if (&req->req == _req)
  805. break;
  806. }
  807. if (&req->req != _req) {
  808. ret = -EINVAL;
  809. goto out;
  810. }
  811. /* The request is in progress, or completed but not dequeued */
  812. if (ep->queue.next == &req->queue) {
  813. _req->status = -ECONNRESET;
  814. fsl_ep_fifo_flush(_ep); /* flush current transfer */
  815. /* The request isn't the last request in this ep queue */
  816. if (req->queue.next != &ep->queue) {
  817. struct fsl_req *next_req;
  818. next_req = list_entry(req->queue.next, struct fsl_req,
  819. queue);
  820. /* prime with dTD of next request */
  821. fsl_prime_ep(ep, next_req->head);
  822. }
  823. /* The request hasn't been processed, patch up the TD chain */
  824. } else {
  825. struct fsl_req *prev_req;
  826. prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
  827. prev_req->tail->next_td_ptr = req->tail->next_td_ptr;
  828. }
  829. done(ep, req, -ECONNRESET);
  830. /* Enable EP */
  831. out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
  832. if (ep_is_in(ep))
  833. epctrl |= EPCTRL_TX_ENABLE;
  834. else
  835. epctrl |= EPCTRL_RX_ENABLE;
  836. fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
  837. ep->stopped = stopped;
  838. spin_unlock_irqrestore(&ep->udc->lock, flags);
  839. return ret;
  840. }
  841. /*-------------------------------------------------------------------------*/
  842. /*-----------------------------------------------------------------
  843. * modify the endpoint halt feature
  844. * @ep: the non-isochronous endpoint being stalled
  845. * @value: 1--set halt 0--clear halt
  846. * Returns zero, or a negative error code.
  847. *----------------------------------------------------------------*/
  848. static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
  849. {
  850. struct fsl_ep *ep = NULL;
  851. unsigned long flags = 0;
  852. int status = -EOPNOTSUPP; /* operation not supported */
  853. unsigned char ep_dir = 0, ep_num = 0;
  854. struct fsl_udc *udc = NULL;
  855. ep = container_of(_ep, struct fsl_ep, ep);
  856. udc = ep->udc;
  857. if (!_ep || !ep->ep.desc) {
  858. status = -EINVAL;
  859. goto out;
  860. }
  861. if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
  862. status = -EOPNOTSUPP;
  863. goto out;
  864. }
  865. /* Attempt to halt IN ep will fail if any transfer requests
  866. * are still queue */
  867. if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
  868. status = -EAGAIN;
  869. goto out;
  870. }
  871. status = 0;
  872. ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
  873. ep_num = (unsigned char)(ep_index(ep));
  874. spin_lock_irqsave(&ep->udc->lock, flags);
  875. dr_ep_change_stall(ep_num, ep_dir, value);
  876. spin_unlock_irqrestore(&ep->udc->lock, flags);
  877. if (ep_index(ep) == 0) {
  878. udc->ep0_state = WAIT_FOR_SETUP;
  879. udc->ep0_dir = 0;
  880. }
  881. out:
  882. VDBG(" %s %s halt stat %d", ep->ep.name,
  883. value ? "set" : "clear", status);
  884. return status;
  885. }
  886. static int fsl_ep_fifo_status(struct usb_ep *_ep)
  887. {
  888. struct fsl_ep *ep;
  889. struct fsl_udc *udc;
  890. int size = 0;
  891. u32 bitmask;
  892. struct ep_queue_head *qh;
  893. ep = container_of(_ep, struct fsl_ep, ep);
  894. if (!_ep || (!ep->ep.desc && ep_index(ep) != 0))
  895. return -ENODEV;
  896. udc = (struct fsl_udc *)ep->udc;
  897. if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
  898. return -ESHUTDOWN;
  899. qh = get_qh_by_ep(ep);
  900. bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
  901. (1 << (ep_index(ep)));
  902. if (fsl_readl(&dr_regs->endptstatus) & bitmask)
  903. size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE)
  904. >> DTD_LENGTH_BIT_POS;
  905. pr_debug("%s %u\n", __func__, size);
  906. return size;
  907. }
  908. static void fsl_ep_fifo_flush(struct usb_ep *_ep)
  909. {
  910. struct fsl_ep *ep;
  911. int ep_num, ep_dir;
  912. u32 bits;
  913. unsigned long timeout;
  914. #define FSL_UDC_FLUSH_TIMEOUT 1000
  915. if (!_ep) {
  916. return;
  917. } else {
  918. ep = container_of(_ep, struct fsl_ep, ep);
  919. if (!ep->ep.desc)
  920. return;
  921. }
  922. ep_num = ep_index(ep);
  923. ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
  924. if (ep_num == 0)
  925. bits = (1 << 16) | 1;
  926. else if (ep_dir == USB_SEND)
  927. bits = 1 << (16 + ep_num);
  928. else
  929. bits = 1 << ep_num;
  930. timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
  931. do {
  932. fsl_writel(bits, &dr_regs->endptflush);
  933. /* Wait until flush complete */
  934. while (fsl_readl(&dr_regs->endptflush)) {
  935. if (time_after(jiffies, timeout)) {
  936. ERR("ep flush timeout\n");
  937. return;
  938. }
  939. cpu_relax();
  940. }
  941. /* See if we need to flush again */
  942. } while (fsl_readl(&dr_regs->endptstatus) & bits);
  943. }
  944. static struct usb_ep_ops fsl_ep_ops = {
  945. .enable = fsl_ep_enable,
  946. .disable = fsl_ep_disable,
  947. .alloc_request = fsl_alloc_request,
  948. .free_request = fsl_free_request,
  949. .queue = fsl_ep_queue,
  950. .dequeue = fsl_ep_dequeue,
  951. .set_halt = fsl_ep_set_halt,
  952. .fifo_status = fsl_ep_fifo_status,
  953. .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */
  954. };
  955. /*-------------------------------------------------------------------------
  956. Gadget Driver Layer Operations
  957. -------------------------------------------------------------------------*/
  958. /*----------------------------------------------------------------------
  959. * Get the current frame number (from DR frame_index Reg )
  960. *----------------------------------------------------------------------*/
  961. static int fsl_get_frame(struct usb_gadget *gadget)
  962. {
  963. return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
  964. }
  965. /*-----------------------------------------------------------------------
  966. * Tries to wake up the host connected to this gadget
  967. -----------------------------------------------------------------------*/
  968. static int fsl_wakeup(struct usb_gadget *gadget)
  969. {
  970. struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
  971. u32 portsc;
  972. /* Remote wakeup feature not enabled by host */
  973. if (!udc->remote_wakeup)
  974. return -ENOTSUPP;
  975. portsc = fsl_readl(&dr_regs->portsc1);
  976. /* not suspended? */
  977. if (!(portsc & PORTSCX_PORT_SUSPEND))
  978. return 0;
  979. /* trigger force resume */
  980. portsc |= PORTSCX_PORT_FORCE_RESUME;
  981. fsl_writel(portsc, &dr_regs->portsc1);
  982. return 0;
  983. }
  984. static int can_pullup(struct fsl_udc *udc)
  985. {
  986. return udc->driver && udc->softconnect && udc->vbus_active;
  987. }
  988. /* Notify controller that VBUS is powered, Called by whatever
  989. detects VBUS sessions */
  990. static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
  991. {
  992. struct fsl_udc *udc;
  993. unsigned long flags;
  994. udc = container_of(gadget, struct fsl_udc, gadget);
  995. spin_lock_irqsave(&udc->lock, flags);
  996. VDBG("VBUS %s", is_active ? "on" : "off");
  997. udc->vbus_active = (is_active != 0);
  998. if (can_pullup(udc))
  999. fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
  1000. &dr_regs->usbcmd);
  1001. else
  1002. fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
  1003. &dr_regs->usbcmd);
  1004. spin_unlock_irqrestore(&udc->lock, flags);
  1005. return 0;
  1006. }
  1007. /* constrain controller's VBUS power usage
  1008. * This call is used by gadget drivers during SET_CONFIGURATION calls,
  1009. * reporting how much power the device may consume. For example, this
  1010. * could affect how quickly batteries are recharged.
  1011. *
  1012. * Returns zero on success, else negative errno.
  1013. */
  1014. static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
  1015. {
  1016. struct fsl_udc *udc;
  1017. udc = container_of(gadget, struct fsl_udc, gadget);
  1018. if (udc->transceiver)
  1019. return usb_phy_set_power(udc->transceiver, mA);
  1020. return -ENOTSUPP;
  1021. }
  1022. /* Change Data+ pullup status
  1023. * this func is used by usb_gadget_connect/disconnet
  1024. */
  1025. static int fsl_pullup(struct usb_gadget *gadget, int is_on)
  1026. {
  1027. struct fsl_udc *udc;
  1028. udc = container_of(gadget, struct fsl_udc, gadget);
  1029. udc->softconnect = (is_on != 0);
  1030. if (can_pullup(udc))
  1031. fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
  1032. &dr_regs->usbcmd);
  1033. else
  1034. fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
  1035. &dr_regs->usbcmd);
  1036. return 0;
  1037. }
  1038. static int fsl_start(struct usb_gadget_driver *driver,
  1039. int (*bind)(struct usb_gadget *));
  1040. static int fsl_stop(struct usb_gadget_driver *driver);
  1041. /* defined in gadget.h */
  1042. static struct usb_gadget_ops fsl_gadget_ops = {
  1043. .get_frame = fsl_get_frame,
  1044. .wakeup = fsl_wakeup,
  1045. /* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
  1046. .vbus_session = fsl_vbus_session,
  1047. .vbus_draw = fsl_vbus_draw,
  1048. .pullup = fsl_pullup,
  1049. .start = fsl_start,
  1050. .stop = fsl_stop,
  1051. };
  1052. /* Set protocol stall on ep0, protocol stall will automatically be cleared
  1053. on new transaction */
  1054. static void ep0stall(struct fsl_udc *udc)
  1055. {
  1056. u32 tmp;
  1057. /* must set tx and rx to stall at the same time */
  1058. tmp = fsl_readl(&dr_regs->endptctrl[0]);
  1059. tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
  1060. fsl_writel(tmp, &dr_regs->endptctrl[0]);
  1061. udc->ep0_state = WAIT_FOR_SETUP;
  1062. udc->ep0_dir = 0;
  1063. }
  1064. /* Prime a status phase for ep0 */
  1065. static int ep0_prime_status(struct fsl_udc *udc, int direction)
  1066. {
  1067. struct fsl_req *req = udc->status_req;
  1068. struct fsl_ep *ep;
  1069. if (direction == EP_DIR_IN)
  1070. udc->ep0_dir = USB_DIR_IN;
  1071. else
  1072. udc->ep0_dir = USB_DIR_OUT;
  1073. ep = &udc->eps[0];
  1074. if (udc->ep0_state != DATA_STATE_XMIT)
  1075. udc->ep0_state = WAIT_FOR_OUT_STATUS;
  1076. req->ep = ep;
  1077. req->req.length = 0;
  1078. req->req.status = -EINPROGRESS;
  1079. req->req.actual = 0;
  1080. req->req.complete = NULL;
  1081. req->dtd_count = 0;
  1082. req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
  1083. req->req.buf, req->req.length,
  1084. ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  1085. req->mapped = 1;
  1086. if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
  1087. fsl_queue_td(ep, req);
  1088. else
  1089. return -ENOMEM;
  1090. list_add_tail(&req->queue, &ep->queue);
  1091. return 0;
  1092. }
  1093. static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
  1094. {
  1095. struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
  1096. if (ep->name)
  1097. nuke(ep, -ESHUTDOWN);
  1098. }
  1099. /*
  1100. * ch9 Set address
  1101. */
  1102. static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
  1103. {
  1104. /* Save the new address to device struct */
  1105. udc->device_address = (u8) value;
  1106. /* Update usb state */
  1107. udc->usb_state = USB_STATE_ADDRESS;
  1108. /* Status phase */
  1109. if (ep0_prime_status(udc, EP_DIR_IN))
  1110. ep0stall(udc);
  1111. }
  1112. /*
  1113. * ch9 Get status
  1114. */
  1115. static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
  1116. u16 index, u16 length)
  1117. {
  1118. u16 tmp = 0; /* Status, cpu endian */
  1119. struct fsl_req *req;
  1120. struct fsl_ep *ep;
  1121. ep = &udc->eps[0];
  1122. if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  1123. /* Get device status */
  1124. tmp = 1 << USB_DEVICE_SELF_POWERED;
  1125. tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
  1126. } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
  1127. /* Get interface status */
  1128. /* We don't have interface information in udc driver */
  1129. tmp = 0;
  1130. } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
  1131. /* Get endpoint status */
  1132. struct fsl_ep *target_ep;
  1133. target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
  1134. /* stall if endpoint doesn't exist */
  1135. if (!target_ep->ep.desc)
  1136. goto stall;
  1137. tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
  1138. << USB_ENDPOINT_HALT;
  1139. }
  1140. udc->ep0_dir = USB_DIR_IN;
  1141. /* Borrow the per device status_req */
  1142. req = udc->status_req;
  1143. /* Fill in the reqest structure */
  1144. *((u16 *) req->req.buf) = cpu_to_le16(tmp);
  1145. req->ep = ep;
  1146. req->req.length = 2;
  1147. req->req.status = -EINPROGRESS;
  1148. req->req.actual = 0;
  1149. req->req.complete = NULL;
  1150. req->dtd_count = 0;
  1151. req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
  1152. req->req.buf, req->req.length,
  1153. ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  1154. req->mapped = 1;
  1155. /* prime the data phase */
  1156. if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
  1157. fsl_queue_td(ep, req);
  1158. else /* no mem */
  1159. goto stall;
  1160. list_add_tail(&req->queue, &ep->queue);
  1161. udc->ep0_state = DATA_STATE_XMIT;
  1162. if (ep0_prime_status(udc, EP_DIR_OUT))
  1163. ep0stall(udc);
  1164. return;
  1165. stall:
  1166. ep0stall(udc);
  1167. }
  1168. static void setup_received_irq(struct fsl_udc *udc,
  1169. struct usb_ctrlrequest *setup)
  1170. {
  1171. u16 wValue = le16_to_cpu(setup->wValue);
  1172. u16 wIndex = le16_to_cpu(setup->wIndex);
  1173. u16 wLength = le16_to_cpu(setup->wLength);
  1174. udc_reset_ep_queue(udc, 0);
  1175. /* We process some stardard setup requests here */
  1176. switch (setup->bRequest) {
  1177. case USB_REQ_GET_STATUS:
  1178. /* Data+Status phase from udc */
  1179. if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
  1180. != (USB_DIR_IN | USB_TYPE_STANDARD))
  1181. break;
  1182. ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
  1183. return;
  1184. case USB_REQ_SET_ADDRESS:
  1185. /* Status phase from udc */
  1186. if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
  1187. | USB_RECIP_DEVICE))
  1188. break;
  1189. ch9setaddress(udc, wValue, wIndex, wLength);
  1190. return;
  1191. case USB_REQ_CLEAR_FEATURE:
  1192. case USB_REQ_SET_FEATURE:
  1193. /* Status phase from udc */
  1194. {
  1195. int rc = -EOPNOTSUPP;
  1196. u16 ptc = 0;
  1197. if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
  1198. == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
  1199. int pipe = get_pipe_by_windex(wIndex);
  1200. struct fsl_ep *ep;
  1201. if (wValue != 0 || wLength != 0 || pipe >= udc->max_ep)
  1202. break;
  1203. ep = get_ep_by_pipe(udc, pipe);
  1204. spin_unlock(&udc->lock);
  1205. rc = fsl_ep_set_halt(&ep->ep,
  1206. (setup->bRequest == USB_REQ_SET_FEATURE)
  1207. ? 1 : 0);
  1208. spin_lock(&udc->lock);
  1209. } else if ((setup->bRequestType & (USB_RECIP_MASK
  1210. | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
  1211. | USB_TYPE_STANDARD)) {
  1212. /* Note: The driver has not include OTG support yet.
  1213. * This will be set when OTG support is added */
  1214. if (wValue == USB_DEVICE_TEST_MODE)
  1215. ptc = wIndex >> 8;
  1216. else if (gadget_is_otg(&udc->gadget)) {
  1217. if (setup->bRequest ==
  1218. USB_DEVICE_B_HNP_ENABLE)
  1219. udc->gadget.b_hnp_enable = 1;
  1220. else if (setup->bRequest ==
  1221. USB_DEVICE_A_HNP_SUPPORT)
  1222. udc->gadget.a_hnp_support = 1;
  1223. else if (setup->bRequest ==
  1224. USB_DEVICE_A_ALT_HNP_SUPPORT)
  1225. udc->gadget.a_alt_hnp_support = 1;
  1226. }
  1227. rc = 0;
  1228. } else
  1229. break;
  1230. if (rc == 0) {
  1231. if (ep0_prime_status(udc, EP_DIR_IN))
  1232. ep0stall(udc);
  1233. }
  1234. if (ptc) {
  1235. u32 tmp;
  1236. mdelay(10);
  1237. tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
  1238. fsl_writel(tmp, &dr_regs->portsc1);
  1239. printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
  1240. }
  1241. return;
  1242. }
  1243. default:
  1244. break;
  1245. }
  1246. /* Requests handled by gadget */
  1247. if (wLength) {
  1248. /* Data phase from gadget, status phase from udc */
  1249. udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
  1250. ? USB_DIR_IN : USB_DIR_OUT;
  1251. spin_unlock(&udc->lock);
  1252. if (udc->driver->setup(&udc->gadget,
  1253. &udc->local_setup_buff) < 0)
  1254. ep0stall(udc);
  1255. spin_lock(&udc->lock);
  1256. udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
  1257. ? DATA_STATE_XMIT : DATA_STATE_RECV;
  1258. /*
  1259. * If the data stage is IN, send status prime immediately.
  1260. * See 2.0 Spec chapter 8.5.3.3 for detail.
  1261. */
  1262. if (udc->ep0_state == DATA_STATE_XMIT)
  1263. if (ep0_prime_status(udc, EP_DIR_OUT))
  1264. ep0stall(udc);
  1265. } else {
  1266. /* No data phase, IN status from gadget */
  1267. udc->ep0_dir = USB_DIR_IN;
  1268. spin_unlock(&udc->lock);
  1269. if (udc->driver->setup(&udc->gadget,
  1270. &udc->local_setup_buff) < 0)
  1271. ep0stall(udc);
  1272. spin_lock(&udc->lock);
  1273. udc->ep0_state = WAIT_FOR_OUT_STATUS;
  1274. }
  1275. }
  1276. /* Process request for Data or Status phase of ep0
  1277. * prime status phase if needed */
  1278. static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
  1279. struct fsl_req *req)
  1280. {
  1281. if (udc->usb_state == USB_STATE_ADDRESS) {
  1282. /* Set the new address */
  1283. u32 new_address = (u32) udc->device_address;
  1284. fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
  1285. &dr_regs->deviceaddr);
  1286. }
  1287. done(ep0, req, 0);
  1288. switch (udc->ep0_state) {
  1289. case DATA_STATE_XMIT:
  1290. /* already primed at setup_received_irq */
  1291. udc->ep0_state = WAIT_FOR_OUT_STATUS;
  1292. break;
  1293. case DATA_STATE_RECV:
  1294. /* send status phase */
  1295. if (ep0_prime_status(udc, EP_DIR_IN))
  1296. ep0stall(udc);
  1297. break;
  1298. case WAIT_FOR_OUT_STATUS:
  1299. udc->ep0_state = WAIT_FOR_SETUP;
  1300. break;
  1301. case WAIT_FOR_SETUP:
  1302. ERR("Unexpect ep0 packets\n");
  1303. break;
  1304. default:
  1305. ep0stall(udc);
  1306. break;
  1307. }
  1308. }
  1309. /* Tripwire mechanism to ensure a setup packet payload is extracted without
  1310. * being corrupted by another incoming setup packet */
  1311. static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
  1312. {
  1313. u32 temp;
  1314. struct ep_queue_head *qh;
  1315. struct fsl_usb2_platform_data *pdata = udc->pdata;
  1316. qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
  1317. /* Clear bit in ENDPTSETUPSTAT */
  1318. temp = fsl_readl(&dr_regs->endptsetupstat);
  1319. fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
  1320. /* while a hazard exists when setup package arrives */
  1321. do {
  1322. /* Set Setup Tripwire */
  1323. temp = fsl_readl(&dr_regs->usbcmd);
  1324. fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
  1325. /* Copy the setup packet to local buffer */
  1326. if (pdata->le_setup_buf) {
  1327. u32 *p = (u32 *)buffer_ptr;
  1328. u32 *s = (u32 *)qh->setup_buffer;
  1329. /* Convert little endian setup buffer to CPU endian */
  1330. *p++ = le32_to_cpu(*s++);
  1331. *p = le32_to_cpu(*s);
  1332. } else {
  1333. memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
  1334. }
  1335. } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
  1336. /* Clear Setup Tripwire */
  1337. temp = fsl_readl(&dr_regs->usbcmd);
  1338. fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
  1339. }
  1340. /* process-ep_req(): free the completed Tds for this req */
  1341. static int process_ep_req(struct fsl_udc *udc, int pipe,
  1342. struct fsl_req *curr_req)
  1343. {
  1344. struct ep_td_struct *curr_td;
  1345. int td_complete, actual, remaining_length, j, tmp;
  1346. int status = 0;
  1347. int errors = 0;
  1348. struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
  1349. int direction = pipe % 2;
  1350. curr_td = curr_req->head;
  1351. td_complete = 0;
  1352. actual = curr_req->req.length;
  1353. for (j = 0; j < curr_req->dtd_count; j++) {
  1354. remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
  1355. & DTD_PACKET_SIZE)
  1356. >> DTD_LENGTH_BIT_POS;
  1357. actual -= remaining_length;
  1358. errors = hc32_to_cpu(curr_td->size_ioc_sts);
  1359. if (errors & DTD_ERROR_MASK) {
  1360. if (errors & DTD_STATUS_HALTED) {
  1361. ERR("dTD error %08x QH=%d\n", errors, pipe);
  1362. /* Clear the errors and Halt condition */
  1363. tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
  1364. tmp &= ~errors;
  1365. curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
  1366. status = -EPIPE;
  1367. /* FIXME: continue with next queued TD? */
  1368. break;
  1369. }
  1370. if (errors & DTD_STATUS_DATA_BUFF_ERR) {
  1371. VDBG("Transfer overflow");
  1372. status = -EPROTO;
  1373. break;
  1374. } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
  1375. VDBG("ISO error");
  1376. status = -EILSEQ;
  1377. break;
  1378. } else
  1379. ERR("Unknown error has occurred (0x%x)!\n",
  1380. errors);
  1381. } else if (hc32_to_cpu(curr_td->size_ioc_sts)
  1382. & DTD_STATUS_ACTIVE) {
  1383. VDBG("Request not complete");
  1384. status = REQ_UNCOMPLETE;
  1385. return status;
  1386. } else if (remaining_length) {
  1387. if (direction) {
  1388. VDBG("Transmit dTD remaining length not zero");
  1389. status = -EPROTO;
  1390. break;
  1391. } else {
  1392. td_complete++;
  1393. break;
  1394. }
  1395. } else {
  1396. td_complete++;
  1397. VDBG("dTD transmitted successful");
  1398. }
  1399. if (j != curr_req->dtd_count - 1)
  1400. curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
  1401. }
  1402. if (status)
  1403. return status;
  1404. curr_req->req.actual = actual;
  1405. return 0;
  1406. }
  1407. /* Process a DTD completion interrupt */
  1408. static void dtd_complete_irq(struct fsl_udc *udc)
  1409. {
  1410. u32 bit_pos;
  1411. int i, ep_num, direction, bit_mask, status;
  1412. struct fsl_ep *curr_ep;
  1413. struct fsl_req *curr_req, *temp_req;
  1414. /* Clear the bits in the register */
  1415. bit_pos = fsl_readl(&dr_regs->endptcomplete);
  1416. fsl_writel(bit_pos, &dr_regs->endptcomplete);
  1417. if (!bit_pos)
  1418. return;
  1419. for (i = 0; i < udc->max_ep; i++) {
  1420. ep_num = i >> 1;
  1421. direction = i % 2;
  1422. bit_mask = 1 << (ep_num + 16 * direction);
  1423. if (!(bit_pos & bit_mask))
  1424. continue;
  1425. curr_ep = get_ep_by_pipe(udc, i);
  1426. /* If the ep is configured */
  1427. if (curr_ep->name == NULL) {
  1428. WARNING("Invalid EP?");
  1429. continue;
  1430. }
  1431. /* process the req queue until an uncomplete request */
  1432. list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
  1433. queue) {
  1434. status = process_ep_req(udc, i, curr_req);
  1435. VDBG("status of process_ep_req= %d, ep = %d",
  1436. status, ep_num);
  1437. if (status == REQ_UNCOMPLETE)
  1438. break;
  1439. /* write back status to req */
  1440. curr_req->req.status = status;
  1441. if (ep_num == 0) {
  1442. ep0_req_complete(udc, curr_ep, curr_req);
  1443. break;
  1444. } else
  1445. done(curr_ep, curr_req, status);
  1446. }
  1447. }
  1448. }
  1449. static inline enum usb_device_speed portscx_device_speed(u32 reg)
  1450. {
  1451. switch (reg & PORTSCX_PORT_SPEED_MASK) {
  1452. case PORTSCX_PORT_SPEED_HIGH:
  1453. return USB_SPEED_HIGH;
  1454. case PORTSCX_PORT_SPEED_FULL:
  1455. return USB_SPEED_FULL;
  1456. case PORTSCX_PORT_SPEED_LOW:
  1457. return USB_SPEED_LOW;
  1458. default:
  1459. return USB_SPEED_UNKNOWN;
  1460. }
  1461. }
  1462. /* Process a port change interrupt */
  1463. static void port_change_irq(struct fsl_udc *udc)
  1464. {
  1465. if (udc->bus_reset)
  1466. udc->bus_reset = 0;
  1467. /* Bus resetting is finished */
  1468. if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
  1469. /* Get the speed */
  1470. udc->gadget.speed =
  1471. portscx_device_speed(fsl_readl(&dr_regs->portsc1));
  1472. /* Update USB state */
  1473. if (!udc->resume_state)
  1474. udc->usb_state = USB_STATE_DEFAULT;
  1475. }
  1476. /* Process suspend interrupt */
  1477. static void suspend_irq(struct fsl_udc *udc)
  1478. {
  1479. udc->resume_state = udc->usb_state;
  1480. udc->usb_state = USB_STATE_SUSPENDED;
  1481. /* report suspend to the driver, serial.c does not support this */
  1482. if (udc->driver->suspend)
  1483. udc->driver->suspend(&udc->gadget);
  1484. }
  1485. static void bus_resume(struct fsl_udc *udc)
  1486. {
  1487. udc->usb_state = udc->resume_state;
  1488. udc->resume_state = 0;
  1489. /* report resume to the driver, serial.c does not support this */
  1490. if (udc->driver->resume)
  1491. udc->driver->resume(&udc->gadget);
  1492. }
  1493. /* Clear up all ep queues */
  1494. static int reset_queues(struct fsl_udc *udc)
  1495. {
  1496. u8 pipe;
  1497. for (pipe = 0; pipe < udc->max_pipes; pipe++)
  1498. udc_reset_ep_queue(udc, pipe);
  1499. /* report disconnect; the driver is already quiesced */
  1500. spin_unlock(&udc->lock);
  1501. udc->driver->disconnect(&udc->gadget);
  1502. spin_lock(&udc->lock);
  1503. return 0;
  1504. }
  1505. /* Process reset interrupt */
  1506. static void reset_irq(struct fsl_udc *udc)
  1507. {
  1508. u32 temp;
  1509. unsigned long timeout;
  1510. /* Clear the device address */
  1511. temp = fsl_readl(&dr_regs->deviceaddr);
  1512. fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
  1513. udc->device_address = 0;
  1514. /* Clear usb state */
  1515. udc->resume_state = 0;
  1516. udc->ep0_dir = 0;
  1517. udc->ep0_state = WAIT_FOR_SETUP;
  1518. udc->remote_wakeup = 0; /* default to 0 on reset */
  1519. udc->gadget.b_hnp_enable = 0;
  1520. udc->gadget.a_hnp_support = 0;
  1521. udc->gadget.a_alt_hnp_support = 0;
  1522. /* Clear all the setup token semaphores */
  1523. temp = fsl_readl(&dr_regs->endptsetupstat);
  1524. fsl_writel(temp, &dr_regs->endptsetupstat);
  1525. /* Clear all the endpoint complete status bits */
  1526. temp = fsl_readl(&dr_regs->endptcomplete);
  1527. fsl_writel(temp, &dr_regs->endptcomplete);
  1528. timeout = jiffies + 100;
  1529. while (fsl_readl(&dr_regs->endpointprime)) {
  1530. /* Wait until all endptprime bits cleared */
  1531. if (time_after(jiffies, timeout)) {
  1532. ERR("Timeout for reset\n");
  1533. break;
  1534. }
  1535. cpu_relax();
  1536. }
  1537. /* Write 1s to the flush register */
  1538. fsl_writel(0xffffffff, &dr_regs->endptflush);
  1539. if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
  1540. VDBG("Bus reset");
  1541. /* Bus is reseting */
  1542. udc->bus_reset = 1;
  1543. /* Reset all the queues, include XD, dTD, EP queue
  1544. * head and TR Queue */
  1545. reset_queues(udc);
  1546. udc->usb_state = USB_STATE_DEFAULT;
  1547. } else {
  1548. VDBG("Controller reset");
  1549. /* initialize usb hw reg except for regs for EP, not
  1550. * touch usbintr reg */
  1551. dr_controller_setup(udc);
  1552. /* Reset all internal used Queues */
  1553. reset_queues(udc);
  1554. ep0_setup(udc);
  1555. /* Enable DR IRQ reg, Set Run bit, change udc state */
  1556. dr_controller_run(udc);
  1557. udc->usb_state = USB_STATE_ATTACHED;
  1558. }
  1559. }
  1560. /*
  1561. * USB device controller interrupt handler
  1562. */
  1563. static irqreturn_t fsl_udc_irq(int irq, void *_udc)
  1564. {
  1565. struct fsl_udc *udc = _udc;
  1566. u32 irq_src;
  1567. irqreturn_t status = IRQ_NONE;
  1568. unsigned long flags;
  1569. /* Disable ISR for OTG host mode */
  1570. if (udc->stopped)
  1571. return IRQ_NONE;
  1572. spin_lock_irqsave(&udc->lock, flags);
  1573. irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
  1574. /* Clear notification bits */
  1575. fsl_writel(irq_src, &dr_regs->usbsts);
  1576. /* VDBG("irq_src [0x%8x]", irq_src); */
  1577. /* Need to resume? */
  1578. if (udc->usb_state == USB_STATE_SUSPENDED)
  1579. if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
  1580. bus_resume(udc);
  1581. /* USB Interrupt */
  1582. if (irq_src & USB_STS_INT) {
  1583. VDBG("Packet int");
  1584. /* Setup package, we only support ep0 as control ep */
  1585. if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
  1586. tripwire_handler(udc, 0,
  1587. (u8 *) (&udc->local_setup_buff));
  1588. setup_received_irq(udc, &udc->local_setup_buff);
  1589. status = IRQ_HANDLED;
  1590. }
  1591. /* completion of dtd */
  1592. if (fsl_readl(&dr_regs->endptcomplete)) {
  1593. dtd_complete_irq(udc);
  1594. status = IRQ_HANDLED;
  1595. }
  1596. }
  1597. /* SOF (for ISO transfer) */
  1598. if (irq_src & USB_STS_SOF) {
  1599. status = IRQ_HANDLED;
  1600. }
  1601. /* Port Change */
  1602. if (irq_src & USB_STS_PORT_CHANGE) {
  1603. port_change_irq(udc);
  1604. status = IRQ_HANDLED;
  1605. }
  1606. /* Reset Received */
  1607. if (irq_src & USB_STS_RESET) {
  1608. VDBG("reset int");
  1609. reset_irq(udc);
  1610. status = IRQ_HANDLED;
  1611. }
  1612. /* Sleep Enable (Suspend) */
  1613. if (irq_src & USB_STS_SUSPEND) {
  1614. suspend_irq(udc);
  1615. status = IRQ_HANDLED;
  1616. }
  1617. if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
  1618. VDBG("Error IRQ %x", irq_src);
  1619. }
  1620. spin_unlock_irqrestore(&udc->lock, flags);
  1621. return status;
  1622. }
  1623. /*----------------------------------------------------------------*
  1624. * Hook to gadget drivers
  1625. * Called by initialization code of gadget drivers
  1626. *----------------------------------------------------------------*/
  1627. static int fsl_start(struct usb_gadget_driver *driver,
  1628. int (*bind)(struct usb_gadget *))
  1629. {
  1630. int retval = -ENODEV;
  1631. unsigned long flags = 0;
  1632. if (!udc_controller)
  1633. return -ENODEV;
  1634. if (!driver || driver->max_speed < USB_SPEED_FULL
  1635. || !bind || !driver->disconnect || !driver->setup)
  1636. return -EINVAL;
  1637. if (udc_controller->driver)
  1638. return -EBUSY;
  1639. /* lock is needed but whether should use this lock or another */
  1640. spin_lock_irqsave(&udc_controller->lock, flags);
  1641. driver->driver.bus = NULL;
  1642. /* hook up the driver */
  1643. udc_controller->driver = driver;
  1644. udc_controller->gadget.dev.driver = &driver->driver;
  1645. spin_unlock_irqrestore(&udc_controller->lock, flags);
  1646. /* bind udc driver to gadget driver */
  1647. retval = bind(&udc_controller->gadget);
  1648. if (retval) {
  1649. VDBG("bind to %s --> %d", driver->driver.name, retval);
  1650. udc_controller->gadget.dev.driver = NULL;
  1651. udc_controller->driver = NULL;
  1652. goto out;
  1653. }
  1654. if (udc_controller->transceiver) {
  1655. /* Suspend the controller until OTG enable it */
  1656. udc_controller->stopped = 1;
  1657. printk(KERN_INFO "Suspend udc for OTG auto detect\n");
  1658. /* connect to bus through transceiver */
  1659. if (udc_controller->transceiver) {
  1660. retval = otg_set_peripheral(
  1661. udc_controller->transceiver->otg,
  1662. &udc_controller->gadget);
  1663. if (retval < 0) {
  1664. ERR("can't bind to transceiver\n");
  1665. driver->unbind(&udc_controller->gadget);
  1666. udc_controller->gadget.dev.driver = 0;
  1667. udc_controller->driver = 0;
  1668. return retval;
  1669. }
  1670. }
  1671. } else {
  1672. /* Enable DR IRQ reg and set USBCMD reg Run bit */
  1673. dr_controller_run(udc_controller);
  1674. udc_controller->usb_state = USB_STATE_ATTACHED;
  1675. udc_controller->ep0_state = WAIT_FOR_SETUP;
  1676. udc_controller->ep0_dir = 0;
  1677. }
  1678. printk(KERN_INFO "%s: bind to driver %s\n",
  1679. udc_controller->gadget.name, driver->driver.name);
  1680. out:
  1681. if (retval)
  1682. printk(KERN_WARNING "gadget driver register failed %d\n",
  1683. retval);
  1684. return retval;
  1685. }
  1686. /* Disconnect from gadget driver */
  1687. static int fsl_stop(struct usb_gadget_driver *driver)
  1688. {
  1689. struct fsl_ep *loop_ep;
  1690. unsigned long flags;
  1691. if (!udc_controller)
  1692. return -ENODEV;
  1693. if (!driver || driver != udc_controller->driver || !driver->unbind)
  1694. return -EINVAL;
  1695. if (udc_controller->transceiver)
  1696. otg_set_peripheral(udc_controller->transceiver->otg, NULL);
  1697. /* stop DR, disable intr */
  1698. dr_controller_stop(udc_controller);
  1699. /* in fact, no needed */
  1700. udc_controller->usb_state = USB_STATE_ATTACHED;
  1701. udc_controller->ep0_state = WAIT_FOR_SETUP;
  1702. udc_controller->ep0_dir = 0;
  1703. /* stand operation */
  1704. spin_lock_irqsave(&udc_controller->lock, flags);
  1705. udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
  1706. nuke(&udc_controller->eps[0], -ESHUTDOWN);
  1707. list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
  1708. ep.ep_list)
  1709. nuke(loop_ep, -ESHUTDOWN);
  1710. spin_unlock_irqrestore(&udc_controller->lock, flags);
  1711. /* report disconnect; the controller is already quiesced */
  1712. driver->disconnect(&udc_controller->gadget);
  1713. /* unbind gadget and unhook driver. */
  1714. driver->unbind(&udc_controller->gadget);
  1715. udc_controller->gadget.dev.driver = NULL;
  1716. udc_controller->driver = NULL;
  1717. printk(KERN_WARNING "unregistered gadget driver '%s'\n",
  1718. driver->driver.name);
  1719. return 0;
  1720. }
  1721. /*-------------------------------------------------------------------------
  1722. PROC File System Support
  1723. -------------------------------------------------------------------------*/
  1724. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  1725. #include <linux/seq_file.h>
  1726. static const char proc_filename[] = "driver/fsl_usb2_udc";
  1727. static int fsl_proc_read(char *page, char **start, off_t off, int count,
  1728. int *eof, void *_dev)
  1729. {
  1730. char *buf = page;
  1731. char *next = buf;
  1732. unsigned size = count;
  1733. unsigned long flags;
  1734. int t, i;
  1735. u32 tmp_reg;
  1736. struct fsl_ep *ep = NULL;
  1737. struct fsl_req *req;
  1738. struct fsl_udc *udc = udc_controller;
  1739. if (off != 0)
  1740. return 0;
  1741. spin_lock_irqsave(&udc->lock, flags);
  1742. /* ------basic driver information ---- */
  1743. t = scnprintf(next, size,
  1744. DRIVER_DESC "\n"
  1745. "%s version: %s\n"
  1746. "Gadget driver: %s\n\n",
  1747. driver_name, DRIVER_VERSION,
  1748. udc->driver ? udc->driver->driver.name : "(none)");
  1749. size -= t;
  1750. next += t;
  1751. /* ------ DR Registers ----- */
  1752. tmp_reg = fsl_readl(&dr_regs->usbcmd);
  1753. t = scnprintf(next, size,
  1754. "USBCMD reg:\n"
  1755. "SetupTW: %d\n"
  1756. "Run/Stop: %s\n\n",
  1757. (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
  1758. (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
  1759. size -= t;
  1760. next += t;
  1761. tmp_reg = fsl_readl(&dr_regs->usbsts);
  1762. t = scnprintf(next, size,
  1763. "USB Status Reg:\n"
  1764. "Dr Suspend: %d Reset Received: %d System Error: %s "
  1765. "USB Error Interrupt: %s\n\n",
  1766. (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
  1767. (tmp_reg & USB_STS_RESET) ? 1 : 0,
  1768. (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
  1769. (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
  1770. size -= t;
  1771. next += t;
  1772. tmp_reg = fsl_readl(&dr_regs->usbintr);
  1773. t = scnprintf(next, size,
  1774. "USB Intrrupt Enable Reg:\n"
  1775. "Sleep Enable: %d SOF Received Enable: %d "
  1776. "Reset Enable: %d\n"
  1777. "System Error Enable: %d "
  1778. "Port Change Dectected Enable: %d\n"
  1779. "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
  1780. (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
  1781. (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
  1782. (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
  1783. (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
  1784. (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
  1785. (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
  1786. (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
  1787. size -= t;
  1788. next += t;
  1789. tmp_reg = fsl_readl(&dr_regs->frindex);
  1790. t = scnprintf(next, size,
  1791. "USB Frame Index Reg: Frame Number is 0x%x\n\n",
  1792. (tmp_reg & USB_FRINDEX_MASKS));
  1793. size -= t;
  1794. next += t;
  1795. tmp_reg = fsl_readl(&dr_regs->deviceaddr);
  1796. t = scnprintf(next, size,
  1797. "USB Device Address Reg: Device Addr is 0x%x\n\n",
  1798. (tmp_reg & USB_DEVICE_ADDRESS_MASK));
  1799. size -= t;
  1800. next += t;
  1801. tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
  1802. t = scnprintf(next, size,
  1803. "USB Endpoint List Address Reg: "
  1804. "Device Addr is 0x%x\n\n",
  1805. (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
  1806. size -= t;
  1807. next += t;
  1808. tmp_reg = fsl_readl(&dr_regs->portsc1);
  1809. t = scnprintf(next, size,
  1810. "USB Port Status&Control Reg:\n"
  1811. "Port Transceiver Type : %s Port Speed: %s\n"
  1812. "PHY Low Power Suspend: %s Port Reset: %s "
  1813. "Port Suspend Mode: %s\n"
  1814. "Over-current Change: %s "
  1815. "Port Enable/Disable Change: %s\n"
  1816. "Port Enabled/Disabled: %s "
  1817. "Current Connect Status: %s\n\n", ( {
  1818. char *s;
  1819. switch (tmp_reg & PORTSCX_PTS_FSLS) {
  1820. case PORTSCX_PTS_UTMI:
  1821. s = "UTMI"; break;
  1822. case PORTSCX_PTS_ULPI:
  1823. s = "ULPI "; break;
  1824. case PORTSCX_PTS_FSLS:
  1825. s = "FS/LS Serial"; break;
  1826. default:
  1827. s = "None"; break;
  1828. }
  1829. s;} ),
  1830. usb_speed_string(portscx_device_speed(tmp_reg)),
  1831. (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
  1832. "Normal PHY mode" : "Low power mode",
  1833. (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
  1834. "Not in Reset",
  1835. (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
  1836. (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
  1837. "No",
  1838. (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
  1839. "Not change",
  1840. (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
  1841. "Not correct",
  1842. (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
  1843. "Attached" : "Not-Att");
  1844. size -= t;
  1845. next += t;
  1846. tmp_reg = fsl_readl(&dr_regs->usbmode);
  1847. t = scnprintf(next, size,
  1848. "USB Mode Reg: Controller Mode is: %s\n\n", ( {
  1849. char *s;
  1850. switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
  1851. case USB_MODE_CTRL_MODE_IDLE:
  1852. s = "Idle"; break;
  1853. case USB_MODE_CTRL_MODE_DEVICE:
  1854. s = "Device Controller"; break;
  1855. case USB_MODE_CTRL_MODE_HOST:
  1856. s = "Host Controller"; break;
  1857. default:
  1858. s = "None"; break;
  1859. }
  1860. s;
  1861. } ));
  1862. size -= t;
  1863. next += t;
  1864. tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
  1865. t = scnprintf(next, size,
  1866. "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
  1867. (tmp_reg & EP_SETUP_STATUS_MASK));
  1868. size -= t;
  1869. next += t;
  1870. for (i = 0; i < udc->max_ep / 2; i++) {
  1871. tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
  1872. t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
  1873. i, tmp_reg);
  1874. size -= t;
  1875. next += t;
  1876. }
  1877. tmp_reg = fsl_readl(&dr_regs->endpointprime);
  1878. t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
  1879. size -= t;
  1880. next += t;
  1881. #ifndef CONFIG_ARCH_MXC
  1882. if (udc->pdata->have_sysif_regs) {
  1883. tmp_reg = usb_sys_regs->snoop1;
  1884. t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
  1885. size -= t;
  1886. next += t;
  1887. tmp_reg = usb_sys_regs->control;
  1888. t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
  1889. tmp_reg);
  1890. size -= t;
  1891. next += t;
  1892. }
  1893. #endif
  1894. /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
  1895. ep = &udc->eps[0];
  1896. t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
  1897. ep->ep.name, ep_maxpacket(ep), ep_index(ep));
  1898. size -= t;
  1899. next += t;
  1900. if (list_empty(&ep->queue)) {
  1901. t = scnprintf(next, size, "its req queue is empty\n\n");
  1902. size -= t;
  1903. next += t;
  1904. } else {
  1905. list_for_each_entry(req, &ep->queue, queue) {
  1906. t = scnprintf(next, size,
  1907. "req %p actual 0x%x length 0x%x buf %p\n",
  1908. &req->req, req->req.actual,
  1909. req->req.length, req->req.buf);
  1910. size -= t;
  1911. next += t;
  1912. }
  1913. }
  1914. /* other gadget->eplist ep */
  1915. list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
  1916. if (ep->ep.desc) {
  1917. t = scnprintf(next, size,
  1918. "\nFor %s Maxpkt is 0x%x "
  1919. "index is 0x%x\n",
  1920. ep->ep.name, ep_maxpacket(ep),
  1921. ep_index(ep));
  1922. size -= t;
  1923. next += t;
  1924. if (list_empty(&ep->queue)) {
  1925. t = scnprintf(next, size,
  1926. "its req queue is empty\n\n");
  1927. size -= t;
  1928. next += t;
  1929. } else {
  1930. list_for_each_entry(req, &ep->queue, queue) {
  1931. t = scnprintf(next, size,
  1932. "req %p actual 0x%x length "
  1933. "0x%x buf %p\n",
  1934. &req->req, req->req.actual,
  1935. req->req.length, req->req.buf);
  1936. size -= t;
  1937. next += t;
  1938. } /* end for each_entry of ep req */
  1939. } /* end for else */
  1940. } /* end for if(ep->queue) */
  1941. } /* end (ep->desc) */
  1942. spin_unlock_irqrestore(&udc->lock, flags);
  1943. *eof = 1;
  1944. return count - size;
  1945. }
  1946. #define create_proc_file() create_proc_read_entry(proc_filename, \
  1947. 0, NULL, fsl_proc_read, NULL)
  1948. #define remove_proc_file() remove_proc_entry(proc_filename, NULL)
  1949. #else /* !CONFIG_USB_GADGET_DEBUG_FILES */
  1950. #define create_proc_file() do {} while (0)
  1951. #define remove_proc_file() do {} while (0)
  1952. #endif /* CONFIG_USB_GADGET_DEBUG_FILES */
  1953. /*-------------------------------------------------------------------------*/
  1954. /* Release udc structures */
  1955. static void fsl_udc_release(struct device *dev)
  1956. {
  1957. complete(udc_controller->done);
  1958. dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
  1959. udc_controller->ep_qh, udc_controller->ep_qh_dma);
  1960. kfree(udc_controller);
  1961. }
  1962. /******************************************************************
  1963. Internal structure setup functions
  1964. *******************************************************************/
  1965. /*------------------------------------------------------------------
  1966. * init resource for globle controller
  1967. * Return the udc handle on success or NULL on failure
  1968. ------------------------------------------------------------------*/
  1969. static int __init struct_udc_setup(struct fsl_udc *udc,
  1970. struct platform_device *pdev)
  1971. {
  1972. struct fsl_usb2_platform_data *pdata;
  1973. size_t size;
  1974. pdata = pdev->dev.platform_data;
  1975. udc->phy_mode = pdata->phy_mode;
  1976. udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
  1977. if (!udc->eps) {
  1978. ERR("malloc fsl_ep failed\n");
  1979. return -1;
  1980. }
  1981. /* initialized QHs, take care of alignment */
  1982. size = udc->max_ep * sizeof(struct ep_queue_head);
  1983. if (size < QH_ALIGNMENT)
  1984. size = QH_ALIGNMENT;
  1985. else if ((size % QH_ALIGNMENT) != 0) {
  1986. size += QH_ALIGNMENT + 1;
  1987. size &= ~(QH_ALIGNMENT - 1);
  1988. }
  1989. udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
  1990. &udc->ep_qh_dma, GFP_KERNEL);
  1991. if (!udc->ep_qh) {
  1992. ERR("malloc QHs for udc failed\n");
  1993. kfree(udc->eps);
  1994. return -1;
  1995. }
  1996. udc->ep_qh_size = size;
  1997. /* Initialize ep0 status request structure */
  1998. /* FIXME: fsl_alloc_request() ignores ep argument */
  1999. udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
  2000. struct fsl_req, req);
  2001. /* allocate a small amount of memory to get valid address */
  2002. udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
  2003. udc->resume_state = USB_STATE_NOTATTACHED;
  2004. udc->usb_state = USB_STATE_POWERED;
  2005. udc->ep0_dir = 0;
  2006. udc->remote_wakeup = 0; /* default to 0 on reset */
  2007. return 0;
  2008. }
  2009. /*----------------------------------------------------------------
  2010. * Setup the fsl_ep struct for eps
  2011. * Link fsl_ep->ep to gadget->ep_list
  2012. * ep0out is not used so do nothing here
  2013. * ep0in should be taken care
  2014. *--------------------------------------------------------------*/
  2015. static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
  2016. char *name, int link)
  2017. {
  2018. struct fsl_ep *ep = &udc->eps[index];
  2019. ep->udc = udc;
  2020. strcpy(ep->name, name);
  2021. ep->ep.name = ep->name;
  2022. ep->ep.ops = &fsl_ep_ops;
  2023. ep->stopped = 0;
  2024. /* for ep0: maxP defined in desc
  2025. * for other eps, maxP is set by epautoconfig() called by gadget layer
  2026. */
  2027. ep->ep.maxpacket = (unsigned short) ~0;
  2028. /* the queue lists any req for this ep */
  2029. INIT_LIST_HEAD(&ep->queue);
  2030. /* gagdet.ep_list used for ep_autoconfig so no ep0 */
  2031. if (link)
  2032. list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
  2033. ep->gadget = &udc->gadget;
  2034. ep->qh = &udc->ep_qh[index];
  2035. return 0;
  2036. }
  2037. /* Driver probe function
  2038. * all intialization operations implemented here except enabling usb_intr reg
  2039. * board setup should have been done in the platform code
  2040. */
  2041. static int __init fsl_udc_probe(struct platform_device *pdev)
  2042. {
  2043. struct fsl_usb2_platform_data *pdata;
  2044. struct resource *res;
  2045. int ret = -ENODEV;
  2046. unsigned int i;
  2047. u32 dccparams;
  2048. if (strcmp(pdev->name, driver_name)) {
  2049. VDBG("Wrong device");
  2050. return -ENODEV;
  2051. }
  2052. udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
  2053. if (udc_controller == NULL) {
  2054. ERR("malloc udc failed\n");
  2055. return -ENOMEM;
  2056. }
  2057. pdata = pdev->dev.platform_data;
  2058. udc_controller->pdata = pdata;
  2059. spin_lock_init(&udc_controller->lock);
  2060. udc_controller->stopped = 1;
  2061. #ifdef CONFIG_USB_OTG
  2062. if (pdata->operating_mode == FSL_USB2_DR_OTG) {
  2063. udc_controller->transceiver = usb_get_transceiver();
  2064. if (!udc_controller->transceiver) {
  2065. ERR("Can't find OTG driver!\n");
  2066. ret = -ENODEV;
  2067. goto err_kfree;
  2068. }
  2069. }
  2070. #endif
  2071. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2072. if (!res) {
  2073. ret = -ENXIO;
  2074. goto err_kfree;
  2075. }
  2076. if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
  2077. if (!request_mem_region(res->start, resource_size(res),
  2078. driver_name)) {
  2079. ERR("request mem region for %s failed\n", pdev->name);
  2080. ret = -EBUSY;
  2081. goto err_kfree;
  2082. }
  2083. }
  2084. dr_regs = ioremap(res->start, resource_size(res));
  2085. if (!dr_regs) {
  2086. ret = -ENOMEM;
  2087. goto err_release_mem_region;
  2088. }
  2089. pdata->regs = (void *)dr_regs;
  2090. /*
  2091. * do platform specific init: check the clock, grab/config pins, etc.
  2092. */
  2093. if (pdata->init && pdata->init(pdev)) {
  2094. ret = -ENODEV;
  2095. goto err_iounmap_noclk;
  2096. }
  2097. /* Set accessors only after pdata->init() ! */
  2098. fsl_set_accessors(pdata);
  2099. #ifndef CONFIG_ARCH_MXC
  2100. if (pdata->have_sysif_regs)
  2101. usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
  2102. #endif
  2103. /* Initialize USB clocks */
  2104. ret = fsl_udc_clk_init(pdev);
  2105. if (ret < 0)
  2106. goto err_iounmap_noclk;
  2107. /* Read Device Controller Capability Parameters register */
  2108. dccparams = fsl_readl(&dr_regs->dccparams);
  2109. if (!(dccparams & DCCPARAMS_DC)) {
  2110. ERR("This SOC doesn't support device role\n");
  2111. ret = -ENODEV;
  2112. goto err_iounmap;
  2113. }
  2114. /* Get max device endpoints */
  2115. /* DEN is bidirectional ep number, max_ep doubles the number */
  2116. udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
  2117. udc_controller->irq = platform_get_irq(pdev, 0);
  2118. if (!udc_controller->irq) {
  2119. ret = -ENODEV;
  2120. goto err_iounmap;
  2121. }
  2122. ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
  2123. driver_name, udc_controller);
  2124. if (ret != 0) {
  2125. ERR("cannot request irq %d err %d\n",
  2126. udc_controller->irq, ret);
  2127. goto err_iounmap;
  2128. }
  2129. /* Initialize the udc structure including QH member and other member */
  2130. if (struct_udc_setup(udc_controller, pdev)) {
  2131. ERR("Can't initialize udc data structure\n");
  2132. ret = -ENOMEM;
  2133. goto err_free_irq;
  2134. }
  2135. if (!udc_controller->transceiver) {
  2136. /* initialize usb hw reg except for regs for EP,
  2137. * leave usbintr reg untouched */
  2138. dr_controller_setup(udc_controller);
  2139. }
  2140. fsl_udc_clk_finalize(pdev);
  2141. /* Setup gadget structure */
  2142. udc_controller->gadget.ops = &fsl_gadget_ops;
  2143. udc_controller->gadget.max_speed = USB_SPEED_HIGH;
  2144. udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
  2145. INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
  2146. udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
  2147. udc_controller->gadget.name = driver_name;
  2148. /* Setup gadget.dev and register with kernel */
  2149. dev_set_name(&udc_controller->gadget.dev, "gadget");
  2150. udc_controller->gadget.dev.release = fsl_udc_release;
  2151. udc_controller->gadget.dev.parent = &pdev->dev;
  2152. ret = device_register(&udc_controller->gadget.dev);
  2153. if (ret < 0)
  2154. goto err_free_irq;
  2155. if (udc_controller->transceiver)
  2156. udc_controller->gadget.is_otg = 1;
  2157. /* setup QH and epctrl for ep0 */
  2158. ep0_setup(udc_controller);
  2159. /* setup udc->eps[] for ep0 */
  2160. struct_ep_setup(udc_controller, 0, "ep0", 0);
  2161. /* for ep0: the desc defined here;
  2162. * for other eps, gadget layer called ep_enable with defined desc
  2163. */
  2164. udc_controller->eps[0].desc = &fsl_ep0_desc;
  2165. udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
  2166. /* setup the udc->eps[] for non-control endpoints and link
  2167. * to gadget.ep_list */
  2168. for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
  2169. char name[14];
  2170. sprintf(name, "ep%dout", i);
  2171. struct_ep_setup(udc_controller, i * 2, name, 1);
  2172. sprintf(name, "ep%din", i);
  2173. struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
  2174. }
  2175. /* use dma_pool for TD management */
  2176. udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
  2177. sizeof(struct ep_td_struct),
  2178. DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
  2179. if (udc_controller->td_pool == NULL) {
  2180. ret = -ENOMEM;
  2181. goto err_unregister;
  2182. }
  2183. ret = usb_add_gadget_udc(&pdev->dev, &udc_controller->gadget);
  2184. if (ret)
  2185. goto err_del_udc;
  2186. create_proc_file();
  2187. return 0;
  2188. err_del_udc:
  2189. dma_pool_destroy(udc_controller->td_pool);
  2190. err_unregister:
  2191. device_unregister(&udc_controller->gadget.dev);
  2192. err_free_irq:
  2193. free_irq(udc_controller->irq, udc_controller);
  2194. err_iounmap:
  2195. if (pdata->exit)
  2196. pdata->exit(pdev);
  2197. fsl_udc_clk_release();
  2198. err_iounmap_noclk:
  2199. iounmap(dr_regs);
  2200. err_release_mem_region:
  2201. if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
  2202. release_mem_region(res->start, resource_size(res));
  2203. err_kfree:
  2204. kfree(udc_controller);
  2205. udc_controller = NULL;
  2206. return ret;
  2207. }
  2208. /* Driver removal function
  2209. * Free resources and finish pending transactions
  2210. */
  2211. static int __exit fsl_udc_remove(struct platform_device *pdev)
  2212. {
  2213. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2214. struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
  2215. DECLARE_COMPLETION(done);
  2216. if (!udc_controller)
  2217. return -ENODEV;
  2218. usb_del_gadget_udc(&udc_controller->gadget);
  2219. udc_controller->done = &done;
  2220. fsl_udc_clk_release();
  2221. /* DR has been stopped in usb_gadget_unregister_driver() */
  2222. remove_proc_file();
  2223. /* Free allocated memory */
  2224. kfree(udc_controller->status_req->req.buf);
  2225. kfree(udc_controller->status_req);
  2226. kfree(udc_controller->eps);
  2227. dma_pool_destroy(udc_controller->td_pool);
  2228. free_irq(udc_controller->irq, udc_controller);
  2229. iounmap(dr_regs);
  2230. if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
  2231. release_mem_region(res->start, resource_size(res));
  2232. device_unregister(&udc_controller->gadget.dev);
  2233. /* free udc --wait for the release() finished */
  2234. wait_for_completion(&done);
  2235. /*
  2236. * do platform specific un-initialization:
  2237. * release iomux pins, etc.
  2238. */
  2239. if (pdata->exit)
  2240. pdata->exit(pdev);
  2241. return 0;
  2242. }
  2243. /*-----------------------------------------------------------------
  2244. * Modify Power management attributes
  2245. * Used by OTG statemachine to disable gadget temporarily
  2246. -----------------------------------------------------------------*/
  2247. static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
  2248. {
  2249. dr_controller_stop(udc_controller);
  2250. return 0;
  2251. }
  2252. /*-----------------------------------------------------------------
  2253. * Invoked on USB resume. May be called in_interrupt.
  2254. * Here we start the DR controller and enable the irq
  2255. *-----------------------------------------------------------------*/
  2256. static int fsl_udc_resume(struct platform_device *pdev)
  2257. {
  2258. /* Enable DR irq reg and set controller Run */
  2259. if (udc_controller->stopped) {
  2260. dr_controller_setup(udc_controller);
  2261. dr_controller_run(udc_controller);
  2262. }
  2263. udc_controller->usb_state = USB_STATE_ATTACHED;
  2264. udc_controller->ep0_state = WAIT_FOR_SETUP;
  2265. udc_controller->ep0_dir = 0;
  2266. return 0;
  2267. }
  2268. static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
  2269. {
  2270. struct fsl_udc *udc = udc_controller;
  2271. u32 mode, usbcmd;
  2272. mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
  2273. pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
  2274. /*
  2275. * If the controller is already stopped, then this must be a
  2276. * PM suspend. Remember this fact, so that we will leave the
  2277. * controller stopped at PM resume time.
  2278. */
  2279. if (udc->stopped) {
  2280. pr_debug("gadget already stopped, leaving early\n");
  2281. udc->already_stopped = 1;
  2282. return 0;
  2283. }
  2284. if (mode != USB_MODE_CTRL_MODE_DEVICE) {
  2285. pr_debug("gadget not in device mode, leaving early\n");
  2286. return 0;
  2287. }
  2288. /* stop the controller */
  2289. usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
  2290. fsl_writel(usbcmd, &dr_regs->usbcmd);
  2291. udc->stopped = 1;
  2292. pr_info("USB Gadget suspended\n");
  2293. return 0;
  2294. }
  2295. static int fsl_udc_otg_resume(struct device *dev)
  2296. {
  2297. pr_debug("%s(): stopped %d already_stopped %d\n", __func__,
  2298. udc_controller->stopped, udc_controller->already_stopped);
  2299. /*
  2300. * If the controller was stopped at suspend time, then
  2301. * don't resume it now.
  2302. */
  2303. if (udc_controller->already_stopped) {
  2304. udc_controller->already_stopped = 0;
  2305. pr_debug("gadget was already stopped, leaving early\n");
  2306. return 0;
  2307. }
  2308. pr_info("USB Gadget resume\n");
  2309. return fsl_udc_resume(NULL);
  2310. }
  2311. /*-------------------------------------------------------------------------
  2312. Register entry point for the peripheral controller driver
  2313. --------------------------------------------------------------------------*/
  2314. static struct platform_driver udc_driver = {
  2315. .remove = __exit_p(fsl_udc_remove),
  2316. /* these suspend and resume are not usb suspend and resume */
  2317. .suspend = fsl_udc_suspend,
  2318. .resume = fsl_udc_resume,
  2319. .driver = {
  2320. .name = (char *)driver_name,
  2321. .owner = THIS_MODULE,
  2322. /* udc suspend/resume called from OTG driver */
  2323. .suspend = fsl_udc_otg_suspend,
  2324. .resume = fsl_udc_otg_resume,
  2325. },
  2326. };
  2327. static int __init udc_init(void)
  2328. {
  2329. printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION);
  2330. return platform_driver_probe(&udc_driver, fsl_udc_probe);
  2331. }
  2332. module_init(udc_init);
  2333. static void __exit udc_exit(void)
  2334. {
  2335. platform_driver_unregister(&udc_driver);
  2336. printk(KERN_WARNING "%s unregistered\n", driver_desc);
  2337. }
  2338. module_exit(udc_exit);
  2339. MODULE_DESCRIPTION(DRIVER_DESC);
  2340. MODULE_AUTHOR(DRIVER_AUTHOR);
  2341. MODULE_LICENSE("GPL");
  2342. MODULE_ALIAS("platform:fsl-usb2-udc");