arizona-core.c 17 KB

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  1. /*
  2. * Arizona core driver
  3. *
  4. * Copyright 2012 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/delay.h>
  13. #include <linux/err.h>
  14. #include <linux/gpio.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/mfd/core.h>
  17. #include <linux/module.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/regmap.h>
  20. #include <linux/regulator/consumer.h>
  21. #include <linux/slab.h>
  22. #include <linux/mfd/arizona/core.h>
  23. #include <linux/mfd/arizona/registers.h>
  24. #include "arizona.h"
  25. static const char *wm5102_core_supplies[] = {
  26. "AVDD",
  27. "DBVDD1",
  28. };
  29. int arizona_clk32k_enable(struct arizona *arizona)
  30. {
  31. int ret = 0;
  32. mutex_lock(&arizona->clk_lock);
  33. arizona->clk32k_ref++;
  34. if (arizona->clk32k_ref == 1) {
  35. switch (arizona->pdata.clk32k_src) {
  36. case ARIZONA_32KZ_MCLK1:
  37. ret = pm_runtime_get_sync(arizona->dev);
  38. if (ret != 0)
  39. goto out;
  40. break;
  41. }
  42. ret = regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  43. ARIZONA_CLK_32K_ENA,
  44. ARIZONA_CLK_32K_ENA);
  45. }
  46. out:
  47. if (ret != 0)
  48. arizona->clk32k_ref--;
  49. mutex_unlock(&arizona->clk_lock);
  50. return ret;
  51. }
  52. EXPORT_SYMBOL_GPL(arizona_clk32k_enable);
  53. int arizona_clk32k_disable(struct arizona *arizona)
  54. {
  55. int ret = 0;
  56. mutex_lock(&arizona->clk_lock);
  57. BUG_ON(arizona->clk32k_ref <= 0);
  58. arizona->clk32k_ref--;
  59. if (arizona->clk32k_ref == 0) {
  60. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  61. ARIZONA_CLK_32K_ENA, 0);
  62. switch (arizona->pdata.clk32k_src) {
  63. case ARIZONA_32KZ_MCLK1:
  64. pm_runtime_put_sync(arizona->dev);
  65. break;
  66. }
  67. }
  68. mutex_unlock(&arizona->clk_lock);
  69. return ret;
  70. }
  71. EXPORT_SYMBOL_GPL(arizona_clk32k_disable);
  72. static irqreturn_t arizona_clkgen_err(int irq, void *data)
  73. {
  74. struct arizona *arizona = data;
  75. dev_err(arizona->dev, "CLKGEN error\n");
  76. return IRQ_HANDLED;
  77. }
  78. static irqreturn_t arizona_underclocked(int irq, void *data)
  79. {
  80. struct arizona *arizona = data;
  81. unsigned int val;
  82. int ret;
  83. ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_8,
  84. &val);
  85. if (ret != 0) {
  86. dev_err(arizona->dev, "Failed to read underclock status: %d\n",
  87. ret);
  88. return IRQ_NONE;
  89. }
  90. if (val & ARIZONA_AIF3_UNDERCLOCKED_STS)
  91. dev_err(arizona->dev, "AIF3 underclocked\n");
  92. if (val & ARIZONA_AIF2_UNDERCLOCKED_STS)
  93. dev_err(arizona->dev, "AIF2 underclocked\n");
  94. if (val & ARIZONA_AIF1_UNDERCLOCKED_STS)
  95. dev_err(arizona->dev, "AIF1 underclocked\n");
  96. if (val & ARIZONA_ISRC2_UNDERCLOCKED_STS)
  97. dev_err(arizona->dev, "ISRC2 underclocked\n");
  98. if (val & ARIZONA_ISRC1_UNDERCLOCKED_STS)
  99. dev_err(arizona->dev, "ISRC1 underclocked\n");
  100. if (val & ARIZONA_FX_UNDERCLOCKED_STS)
  101. dev_err(arizona->dev, "FX underclocked\n");
  102. if (val & ARIZONA_ASRC_UNDERCLOCKED_STS)
  103. dev_err(arizona->dev, "ASRC underclocked\n");
  104. if (val & ARIZONA_DAC_UNDERCLOCKED_STS)
  105. dev_err(arizona->dev, "DAC underclocked\n");
  106. if (val & ARIZONA_ADC_UNDERCLOCKED_STS)
  107. dev_err(arizona->dev, "ADC underclocked\n");
  108. if (val & ARIZONA_MIXER_UNDERCLOCKED_STS)
  109. dev_err(arizona->dev, "Mixer dropped sample\n");
  110. return IRQ_HANDLED;
  111. }
  112. static irqreturn_t arizona_overclocked(int irq, void *data)
  113. {
  114. struct arizona *arizona = data;
  115. unsigned int val[2];
  116. int ret;
  117. ret = regmap_bulk_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_6,
  118. &val[0], 2);
  119. if (ret != 0) {
  120. dev_err(arizona->dev, "Failed to read overclock status: %d\n",
  121. ret);
  122. return IRQ_NONE;
  123. }
  124. if (val[0] & ARIZONA_PWM_OVERCLOCKED_STS)
  125. dev_err(arizona->dev, "PWM overclocked\n");
  126. if (val[0] & ARIZONA_FX_CORE_OVERCLOCKED_STS)
  127. dev_err(arizona->dev, "FX core overclocked\n");
  128. if (val[0] & ARIZONA_DAC_SYS_OVERCLOCKED_STS)
  129. dev_err(arizona->dev, "DAC SYS overclocked\n");
  130. if (val[0] & ARIZONA_DAC_WARP_OVERCLOCKED_STS)
  131. dev_err(arizona->dev, "DAC WARP overclocked\n");
  132. if (val[0] & ARIZONA_ADC_OVERCLOCKED_STS)
  133. dev_err(arizona->dev, "ADC overclocked\n");
  134. if (val[0] & ARIZONA_MIXER_OVERCLOCKED_STS)
  135. dev_err(arizona->dev, "Mixer overclocked\n");
  136. if (val[0] & ARIZONA_AIF3_SYNC_OVERCLOCKED_STS)
  137. dev_err(arizona->dev, "AIF3 overclocked\n");
  138. if (val[0] & ARIZONA_AIF2_SYNC_OVERCLOCKED_STS)
  139. dev_err(arizona->dev, "AIF2 overclocked\n");
  140. if (val[0] & ARIZONA_AIF1_SYNC_OVERCLOCKED_STS)
  141. dev_err(arizona->dev, "AIF1 overclocked\n");
  142. if (val[0] & ARIZONA_PAD_CTRL_OVERCLOCKED_STS)
  143. dev_err(arizona->dev, "Pad control overclocked\n");
  144. if (val[1] & ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS)
  145. dev_err(arizona->dev, "Slimbus subsystem overclocked\n");
  146. if (val[1] & ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS)
  147. dev_err(arizona->dev, "Slimbus async overclocked\n");
  148. if (val[1] & ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS)
  149. dev_err(arizona->dev, "Slimbus sync overclocked\n");
  150. if (val[1] & ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS)
  151. dev_err(arizona->dev, "ASRC async system overclocked\n");
  152. if (val[1] & ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS)
  153. dev_err(arizona->dev, "ASRC async WARP overclocked\n");
  154. if (val[1] & ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS)
  155. dev_err(arizona->dev, "ASRC sync system overclocked\n");
  156. if (val[1] & ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS)
  157. dev_err(arizona->dev, "ASRC sync WARP overclocked\n");
  158. if (val[1] & ARIZONA_ADSP2_1_OVERCLOCKED_STS)
  159. dev_err(arizona->dev, "DSP1 overclocked\n");
  160. if (val[1] & ARIZONA_ISRC2_OVERCLOCKED_STS)
  161. dev_err(arizona->dev, "ISRC2 overclocked\n");
  162. if (val[1] & ARIZONA_ISRC1_OVERCLOCKED_STS)
  163. dev_err(arizona->dev, "ISRC1 overclocked\n");
  164. return IRQ_HANDLED;
  165. }
  166. static int arizona_wait_for_boot(struct arizona *arizona)
  167. {
  168. unsigned int reg;
  169. int ret, i;
  170. /*
  171. * We can't use an interrupt as we need to runtime resume to do so,
  172. * we won't race with the interrupt handler as it'll be blocked on
  173. * runtime resume.
  174. */
  175. for (i = 0; i < 5; i++) {
  176. msleep(1);
  177. ret = regmap_read(arizona->regmap,
  178. ARIZONA_INTERRUPT_RAW_STATUS_5, &reg);
  179. if (ret != 0) {
  180. dev_err(arizona->dev, "Failed to read boot state: %d\n",
  181. ret);
  182. continue;
  183. }
  184. if (reg & ARIZONA_BOOT_DONE_STS)
  185. break;
  186. }
  187. if (reg & ARIZONA_BOOT_DONE_STS) {
  188. regmap_write(arizona->regmap, ARIZONA_INTERRUPT_STATUS_5,
  189. ARIZONA_BOOT_DONE_STS);
  190. } else {
  191. dev_err(arizona->dev, "Device boot timed out: %x\n", reg);
  192. return -ETIMEDOUT;
  193. }
  194. pm_runtime_mark_last_busy(arizona->dev);
  195. return 0;
  196. }
  197. #ifdef CONFIG_PM_RUNTIME
  198. static int arizona_runtime_resume(struct device *dev)
  199. {
  200. struct arizona *arizona = dev_get_drvdata(dev);
  201. int ret;
  202. dev_dbg(arizona->dev, "Leaving AoD mode\n");
  203. ret = regulator_enable(arizona->dcvdd);
  204. if (ret != 0) {
  205. dev_err(arizona->dev, "Failed to enable DCVDD: %d\n", ret);
  206. return ret;
  207. }
  208. regcache_cache_only(arizona->regmap, false);
  209. ret = arizona_wait_for_boot(arizona);
  210. if (ret != 0) {
  211. goto err;
  212. }
  213. switch (arizona->type) {
  214. case WM5102:
  215. ret = wm5102_patch(arizona);
  216. if (ret != 0) {
  217. dev_err(arizona->dev, "Failed to apply patch: %d\n",
  218. ret);
  219. goto err;
  220. }
  221. }
  222. ret = regcache_sync(arizona->regmap);
  223. if (ret != 0) {
  224. dev_err(arizona->dev, "Failed to restore register cache\n");
  225. goto err;
  226. }
  227. return 0;
  228. err:
  229. regcache_cache_only(arizona->regmap, true);
  230. regulator_disable(arizona->dcvdd);
  231. return ret;
  232. }
  233. static int arizona_runtime_suspend(struct device *dev)
  234. {
  235. struct arizona *arizona = dev_get_drvdata(dev);
  236. dev_dbg(arizona->dev, "Entering AoD mode\n");
  237. regulator_disable(arizona->dcvdd);
  238. regcache_cache_only(arizona->regmap, true);
  239. regcache_mark_dirty(arizona->regmap);
  240. return 0;
  241. }
  242. #endif
  243. #ifdef CONFIG_PM_SLEEP
  244. static int arizona_resume_noirq(struct device *dev)
  245. {
  246. struct arizona *arizona = dev_get_drvdata(dev);
  247. dev_dbg(arizona->dev, "Early resume, disabling IRQ\n");
  248. disable_irq(arizona->irq);
  249. return 0;
  250. }
  251. static int arizona_resume(struct device *dev)
  252. {
  253. struct arizona *arizona = dev_get_drvdata(dev);
  254. dev_dbg(arizona->dev, "Late resume, reenabling IRQ\n");
  255. enable_irq(arizona->irq);
  256. return 0;
  257. }
  258. #endif
  259. const struct dev_pm_ops arizona_pm_ops = {
  260. SET_RUNTIME_PM_OPS(arizona_runtime_suspend,
  261. arizona_runtime_resume,
  262. NULL)
  263. SET_SYSTEM_SLEEP_PM_OPS(NULL, arizona_resume)
  264. #ifdef CONFIG_PM_SLEEP
  265. .resume_noirq = arizona_resume_noirq,
  266. #endif
  267. };
  268. EXPORT_SYMBOL_GPL(arizona_pm_ops);
  269. static struct mfd_cell early_devs[] = {
  270. { .name = "arizona-ldo1" },
  271. };
  272. static struct mfd_cell wm5102_devs[] = {
  273. { .name = "arizona-micsupp" },
  274. { .name = "arizona-extcon" },
  275. { .name = "arizona-gpio" },
  276. { .name = "arizona-haptics" },
  277. { .name = "arizona-pwm" },
  278. { .name = "wm5102-codec" },
  279. };
  280. static struct mfd_cell wm5110_devs[] = {
  281. { .name = "arizona-micsupp" },
  282. { .name = "arizona-extcon" },
  283. { .name = "arizona-gpio" },
  284. { .name = "arizona-haptics" },
  285. { .name = "arizona-pwm" },
  286. { .name = "wm5110-codec" },
  287. };
  288. int arizona_dev_init(struct arizona *arizona)
  289. {
  290. struct device *dev = arizona->dev;
  291. const char *type_name;
  292. unsigned int reg, val;
  293. int (*apply_patch)(struct arizona *) = NULL;
  294. int ret, i;
  295. dev_set_drvdata(arizona->dev, arizona);
  296. mutex_init(&arizona->clk_lock);
  297. if (dev_get_platdata(arizona->dev))
  298. memcpy(&arizona->pdata, dev_get_platdata(arizona->dev),
  299. sizeof(arizona->pdata));
  300. regcache_cache_only(arizona->regmap, true);
  301. switch (arizona->type) {
  302. case WM5102:
  303. case WM5110:
  304. for (i = 0; i < ARRAY_SIZE(wm5102_core_supplies); i++)
  305. arizona->core_supplies[i].supply
  306. = wm5102_core_supplies[i];
  307. arizona->num_core_supplies = ARRAY_SIZE(wm5102_core_supplies);
  308. break;
  309. default:
  310. dev_err(arizona->dev, "Unknown device type %d\n",
  311. arizona->type);
  312. return -EINVAL;
  313. }
  314. ret = mfd_add_devices(arizona->dev, -1, early_devs,
  315. ARRAY_SIZE(early_devs), NULL, 0, NULL);
  316. if (ret != 0) {
  317. dev_err(dev, "Failed to add early children: %d\n", ret);
  318. return ret;
  319. }
  320. ret = devm_regulator_bulk_get(dev, arizona->num_core_supplies,
  321. arizona->core_supplies);
  322. if (ret != 0) {
  323. dev_err(dev, "Failed to request core supplies: %d\n",
  324. ret);
  325. goto err_early;
  326. }
  327. arizona->dcvdd = devm_regulator_get(arizona->dev, "DCVDD");
  328. if (IS_ERR(arizona->dcvdd)) {
  329. ret = PTR_ERR(arizona->dcvdd);
  330. dev_err(dev, "Failed to request DCVDD: %d\n", ret);
  331. goto err_early;
  332. }
  333. ret = regulator_bulk_enable(arizona->num_core_supplies,
  334. arizona->core_supplies);
  335. if (ret != 0) {
  336. dev_err(dev, "Failed to enable core supplies: %d\n",
  337. ret);
  338. goto err_early;
  339. }
  340. ret = regulator_enable(arizona->dcvdd);
  341. if (ret != 0) {
  342. dev_err(dev, "Failed to enable DCVDD: %d\n", ret);
  343. goto err_enable;
  344. }
  345. if (arizona->pdata.reset) {
  346. /* Start out with /RESET low to put the chip into reset */
  347. ret = gpio_request_one(arizona->pdata.reset,
  348. GPIOF_DIR_OUT | GPIOF_INIT_LOW,
  349. "arizona /RESET");
  350. if (ret != 0) {
  351. dev_err(dev, "Failed to request /RESET: %d\n", ret);
  352. goto err_dcvdd;
  353. }
  354. gpio_set_value_cansleep(arizona->pdata.reset, 1);
  355. }
  356. regcache_cache_only(arizona->regmap, false);
  357. ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, &reg);
  358. if (ret != 0) {
  359. dev_err(dev, "Failed to read ID register: %d\n", ret);
  360. goto err_reset;
  361. }
  362. ret = regmap_read(arizona->regmap, ARIZONA_DEVICE_REVISION,
  363. &arizona->rev);
  364. if (ret != 0) {
  365. dev_err(dev, "Failed to read revision register: %d\n", ret);
  366. goto err_reset;
  367. }
  368. arizona->rev &= ARIZONA_DEVICE_REVISION_MASK;
  369. switch (reg) {
  370. #ifdef CONFIG_MFD_WM5102
  371. case 0x5102:
  372. type_name = "WM5102";
  373. if (arizona->type != WM5102) {
  374. dev_err(arizona->dev, "WM5102 registered as %d\n",
  375. arizona->type);
  376. arizona->type = WM5102;
  377. }
  378. apply_patch = wm5102_patch;
  379. arizona->rev &= 0x7;
  380. break;
  381. #endif
  382. #ifdef CONFIG_MFD_WM5110
  383. case 0x5110:
  384. type_name = "WM5110";
  385. if (arizona->type != WM5110) {
  386. dev_err(arizona->dev, "WM5110 registered as %d\n",
  387. arizona->type);
  388. arizona->type = WM5110;
  389. }
  390. apply_patch = wm5110_patch;
  391. break;
  392. #endif
  393. default:
  394. dev_err(arizona->dev, "Unknown device ID %x\n", reg);
  395. goto err_reset;
  396. }
  397. dev_info(dev, "%s revision %c\n", type_name, arizona->rev + 'A');
  398. /* If we have a /RESET GPIO we'll already be reset */
  399. if (!arizona->pdata.reset) {
  400. regcache_mark_dirty(arizona->regmap);
  401. ret = regmap_write(arizona->regmap, ARIZONA_SOFTWARE_RESET, 0);
  402. if (ret != 0) {
  403. dev_err(dev, "Failed to reset device: %d\n", ret);
  404. goto err_reset;
  405. }
  406. ret = regcache_sync(arizona->regmap);
  407. if (ret != 0) {
  408. dev_err(dev, "Failed to sync device: %d\n", ret);
  409. goto err_reset;
  410. }
  411. }
  412. ret = arizona_wait_for_boot(arizona);
  413. if (ret != 0) {
  414. dev_err(arizona->dev, "Device failed initial boot: %d\n", ret);
  415. goto err_reset;
  416. }
  417. if (apply_patch) {
  418. ret = apply_patch(arizona);
  419. if (ret != 0) {
  420. dev_err(arizona->dev, "Failed to apply patch: %d\n",
  421. ret);
  422. goto err_reset;
  423. }
  424. }
  425. for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
  426. if (!arizona->pdata.gpio_defaults[i])
  427. continue;
  428. regmap_write(arizona->regmap, ARIZONA_GPIO1_CTRL + i,
  429. arizona->pdata.gpio_defaults[i]);
  430. }
  431. pm_runtime_set_autosuspend_delay(arizona->dev, 100);
  432. pm_runtime_use_autosuspend(arizona->dev);
  433. pm_runtime_enable(arizona->dev);
  434. /* Chip default */
  435. if (!arizona->pdata.clk32k_src)
  436. arizona->pdata.clk32k_src = ARIZONA_32KZ_MCLK2;
  437. switch (arizona->pdata.clk32k_src) {
  438. case ARIZONA_32KZ_MCLK1:
  439. case ARIZONA_32KZ_MCLK2:
  440. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  441. ARIZONA_CLK_32K_SRC_MASK,
  442. arizona->pdata.clk32k_src - 1);
  443. arizona_clk32k_enable(arizona);
  444. break;
  445. case ARIZONA_32KZ_NONE:
  446. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  447. ARIZONA_CLK_32K_SRC_MASK, 2);
  448. break;
  449. default:
  450. dev_err(arizona->dev, "Invalid 32kHz clock source: %d\n",
  451. arizona->pdata.clk32k_src);
  452. ret = -EINVAL;
  453. goto err_reset;
  454. }
  455. for (i = 0; i < ARIZONA_MAX_MICBIAS; i++) {
  456. if (!arizona->pdata.micbias[i].mV &&
  457. !arizona->pdata.micbias[i].bypass)
  458. continue;
  459. /* Apply default for bypass mode */
  460. if (!arizona->pdata.micbias[i].mV)
  461. arizona->pdata.micbias[i].mV = 2800;
  462. val = (arizona->pdata.micbias[i].mV - 1500) / 100;
  463. val <<= ARIZONA_MICB1_LVL_SHIFT;
  464. if (arizona->pdata.micbias[i].ext_cap)
  465. val |= ARIZONA_MICB1_EXT_CAP;
  466. if (arizona->pdata.micbias[i].discharge)
  467. val |= ARIZONA_MICB1_DISCH;
  468. if (arizona->pdata.micbias[i].fast_start)
  469. val |= ARIZONA_MICB1_RATE;
  470. if (arizona->pdata.micbias[i].bypass)
  471. val |= ARIZONA_MICB1_BYPASS;
  472. regmap_update_bits(arizona->regmap,
  473. ARIZONA_MIC_BIAS_CTRL_1 + i,
  474. ARIZONA_MICB1_LVL_MASK |
  475. ARIZONA_MICB1_DISCH |
  476. ARIZONA_MICB1_BYPASS |
  477. ARIZONA_MICB1_RATE, val);
  478. }
  479. for (i = 0; i < ARIZONA_MAX_INPUT; i++) {
  480. /* Default for both is 0 so noop with defaults */
  481. val = arizona->pdata.dmic_ref[i]
  482. << ARIZONA_IN1_DMIC_SUP_SHIFT;
  483. val |= arizona->pdata.inmode[i] << ARIZONA_IN1_MODE_SHIFT;
  484. regmap_update_bits(arizona->regmap,
  485. ARIZONA_IN1L_CONTROL + (i * 8),
  486. ARIZONA_IN1_DMIC_SUP_MASK |
  487. ARIZONA_IN1_MODE_MASK, val);
  488. }
  489. for (i = 0; i < ARIZONA_MAX_OUTPUT; i++) {
  490. /* Default is 0 so noop with defaults */
  491. if (arizona->pdata.out_mono[i])
  492. val = ARIZONA_OUT1_MONO;
  493. else
  494. val = 0;
  495. regmap_update_bits(arizona->regmap,
  496. ARIZONA_OUTPUT_PATH_CONFIG_1L + (i * 8),
  497. ARIZONA_OUT1_MONO, val);
  498. }
  499. for (i = 0; i < ARIZONA_MAX_PDM_SPK; i++) {
  500. if (arizona->pdata.spk_mute[i])
  501. regmap_update_bits(arizona->regmap,
  502. ARIZONA_PDM_SPK1_CTRL_1 + (i * 2),
  503. ARIZONA_SPK1_MUTE_ENDIAN_MASK |
  504. ARIZONA_SPK1_MUTE_SEQ1_MASK,
  505. arizona->pdata.spk_mute[i]);
  506. if (arizona->pdata.spk_fmt[i])
  507. regmap_update_bits(arizona->regmap,
  508. ARIZONA_PDM_SPK1_CTRL_2 + (i * 2),
  509. ARIZONA_SPK1_FMT_MASK,
  510. arizona->pdata.spk_fmt[i]);
  511. }
  512. /* Set up for interrupts */
  513. ret = arizona_irq_init(arizona);
  514. if (ret != 0)
  515. goto err_reset;
  516. arizona_request_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, "CLKGEN error",
  517. arizona_clkgen_err, arizona);
  518. arizona_request_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, "Overclocked",
  519. arizona_overclocked, arizona);
  520. arizona_request_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, "Underclocked",
  521. arizona_underclocked, arizona);
  522. switch (arizona->type) {
  523. case WM5102:
  524. ret = mfd_add_devices(arizona->dev, -1, wm5102_devs,
  525. ARRAY_SIZE(wm5102_devs), NULL, 0, NULL);
  526. break;
  527. case WM5110:
  528. ret = mfd_add_devices(arizona->dev, -1, wm5110_devs,
  529. ARRAY_SIZE(wm5110_devs), NULL, 0, NULL);
  530. break;
  531. }
  532. if (ret != 0) {
  533. dev_err(arizona->dev, "Failed to add subdevices: %d\n", ret);
  534. goto err_irq;
  535. }
  536. #ifdef CONFIG_PM_RUNTIME
  537. regulator_disable(arizona->dcvdd);
  538. #endif
  539. return 0;
  540. err_irq:
  541. arizona_irq_exit(arizona);
  542. err_reset:
  543. if (arizona->pdata.reset) {
  544. gpio_set_value_cansleep(arizona->pdata.reset, 1);
  545. gpio_free(arizona->pdata.reset);
  546. }
  547. err_dcvdd:
  548. regulator_disable(arizona->dcvdd);
  549. err_enable:
  550. regulator_bulk_disable(arizona->num_core_supplies,
  551. arizona->core_supplies);
  552. err_early:
  553. mfd_remove_devices(dev);
  554. return ret;
  555. }
  556. EXPORT_SYMBOL_GPL(arizona_dev_init);
  557. int arizona_dev_exit(struct arizona *arizona)
  558. {
  559. mfd_remove_devices(arizona->dev);
  560. arizona_free_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, arizona);
  561. arizona_free_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, arizona);
  562. arizona_free_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, arizona);
  563. pm_runtime_disable(arizona->dev);
  564. arizona_irq_exit(arizona);
  565. return 0;
  566. }
  567. EXPORT_SYMBOL_GPL(arizona_dev_exit);