iwl3945-base.c 234 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/ieee80211_radiotap.h>
  42. #include <net/lib80211.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #include "iwl-3945-core.h"
  46. #include "iwl-commands.h"
  47. #include "iwl-3945-commands.h"
  48. #include "iwl-3945.h"
  49. #include "iwl-3945-fh.h"
  50. #include "iwl-helpers.h"
  51. #ifdef CONFIG_IWL3945_DEBUG
  52. u32 iwl3945_debug_level;
  53. #endif
  54. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  55. struct iwl3945_tx_queue *txq);
  56. /******************************************************************************
  57. *
  58. * module boiler plate
  59. *
  60. ******************************************************************************/
  61. /* module parameters */
  62. static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
  63. static u32 iwl3945_param_debug; /* def: 0 = minimal debug log messages */
  64. static int iwl3945_param_disable; /* def: 0 = enable radio */
  65. static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
  66. int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
  67. int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */
  68. /*
  69. * module name, copyright, version, etc.
  70. * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
  71. */
  72. #define DRV_DESCRIPTION \
  73. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  74. #ifdef CONFIG_IWL3945_DEBUG
  75. #define VD "d"
  76. #else
  77. #define VD
  78. #endif
  79. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  80. #define VS "s"
  81. #else
  82. #define VS
  83. #endif
  84. #define IWLWIFI_VERSION "1.2.26k" VD VS
  85. #define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
  86. #define DRV_AUTHOR "<ilw@linux.intel.com>"
  87. #define DRV_VERSION IWLWIFI_VERSION
  88. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  89. MODULE_VERSION(DRV_VERSION);
  90. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  91. MODULE_LICENSE("GPL");
  92. static const struct ieee80211_supported_band *iwl3945_get_band(
  93. struct iwl3945_priv *priv, enum ieee80211_band band)
  94. {
  95. return priv->hw->wiphy->bands[band];
  96. }
  97. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  98. * DMA services
  99. *
  100. * Theory of operation
  101. *
  102. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  103. * of buffer descriptors, each of which points to one or more data buffers for
  104. * the device to read from or fill. Driver and device exchange status of each
  105. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  106. * entries in each circular buffer, to protect against confusing empty and full
  107. * queue states.
  108. *
  109. * The device reads or writes the data in the queues via the device's several
  110. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  111. *
  112. * For Tx queue, there are low mark and high mark limits. If, after queuing
  113. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  114. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  115. * Tx queue resumed.
  116. *
  117. * The 3945 operates with six queues: One receive queue, one transmit queue
  118. * (#4) for sending commands to the device firmware, and four transmit queues
  119. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  120. ***************************************************/
  121. int iwl3945_queue_space(const struct iwl3945_queue *q)
  122. {
  123. int s = q->read_ptr - q->write_ptr;
  124. if (q->read_ptr > q->write_ptr)
  125. s -= q->n_bd;
  126. if (s <= 0)
  127. s += q->n_window;
  128. /* keep some reserve to not confuse empty and full situations */
  129. s -= 2;
  130. if (s < 0)
  131. s = 0;
  132. return s;
  133. }
  134. int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
  135. {
  136. return q->write_ptr > q->read_ptr ?
  137. (i >= q->read_ptr && i < q->write_ptr) :
  138. !(i < q->read_ptr && i >= q->write_ptr);
  139. }
  140. static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
  141. {
  142. /* This is for scan command, the big buffer at end of command array */
  143. if (is_huge)
  144. return q->n_window; /* must be power of 2 */
  145. /* Otherwise, use normal size buffers */
  146. return index & (q->n_window - 1);
  147. }
  148. /**
  149. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  150. */
  151. static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
  152. int count, int slots_num, u32 id)
  153. {
  154. q->n_bd = count;
  155. q->n_window = slots_num;
  156. q->id = id;
  157. /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
  158. * and iwl_queue_dec_wrap are broken. */
  159. BUG_ON(!is_power_of_2(count));
  160. /* slots_num must be power-of-two size, otherwise
  161. * get_cmd_index is broken. */
  162. BUG_ON(!is_power_of_2(slots_num));
  163. q->low_mark = q->n_window / 4;
  164. if (q->low_mark < 4)
  165. q->low_mark = 4;
  166. q->high_mark = q->n_window / 8;
  167. if (q->high_mark < 2)
  168. q->high_mark = 2;
  169. q->write_ptr = q->read_ptr = 0;
  170. return 0;
  171. }
  172. /**
  173. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  174. */
  175. static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
  176. struct iwl3945_tx_queue *txq, u32 id)
  177. {
  178. struct pci_dev *dev = priv->pci_dev;
  179. /* Driver private data, only for Tx (not command) queues,
  180. * not shared with device. */
  181. if (id != IWL_CMD_QUEUE_NUM) {
  182. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  183. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  184. if (!txq->txb) {
  185. IWL_ERROR("kmalloc for auxiliary BD "
  186. "structures failed\n");
  187. goto error;
  188. }
  189. } else
  190. txq->txb = NULL;
  191. /* Circular buffer of transmit frame descriptors (TFDs),
  192. * shared with device */
  193. txq->bd = pci_alloc_consistent(dev,
  194. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
  195. &txq->q.dma_addr);
  196. if (!txq->bd) {
  197. IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
  198. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
  199. goto error;
  200. }
  201. txq->q.id = id;
  202. return 0;
  203. error:
  204. kfree(txq->txb);
  205. txq->txb = NULL;
  206. return -ENOMEM;
  207. }
  208. /**
  209. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  210. */
  211. int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
  212. struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
  213. {
  214. struct pci_dev *dev = priv->pci_dev;
  215. int len;
  216. int rc = 0;
  217. /*
  218. * Alloc buffer array for commands (Tx or other types of commands).
  219. * For the command queue (#4), allocate command space + one big
  220. * command for scan, since scan command is very huge; the system will
  221. * not have two scans at the same time, so only one is needed.
  222. * For data Tx queues (all other queues), no super-size command
  223. * space is needed.
  224. */
  225. len = sizeof(struct iwl3945_cmd) * slots_num;
  226. if (txq_id == IWL_CMD_QUEUE_NUM)
  227. len += IWL_MAX_SCAN_SIZE;
  228. txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
  229. if (!txq->cmd)
  230. return -ENOMEM;
  231. /* Alloc driver data array and TFD circular buffer */
  232. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  233. if (rc) {
  234. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  235. return -ENOMEM;
  236. }
  237. txq->need_update = 0;
  238. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  239. * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
  240. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  241. /* Initialize queue high/low-water, head/tail indexes */
  242. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  243. /* Tell device where to find queue, enable DMA channel. */
  244. iwl3945_hw_tx_queue_init(priv, txq);
  245. return 0;
  246. }
  247. /**
  248. * iwl3945_tx_queue_free - Deallocate DMA queue.
  249. * @txq: Transmit queue to deallocate.
  250. *
  251. * Empty queue by removing and destroying all BD's.
  252. * Free all buffers.
  253. * 0-fill, but do not free "txq" descriptor structure.
  254. */
  255. void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
  256. {
  257. struct iwl3945_queue *q = &txq->q;
  258. struct pci_dev *dev = priv->pci_dev;
  259. int len;
  260. if (q->n_bd == 0)
  261. return;
  262. /* first, empty all BD's */
  263. for (; q->write_ptr != q->read_ptr;
  264. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
  265. iwl3945_hw_txq_free_tfd(priv, txq);
  266. len = sizeof(struct iwl3945_cmd) * q->n_window;
  267. if (q->id == IWL_CMD_QUEUE_NUM)
  268. len += IWL_MAX_SCAN_SIZE;
  269. /* De-alloc array of command/tx buffers */
  270. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  271. /* De-alloc circular buffer of TFDs */
  272. if (txq->q.n_bd)
  273. pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
  274. txq->q.n_bd, txq->bd, txq->q.dma_addr);
  275. /* De-alloc array of per-TFD driver data */
  276. kfree(txq->txb);
  277. txq->txb = NULL;
  278. /* 0-fill queue descriptor structure */
  279. memset(txq, 0, sizeof(*txq));
  280. }
  281. const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  282. /*************** STATION TABLE MANAGEMENT ****
  283. * mac80211 should be examined to determine if sta_info is duplicating
  284. * the functionality provided here
  285. */
  286. /**************************************************************/
  287. #if 0 /* temporary disable till we add real remove station */
  288. /**
  289. * iwl3945_remove_station - Remove driver's knowledge of station.
  290. *
  291. * NOTE: This does not remove station from device's station table.
  292. */
  293. static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
  294. {
  295. int index = IWL_INVALID_STATION;
  296. int i;
  297. unsigned long flags;
  298. spin_lock_irqsave(&priv->sta_lock, flags);
  299. if (is_ap)
  300. index = IWL_AP_ID;
  301. else if (is_broadcast_ether_addr(addr))
  302. index = priv->hw_setting.bcast_sta_id;
  303. else
  304. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
  305. if (priv->stations[i].used &&
  306. !compare_ether_addr(priv->stations[i].sta.sta.addr,
  307. addr)) {
  308. index = i;
  309. break;
  310. }
  311. if (unlikely(index == IWL_INVALID_STATION))
  312. goto out;
  313. if (priv->stations[index].used) {
  314. priv->stations[index].used = 0;
  315. priv->num_stations--;
  316. }
  317. BUG_ON(priv->num_stations < 0);
  318. out:
  319. spin_unlock_irqrestore(&priv->sta_lock, flags);
  320. return 0;
  321. }
  322. #endif
  323. /**
  324. * iwl3945_clear_stations_table - Clear the driver's station table
  325. *
  326. * NOTE: This does not clear or otherwise alter the device's station table.
  327. */
  328. static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
  329. {
  330. unsigned long flags;
  331. spin_lock_irqsave(&priv->sta_lock, flags);
  332. priv->num_stations = 0;
  333. memset(priv->stations, 0, sizeof(priv->stations));
  334. spin_unlock_irqrestore(&priv->sta_lock, flags);
  335. }
  336. /**
  337. * iwl3945_add_station - Add station to station tables in driver and device
  338. */
  339. u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
  340. {
  341. int i;
  342. int index = IWL_INVALID_STATION;
  343. struct iwl3945_station_entry *station;
  344. unsigned long flags_spin;
  345. u8 rate;
  346. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  347. if (is_ap)
  348. index = IWL_AP_ID;
  349. else if (is_broadcast_ether_addr(addr))
  350. index = priv->hw_setting.bcast_sta_id;
  351. else
  352. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
  353. if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
  354. addr)) {
  355. index = i;
  356. break;
  357. }
  358. if (!priv->stations[i].used &&
  359. index == IWL_INVALID_STATION)
  360. index = i;
  361. }
  362. /* These two conditions has the same outcome but keep them separate
  363. since they have different meaning */
  364. if (unlikely(index == IWL_INVALID_STATION)) {
  365. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  366. return index;
  367. }
  368. if (priv->stations[index].used &&
  369. !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
  370. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  371. return index;
  372. }
  373. IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr);
  374. station = &priv->stations[index];
  375. station->used = 1;
  376. priv->num_stations++;
  377. /* Set up the REPLY_ADD_STA command to send to device */
  378. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  379. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  380. station->sta.mode = 0;
  381. station->sta.sta.sta_id = index;
  382. station->sta.station_flags = 0;
  383. if (priv->band == IEEE80211_BAND_5GHZ)
  384. rate = IWL_RATE_6M_PLCP;
  385. else
  386. rate = IWL_RATE_1M_PLCP;
  387. /* Turn on both antennas for the station... */
  388. station->sta.rate_n_flags =
  389. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  390. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  391. /* Add station to device's station table */
  392. iwl3945_send_add_station(priv, &station->sta, flags);
  393. return index;
  394. }
  395. /*************** DRIVER STATUS FUNCTIONS *****/
  396. static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
  397. {
  398. /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
  399. * set but EXIT_PENDING is not */
  400. return test_bit(STATUS_READY, &priv->status) &&
  401. test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
  402. !test_bit(STATUS_EXIT_PENDING, &priv->status);
  403. }
  404. static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
  405. {
  406. return test_bit(STATUS_ALIVE, &priv->status);
  407. }
  408. static inline int iwl3945_is_init(struct iwl3945_priv *priv)
  409. {
  410. return test_bit(STATUS_INIT, &priv->status);
  411. }
  412. static inline int iwl3945_is_rfkill_sw(struct iwl3945_priv *priv)
  413. {
  414. return test_bit(STATUS_RF_KILL_SW, &priv->status);
  415. }
  416. static inline int iwl3945_is_rfkill_hw(struct iwl3945_priv *priv)
  417. {
  418. return test_bit(STATUS_RF_KILL_HW, &priv->status);
  419. }
  420. static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
  421. {
  422. return iwl3945_is_rfkill_hw(priv) ||
  423. iwl3945_is_rfkill_sw(priv);
  424. }
  425. static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
  426. {
  427. if (iwl3945_is_rfkill(priv))
  428. return 0;
  429. return iwl3945_is_ready(priv);
  430. }
  431. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  432. #define IWL_CMD(x) case x: return #x
  433. static const char *get_cmd_string(u8 cmd)
  434. {
  435. switch (cmd) {
  436. IWL_CMD(REPLY_ALIVE);
  437. IWL_CMD(REPLY_ERROR);
  438. IWL_CMD(REPLY_RXON);
  439. IWL_CMD(REPLY_RXON_ASSOC);
  440. IWL_CMD(REPLY_QOS_PARAM);
  441. IWL_CMD(REPLY_RXON_TIMING);
  442. IWL_CMD(REPLY_ADD_STA);
  443. IWL_CMD(REPLY_REMOVE_STA);
  444. IWL_CMD(REPLY_REMOVE_ALL_STA);
  445. IWL_CMD(REPLY_3945_RX);
  446. IWL_CMD(REPLY_TX);
  447. IWL_CMD(REPLY_RATE_SCALE);
  448. IWL_CMD(REPLY_LEDS_CMD);
  449. IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
  450. IWL_CMD(RADAR_NOTIFICATION);
  451. IWL_CMD(REPLY_QUIET_CMD);
  452. IWL_CMD(REPLY_CHANNEL_SWITCH);
  453. IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
  454. IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
  455. IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
  456. IWL_CMD(POWER_TABLE_CMD);
  457. IWL_CMD(PM_SLEEP_NOTIFICATION);
  458. IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
  459. IWL_CMD(REPLY_SCAN_CMD);
  460. IWL_CMD(REPLY_SCAN_ABORT_CMD);
  461. IWL_CMD(SCAN_START_NOTIFICATION);
  462. IWL_CMD(SCAN_RESULTS_NOTIFICATION);
  463. IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
  464. IWL_CMD(BEACON_NOTIFICATION);
  465. IWL_CMD(REPLY_TX_BEACON);
  466. IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
  467. IWL_CMD(QUIET_NOTIFICATION);
  468. IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
  469. IWL_CMD(MEASURE_ABORT_NOTIFICATION);
  470. IWL_CMD(REPLY_BT_CONFIG);
  471. IWL_CMD(REPLY_STATISTICS_CMD);
  472. IWL_CMD(STATISTICS_NOTIFICATION);
  473. IWL_CMD(REPLY_CARD_STATE_CMD);
  474. IWL_CMD(CARD_STATE_NOTIFICATION);
  475. IWL_CMD(MISSED_BEACONS_NOTIFICATION);
  476. default:
  477. return "UNKNOWN";
  478. }
  479. }
  480. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  481. /**
  482. * iwl3945_enqueue_hcmd - enqueue a uCode command
  483. * @priv: device private data point
  484. * @cmd: a point to the ucode command structure
  485. *
  486. * The function returns < 0 values to indicate the operation is
  487. * failed. On success, it turns the index (> 0) of command in the
  488. * command queue.
  489. */
  490. static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  491. {
  492. struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
  493. struct iwl3945_queue *q = &txq->q;
  494. struct iwl3945_tfd_frame *tfd;
  495. u32 *control_flags;
  496. struct iwl3945_cmd *out_cmd;
  497. u32 idx;
  498. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  499. dma_addr_t phys_addr;
  500. int pad;
  501. u16 count;
  502. int ret;
  503. unsigned long flags;
  504. /* If any of the command structures end up being larger than
  505. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  506. * we will need to increase the size of the TFD entries */
  507. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  508. !(cmd->meta.flags & CMD_SIZE_HUGE));
  509. if (iwl3945_is_rfkill(priv)) {
  510. IWL_DEBUG_INFO("Not sending command - RF KILL");
  511. return -EIO;
  512. }
  513. if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  514. IWL_ERROR("No space for Tx\n");
  515. return -ENOSPC;
  516. }
  517. spin_lock_irqsave(&priv->hcmd_lock, flags);
  518. tfd = &txq->bd[q->write_ptr];
  519. memset(tfd, 0, sizeof(*tfd));
  520. control_flags = (u32 *) tfd;
  521. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  522. out_cmd = &txq->cmd[idx];
  523. out_cmd->hdr.cmd = cmd->id;
  524. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  525. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  526. /* At this point, the out_cmd now has all of the incoming cmd
  527. * information */
  528. out_cmd->hdr.flags = 0;
  529. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  530. INDEX_TO_SEQ(q->write_ptr));
  531. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  532. out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
  533. phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
  534. offsetof(struct iwl3945_cmd, hdr);
  535. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  536. pad = U32_PAD(cmd->len);
  537. count = TFD_CTL_COUNT_GET(*control_flags);
  538. *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
  539. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  540. "%d bytes at %d[%d]:%d\n",
  541. get_cmd_string(out_cmd->hdr.cmd),
  542. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  543. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  544. txq->need_update = 1;
  545. /* Increment and update queue's write index */
  546. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  547. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  548. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  549. return ret ? ret : idx;
  550. }
  551. static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  552. {
  553. int ret;
  554. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  555. /* An asynchronous command can not expect an SKB to be set. */
  556. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  557. /* An asynchronous command MUST have a callback. */
  558. BUG_ON(!cmd->meta.u.callback);
  559. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  560. return -EBUSY;
  561. ret = iwl3945_enqueue_hcmd(priv, cmd);
  562. if (ret < 0) {
  563. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  564. get_cmd_string(cmd->id), ret);
  565. return ret;
  566. }
  567. return 0;
  568. }
  569. static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  570. {
  571. int cmd_idx;
  572. int ret;
  573. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  574. /* A synchronous command can not have a callback set. */
  575. BUG_ON(cmd->meta.u.callback != NULL);
  576. if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
  577. IWL_ERROR("Error sending %s: Already sending a host command\n",
  578. get_cmd_string(cmd->id));
  579. ret = -EBUSY;
  580. goto out;
  581. }
  582. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  583. if (cmd->meta.flags & CMD_WANT_SKB)
  584. cmd->meta.source = &cmd->meta;
  585. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  586. if (cmd_idx < 0) {
  587. ret = cmd_idx;
  588. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  589. get_cmd_string(cmd->id), ret);
  590. goto out;
  591. }
  592. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  593. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  594. HOST_COMPLETE_TIMEOUT);
  595. if (!ret) {
  596. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  597. IWL_ERROR("Error sending %s: time out after %dms.\n",
  598. get_cmd_string(cmd->id),
  599. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  600. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  601. ret = -ETIMEDOUT;
  602. goto cancel;
  603. }
  604. }
  605. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  606. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  607. get_cmd_string(cmd->id));
  608. ret = -ECANCELED;
  609. goto fail;
  610. }
  611. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  612. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  613. get_cmd_string(cmd->id));
  614. ret = -EIO;
  615. goto fail;
  616. }
  617. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  618. IWL_ERROR("Error: Response NULL in '%s'\n",
  619. get_cmd_string(cmd->id));
  620. ret = -EIO;
  621. goto cancel;
  622. }
  623. ret = 0;
  624. goto out;
  625. cancel:
  626. if (cmd->meta.flags & CMD_WANT_SKB) {
  627. struct iwl3945_cmd *qcmd;
  628. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  629. * TX cmd queue. Otherwise in case the cmd comes
  630. * in later, it will possibly set an invalid
  631. * address (cmd->meta.source). */
  632. qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  633. qcmd->meta.flags &= ~CMD_WANT_SKB;
  634. }
  635. fail:
  636. if (cmd->meta.u.skb) {
  637. dev_kfree_skb_any(cmd->meta.u.skb);
  638. cmd->meta.u.skb = NULL;
  639. }
  640. out:
  641. clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
  642. return ret;
  643. }
  644. int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  645. {
  646. if (cmd->meta.flags & CMD_ASYNC)
  647. return iwl3945_send_cmd_async(priv, cmd);
  648. return iwl3945_send_cmd_sync(priv, cmd);
  649. }
  650. int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
  651. {
  652. struct iwl3945_host_cmd cmd = {
  653. .id = id,
  654. .len = len,
  655. .data = data,
  656. };
  657. return iwl3945_send_cmd_sync(priv, &cmd);
  658. }
  659. static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
  660. {
  661. struct iwl3945_host_cmd cmd = {
  662. .id = id,
  663. .len = sizeof(val),
  664. .data = &val,
  665. };
  666. return iwl3945_send_cmd_sync(priv, &cmd);
  667. }
  668. int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
  669. {
  670. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  671. }
  672. /**
  673. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  674. * @band: 2.4 or 5 GHz band
  675. * @channel: Any channel valid for the requested band
  676. * In addition to setting the staging RXON, priv->band is also set.
  677. *
  678. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  679. * in the staging RXON flag structure based on the band
  680. */
  681. static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
  682. enum ieee80211_band band,
  683. u16 channel)
  684. {
  685. if (!iwl3945_get_channel_info(priv, band, channel)) {
  686. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  687. channel, band);
  688. return -EINVAL;
  689. }
  690. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  691. (priv->band == band))
  692. return 0;
  693. priv->staging_rxon.channel = cpu_to_le16(channel);
  694. if (band == IEEE80211_BAND_5GHZ)
  695. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  696. else
  697. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  698. priv->band = band;
  699. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
  700. return 0;
  701. }
  702. /**
  703. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  704. *
  705. * NOTE: This is really only useful during development and can eventually
  706. * be #ifdef'd out once the driver is stable and folks aren't actively
  707. * making changes
  708. */
  709. static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
  710. {
  711. int error = 0;
  712. int counter = 1;
  713. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  714. error |= le32_to_cpu(rxon->flags &
  715. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  716. RXON_FLG_RADAR_DETECT_MSK));
  717. if (error)
  718. IWL_WARNING("check 24G fields %d | %d\n",
  719. counter++, error);
  720. } else {
  721. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  722. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  723. if (error)
  724. IWL_WARNING("check 52 fields %d | %d\n",
  725. counter++, error);
  726. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  727. if (error)
  728. IWL_WARNING("check 52 CCK %d | %d\n",
  729. counter++, error);
  730. }
  731. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  732. if (error)
  733. IWL_WARNING("check mac addr %d | %d\n", counter++, error);
  734. /* make sure basic rates 6Mbps and 1Mbps are supported */
  735. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  736. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  737. if (error)
  738. IWL_WARNING("check basic rate %d | %d\n", counter++, error);
  739. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  740. if (error)
  741. IWL_WARNING("check assoc id %d | %d\n", counter++, error);
  742. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  743. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  744. if (error)
  745. IWL_WARNING("check CCK and short slot %d | %d\n",
  746. counter++, error);
  747. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  748. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  749. if (error)
  750. IWL_WARNING("check CCK & auto detect %d | %d\n",
  751. counter++, error);
  752. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  753. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  754. if (error)
  755. IWL_WARNING("check TGG and auto detect %d | %d\n",
  756. counter++, error);
  757. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  758. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  759. RXON_FLG_ANT_A_MSK)) == 0);
  760. if (error)
  761. IWL_WARNING("check antenna %d %d\n", counter++, error);
  762. if (error)
  763. IWL_WARNING("Tuning to channel %d\n",
  764. le16_to_cpu(rxon->channel));
  765. if (error) {
  766. IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
  767. return -1;
  768. }
  769. return 0;
  770. }
  771. /**
  772. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  773. * @priv: staging_rxon is compared to active_rxon
  774. *
  775. * If the RXON structure is changing enough to require a new tune,
  776. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  777. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  778. */
  779. static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
  780. {
  781. /* These items are only settable from the full RXON command */
  782. if (!(iwl3945_is_associated(priv)) ||
  783. compare_ether_addr(priv->staging_rxon.bssid_addr,
  784. priv->active_rxon.bssid_addr) ||
  785. compare_ether_addr(priv->staging_rxon.node_addr,
  786. priv->active_rxon.node_addr) ||
  787. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  788. priv->active_rxon.wlap_bssid_addr) ||
  789. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  790. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  791. (priv->staging_rxon.air_propagation !=
  792. priv->active_rxon.air_propagation) ||
  793. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  794. return 1;
  795. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  796. * be updated with the RXON_ASSOC command -- however only some
  797. * flag transitions are allowed using RXON_ASSOC */
  798. /* Check if we are not switching bands */
  799. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  800. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  801. return 1;
  802. /* Check if we are switching association toggle */
  803. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  804. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  805. return 1;
  806. return 0;
  807. }
  808. static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
  809. {
  810. int rc = 0;
  811. struct iwl3945_rx_packet *res = NULL;
  812. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  813. struct iwl3945_host_cmd cmd = {
  814. .id = REPLY_RXON_ASSOC,
  815. .len = sizeof(rxon_assoc),
  816. .meta.flags = CMD_WANT_SKB,
  817. .data = &rxon_assoc,
  818. };
  819. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
  820. const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
  821. if ((rxon1->flags == rxon2->flags) &&
  822. (rxon1->filter_flags == rxon2->filter_flags) &&
  823. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  824. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  825. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  826. return 0;
  827. }
  828. rxon_assoc.flags = priv->staging_rxon.flags;
  829. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  830. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  831. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  832. rxon_assoc.reserved = 0;
  833. rc = iwl3945_send_cmd_sync(priv, &cmd);
  834. if (rc)
  835. return rc;
  836. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  837. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  838. IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
  839. rc = -EIO;
  840. }
  841. priv->alloc_rxb_skb--;
  842. dev_kfree_skb_any(cmd.meta.u.skb);
  843. return rc;
  844. }
  845. /**
  846. * iwl3945_commit_rxon - commit staging_rxon to hardware
  847. *
  848. * The RXON command in staging_rxon is committed to the hardware and
  849. * the active_rxon structure is updated with the new data. This
  850. * function correctly transitions out of the RXON_ASSOC_MSK state if
  851. * a HW tune is required based on the RXON structure changes.
  852. */
  853. static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
  854. {
  855. /* cast away the const for active_rxon in this function */
  856. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  857. int rc = 0;
  858. if (!iwl3945_is_alive(priv))
  859. return -1;
  860. /* always get timestamp with Rx frame */
  861. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  862. /* select antenna */
  863. priv->staging_rxon.flags &=
  864. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  865. priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
  866. rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
  867. if (rc) {
  868. IWL_ERROR("Invalid RXON configuration. Not committing.\n");
  869. return -EINVAL;
  870. }
  871. /* If we don't need to send a full RXON, we can use
  872. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  873. * and other flags for the current radio configuration. */
  874. if (!iwl3945_full_rxon_required(priv)) {
  875. rc = iwl3945_send_rxon_assoc(priv);
  876. if (rc) {
  877. IWL_ERROR("Error setting RXON_ASSOC "
  878. "configuration (%d).\n", rc);
  879. return rc;
  880. }
  881. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  882. return 0;
  883. }
  884. /* If we are currently associated and the new config requires
  885. * an RXON_ASSOC and the new config wants the associated mask enabled,
  886. * we must clear the associated from the active configuration
  887. * before we apply the new config */
  888. if (iwl3945_is_associated(priv) &&
  889. (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  890. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  891. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  892. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  893. sizeof(struct iwl3945_rxon_cmd),
  894. &priv->active_rxon);
  895. /* If the mask clearing failed then we set
  896. * active_rxon back to what it was previously */
  897. if (rc) {
  898. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  899. IWL_ERROR("Error clearing ASSOC_MSK on current "
  900. "configuration (%d).\n", rc);
  901. return rc;
  902. }
  903. }
  904. IWL_DEBUG_INFO("Sending RXON\n"
  905. "* with%s RXON_FILTER_ASSOC_MSK\n"
  906. "* channel = %d\n"
  907. "* bssid = %pM\n",
  908. ((priv->staging_rxon.filter_flags &
  909. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  910. le16_to_cpu(priv->staging_rxon.channel),
  911. priv->staging_rxon.bssid_addr);
  912. /* Apply the new configuration */
  913. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  914. sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
  915. if (rc) {
  916. IWL_ERROR("Error setting new configuration (%d).\n", rc);
  917. return rc;
  918. }
  919. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  920. iwl3945_clear_stations_table(priv);
  921. /* If we issue a new RXON command which required a tune then we must
  922. * send a new TXPOWER command or we won't be able to Tx any frames */
  923. rc = iwl3945_hw_reg_send_txpower(priv);
  924. if (rc) {
  925. IWL_ERROR("Error setting Tx power (%d).\n", rc);
  926. return rc;
  927. }
  928. /* Add the broadcast address so we can send broadcast frames */
  929. if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
  930. IWL_INVALID_STATION) {
  931. IWL_ERROR("Error adding BROADCAST address for transmit.\n");
  932. return -EIO;
  933. }
  934. /* If we have set the ASSOC_MSK and we are in BSS mode then
  935. * add the IWL_AP_ID to the station rate table */
  936. if (iwl3945_is_associated(priv) &&
  937. (priv->iw_mode == NL80211_IFTYPE_STATION))
  938. if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
  939. == IWL_INVALID_STATION) {
  940. IWL_ERROR("Error adding AP address for transmit.\n");
  941. return -EIO;
  942. }
  943. /* Init the hardware's rate fallback order based on the band */
  944. rc = iwl3945_init_hw_rate_table(priv);
  945. if (rc) {
  946. IWL_ERROR("Error setting HW rate table: %02X\n", rc);
  947. return -EIO;
  948. }
  949. return 0;
  950. }
  951. static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
  952. {
  953. struct iwl_bt_cmd bt_cmd = {
  954. .flags = 3,
  955. .lead_time = 0xAA,
  956. .max_kill = 1,
  957. .kill_ack_mask = 0,
  958. .kill_cts_mask = 0,
  959. };
  960. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  961. sizeof(bt_cmd), &bt_cmd);
  962. }
  963. static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
  964. {
  965. int rc = 0;
  966. struct iwl3945_rx_packet *res;
  967. struct iwl3945_host_cmd cmd = {
  968. .id = REPLY_SCAN_ABORT_CMD,
  969. .meta.flags = CMD_WANT_SKB,
  970. };
  971. /* If there isn't a scan actively going on in the hardware
  972. * then we are in between scan bands and not actually
  973. * actively scanning, so don't send the abort command */
  974. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  975. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  976. return 0;
  977. }
  978. rc = iwl3945_send_cmd_sync(priv, &cmd);
  979. if (rc) {
  980. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  981. return rc;
  982. }
  983. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  984. if (res->u.status != CAN_ABORT_STATUS) {
  985. /* The scan abort will return 1 for success or
  986. * 2 for "failure". A failure condition can be
  987. * due to simply not being in an active scan which
  988. * can occur if we send the scan abort before we
  989. * the microcode has notified us that a scan is
  990. * completed. */
  991. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  992. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  993. clear_bit(STATUS_SCAN_HW, &priv->status);
  994. }
  995. dev_kfree_skb_any(cmd.meta.u.skb);
  996. return rc;
  997. }
  998. static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
  999. struct iwl3945_cmd *cmd,
  1000. struct sk_buff *skb)
  1001. {
  1002. return 1;
  1003. }
  1004. /*
  1005. * CARD_STATE_CMD
  1006. *
  1007. * Use: Sets the device's internal card state to enable, disable, or halt
  1008. *
  1009. * When in the 'enable' state the card operates as normal.
  1010. * When in the 'disable' state, the card enters into a low power mode.
  1011. * When in the 'halt' state, the card is shut down and must be fully
  1012. * restarted to come back on.
  1013. */
  1014. static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
  1015. {
  1016. struct iwl3945_host_cmd cmd = {
  1017. .id = REPLY_CARD_STATE_CMD,
  1018. .len = sizeof(u32),
  1019. .data = &flags,
  1020. .meta.flags = meta_flag,
  1021. };
  1022. if (meta_flag & CMD_ASYNC)
  1023. cmd.meta.u.callback = iwl3945_card_state_sync_callback;
  1024. return iwl3945_send_cmd(priv, &cmd);
  1025. }
  1026. static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
  1027. struct iwl3945_cmd *cmd, struct sk_buff *skb)
  1028. {
  1029. struct iwl3945_rx_packet *res = NULL;
  1030. if (!skb) {
  1031. IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
  1032. return 1;
  1033. }
  1034. res = (struct iwl3945_rx_packet *)skb->data;
  1035. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1036. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1037. res->hdr.flags);
  1038. return 1;
  1039. }
  1040. switch (res->u.add_sta.status) {
  1041. case ADD_STA_SUCCESS_MSK:
  1042. break;
  1043. default:
  1044. break;
  1045. }
  1046. /* We didn't cache the SKB; let the caller free it */
  1047. return 1;
  1048. }
  1049. int iwl3945_send_add_station(struct iwl3945_priv *priv,
  1050. struct iwl3945_addsta_cmd *sta, u8 flags)
  1051. {
  1052. struct iwl3945_rx_packet *res = NULL;
  1053. int rc = 0;
  1054. struct iwl3945_host_cmd cmd = {
  1055. .id = REPLY_ADD_STA,
  1056. .len = sizeof(struct iwl3945_addsta_cmd),
  1057. .meta.flags = flags,
  1058. .data = sta,
  1059. };
  1060. if (flags & CMD_ASYNC)
  1061. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  1062. else
  1063. cmd.meta.flags |= CMD_WANT_SKB;
  1064. rc = iwl3945_send_cmd(priv, &cmd);
  1065. if (rc || (flags & CMD_ASYNC))
  1066. return rc;
  1067. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1068. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1069. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1070. res->hdr.flags);
  1071. rc = -EIO;
  1072. }
  1073. if (rc == 0) {
  1074. switch (res->u.add_sta.status) {
  1075. case ADD_STA_SUCCESS_MSK:
  1076. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  1077. break;
  1078. default:
  1079. rc = -EIO;
  1080. IWL_WARNING("REPLY_ADD_STA failed\n");
  1081. break;
  1082. }
  1083. }
  1084. priv->alloc_rxb_skb--;
  1085. dev_kfree_skb_any(cmd.meta.u.skb);
  1086. return rc;
  1087. }
  1088. static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
  1089. struct ieee80211_key_conf *keyconf,
  1090. u8 sta_id)
  1091. {
  1092. unsigned long flags;
  1093. __le16 key_flags = 0;
  1094. switch (keyconf->alg) {
  1095. case ALG_CCMP:
  1096. key_flags |= STA_KEY_FLG_CCMP;
  1097. key_flags |= cpu_to_le16(
  1098. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  1099. key_flags &= ~STA_KEY_FLG_INVALID;
  1100. break;
  1101. case ALG_TKIP:
  1102. case ALG_WEP:
  1103. default:
  1104. return -EINVAL;
  1105. }
  1106. spin_lock_irqsave(&priv->sta_lock, flags);
  1107. priv->stations[sta_id].keyinfo.alg = keyconf->alg;
  1108. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  1109. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  1110. keyconf->keylen);
  1111. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  1112. keyconf->keylen);
  1113. priv->stations[sta_id].sta.key.key_flags = key_flags;
  1114. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1115. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1116. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1117. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  1118. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1119. return 0;
  1120. }
  1121. static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
  1122. {
  1123. unsigned long flags;
  1124. spin_lock_irqsave(&priv->sta_lock, flags);
  1125. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  1126. memset(&priv->stations[sta_id].sta.key, 0,
  1127. sizeof(struct iwl4965_keyinfo));
  1128. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1129. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1130. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1131. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1132. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1133. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1134. return 0;
  1135. }
  1136. static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
  1137. {
  1138. struct list_head *element;
  1139. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1140. priv->frames_count);
  1141. while (!list_empty(&priv->free_frames)) {
  1142. element = priv->free_frames.next;
  1143. list_del(element);
  1144. kfree(list_entry(element, struct iwl3945_frame, list));
  1145. priv->frames_count--;
  1146. }
  1147. if (priv->frames_count) {
  1148. IWL_WARNING("%d frames still in use. Did we lose one?\n",
  1149. priv->frames_count);
  1150. priv->frames_count = 0;
  1151. }
  1152. }
  1153. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
  1154. {
  1155. struct iwl3945_frame *frame;
  1156. struct list_head *element;
  1157. if (list_empty(&priv->free_frames)) {
  1158. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1159. if (!frame) {
  1160. IWL_ERROR("Could not allocate frame!\n");
  1161. return NULL;
  1162. }
  1163. priv->frames_count++;
  1164. return frame;
  1165. }
  1166. element = priv->free_frames.next;
  1167. list_del(element);
  1168. return list_entry(element, struct iwl3945_frame, list);
  1169. }
  1170. static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
  1171. {
  1172. memset(frame, 0, sizeof(*frame));
  1173. list_add(&frame->list, &priv->free_frames);
  1174. }
  1175. unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
  1176. struct ieee80211_hdr *hdr,
  1177. int left)
  1178. {
  1179. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1180. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  1181. (priv->iw_mode != NL80211_IFTYPE_AP)))
  1182. return 0;
  1183. if (priv->ibss_beacon->len > left)
  1184. return 0;
  1185. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1186. return priv->ibss_beacon->len;
  1187. }
  1188. static u8 iwl3945_rate_get_lowest_plcp(struct iwl3945_priv *priv)
  1189. {
  1190. u8 i;
  1191. int rate_mask;
  1192. /* Set rate mask*/
  1193. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  1194. rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
  1195. else
  1196. rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
  1197. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1198. i = iwl3945_rates[i].next_ieee) {
  1199. if (rate_mask & (1 << i))
  1200. return iwl3945_rates[i].plcp;
  1201. }
  1202. /* No valid rate was found. Assign the lowest one */
  1203. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  1204. return IWL_RATE_1M_PLCP;
  1205. else
  1206. return IWL_RATE_6M_PLCP;
  1207. }
  1208. static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
  1209. {
  1210. struct iwl3945_frame *frame;
  1211. unsigned int frame_size;
  1212. int rc;
  1213. u8 rate;
  1214. frame = iwl3945_get_free_frame(priv);
  1215. if (!frame) {
  1216. IWL_ERROR("Could not obtain free frame buffer for beacon "
  1217. "command.\n");
  1218. return -ENOMEM;
  1219. }
  1220. rate = iwl3945_rate_get_lowest_plcp(priv);
  1221. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1222. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1223. &frame->u.cmd[0]);
  1224. iwl3945_free_frame(priv, frame);
  1225. return rc;
  1226. }
  1227. /******************************************************************************
  1228. *
  1229. * EEPROM related functions
  1230. *
  1231. ******************************************************************************/
  1232. static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
  1233. {
  1234. memcpy(mac, priv->eeprom.mac_address, 6);
  1235. }
  1236. /*
  1237. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  1238. * embedded controller) as EEPROM reader; each read is a series of pulses
  1239. * to/from the EEPROM chip, not a single event, so even reads could conflict
  1240. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  1241. * simply claims ownership, which should be safe when this function is called
  1242. * (i.e. before loading uCode!).
  1243. */
  1244. static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
  1245. {
  1246. _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  1247. return 0;
  1248. }
  1249. /**
  1250. * iwl3945_eeprom_init - read EEPROM contents
  1251. *
  1252. * Load the EEPROM contents from adapter into priv->eeprom
  1253. *
  1254. * NOTE: This routine uses the non-debug IO access functions.
  1255. */
  1256. int iwl3945_eeprom_init(struct iwl3945_priv *priv)
  1257. {
  1258. u16 *e = (u16 *)&priv->eeprom;
  1259. u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
  1260. int sz = sizeof(priv->eeprom);
  1261. int ret;
  1262. u16 addr;
  1263. /* The EEPROM structure has several padding buffers within it
  1264. * and when adding new EEPROM maps is subject to programmer errors
  1265. * which may be very difficult to identify without explicitly
  1266. * checking the resulting size of the eeprom map. */
  1267. BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
  1268. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1269. IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
  1270. return -ENOENT;
  1271. }
  1272. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1273. ret = iwl3945_eeprom_acquire_semaphore(priv);
  1274. if (ret < 0) {
  1275. IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
  1276. return -ENOENT;
  1277. }
  1278. /* eeprom is an array of 16bit values */
  1279. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1280. u32 r;
  1281. _iwl3945_write32(priv, CSR_EEPROM_REG,
  1282. CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
  1283. _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1284. ret = iwl3945_poll_direct_bit(priv, CSR_EEPROM_REG,
  1285. CSR_EEPROM_REG_READ_VALID_MSK,
  1286. IWL_EEPROM_ACCESS_TIMEOUT);
  1287. if (ret < 0) {
  1288. IWL_ERROR("Time out reading EEPROM[%d]\n", addr);
  1289. return ret;
  1290. }
  1291. r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
  1292. e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
  1293. }
  1294. return 0;
  1295. }
  1296. static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
  1297. {
  1298. if (priv->hw_setting.shared_virt)
  1299. pci_free_consistent(priv->pci_dev,
  1300. sizeof(struct iwl3945_shared),
  1301. priv->hw_setting.shared_virt,
  1302. priv->hw_setting.shared_phys);
  1303. }
  1304. /**
  1305. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1306. *
  1307. * return : set the bit for each supported rate insert in ie
  1308. */
  1309. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1310. u16 basic_rate, int *left)
  1311. {
  1312. u16 ret_rates = 0, bit;
  1313. int i;
  1314. u8 *cnt = ie;
  1315. u8 *rates = ie + 1;
  1316. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1317. if (bit & supported_rate) {
  1318. ret_rates |= bit;
  1319. rates[*cnt] = iwl3945_rates[i].ieee |
  1320. ((bit & basic_rate) ? 0x80 : 0x00);
  1321. (*cnt)++;
  1322. (*left)--;
  1323. if ((*left <= 0) ||
  1324. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1325. break;
  1326. }
  1327. }
  1328. return ret_rates;
  1329. }
  1330. /**
  1331. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1332. */
  1333. static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
  1334. struct ieee80211_mgmt *frame,
  1335. int left)
  1336. {
  1337. int len = 0;
  1338. u8 *pos = NULL;
  1339. u16 active_rates, ret_rates, cck_rates;
  1340. /* Make sure there is enough space for the probe request,
  1341. * two mandatory IEs and the data */
  1342. left -= 24;
  1343. if (left < 0)
  1344. return 0;
  1345. len += 24;
  1346. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1347. memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
  1348. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1349. memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
  1350. frame->seq_ctrl = 0;
  1351. /* fill in our indirect SSID IE */
  1352. /* ...next IE... */
  1353. left -= 2;
  1354. if (left < 0)
  1355. return 0;
  1356. len += 2;
  1357. pos = &(frame->u.probe_req.variable[0]);
  1358. *pos++ = WLAN_EID_SSID;
  1359. *pos++ = 0;
  1360. /* fill in supported rate */
  1361. /* ...next IE... */
  1362. left -= 2;
  1363. if (left < 0)
  1364. return 0;
  1365. /* ... fill it in... */
  1366. *pos++ = WLAN_EID_SUPP_RATES;
  1367. *pos = 0;
  1368. priv->active_rate = priv->rates_mask;
  1369. active_rates = priv->active_rate;
  1370. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1371. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1372. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1373. priv->active_rate_basic, &left);
  1374. active_rates &= ~ret_rates;
  1375. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1376. priv->active_rate_basic, &left);
  1377. active_rates &= ~ret_rates;
  1378. len += 2 + *pos;
  1379. pos += (*pos) + 1;
  1380. if (active_rates == 0)
  1381. goto fill_end;
  1382. /* fill in supported extended rate */
  1383. /* ...next IE... */
  1384. left -= 2;
  1385. if (left < 0)
  1386. return 0;
  1387. /* ... fill it in... */
  1388. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1389. *pos = 0;
  1390. iwl3945_supported_rate_to_ie(pos, active_rates,
  1391. priv->active_rate_basic, &left);
  1392. if (*pos > 0)
  1393. len += 2 + *pos;
  1394. fill_end:
  1395. return (u16)len;
  1396. }
  1397. /*
  1398. * QoS support
  1399. */
  1400. static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
  1401. struct iwl_qosparam_cmd *qos)
  1402. {
  1403. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1404. sizeof(struct iwl_qosparam_cmd), qos);
  1405. }
  1406. static void iwl3945_reset_qos(struct iwl3945_priv *priv)
  1407. {
  1408. u16 cw_min = 15;
  1409. u16 cw_max = 1023;
  1410. u8 aifs = 2;
  1411. u8 is_legacy = 0;
  1412. unsigned long flags;
  1413. int i;
  1414. spin_lock_irqsave(&priv->lock, flags);
  1415. priv->qos_data.qos_active = 0;
  1416. /* QoS always active in AP and ADHOC mode
  1417. * In STA mode wait for association
  1418. */
  1419. if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
  1420. priv->iw_mode == NL80211_IFTYPE_AP)
  1421. priv->qos_data.qos_active = 1;
  1422. else
  1423. priv->qos_data.qos_active = 0;
  1424. /* check for legacy mode */
  1425. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  1426. (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
  1427. (priv->iw_mode == NL80211_IFTYPE_STATION &&
  1428. (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
  1429. cw_min = 31;
  1430. is_legacy = 1;
  1431. }
  1432. if (priv->qos_data.qos_active)
  1433. aifs = 3;
  1434. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  1435. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  1436. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  1437. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  1438. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  1439. if (priv->qos_data.qos_active) {
  1440. i = 1;
  1441. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  1442. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  1443. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  1444. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1445. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1446. i = 2;
  1447. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1448. cpu_to_le16((cw_min + 1) / 2 - 1);
  1449. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1450. cpu_to_le16(cw_max);
  1451. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1452. if (is_legacy)
  1453. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1454. cpu_to_le16(6016);
  1455. else
  1456. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1457. cpu_to_le16(3008);
  1458. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1459. i = 3;
  1460. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1461. cpu_to_le16((cw_min + 1) / 4 - 1);
  1462. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1463. cpu_to_le16((cw_max + 1) / 2 - 1);
  1464. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1465. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1466. if (is_legacy)
  1467. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1468. cpu_to_le16(3264);
  1469. else
  1470. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1471. cpu_to_le16(1504);
  1472. } else {
  1473. for (i = 1; i < 4; i++) {
  1474. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1475. cpu_to_le16(cw_min);
  1476. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1477. cpu_to_le16(cw_max);
  1478. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  1479. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1480. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1481. }
  1482. }
  1483. IWL_DEBUG_QOS("set QoS to default \n");
  1484. spin_unlock_irqrestore(&priv->lock, flags);
  1485. }
  1486. static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
  1487. {
  1488. unsigned long flags;
  1489. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1490. return;
  1491. spin_lock_irqsave(&priv->lock, flags);
  1492. priv->qos_data.def_qos_parm.qos_flags = 0;
  1493. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1494. !priv->qos_data.qos_cap.q_AP.txop_request)
  1495. priv->qos_data.def_qos_parm.qos_flags |=
  1496. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1497. if (priv->qos_data.qos_active)
  1498. priv->qos_data.def_qos_parm.qos_flags |=
  1499. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1500. spin_unlock_irqrestore(&priv->lock, flags);
  1501. if (force || iwl3945_is_associated(priv)) {
  1502. IWL_DEBUG_QOS("send QoS cmd with QoS active %d \n",
  1503. priv->qos_data.qos_active);
  1504. iwl3945_send_qos_params_command(priv,
  1505. &(priv->qos_data.def_qos_parm));
  1506. }
  1507. }
  1508. /*
  1509. * Power management (not Tx power!) functions
  1510. */
  1511. #define MSEC_TO_USEC 1024
  1512. #define NOSLP __constant_cpu_to_le16(0), 0, 0
  1513. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
  1514. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1515. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1516. __constant_cpu_to_le32(X1), \
  1517. __constant_cpu_to_le32(X2), \
  1518. __constant_cpu_to_le32(X3), \
  1519. __constant_cpu_to_le32(X4)}
  1520. /* default power management (not Tx power) table values */
  1521. /* for TIM 0-10 */
  1522. static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
  1523. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1524. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1525. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1526. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1527. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1528. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1529. };
  1530. /* for TIM > 10 */
  1531. static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
  1532. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1533. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1534. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1535. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1536. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1537. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1538. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1539. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1540. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1541. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1542. };
  1543. int iwl3945_power_init_handle(struct iwl3945_priv *priv)
  1544. {
  1545. int rc = 0, i;
  1546. struct iwl3945_power_mgr *pow_data;
  1547. int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
  1548. u16 pci_pm;
  1549. IWL_DEBUG_POWER("Initialize power \n");
  1550. pow_data = &(priv->power_data);
  1551. memset(pow_data, 0, sizeof(*pow_data));
  1552. pow_data->active_index = IWL_POWER_RANGE_0;
  1553. pow_data->dtim_val = 0xffff;
  1554. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1555. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1556. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1557. if (rc != 0)
  1558. return 0;
  1559. else {
  1560. struct iwl_powertable_cmd *cmd;
  1561. IWL_DEBUG_POWER("adjust power command flags\n");
  1562. for (i = 0; i < IWL_POWER_AC; i++) {
  1563. cmd = &pow_data->pwr_range_0[i].cmd;
  1564. if (pci_pm & 0x1)
  1565. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1566. else
  1567. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1568. }
  1569. }
  1570. return rc;
  1571. }
  1572. static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
  1573. struct iwl_powertable_cmd *cmd, u32 mode)
  1574. {
  1575. int rc = 0, i;
  1576. u8 skip;
  1577. u32 max_sleep = 0;
  1578. struct iwl3945_power_vec_entry *range;
  1579. u8 period = 0;
  1580. struct iwl3945_power_mgr *pow_data;
  1581. if (mode > IWL_POWER_INDEX_5) {
  1582. IWL_DEBUG_POWER("Error invalid power mode \n");
  1583. return -1;
  1584. }
  1585. pow_data = &(priv->power_data);
  1586. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1587. range = &pow_data->pwr_range_0[0];
  1588. else
  1589. range = &pow_data->pwr_range_1[1];
  1590. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1591. #ifdef IWL_MAC80211_DISABLE
  1592. if (priv->assoc_network != NULL) {
  1593. unsigned long flags;
  1594. period = priv->assoc_network->tim.tim_period;
  1595. }
  1596. #endif /*IWL_MAC80211_DISABLE */
  1597. skip = range[mode].no_dtim;
  1598. if (period == 0) {
  1599. period = 1;
  1600. skip = 0;
  1601. }
  1602. if (skip == 0) {
  1603. max_sleep = period;
  1604. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1605. } else {
  1606. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1607. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1608. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1609. }
  1610. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1611. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1612. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1613. }
  1614. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1615. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1616. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1617. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1618. le32_to_cpu(cmd->sleep_interval[0]),
  1619. le32_to_cpu(cmd->sleep_interval[1]),
  1620. le32_to_cpu(cmd->sleep_interval[2]),
  1621. le32_to_cpu(cmd->sleep_interval[3]),
  1622. le32_to_cpu(cmd->sleep_interval[4]));
  1623. return rc;
  1624. }
  1625. static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
  1626. {
  1627. u32 uninitialized_var(final_mode);
  1628. int rc;
  1629. struct iwl_powertable_cmd cmd;
  1630. /* If on battery, set to 3,
  1631. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1632. * else user level */
  1633. switch (mode) {
  1634. case IWL_POWER_BATTERY:
  1635. final_mode = IWL_POWER_INDEX_3;
  1636. break;
  1637. case IWL_POWER_AC:
  1638. final_mode = IWL_POWER_MODE_CAM;
  1639. break;
  1640. default:
  1641. final_mode = mode;
  1642. break;
  1643. }
  1644. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1645. /* FIXME use get_hcmd_size 3945 command is 4 bytes shorter */
  1646. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD,
  1647. sizeof(struct iwl3945_powertable_cmd), &cmd);
  1648. if (final_mode == IWL_POWER_MODE_CAM)
  1649. clear_bit(STATUS_POWER_PMI, &priv->status);
  1650. else
  1651. set_bit(STATUS_POWER_PMI, &priv->status);
  1652. return rc;
  1653. }
  1654. /**
  1655. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1656. *
  1657. * NOTE: priv->mutex is not required before calling this function
  1658. */
  1659. static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
  1660. {
  1661. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1662. clear_bit(STATUS_SCANNING, &priv->status);
  1663. return 0;
  1664. }
  1665. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1666. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1667. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1668. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1669. queue_work(priv->workqueue, &priv->abort_scan);
  1670. } else
  1671. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1672. return test_bit(STATUS_SCANNING, &priv->status);
  1673. }
  1674. return 0;
  1675. }
  1676. /**
  1677. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1678. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1679. *
  1680. * NOTE: priv->mutex must be held before calling this function
  1681. */
  1682. static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
  1683. {
  1684. unsigned long now = jiffies;
  1685. int ret;
  1686. ret = iwl3945_scan_cancel(priv);
  1687. if (ret && ms) {
  1688. mutex_unlock(&priv->mutex);
  1689. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1690. test_bit(STATUS_SCANNING, &priv->status))
  1691. msleep(1);
  1692. mutex_lock(&priv->mutex);
  1693. return test_bit(STATUS_SCANNING, &priv->status);
  1694. }
  1695. return ret;
  1696. }
  1697. #define MAX_UCODE_BEACON_INTERVAL 1024
  1698. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1699. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1700. {
  1701. u16 new_val = 0;
  1702. u16 beacon_factor = 0;
  1703. beacon_factor =
  1704. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1705. / MAX_UCODE_BEACON_INTERVAL;
  1706. new_val = beacon_val / beacon_factor;
  1707. return cpu_to_le16(new_val);
  1708. }
  1709. static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
  1710. {
  1711. u64 interval_tm_unit;
  1712. u64 tsf, result;
  1713. unsigned long flags;
  1714. struct ieee80211_conf *conf = NULL;
  1715. u16 beacon_int = 0;
  1716. conf = ieee80211_get_hw_conf(priv->hw);
  1717. spin_lock_irqsave(&priv->lock, flags);
  1718. priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
  1719. priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
  1720. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1721. tsf = priv->timestamp1;
  1722. tsf = ((tsf << 32) | priv->timestamp0);
  1723. beacon_int = priv->beacon_int;
  1724. spin_unlock_irqrestore(&priv->lock, flags);
  1725. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  1726. if (beacon_int == 0) {
  1727. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  1728. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  1729. } else {
  1730. priv->rxon_timing.beacon_interval =
  1731. cpu_to_le16(beacon_int);
  1732. priv->rxon_timing.beacon_interval =
  1733. iwl3945_adjust_beacon_interval(
  1734. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1735. }
  1736. priv->rxon_timing.atim_window = 0;
  1737. } else {
  1738. priv->rxon_timing.beacon_interval =
  1739. iwl3945_adjust_beacon_interval(conf->beacon_int);
  1740. /* TODO: we need to get atim_window from upper stack
  1741. * for now we set to 0 */
  1742. priv->rxon_timing.atim_window = 0;
  1743. }
  1744. interval_tm_unit =
  1745. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  1746. result = do_div(tsf, interval_tm_unit);
  1747. priv->rxon_timing.beacon_init_val =
  1748. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  1749. IWL_DEBUG_ASSOC
  1750. ("beacon interval %d beacon timer %d beacon tim %d\n",
  1751. le16_to_cpu(priv->rxon_timing.beacon_interval),
  1752. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  1753. le16_to_cpu(priv->rxon_timing.atim_window));
  1754. }
  1755. static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
  1756. {
  1757. if (!iwl3945_is_ready_rf(priv)) {
  1758. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  1759. return -EIO;
  1760. }
  1761. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1762. IWL_DEBUG_SCAN("Scan already in progress.\n");
  1763. return -EAGAIN;
  1764. }
  1765. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1766. IWL_DEBUG_SCAN("Scan request while abort pending. "
  1767. "Queuing.\n");
  1768. return -EAGAIN;
  1769. }
  1770. IWL_DEBUG_INFO("Starting scan...\n");
  1771. if (priv->cfg->sku & IWL_SKU_G)
  1772. priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
  1773. if (priv->cfg->sku & IWL_SKU_A)
  1774. priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
  1775. set_bit(STATUS_SCANNING, &priv->status);
  1776. priv->scan_start = jiffies;
  1777. priv->scan_pass_start = priv->scan_start;
  1778. queue_work(priv->workqueue, &priv->request_scan);
  1779. return 0;
  1780. }
  1781. static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
  1782. {
  1783. struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
  1784. if (hw_decrypt)
  1785. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  1786. else
  1787. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  1788. return 0;
  1789. }
  1790. static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
  1791. enum ieee80211_band band)
  1792. {
  1793. if (band == IEEE80211_BAND_5GHZ) {
  1794. priv->staging_rxon.flags &=
  1795. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  1796. | RXON_FLG_CCK_MSK);
  1797. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1798. } else {
  1799. /* Copied from iwl3945_bg_post_associate() */
  1800. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1801. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1802. else
  1803. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1804. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1805. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1806. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1807. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1808. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1809. }
  1810. }
  1811. /*
  1812. * initialize rxon structure with default values from eeprom
  1813. */
  1814. static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv,
  1815. int mode)
  1816. {
  1817. const struct iwl3945_channel_info *ch_info;
  1818. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  1819. switch (mode) {
  1820. case NL80211_IFTYPE_AP:
  1821. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  1822. break;
  1823. case NL80211_IFTYPE_STATION:
  1824. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1825. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1826. break;
  1827. case NL80211_IFTYPE_ADHOC:
  1828. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1829. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1830. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1831. RXON_FILTER_ACCEPT_GRP_MSK;
  1832. break;
  1833. case NL80211_IFTYPE_MONITOR:
  1834. priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  1835. priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  1836. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  1837. break;
  1838. default:
  1839. IWL_ERROR("Unsupported interface type %d\n", mode);
  1840. break;
  1841. }
  1842. #if 0
  1843. /* TODO: Figure out when short_preamble would be set and cache from
  1844. * that */
  1845. if (!hw_to_local(priv->hw)->short_preamble)
  1846. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1847. else
  1848. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1849. #endif
  1850. ch_info = iwl3945_get_channel_info(priv, priv->band,
  1851. le16_to_cpu(priv->active_rxon.channel));
  1852. if (!ch_info)
  1853. ch_info = &priv->channel_info[0];
  1854. /*
  1855. * in some case A channels are all non IBSS
  1856. * in this case force B/G channel
  1857. */
  1858. if ((mode == NL80211_IFTYPE_ADHOC) && !(is_channel_ibss(ch_info)))
  1859. ch_info = &priv->channel_info[0];
  1860. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  1861. if (is_channel_a_band(ch_info))
  1862. priv->band = IEEE80211_BAND_5GHZ;
  1863. else
  1864. priv->band = IEEE80211_BAND_2GHZ;
  1865. iwl3945_set_flags_for_phymode(priv, priv->band);
  1866. priv->staging_rxon.ofdm_basic_rates =
  1867. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1868. priv->staging_rxon.cck_basic_rates =
  1869. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1870. }
  1871. static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
  1872. {
  1873. if (mode == NL80211_IFTYPE_ADHOC) {
  1874. const struct iwl3945_channel_info *ch_info;
  1875. ch_info = iwl3945_get_channel_info(priv,
  1876. priv->band,
  1877. le16_to_cpu(priv->staging_rxon.channel));
  1878. if (!ch_info || !is_channel_ibss(ch_info)) {
  1879. IWL_ERROR("channel %d not IBSS channel\n",
  1880. le16_to_cpu(priv->staging_rxon.channel));
  1881. return -EINVAL;
  1882. }
  1883. }
  1884. iwl3945_connection_init_rx_config(priv, mode);
  1885. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1886. iwl3945_clear_stations_table(priv);
  1887. /* don't commit rxon if rf-kill is on*/
  1888. if (!iwl3945_is_ready_rf(priv))
  1889. return -EAGAIN;
  1890. cancel_delayed_work(&priv->scan_check);
  1891. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  1892. IWL_WARNING("Aborted scan still in progress after 100ms\n");
  1893. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  1894. return -EAGAIN;
  1895. }
  1896. iwl3945_commit_rxon(priv);
  1897. return 0;
  1898. }
  1899. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
  1900. struct ieee80211_tx_info *info,
  1901. struct iwl3945_cmd *cmd,
  1902. struct sk_buff *skb_frag,
  1903. int last_frag)
  1904. {
  1905. struct iwl3945_hw_key *keyinfo =
  1906. &priv->stations[info->control.hw_key->hw_key_idx].keyinfo;
  1907. switch (keyinfo->alg) {
  1908. case ALG_CCMP:
  1909. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
  1910. memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
  1911. IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
  1912. break;
  1913. case ALG_TKIP:
  1914. #if 0
  1915. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
  1916. if (last_frag)
  1917. memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
  1918. 8);
  1919. else
  1920. memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
  1921. #endif
  1922. break;
  1923. case ALG_WEP:
  1924. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
  1925. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  1926. if (keyinfo->keylen == 13)
  1927. cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
  1928. memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
  1929. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  1930. "with key %d\n", info->control.hw_key->hw_key_idx);
  1931. break;
  1932. default:
  1933. printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
  1934. break;
  1935. }
  1936. }
  1937. /*
  1938. * handle build REPLY_TX command notification.
  1939. */
  1940. static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
  1941. struct iwl3945_cmd *cmd,
  1942. struct ieee80211_tx_info *info,
  1943. struct ieee80211_hdr *hdr,
  1944. int is_unicast, u8 std_id)
  1945. {
  1946. __le16 fc = hdr->frame_control;
  1947. __le32 tx_flags = cmd->cmd.tx.tx_flags;
  1948. u8 rc_flags = info->control.rates[0].flags;
  1949. cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  1950. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  1951. tx_flags |= TX_CMD_FLG_ACK_MSK;
  1952. if (ieee80211_is_mgmt(fc))
  1953. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1954. if (ieee80211_is_probe_resp(fc) &&
  1955. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  1956. tx_flags |= TX_CMD_FLG_TSF_MSK;
  1957. } else {
  1958. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  1959. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1960. }
  1961. cmd->cmd.tx.sta_id = std_id;
  1962. if (ieee80211_has_morefrags(fc))
  1963. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  1964. if (ieee80211_is_data_qos(fc)) {
  1965. u8 *qc = ieee80211_get_qos_ctl(hdr);
  1966. cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
  1967. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  1968. } else {
  1969. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1970. }
  1971. if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  1972. tx_flags |= TX_CMD_FLG_RTS_MSK;
  1973. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  1974. } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  1975. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  1976. tx_flags |= TX_CMD_FLG_CTS_MSK;
  1977. }
  1978. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  1979. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  1980. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  1981. if (ieee80211_is_mgmt(fc)) {
  1982. if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
  1983. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
  1984. else
  1985. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
  1986. } else {
  1987. cmd->cmd.tx.timeout.pm_frame_timeout = 0;
  1988. #ifdef CONFIG_IWL3945_LEDS
  1989. priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
  1990. #endif
  1991. }
  1992. cmd->cmd.tx.driver_txop = 0;
  1993. cmd->cmd.tx.tx_flags = tx_flags;
  1994. cmd->cmd.tx.next_frame_len = 0;
  1995. }
  1996. /**
  1997. * iwl3945_get_sta_id - Find station's index within station table
  1998. */
  1999. static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
  2000. {
  2001. int sta_id;
  2002. u16 fc = le16_to_cpu(hdr->frame_control);
  2003. /* If this frame is broadcast or management, use broadcast station id */
  2004. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  2005. is_multicast_ether_addr(hdr->addr1))
  2006. return priv->hw_setting.bcast_sta_id;
  2007. switch (priv->iw_mode) {
  2008. /* If we are a client station in a BSS network, use the special
  2009. * AP station entry (that's the only station we communicate with) */
  2010. case NL80211_IFTYPE_STATION:
  2011. return IWL_AP_ID;
  2012. /* If we are an AP, then find the station, or use BCAST */
  2013. case NL80211_IFTYPE_AP:
  2014. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2015. if (sta_id != IWL_INVALID_STATION)
  2016. return sta_id;
  2017. return priv->hw_setting.bcast_sta_id;
  2018. /* If this frame is going out to an IBSS network, find the station,
  2019. * or create a new station table entry */
  2020. case NL80211_IFTYPE_ADHOC: {
  2021. /* Create new station table entry */
  2022. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2023. if (sta_id != IWL_INVALID_STATION)
  2024. return sta_id;
  2025. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  2026. if (sta_id != IWL_INVALID_STATION)
  2027. return sta_id;
  2028. IWL_DEBUG_DROP("Station %pM not in station map. "
  2029. "Defaulting to broadcast...\n",
  2030. hdr->addr1);
  2031. iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  2032. return priv->hw_setting.bcast_sta_id;
  2033. }
  2034. /* If we are in monitor mode, use BCAST. This is required for
  2035. * packet injection. */
  2036. case NL80211_IFTYPE_MONITOR:
  2037. return priv->hw_setting.bcast_sta_id;
  2038. default:
  2039. IWL_WARNING("Unknown mode of operation: %d\n", priv->iw_mode);
  2040. return priv->hw_setting.bcast_sta_id;
  2041. }
  2042. }
  2043. /*
  2044. * start REPLY_TX command process
  2045. */
  2046. static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb)
  2047. {
  2048. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  2049. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  2050. struct iwl3945_tfd_frame *tfd;
  2051. u32 *control_flags;
  2052. int txq_id = skb_get_queue_mapping(skb);
  2053. struct iwl3945_tx_queue *txq = NULL;
  2054. struct iwl3945_queue *q = NULL;
  2055. dma_addr_t phys_addr;
  2056. dma_addr_t txcmd_phys;
  2057. struct iwl3945_cmd *out_cmd = NULL;
  2058. u16 len, idx, len_org, hdr_len;
  2059. u8 id;
  2060. u8 unicast;
  2061. u8 sta_id;
  2062. u8 tid = 0;
  2063. u16 seq_number = 0;
  2064. __le16 fc;
  2065. u8 wait_write_ptr = 0;
  2066. u8 *qc = NULL;
  2067. unsigned long flags;
  2068. int rc;
  2069. spin_lock_irqsave(&priv->lock, flags);
  2070. if (iwl3945_is_rfkill(priv)) {
  2071. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  2072. goto drop_unlock;
  2073. }
  2074. if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
  2075. IWL_ERROR("ERROR: No TX rate available.\n");
  2076. goto drop_unlock;
  2077. }
  2078. unicast = !is_multicast_ether_addr(hdr->addr1);
  2079. id = 0;
  2080. fc = hdr->frame_control;
  2081. #ifdef CONFIG_IWL3945_DEBUG
  2082. if (ieee80211_is_auth(fc))
  2083. IWL_DEBUG_TX("Sending AUTH frame\n");
  2084. else if (ieee80211_is_assoc_req(fc))
  2085. IWL_DEBUG_TX("Sending ASSOC frame\n");
  2086. else if (ieee80211_is_reassoc_req(fc))
  2087. IWL_DEBUG_TX("Sending REASSOC frame\n");
  2088. #endif
  2089. /* drop all data frame if we are not associated */
  2090. if (ieee80211_is_data(fc) &&
  2091. (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
  2092. (!iwl3945_is_associated(priv) ||
  2093. ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
  2094. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  2095. goto drop_unlock;
  2096. }
  2097. spin_unlock_irqrestore(&priv->lock, flags);
  2098. hdr_len = ieee80211_hdrlen(fc);
  2099. /* Find (or create) index into station table for destination station */
  2100. sta_id = iwl3945_get_sta_id(priv, hdr);
  2101. if (sta_id == IWL_INVALID_STATION) {
  2102. IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
  2103. hdr->addr1);
  2104. goto drop;
  2105. }
  2106. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  2107. if (ieee80211_is_data_qos(fc)) {
  2108. qc = ieee80211_get_qos_ctl(hdr);
  2109. tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
  2110. seq_number = priv->stations[sta_id].tid[tid].seq_number &
  2111. IEEE80211_SCTL_SEQ;
  2112. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  2113. (hdr->seq_ctrl &
  2114. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  2115. seq_number += 0x10;
  2116. }
  2117. /* Descriptor for chosen Tx queue */
  2118. txq = &priv->txq[txq_id];
  2119. q = &txq->q;
  2120. spin_lock_irqsave(&priv->lock, flags);
  2121. /* Set up first empty TFD within this queue's circular TFD buffer */
  2122. tfd = &txq->bd[q->write_ptr];
  2123. memset(tfd, 0, sizeof(*tfd));
  2124. control_flags = (u32 *) tfd;
  2125. idx = get_cmd_index(q, q->write_ptr, 0);
  2126. /* Set up driver data for this TFD */
  2127. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
  2128. txq->txb[q->write_ptr].skb[0] = skb;
  2129. /* Init first empty entry in queue's array of Tx/cmd buffers */
  2130. out_cmd = &txq->cmd[idx];
  2131. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  2132. memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
  2133. /*
  2134. * Set up the Tx-command (not MAC!) header.
  2135. * Store the chosen Tx queue and TFD index within the sequence field;
  2136. * after Tx, uCode's Tx response will return this value so driver can
  2137. * locate the frame within the tx queue and do post-tx processing.
  2138. */
  2139. out_cmd->hdr.cmd = REPLY_TX;
  2140. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  2141. INDEX_TO_SEQ(q->write_ptr)));
  2142. /* Copy MAC header from skb into command buffer */
  2143. memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
  2144. /*
  2145. * Use the first empty entry in this queue's command buffer array
  2146. * to contain the Tx command and MAC header concatenated together
  2147. * (payload data will be in another buffer).
  2148. * Size of this varies, due to varying MAC header length.
  2149. * If end is not dword aligned, we'll have 2 extra bytes at the end
  2150. * of the MAC header (device reads on dword boundaries).
  2151. * We'll tell device about this padding later.
  2152. */
  2153. len = priv->hw_setting.tx_cmd_len +
  2154. sizeof(struct iwl_cmd_header) + hdr_len;
  2155. len_org = len;
  2156. len = (len + 3) & ~3;
  2157. if (len_org != len)
  2158. len_org = 1;
  2159. else
  2160. len_org = 0;
  2161. /* Physical address of this Tx command's header (not MAC header!),
  2162. * within command buffer array. */
  2163. txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
  2164. offsetof(struct iwl3945_cmd, hdr);
  2165. /* Add buffer containing Tx command and MAC(!) header to TFD's
  2166. * first entry */
  2167. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  2168. if (info->control.hw_key)
  2169. iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
  2170. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  2171. * if any (802.11 null frames have no payload). */
  2172. len = skb->len - hdr_len;
  2173. if (len) {
  2174. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  2175. len, PCI_DMA_TODEVICE);
  2176. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  2177. }
  2178. if (!len)
  2179. /* If there is no payload, then we use only one Tx buffer */
  2180. *control_flags = TFD_CTL_COUNT_SET(1);
  2181. else
  2182. /* Else use 2 buffers.
  2183. * Tell 3945 about any padding after MAC header */
  2184. *control_flags = TFD_CTL_COUNT_SET(2) |
  2185. TFD_CTL_PAD_SET(U32_PAD(len));
  2186. /* Total # bytes to be transmitted */
  2187. len = (u16)skb->len;
  2188. out_cmd->cmd.tx.len = cpu_to_le16(len);
  2189. /* TODO need this for burst mode later on */
  2190. iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
  2191. /* set is_hcca to 0; it probably will never be implemented */
  2192. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
  2193. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  2194. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  2195. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  2196. txq->need_update = 1;
  2197. if (qc)
  2198. priv->stations[sta_id].tid[tid].seq_number = seq_number;
  2199. } else {
  2200. wait_write_ptr = 1;
  2201. txq->need_update = 0;
  2202. }
  2203. iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
  2204. sizeof(out_cmd->cmd.tx));
  2205. iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
  2206. ieee80211_hdrlen(fc));
  2207. /* Tell device the write index *just past* this latest filled TFD */
  2208. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  2209. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2210. spin_unlock_irqrestore(&priv->lock, flags);
  2211. if (rc)
  2212. return rc;
  2213. if ((iwl3945_queue_space(q) < q->high_mark)
  2214. && priv->mac80211_registered) {
  2215. if (wait_write_ptr) {
  2216. spin_lock_irqsave(&priv->lock, flags);
  2217. txq->need_update = 1;
  2218. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2219. spin_unlock_irqrestore(&priv->lock, flags);
  2220. }
  2221. ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
  2222. }
  2223. return 0;
  2224. drop_unlock:
  2225. spin_unlock_irqrestore(&priv->lock, flags);
  2226. drop:
  2227. return -1;
  2228. }
  2229. static void iwl3945_set_rate(struct iwl3945_priv *priv)
  2230. {
  2231. const struct ieee80211_supported_band *sband = NULL;
  2232. struct ieee80211_rate *rate;
  2233. int i;
  2234. sband = iwl3945_get_band(priv, priv->band);
  2235. if (!sband) {
  2236. IWL_ERROR("Failed to set rate: unable to get hw mode\n");
  2237. return;
  2238. }
  2239. priv->active_rate = 0;
  2240. priv->active_rate_basic = 0;
  2241. IWL_DEBUG_RATE("Setting rates for %s GHz\n",
  2242. sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
  2243. for (i = 0; i < sband->n_bitrates; i++) {
  2244. rate = &sband->bitrates[i];
  2245. if ((rate->hw_value < IWL_RATE_COUNT) &&
  2246. !(rate->flags & IEEE80211_CHAN_DISABLED)) {
  2247. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
  2248. rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
  2249. priv->active_rate |= (1 << rate->hw_value);
  2250. }
  2251. }
  2252. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2253. priv->active_rate, priv->active_rate_basic);
  2254. /*
  2255. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2256. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2257. * OFDM
  2258. */
  2259. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2260. priv->staging_rxon.cck_basic_rates =
  2261. ((priv->active_rate_basic &
  2262. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2263. else
  2264. priv->staging_rxon.cck_basic_rates =
  2265. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2266. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2267. priv->staging_rxon.ofdm_basic_rates =
  2268. ((priv->active_rate_basic &
  2269. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2270. IWL_FIRST_OFDM_RATE) & 0xFF;
  2271. else
  2272. priv->staging_rxon.ofdm_basic_rates =
  2273. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2274. }
  2275. static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
  2276. {
  2277. unsigned long flags;
  2278. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2279. return;
  2280. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2281. disable_radio ? "OFF" : "ON");
  2282. if (disable_radio) {
  2283. iwl3945_scan_cancel(priv);
  2284. /* FIXME: This is a workaround for AP */
  2285. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  2286. spin_lock_irqsave(&priv->lock, flags);
  2287. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2288. CSR_UCODE_SW_BIT_RFKILL);
  2289. spin_unlock_irqrestore(&priv->lock, flags);
  2290. iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2291. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2292. }
  2293. return;
  2294. }
  2295. spin_lock_irqsave(&priv->lock, flags);
  2296. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2297. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2298. spin_unlock_irqrestore(&priv->lock, flags);
  2299. /* wake up ucode */
  2300. msleep(10);
  2301. spin_lock_irqsave(&priv->lock, flags);
  2302. iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2303. if (!iwl3945_grab_nic_access(priv))
  2304. iwl3945_release_nic_access(priv);
  2305. spin_unlock_irqrestore(&priv->lock, flags);
  2306. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2307. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2308. "disabled by HW switch\n");
  2309. return;
  2310. }
  2311. if (priv->is_open)
  2312. queue_work(priv->workqueue, &priv->restart);
  2313. return;
  2314. }
  2315. void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
  2316. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2317. {
  2318. u16 fc =
  2319. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2320. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2321. return;
  2322. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2323. return;
  2324. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2325. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2326. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2327. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2328. RX_RES_STATUS_BAD_ICV_MIC)
  2329. stats->flag |= RX_FLAG_MMIC_ERROR;
  2330. case RX_RES_STATUS_SEC_TYPE_WEP:
  2331. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2332. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2333. RX_RES_STATUS_DECRYPT_OK) {
  2334. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2335. stats->flag |= RX_FLAG_DECRYPTED;
  2336. }
  2337. break;
  2338. default:
  2339. break;
  2340. }
  2341. }
  2342. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2343. #include "iwl-spectrum.h"
  2344. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2345. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2346. #define TIME_UNIT 1024
  2347. /*
  2348. * extended beacon time format
  2349. * time in usec will be changed into a 32-bit value in 8:24 format
  2350. * the high 1 byte is the beacon counts
  2351. * the lower 3 bytes is the time in usec within one beacon interval
  2352. */
  2353. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2354. {
  2355. u32 quot;
  2356. u32 rem;
  2357. u32 interval = beacon_interval * 1024;
  2358. if (!interval || !usec)
  2359. return 0;
  2360. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2361. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2362. return (quot << 24) + rem;
  2363. }
  2364. /* base is usually what we get from ucode with each received frame,
  2365. * the same as HW timer counter counting down
  2366. */
  2367. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2368. {
  2369. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2370. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2371. u32 interval = beacon_interval * TIME_UNIT;
  2372. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2373. (addon & BEACON_TIME_MASK_HIGH);
  2374. if (base_low > addon_low)
  2375. res += base_low - addon_low;
  2376. else if (base_low < addon_low) {
  2377. res += interval + base_low - addon_low;
  2378. res += (1 << 24);
  2379. } else
  2380. res += (1 << 24);
  2381. return cpu_to_le32(res);
  2382. }
  2383. static int iwl3945_get_measurement(struct iwl3945_priv *priv,
  2384. struct ieee80211_measurement_params *params,
  2385. u8 type)
  2386. {
  2387. struct iwl_spectrum_cmd spectrum;
  2388. struct iwl3945_rx_packet *res;
  2389. struct iwl3945_host_cmd cmd = {
  2390. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2391. .data = (void *)&spectrum,
  2392. .meta.flags = CMD_WANT_SKB,
  2393. };
  2394. u32 add_time = le64_to_cpu(params->start_time);
  2395. int rc;
  2396. int spectrum_resp_status;
  2397. int duration = le16_to_cpu(params->duration);
  2398. if (iwl3945_is_associated(priv))
  2399. add_time =
  2400. iwl3945_usecs_to_beacons(
  2401. le64_to_cpu(params->start_time) - priv->last_tsf,
  2402. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2403. memset(&spectrum, 0, sizeof(spectrum));
  2404. spectrum.channel_count = cpu_to_le16(1);
  2405. spectrum.flags =
  2406. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2407. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2408. cmd.len = sizeof(spectrum);
  2409. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2410. if (iwl3945_is_associated(priv))
  2411. spectrum.start_time =
  2412. iwl3945_add_beacon_time(priv->last_beacon_time,
  2413. add_time,
  2414. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2415. else
  2416. spectrum.start_time = 0;
  2417. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2418. spectrum.channels[0].channel = params->channel;
  2419. spectrum.channels[0].type = type;
  2420. if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2421. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2422. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2423. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2424. if (rc)
  2425. return rc;
  2426. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  2427. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2428. IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
  2429. rc = -EIO;
  2430. }
  2431. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2432. switch (spectrum_resp_status) {
  2433. case 0: /* Command will be handled */
  2434. if (res->u.spectrum.id != 0xff) {
  2435. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2436. res->u.spectrum.id);
  2437. priv->measurement_status &= ~MEASUREMENT_READY;
  2438. }
  2439. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2440. rc = 0;
  2441. break;
  2442. case 1: /* Command will not be handled */
  2443. rc = -EAGAIN;
  2444. break;
  2445. }
  2446. dev_kfree_skb_any(cmd.meta.u.skb);
  2447. return rc;
  2448. }
  2449. #endif
  2450. static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
  2451. struct iwl3945_rx_mem_buffer *rxb)
  2452. {
  2453. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2454. struct iwl3945_alive_resp *palive;
  2455. struct delayed_work *pwork;
  2456. palive = &pkt->u.alive_frame;
  2457. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2458. "0x%01X 0x%01X\n",
  2459. palive->is_valid, palive->ver_type,
  2460. palive->ver_subtype);
  2461. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2462. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2463. memcpy(&priv->card_alive_init,
  2464. &pkt->u.alive_frame,
  2465. sizeof(struct iwl3945_init_alive_resp));
  2466. pwork = &priv->init_alive_start;
  2467. } else {
  2468. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2469. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2470. sizeof(struct iwl3945_alive_resp));
  2471. pwork = &priv->alive_start;
  2472. iwl3945_disable_events(priv);
  2473. }
  2474. /* We delay the ALIVE response by 5ms to
  2475. * give the HW RF Kill time to activate... */
  2476. if (palive->is_valid == UCODE_VALID_OK)
  2477. queue_delayed_work(priv->workqueue, pwork,
  2478. msecs_to_jiffies(5));
  2479. else
  2480. IWL_WARNING("uCode did not respond OK.\n");
  2481. }
  2482. static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
  2483. struct iwl3945_rx_mem_buffer *rxb)
  2484. {
  2485. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2486. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2487. return;
  2488. }
  2489. static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
  2490. struct iwl3945_rx_mem_buffer *rxb)
  2491. {
  2492. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2493. IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
  2494. "seq 0x%04X ser 0x%08X\n",
  2495. le32_to_cpu(pkt->u.err_resp.error_type),
  2496. get_cmd_string(pkt->u.err_resp.cmd_id),
  2497. pkt->u.err_resp.cmd_id,
  2498. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2499. le32_to_cpu(pkt->u.err_resp.error_info));
  2500. }
  2501. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2502. static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
  2503. {
  2504. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2505. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
  2506. struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
  2507. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2508. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2509. rxon->channel = csa->channel;
  2510. priv->staging_rxon.channel = csa->channel;
  2511. }
  2512. static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
  2513. struct iwl3945_rx_mem_buffer *rxb)
  2514. {
  2515. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2516. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2517. struct iwl_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2518. if (!report->state) {
  2519. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2520. "Spectrum Measure Notification: Start\n");
  2521. return;
  2522. }
  2523. memcpy(&priv->measure_report, report, sizeof(*report));
  2524. priv->measurement_status |= MEASUREMENT_READY;
  2525. #endif
  2526. }
  2527. static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
  2528. struct iwl3945_rx_mem_buffer *rxb)
  2529. {
  2530. #ifdef CONFIG_IWL3945_DEBUG
  2531. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2532. struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2533. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2534. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2535. #endif
  2536. }
  2537. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
  2538. struct iwl3945_rx_mem_buffer *rxb)
  2539. {
  2540. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2541. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2542. "notification for %s:\n",
  2543. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2544. iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
  2545. }
  2546. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2547. {
  2548. struct iwl3945_priv *priv =
  2549. container_of(work, struct iwl3945_priv, beacon_update);
  2550. struct sk_buff *beacon;
  2551. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2552. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  2553. if (!beacon) {
  2554. IWL_ERROR("update beacon failed\n");
  2555. return;
  2556. }
  2557. mutex_lock(&priv->mutex);
  2558. /* new beacon skb is allocated every time; dispose previous.*/
  2559. if (priv->ibss_beacon)
  2560. dev_kfree_skb(priv->ibss_beacon);
  2561. priv->ibss_beacon = beacon;
  2562. mutex_unlock(&priv->mutex);
  2563. iwl3945_send_beacon_cmd(priv);
  2564. }
  2565. static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
  2566. struct iwl3945_rx_mem_buffer *rxb)
  2567. {
  2568. #ifdef CONFIG_IWL3945_DEBUG
  2569. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2570. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  2571. u8 rate = beacon->beacon_notify_hdr.rate;
  2572. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  2573. "tsf %d %d rate %d\n",
  2574. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  2575. beacon->beacon_notify_hdr.failure_frame,
  2576. le32_to_cpu(beacon->ibss_mgr_status),
  2577. le32_to_cpu(beacon->high_tsf),
  2578. le32_to_cpu(beacon->low_tsf), rate);
  2579. #endif
  2580. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  2581. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  2582. queue_work(priv->workqueue, &priv->beacon_update);
  2583. }
  2584. /* Service response to REPLY_SCAN_CMD (0x80) */
  2585. static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
  2586. struct iwl3945_rx_mem_buffer *rxb)
  2587. {
  2588. #ifdef CONFIG_IWL3945_DEBUG
  2589. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2590. struct iwl_scanreq_notification *notif =
  2591. (struct iwl_scanreq_notification *)pkt->u.raw;
  2592. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  2593. #endif
  2594. }
  2595. /* Service SCAN_START_NOTIFICATION (0x82) */
  2596. static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
  2597. struct iwl3945_rx_mem_buffer *rxb)
  2598. {
  2599. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2600. struct iwl_scanstart_notification *notif =
  2601. (struct iwl_scanstart_notification *)pkt->u.raw;
  2602. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  2603. IWL_DEBUG_SCAN("Scan start: "
  2604. "%d [802.11%s] "
  2605. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  2606. notif->channel,
  2607. notif->band ? "bg" : "a",
  2608. notif->tsf_high,
  2609. notif->tsf_low, notif->status, notif->beacon_timer);
  2610. }
  2611. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  2612. static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
  2613. struct iwl3945_rx_mem_buffer *rxb)
  2614. {
  2615. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2616. struct iwl_scanresults_notification *notif =
  2617. (struct iwl_scanresults_notification *)pkt->u.raw;
  2618. IWL_DEBUG_SCAN("Scan ch.res: "
  2619. "%d [802.11%s] "
  2620. "(TSF: 0x%08X:%08X) - %d "
  2621. "elapsed=%lu usec (%dms since last)\n",
  2622. notif->channel,
  2623. notif->band ? "bg" : "a",
  2624. le32_to_cpu(notif->tsf_high),
  2625. le32_to_cpu(notif->tsf_low),
  2626. le32_to_cpu(notif->statistics[0]),
  2627. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  2628. jiffies_to_msecs(elapsed_jiffies
  2629. (priv->last_scan_jiffies, jiffies)));
  2630. priv->last_scan_jiffies = jiffies;
  2631. priv->next_scan_jiffies = 0;
  2632. }
  2633. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  2634. static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
  2635. struct iwl3945_rx_mem_buffer *rxb)
  2636. {
  2637. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2638. struct iwl_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  2639. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  2640. scan_notif->scanned_channels,
  2641. scan_notif->tsf_low,
  2642. scan_notif->tsf_high, scan_notif->status);
  2643. /* The HW is no longer scanning */
  2644. clear_bit(STATUS_SCAN_HW, &priv->status);
  2645. /* The scan completion notification came in, so kill that timer... */
  2646. cancel_delayed_work(&priv->scan_check);
  2647. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  2648. (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
  2649. "2.4" : "5.2",
  2650. jiffies_to_msecs(elapsed_jiffies
  2651. (priv->scan_pass_start, jiffies)));
  2652. /* Remove this scanned band from the list of pending
  2653. * bands to scan, band G precedes A in order of scanning
  2654. * as seen in iwl3945_bg_request_scan */
  2655. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
  2656. priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
  2657. else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
  2658. priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
  2659. /* If a request to abort was given, or the scan did not succeed
  2660. * then we reset the scan state machine and terminate,
  2661. * re-queuing another scan if one has been requested */
  2662. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2663. IWL_DEBUG_INFO("Aborted scan completed.\n");
  2664. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  2665. } else {
  2666. /* If there are more bands on this scan pass reschedule */
  2667. if (priv->scan_bands > 0)
  2668. goto reschedule;
  2669. }
  2670. priv->last_scan_jiffies = jiffies;
  2671. priv->next_scan_jiffies = 0;
  2672. IWL_DEBUG_INFO("Setting scan to off\n");
  2673. clear_bit(STATUS_SCANNING, &priv->status);
  2674. IWL_DEBUG_INFO("Scan took %dms\n",
  2675. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  2676. queue_work(priv->workqueue, &priv->scan_completed);
  2677. return;
  2678. reschedule:
  2679. priv->scan_pass_start = jiffies;
  2680. queue_work(priv->workqueue, &priv->request_scan);
  2681. }
  2682. /* Handle notification from uCode that card's power state is changing
  2683. * due to software, hardware, or critical temperature RFKILL */
  2684. static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
  2685. struct iwl3945_rx_mem_buffer *rxb)
  2686. {
  2687. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2688. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  2689. unsigned long status = priv->status;
  2690. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  2691. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  2692. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  2693. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2694. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2695. if (flags & HW_CARD_DISABLED)
  2696. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2697. else
  2698. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2699. if (flags & SW_CARD_DISABLED)
  2700. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2701. else
  2702. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2703. iwl3945_scan_cancel(priv);
  2704. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  2705. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  2706. (test_bit(STATUS_RF_KILL_SW, &status) !=
  2707. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  2708. queue_work(priv->workqueue, &priv->rf_kill);
  2709. else
  2710. wake_up_interruptible(&priv->wait_command_queue);
  2711. }
  2712. /**
  2713. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  2714. *
  2715. * Setup the RX handlers for each of the reply types sent from the uCode
  2716. * to the host.
  2717. *
  2718. * This function chains into the hardware specific files for them to setup
  2719. * any hardware specific handlers as well.
  2720. */
  2721. static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
  2722. {
  2723. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  2724. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  2725. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  2726. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  2727. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  2728. iwl3945_rx_spectrum_measure_notif;
  2729. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  2730. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  2731. iwl3945_rx_pm_debug_statistics_notif;
  2732. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  2733. /*
  2734. * The same handler is used for both the REPLY to a discrete
  2735. * statistics request from the host as well as for the periodic
  2736. * statistics notifications (after received beacons) from the uCode.
  2737. */
  2738. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  2739. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  2740. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  2741. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  2742. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  2743. iwl3945_rx_scan_results_notif;
  2744. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  2745. iwl3945_rx_scan_complete_notif;
  2746. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  2747. /* Set up hardware specific Rx handlers */
  2748. iwl3945_hw_rx_handler_setup(priv);
  2749. }
  2750. /**
  2751. * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
  2752. * When FW advances 'R' index, all entries between old and new 'R' index
  2753. * need to be reclaimed.
  2754. */
  2755. static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
  2756. int txq_id, int index)
  2757. {
  2758. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2759. struct iwl3945_queue *q = &txq->q;
  2760. int nfreed = 0;
  2761. if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
  2762. IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
  2763. "is out of range [0-%d] %d %d.\n", txq_id,
  2764. index, q->n_bd, q->write_ptr, q->read_ptr);
  2765. return;
  2766. }
  2767. for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
  2768. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2769. if (nfreed > 1) {
  2770. IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
  2771. q->write_ptr, q->read_ptr);
  2772. queue_work(priv->workqueue, &priv->restart);
  2773. break;
  2774. }
  2775. nfreed++;
  2776. }
  2777. }
  2778. /**
  2779. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2780. * @rxb: Rx buffer to reclaim
  2781. *
  2782. * If an Rx buffer has an async callback associated with it the callback
  2783. * will be executed. The attached skb (if present) will only be freed
  2784. * if the callback returns 1
  2785. */
  2786. static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
  2787. struct iwl3945_rx_mem_buffer *rxb)
  2788. {
  2789. struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  2790. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2791. int txq_id = SEQ_TO_QUEUE(sequence);
  2792. int index = SEQ_TO_INDEX(sequence);
  2793. int huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
  2794. int cmd_index;
  2795. struct iwl3945_cmd *cmd;
  2796. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  2797. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  2798. cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  2799. /* Input error checking is done when commands are added to queue. */
  2800. if (cmd->meta.flags & CMD_WANT_SKB) {
  2801. cmd->meta.source->u.skb = rxb->skb;
  2802. rxb->skb = NULL;
  2803. } else if (cmd->meta.u.callback &&
  2804. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  2805. rxb->skb = NULL;
  2806. iwl3945_cmd_queue_reclaim(priv, txq_id, index);
  2807. if (!(cmd->meta.flags & CMD_ASYNC)) {
  2808. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  2809. wake_up_interruptible(&priv->wait_command_queue);
  2810. }
  2811. }
  2812. /************************** RX-FUNCTIONS ****************************/
  2813. /*
  2814. * Rx theory of operation
  2815. *
  2816. * The host allocates 32 DMA target addresses and passes the host address
  2817. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  2818. * 0 to 31
  2819. *
  2820. * Rx Queue Indexes
  2821. * The host/firmware share two index registers for managing the Rx buffers.
  2822. *
  2823. * The READ index maps to the first position that the firmware may be writing
  2824. * to -- the driver can read up to (but not including) this position and get
  2825. * good data.
  2826. * The READ index is managed by the firmware once the card is enabled.
  2827. *
  2828. * The WRITE index maps to the last position the driver has read from -- the
  2829. * position preceding WRITE is the last slot the firmware can place a packet.
  2830. *
  2831. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2832. * WRITE = READ.
  2833. *
  2834. * During initialization, the host sets up the READ queue position to the first
  2835. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  2836. *
  2837. * When the firmware places a packet in a buffer, it will advance the READ index
  2838. * and fire the RX interrupt. The driver can then query the READ index and
  2839. * process as many packets as possible, moving the WRITE index forward as it
  2840. * resets the Rx queue buffers with new memory.
  2841. *
  2842. * The management in the driver is as follows:
  2843. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2844. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2845. * to replenish the iwl->rxq->rx_free.
  2846. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  2847. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  2848. * 'processed' and 'read' driver indexes as well)
  2849. * + A received packet is processed and handed to the kernel network stack,
  2850. * detached from the iwl->rxq. The driver 'processed' index is updated.
  2851. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2852. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  2853. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  2854. * were enough free buffers and RX_STALLED is set it is cleared.
  2855. *
  2856. *
  2857. * Driver sequence:
  2858. *
  2859. * iwl3945_rx_queue_alloc() Allocates rx_free
  2860. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  2861. * iwl3945_rx_queue_restock
  2862. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  2863. * queue, updates firmware pointers, and updates
  2864. * the WRITE index. If insufficient rx_free buffers
  2865. * are available, schedules iwl3945_rx_replenish
  2866. *
  2867. * -- enable interrupts --
  2868. * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
  2869. * READ INDEX, detaching the SKB from the pool.
  2870. * Moves the packet buffer from queue to rx_used.
  2871. * Calls iwl3945_rx_queue_restock to refill any empty
  2872. * slots.
  2873. * ...
  2874. *
  2875. */
  2876. /**
  2877. * iwl3945_rx_queue_space - Return number of free slots available in queue.
  2878. */
  2879. static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
  2880. {
  2881. int s = q->read - q->write;
  2882. if (s <= 0)
  2883. s += RX_QUEUE_SIZE;
  2884. /* keep some buffer to not confuse full and empty queue */
  2885. s -= 2;
  2886. if (s < 0)
  2887. s = 0;
  2888. return s;
  2889. }
  2890. /**
  2891. * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  2892. */
  2893. int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
  2894. {
  2895. u32 reg = 0;
  2896. int rc = 0;
  2897. unsigned long flags;
  2898. spin_lock_irqsave(&q->lock, flags);
  2899. if (q->need_update == 0)
  2900. goto exit_unlock;
  2901. /* If power-saving is in use, make sure device is awake */
  2902. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  2903. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2904. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2905. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  2906. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2907. goto exit_unlock;
  2908. }
  2909. rc = iwl3945_grab_nic_access(priv);
  2910. if (rc)
  2911. goto exit_unlock;
  2912. /* Device expects a multiple of 8 */
  2913. iwl3945_write_direct32(priv, FH39_RSCSR_CHNL0_WPTR,
  2914. q->write & ~0x7);
  2915. iwl3945_release_nic_access(priv);
  2916. /* Else device is assumed to be awake */
  2917. } else
  2918. /* Device expects a multiple of 8 */
  2919. iwl3945_write32(priv, FH39_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  2920. q->need_update = 0;
  2921. exit_unlock:
  2922. spin_unlock_irqrestore(&q->lock, flags);
  2923. return rc;
  2924. }
  2925. /**
  2926. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  2927. */
  2928. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
  2929. dma_addr_t dma_addr)
  2930. {
  2931. return cpu_to_le32((u32)dma_addr);
  2932. }
  2933. /**
  2934. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  2935. *
  2936. * If there are slots in the RX queue that need to be restocked,
  2937. * and we have free pre-allocated buffers, fill the ranks as much
  2938. * as we can, pulling from rx_free.
  2939. *
  2940. * This moves the 'write' index forward to catch up with 'processed', and
  2941. * also updates the memory address in the firmware to reference the new
  2942. * target buffer.
  2943. */
  2944. static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
  2945. {
  2946. struct iwl3945_rx_queue *rxq = &priv->rxq;
  2947. struct list_head *element;
  2948. struct iwl3945_rx_mem_buffer *rxb;
  2949. unsigned long flags;
  2950. int write, rc;
  2951. spin_lock_irqsave(&rxq->lock, flags);
  2952. write = rxq->write & ~0x7;
  2953. while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  2954. /* Get next free Rx buffer, remove from free list */
  2955. element = rxq->rx_free.next;
  2956. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  2957. list_del(element);
  2958. /* Point to Rx buffer via next RBD in circular buffer */
  2959. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
  2960. rxq->queue[rxq->write] = rxb;
  2961. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  2962. rxq->free_count--;
  2963. }
  2964. spin_unlock_irqrestore(&rxq->lock, flags);
  2965. /* If the pre-allocated buffer pool is dropping low, schedule to
  2966. * refill it */
  2967. if (rxq->free_count <= RX_LOW_WATERMARK)
  2968. queue_work(priv->workqueue, &priv->rx_replenish);
  2969. /* If we've added more space for the firmware to place data, tell it.
  2970. * Increment device's write pointer in multiples of 8. */
  2971. if ((write != (rxq->write & ~0x7))
  2972. || (abs(rxq->write - rxq->read) > 7)) {
  2973. spin_lock_irqsave(&rxq->lock, flags);
  2974. rxq->need_update = 1;
  2975. spin_unlock_irqrestore(&rxq->lock, flags);
  2976. rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
  2977. if (rc)
  2978. return rc;
  2979. }
  2980. return 0;
  2981. }
  2982. /**
  2983. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  2984. *
  2985. * When moving to rx_free an SKB is allocated for the slot.
  2986. *
  2987. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  2988. * This is called as a scheduled work item (except for during initialization)
  2989. */
  2990. static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
  2991. {
  2992. struct iwl3945_rx_queue *rxq = &priv->rxq;
  2993. struct list_head *element;
  2994. struct iwl3945_rx_mem_buffer *rxb;
  2995. unsigned long flags;
  2996. spin_lock_irqsave(&rxq->lock, flags);
  2997. while (!list_empty(&rxq->rx_used)) {
  2998. element = rxq->rx_used.next;
  2999. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3000. /* Alloc a new receive buffer */
  3001. rxb->skb =
  3002. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  3003. if (!rxb->skb) {
  3004. if (net_ratelimit())
  3005. printk(KERN_CRIT DRV_NAME
  3006. ": Can not allocate SKB buffers\n");
  3007. /* We don't reschedule replenish work here -- we will
  3008. * call the restock method and if it still needs
  3009. * more buffers it will schedule replenish */
  3010. break;
  3011. }
  3012. /* If radiotap head is required, reserve some headroom here.
  3013. * The physical head count is a variable rx_stats->phy_count.
  3014. * We reserve 4 bytes here. Plus these extra bytes, the
  3015. * headroom of the physical head should be enough for the
  3016. * radiotap head that iwl3945 supported. See iwl3945_rt.
  3017. */
  3018. skb_reserve(rxb->skb, 4);
  3019. priv->alloc_rxb_skb++;
  3020. list_del(element);
  3021. /* Get physical address of RB/SKB */
  3022. rxb->dma_addr =
  3023. pci_map_single(priv->pci_dev, rxb->skb->data,
  3024. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3025. list_add_tail(&rxb->list, &rxq->rx_free);
  3026. rxq->free_count++;
  3027. }
  3028. spin_unlock_irqrestore(&rxq->lock, flags);
  3029. }
  3030. /*
  3031. * this should be called while priv->lock is locked
  3032. */
  3033. static void __iwl3945_rx_replenish(void *data)
  3034. {
  3035. struct iwl3945_priv *priv = data;
  3036. iwl3945_rx_allocate(priv);
  3037. iwl3945_rx_queue_restock(priv);
  3038. }
  3039. void iwl3945_rx_replenish(void *data)
  3040. {
  3041. struct iwl3945_priv *priv = data;
  3042. unsigned long flags;
  3043. iwl3945_rx_allocate(priv);
  3044. spin_lock_irqsave(&priv->lock, flags);
  3045. iwl3945_rx_queue_restock(priv);
  3046. spin_unlock_irqrestore(&priv->lock, flags);
  3047. }
  3048. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  3049. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  3050. * This free routine walks the list of POOL entries and if SKB is set to
  3051. * non NULL it is unmapped and freed
  3052. */
  3053. static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3054. {
  3055. int i;
  3056. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  3057. if (rxq->pool[i].skb != NULL) {
  3058. pci_unmap_single(priv->pci_dev,
  3059. rxq->pool[i].dma_addr,
  3060. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3061. dev_kfree_skb(rxq->pool[i].skb);
  3062. }
  3063. }
  3064. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  3065. rxq->dma_addr);
  3066. rxq->bd = NULL;
  3067. }
  3068. int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
  3069. {
  3070. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3071. struct pci_dev *dev = priv->pci_dev;
  3072. int i;
  3073. spin_lock_init(&rxq->lock);
  3074. INIT_LIST_HEAD(&rxq->rx_free);
  3075. INIT_LIST_HEAD(&rxq->rx_used);
  3076. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  3077. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  3078. if (!rxq->bd)
  3079. return -ENOMEM;
  3080. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3081. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  3082. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3083. /* Set us so that we have processed and used all buffers, but have
  3084. * not restocked the Rx queue with fresh buffers */
  3085. rxq->read = rxq->write = 0;
  3086. rxq->free_count = 0;
  3087. rxq->need_update = 0;
  3088. return 0;
  3089. }
  3090. void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3091. {
  3092. unsigned long flags;
  3093. int i;
  3094. spin_lock_irqsave(&rxq->lock, flags);
  3095. INIT_LIST_HEAD(&rxq->rx_free);
  3096. INIT_LIST_HEAD(&rxq->rx_used);
  3097. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3098. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  3099. /* In the reset function, these buffers may have been allocated
  3100. * to an SKB, so we need to unmap and free potential storage */
  3101. if (rxq->pool[i].skb != NULL) {
  3102. pci_unmap_single(priv->pci_dev,
  3103. rxq->pool[i].dma_addr,
  3104. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3105. priv->alloc_rxb_skb--;
  3106. dev_kfree_skb(rxq->pool[i].skb);
  3107. rxq->pool[i].skb = NULL;
  3108. }
  3109. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3110. }
  3111. /* Set us so that we have processed and used all buffers, but have
  3112. * not restocked the Rx queue with fresh buffers */
  3113. rxq->read = rxq->write = 0;
  3114. rxq->free_count = 0;
  3115. spin_unlock_irqrestore(&rxq->lock, flags);
  3116. }
  3117. /* Convert linear signal-to-noise ratio into dB */
  3118. static u8 ratio2dB[100] = {
  3119. /* 0 1 2 3 4 5 6 7 8 9 */
  3120. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  3121. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  3122. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  3123. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  3124. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  3125. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  3126. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  3127. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  3128. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  3129. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  3130. };
  3131. /* Calculates a relative dB value from a ratio of linear
  3132. * (i.e. not dB) signal levels.
  3133. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  3134. int iwl3945_calc_db_from_ratio(int sig_ratio)
  3135. {
  3136. /* 1000:1 or higher just report as 60 dB */
  3137. if (sig_ratio >= 1000)
  3138. return 60;
  3139. /* 100:1 or higher, divide by 10 and use table,
  3140. * add 20 dB to make up for divide by 10 */
  3141. if (sig_ratio >= 100)
  3142. return 20 + (int)ratio2dB[sig_ratio/10];
  3143. /* We shouldn't see this */
  3144. if (sig_ratio < 1)
  3145. return 0;
  3146. /* Use table for ratios 1:1 - 99:1 */
  3147. return (int)ratio2dB[sig_ratio];
  3148. }
  3149. #define PERFECT_RSSI (-20) /* dBm */
  3150. #define WORST_RSSI (-95) /* dBm */
  3151. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  3152. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  3153. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  3154. * about formulas used below. */
  3155. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  3156. {
  3157. int sig_qual;
  3158. int degradation = PERFECT_RSSI - rssi_dbm;
  3159. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  3160. * as indicator; formula is (signal dbm - noise dbm).
  3161. * SNR at or above 40 is a great signal (100%).
  3162. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  3163. * Weakest usable signal is usually 10 - 15 dB SNR. */
  3164. if (noise_dbm) {
  3165. if (rssi_dbm - noise_dbm >= 40)
  3166. return 100;
  3167. else if (rssi_dbm < noise_dbm)
  3168. return 0;
  3169. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  3170. /* Else use just the signal level.
  3171. * This formula is a least squares fit of data points collected and
  3172. * compared with a reference system that had a percentage (%) display
  3173. * for signal quality. */
  3174. } else
  3175. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  3176. (15 * RSSI_RANGE + 62 * degradation)) /
  3177. (RSSI_RANGE * RSSI_RANGE);
  3178. if (sig_qual > 100)
  3179. sig_qual = 100;
  3180. else if (sig_qual < 1)
  3181. sig_qual = 0;
  3182. return sig_qual;
  3183. }
  3184. /**
  3185. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  3186. *
  3187. * Uses the priv->rx_handlers callback function array to invoke
  3188. * the appropriate handlers, including command responses,
  3189. * frame-received notifications, and other notifications.
  3190. */
  3191. static void iwl3945_rx_handle(struct iwl3945_priv *priv)
  3192. {
  3193. struct iwl3945_rx_mem_buffer *rxb;
  3194. struct iwl3945_rx_packet *pkt;
  3195. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3196. u32 r, i;
  3197. int reclaim;
  3198. unsigned long flags;
  3199. u8 fill_rx = 0;
  3200. u32 count = 8;
  3201. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  3202. * buffer that the driver may process (last buffer filled by ucode). */
  3203. r = iwl3945_hw_get_rx_read(priv);
  3204. i = rxq->read;
  3205. if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  3206. fill_rx = 1;
  3207. /* Rx interrupt, but nothing sent from uCode */
  3208. if (i == r)
  3209. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  3210. while (i != r) {
  3211. rxb = rxq->queue[i];
  3212. /* If an RXB doesn't have a Rx queue slot associated with it,
  3213. * then a bug has been introduced in the queue refilling
  3214. * routines -- catch it here */
  3215. BUG_ON(rxb == NULL);
  3216. rxq->queue[i] = NULL;
  3217. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
  3218. IWL_RX_BUF_SIZE,
  3219. PCI_DMA_FROMDEVICE);
  3220. pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  3221. /* Reclaim a command buffer only if this packet is a response
  3222. * to a (driver-originated) command.
  3223. * If the packet (e.g. Rx frame) originated from uCode,
  3224. * there is no command buffer to reclaim.
  3225. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  3226. * but apparently a few don't get set; catch them here. */
  3227. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  3228. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  3229. (pkt->hdr.cmd != REPLY_TX);
  3230. /* Based on type of command response or notification,
  3231. * handle those that need handling via function in
  3232. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  3233. if (priv->rx_handlers[pkt->hdr.cmd]) {
  3234. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3235. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  3236. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  3237. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  3238. } else {
  3239. /* No handling needed */
  3240. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3241. "r %d i %d No handler needed for %s, 0x%02x\n",
  3242. r, i, get_cmd_string(pkt->hdr.cmd),
  3243. pkt->hdr.cmd);
  3244. }
  3245. if (reclaim) {
  3246. /* Invoke any callbacks, transfer the skb to caller, and
  3247. * fire off the (possibly) blocking iwl3945_send_cmd()
  3248. * as we reclaim the driver command queue */
  3249. if (rxb && rxb->skb)
  3250. iwl3945_tx_cmd_complete(priv, rxb);
  3251. else
  3252. IWL_WARNING("Claim null rxb?\n");
  3253. }
  3254. /* For now we just don't re-use anything. We can tweak this
  3255. * later to try and re-use notification packets and SKBs that
  3256. * fail to Rx correctly */
  3257. if (rxb->skb != NULL) {
  3258. priv->alloc_rxb_skb--;
  3259. dev_kfree_skb_any(rxb->skb);
  3260. rxb->skb = NULL;
  3261. }
  3262. pci_unmap_single(priv->pci_dev, rxb->dma_addr,
  3263. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3264. spin_lock_irqsave(&rxq->lock, flags);
  3265. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  3266. spin_unlock_irqrestore(&rxq->lock, flags);
  3267. i = (i + 1) & RX_QUEUE_MASK;
  3268. /* If there are a lot of unused frames,
  3269. * restock the Rx queue so ucode won't assert. */
  3270. if (fill_rx) {
  3271. count++;
  3272. if (count >= 8) {
  3273. priv->rxq.read = i;
  3274. __iwl3945_rx_replenish(priv);
  3275. count = 0;
  3276. }
  3277. }
  3278. }
  3279. /* Backtrack one entry */
  3280. priv->rxq.read = i;
  3281. iwl3945_rx_queue_restock(priv);
  3282. }
  3283. /**
  3284. * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
  3285. */
  3286. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  3287. struct iwl3945_tx_queue *txq)
  3288. {
  3289. u32 reg = 0;
  3290. int rc = 0;
  3291. int txq_id = txq->q.id;
  3292. if (txq->need_update == 0)
  3293. return rc;
  3294. /* if we're trying to save power */
  3295. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3296. /* wake up nic if it's powered down ...
  3297. * uCode will wake up, and interrupt us again, so next
  3298. * time we'll skip this part. */
  3299. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3300. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3301. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  3302. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3303. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3304. return rc;
  3305. }
  3306. /* restore this queue's parameters in nic hardware. */
  3307. rc = iwl3945_grab_nic_access(priv);
  3308. if (rc)
  3309. return rc;
  3310. iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
  3311. txq->q.write_ptr | (txq_id << 8));
  3312. iwl3945_release_nic_access(priv);
  3313. /* else not in power-save mode, uCode will never sleep when we're
  3314. * trying to tx (during RFKILL, we're not trying to tx). */
  3315. } else
  3316. iwl3945_write32(priv, HBUS_TARG_WRPTR,
  3317. txq->q.write_ptr | (txq_id << 8));
  3318. txq->need_update = 0;
  3319. return rc;
  3320. }
  3321. #ifdef CONFIG_IWL3945_DEBUG
  3322. static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
  3323. {
  3324. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3325. iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3326. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3327. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3328. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3329. le32_to_cpu(rxon->filter_flags));
  3330. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3331. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3332. rxon->ofdm_basic_rates);
  3333. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3334. IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
  3335. IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  3336. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3337. }
  3338. #endif
  3339. static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
  3340. {
  3341. IWL_DEBUG_ISR("Enabling interrupts\n");
  3342. set_bit(STATUS_INT_ENABLED, &priv->status);
  3343. iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3344. }
  3345. /* call this function to flush any scheduled tasklet */
  3346. static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
  3347. {
  3348. /* wait to make sure we flush pending tasklet*/
  3349. synchronize_irq(priv->pci_dev->irq);
  3350. tasklet_kill(&priv->irq_tasklet);
  3351. }
  3352. static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
  3353. {
  3354. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3355. /* disable interrupts from uCode/NIC to host */
  3356. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3357. /* acknowledge/clear/reset any interrupts still pending
  3358. * from uCode or flow handler (Rx/Tx DMA) */
  3359. iwl3945_write32(priv, CSR_INT, 0xffffffff);
  3360. iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3361. IWL_DEBUG_ISR("Disabled interrupts\n");
  3362. }
  3363. static const char *desc_lookup(int i)
  3364. {
  3365. switch (i) {
  3366. case 1:
  3367. return "FAIL";
  3368. case 2:
  3369. return "BAD_PARAM";
  3370. case 3:
  3371. return "BAD_CHECKSUM";
  3372. case 4:
  3373. return "NMI_INTERRUPT";
  3374. case 5:
  3375. return "SYSASSERT";
  3376. case 6:
  3377. return "FATAL_ERROR";
  3378. }
  3379. return "UNKNOWN";
  3380. }
  3381. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3382. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3383. static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
  3384. {
  3385. u32 i;
  3386. u32 desc, time, count, base, data1;
  3387. u32 blink1, blink2, ilink1, ilink2;
  3388. int rc;
  3389. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3390. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3391. IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
  3392. return;
  3393. }
  3394. rc = iwl3945_grab_nic_access(priv);
  3395. if (rc) {
  3396. IWL_WARNING("Can not read from adapter at this time.\n");
  3397. return;
  3398. }
  3399. count = iwl3945_read_targ_mem(priv, base);
  3400. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3401. IWL_ERROR("Start IWL Error Log Dump:\n");
  3402. IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
  3403. }
  3404. IWL_ERROR("Desc Time asrtPC blink2 "
  3405. "ilink1 nmiPC Line\n");
  3406. for (i = ERROR_START_OFFSET;
  3407. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3408. i += ERROR_ELEM_SIZE) {
  3409. desc = iwl3945_read_targ_mem(priv, base + i);
  3410. time =
  3411. iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3412. blink1 =
  3413. iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3414. blink2 =
  3415. iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3416. ilink1 =
  3417. iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3418. ilink2 =
  3419. iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3420. data1 =
  3421. iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3422. IWL_ERROR
  3423. ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3424. desc_lookup(desc), desc, time, blink1, blink2,
  3425. ilink1, ilink2, data1);
  3426. }
  3427. iwl3945_release_nic_access(priv);
  3428. }
  3429. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3430. /**
  3431. * iwl3945_print_event_log - Dump error event log to syslog
  3432. *
  3433. * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
  3434. */
  3435. static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
  3436. u32 num_events, u32 mode)
  3437. {
  3438. u32 i;
  3439. u32 base; /* SRAM byte address of event log header */
  3440. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3441. u32 ptr; /* SRAM byte address of log data */
  3442. u32 ev, time, data; /* event log data */
  3443. if (num_events == 0)
  3444. return;
  3445. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3446. if (mode == 0)
  3447. event_size = 2 * sizeof(u32);
  3448. else
  3449. event_size = 3 * sizeof(u32);
  3450. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3451. /* "time" is actually "data" for mode 0 (no timestamp).
  3452. * place event id # at far right for easier visual parsing. */
  3453. for (i = 0; i < num_events; i++) {
  3454. ev = iwl3945_read_targ_mem(priv, ptr);
  3455. ptr += sizeof(u32);
  3456. time = iwl3945_read_targ_mem(priv, ptr);
  3457. ptr += sizeof(u32);
  3458. if (mode == 0)
  3459. IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
  3460. else {
  3461. data = iwl3945_read_targ_mem(priv, ptr);
  3462. ptr += sizeof(u32);
  3463. IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
  3464. }
  3465. }
  3466. }
  3467. static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
  3468. {
  3469. int rc;
  3470. u32 base; /* SRAM byte address of event log header */
  3471. u32 capacity; /* event log capacity in # entries */
  3472. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3473. u32 num_wraps; /* # times uCode wrapped to top of log */
  3474. u32 next_entry; /* index of next entry to be written by uCode */
  3475. u32 size; /* # entries that we'll print */
  3476. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3477. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3478. IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
  3479. return;
  3480. }
  3481. rc = iwl3945_grab_nic_access(priv);
  3482. if (rc) {
  3483. IWL_WARNING("Can not read from adapter at this time.\n");
  3484. return;
  3485. }
  3486. /* event log header */
  3487. capacity = iwl3945_read_targ_mem(priv, base);
  3488. mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3489. num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3490. next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3491. size = num_wraps ? capacity : next_entry;
  3492. /* bail out if nothing in log */
  3493. if (size == 0) {
  3494. IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
  3495. iwl3945_release_nic_access(priv);
  3496. return;
  3497. }
  3498. IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
  3499. size, num_wraps);
  3500. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3501. * i.e the next one that uCode would fill. */
  3502. if (num_wraps)
  3503. iwl3945_print_event_log(priv, next_entry,
  3504. capacity - next_entry, mode);
  3505. /* (then/else) start at top of log */
  3506. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3507. iwl3945_release_nic_access(priv);
  3508. }
  3509. /**
  3510. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3511. */
  3512. static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
  3513. {
  3514. /* Set the FW error flag -- cleared on iwl3945_down */
  3515. set_bit(STATUS_FW_ERROR, &priv->status);
  3516. /* Cancel currently queued command. */
  3517. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3518. #ifdef CONFIG_IWL3945_DEBUG
  3519. if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
  3520. iwl3945_dump_nic_error_log(priv);
  3521. iwl3945_dump_nic_event_log(priv);
  3522. iwl3945_print_rx_config_cmd(&priv->staging_rxon);
  3523. }
  3524. #endif
  3525. wake_up_interruptible(&priv->wait_command_queue);
  3526. /* Keep the restart process from trying to send host
  3527. * commands by clearing the INIT status bit */
  3528. clear_bit(STATUS_READY, &priv->status);
  3529. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3530. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3531. "Restarting adapter due to uCode error.\n");
  3532. if (iwl3945_is_associated(priv)) {
  3533. memcpy(&priv->recovery_rxon, &priv->active_rxon,
  3534. sizeof(priv->recovery_rxon));
  3535. priv->error_recovering = 1;
  3536. }
  3537. queue_work(priv->workqueue, &priv->restart);
  3538. }
  3539. }
  3540. static void iwl3945_error_recovery(struct iwl3945_priv *priv)
  3541. {
  3542. unsigned long flags;
  3543. memcpy(&priv->staging_rxon, &priv->recovery_rxon,
  3544. sizeof(priv->staging_rxon));
  3545. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3546. iwl3945_commit_rxon(priv);
  3547. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3548. spin_lock_irqsave(&priv->lock, flags);
  3549. priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
  3550. priv->error_recovering = 0;
  3551. spin_unlock_irqrestore(&priv->lock, flags);
  3552. }
  3553. static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
  3554. {
  3555. u32 inta, handled = 0;
  3556. u32 inta_fh;
  3557. unsigned long flags;
  3558. #ifdef CONFIG_IWL3945_DEBUG
  3559. u32 inta_mask;
  3560. #endif
  3561. spin_lock_irqsave(&priv->lock, flags);
  3562. /* Ack/clear/reset pending uCode interrupts.
  3563. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3564. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3565. inta = iwl3945_read32(priv, CSR_INT);
  3566. iwl3945_write32(priv, CSR_INT, inta);
  3567. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3568. * Any new interrupts that happen after this, either while we're
  3569. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3570. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3571. iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3572. #ifdef CONFIG_IWL3945_DEBUG
  3573. if (iwl3945_debug_level & IWL_DL_ISR) {
  3574. /* just for debug */
  3575. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3576. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3577. inta, inta_mask, inta_fh);
  3578. }
  3579. #endif
  3580. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3581. * atomic, make sure that inta covers all the interrupts that
  3582. * we've discovered, even if FH interrupt came in just after
  3583. * reading CSR_INT. */
  3584. if (inta_fh & CSR39_FH_INT_RX_MASK)
  3585. inta |= CSR_INT_BIT_FH_RX;
  3586. if (inta_fh & CSR39_FH_INT_TX_MASK)
  3587. inta |= CSR_INT_BIT_FH_TX;
  3588. /* Now service all interrupt bits discovered above. */
  3589. if (inta & CSR_INT_BIT_HW_ERR) {
  3590. IWL_ERROR("Microcode HW error detected. Restarting.\n");
  3591. /* Tell the device to stop sending interrupts */
  3592. iwl3945_disable_interrupts(priv);
  3593. iwl3945_irq_handle_error(priv);
  3594. handled |= CSR_INT_BIT_HW_ERR;
  3595. spin_unlock_irqrestore(&priv->lock, flags);
  3596. return;
  3597. }
  3598. #ifdef CONFIG_IWL3945_DEBUG
  3599. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3600. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  3601. if (inta & CSR_INT_BIT_SCD)
  3602. IWL_DEBUG_ISR("Scheduler finished to transmit "
  3603. "the frame/frames.\n");
  3604. /* Alive notification via Rx interrupt will do the real work */
  3605. if (inta & CSR_INT_BIT_ALIVE)
  3606. IWL_DEBUG_ISR("Alive interrupt\n");
  3607. }
  3608. #endif
  3609. /* Safely ignore these bits for debug checks below */
  3610. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  3611. /* Error detected by uCode */
  3612. if (inta & CSR_INT_BIT_SW_ERR) {
  3613. IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
  3614. inta);
  3615. iwl3945_irq_handle_error(priv);
  3616. handled |= CSR_INT_BIT_SW_ERR;
  3617. }
  3618. /* uCode wakes up after power-down sleep */
  3619. if (inta & CSR_INT_BIT_WAKEUP) {
  3620. IWL_DEBUG_ISR("Wakeup interrupt\n");
  3621. iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
  3622. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
  3623. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
  3624. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
  3625. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
  3626. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
  3627. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
  3628. handled |= CSR_INT_BIT_WAKEUP;
  3629. }
  3630. /* All uCode command responses, including Tx command responses,
  3631. * Rx "responses" (frame-received notification), and other
  3632. * notifications from uCode come through here*/
  3633. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  3634. iwl3945_rx_handle(priv);
  3635. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  3636. }
  3637. if (inta & CSR_INT_BIT_FH_TX) {
  3638. IWL_DEBUG_ISR("Tx interrupt\n");
  3639. iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  3640. if (!iwl3945_grab_nic_access(priv)) {
  3641. iwl3945_write_direct32(priv, FH39_TCSR_CREDIT
  3642. (FH39_SRVC_CHNL), 0x0);
  3643. iwl3945_release_nic_access(priv);
  3644. }
  3645. handled |= CSR_INT_BIT_FH_TX;
  3646. }
  3647. if (inta & ~handled)
  3648. IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
  3649. if (inta & ~CSR_INI_SET_MASK) {
  3650. IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
  3651. inta & ~CSR_INI_SET_MASK);
  3652. IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
  3653. }
  3654. /* Re-enable all interrupts */
  3655. /* only Re-enable if disabled by irq */
  3656. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3657. iwl3945_enable_interrupts(priv);
  3658. #ifdef CONFIG_IWL3945_DEBUG
  3659. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3660. inta = iwl3945_read32(priv, CSR_INT);
  3661. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3662. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3663. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  3664. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  3665. }
  3666. #endif
  3667. spin_unlock_irqrestore(&priv->lock, flags);
  3668. }
  3669. static irqreturn_t iwl3945_isr(int irq, void *data)
  3670. {
  3671. struct iwl3945_priv *priv = data;
  3672. u32 inta, inta_mask;
  3673. u32 inta_fh;
  3674. if (!priv)
  3675. return IRQ_NONE;
  3676. spin_lock(&priv->lock);
  3677. /* Disable (but don't clear!) interrupts here to avoid
  3678. * back-to-back ISRs and sporadic interrupts from our NIC.
  3679. * If we have something to service, the tasklet will re-enable ints.
  3680. * If we *don't* have something, we'll re-enable before leaving here. */
  3681. inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
  3682. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3683. /* Discover which interrupts are active/pending */
  3684. inta = iwl3945_read32(priv, CSR_INT);
  3685. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3686. /* Ignore interrupt if there's nothing in NIC to service.
  3687. * This may be due to IRQ shared with another device,
  3688. * or due to sporadic interrupts thrown from our NIC. */
  3689. if (!inta && !inta_fh) {
  3690. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  3691. goto none;
  3692. }
  3693. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  3694. /* Hardware disappeared */
  3695. IWL_WARNING("HARDWARE GONE?? INTA == 0x%08x\n", inta);
  3696. goto unplugged;
  3697. }
  3698. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3699. inta, inta_mask, inta_fh);
  3700. inta &= ~CSR_INT_BIT_SCD;
  3701. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  3702. if (likely(inta || inta_fh))
  3703. tasklet_schedule(&priv->irq_tasklet);
  3704. unplugged:
  3705. spin_unlock(&priv->lock);
  3706. return IRQ_HANDLED;
  3707. none:
  3708. /* re-enable interrupts here since we don't have anything to service. */
  3709. /* only Re-enable if disabled by irq */
  3710. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3711. iwl3945_enable_interrupts(priv);
  3712. spin_unlock(&priv->lock);
  3713. return IRQ_NONE;
  3714. }
  3715. /************************** EEPROM BANDS ****************************
  3716. *
  3717. * The iwl3945_eeprom_band definitions below provide the mapping from the
  3718. * EEPROM contents to the specific channel number supported for each
  3719. * band.
  3720. *
  3721. * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
  3722. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  3723. * The specific geography and calibration information for that channel
  3724. * is contained in the eeprom map itself.
  3725. *
  3726. * During init, we copy the eeprom information and channel map
  3727. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  3728. *
  3729. * channel_map_24/52 provides the index in the channel_info array for a
  3730. * given channel. We have to have two separate maps as there is channel
  3731. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  3732. * band_2
  3733. *
  3734. * A value of 0xff stored in the channel_map indicates that the channel
  3735. * is not supported by the hardware at all.
  3736. *
  3737. * A value of 0xfe in the channel_map indicates that the channel is not
  3738. * valid for Tx with the current hardware. This means that
  3739. * while the system can tune and receive on a given channel, it may not
  3740. * be able to associate or transmit any frames on that
  3741. * channel. There is no corresponding channel information for that
  3742. * entry.
  3743. *
  3744. *********************************************************************/
  3745. /* 2.4 GHz */
  3746. static const u8 iwl3945_eeprom_band_1[14] = {
  3747. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  3748. };
  3749. /* 5.2 GHz bands */
  3750. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  3751. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  3752. };
  3753. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  3754. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  3755. };
  3756. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  3757. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  3758. };
  3759. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  3760. 145, 149, 153, 157, 161, 165
  3761. };
  3762. static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
  3763. int *eeprom_ch_count,
  3764. const struct iwl3945_eeprom_channel
  3765. **eeprom_ch_info,
  3766. const u8 **eeprom_ch_index)
  3767. {
  3768. switch (band) {
  3769. case 1: /* 2.4GHz band */
  3770. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  3771. *eeprom_ch_info = priv->eeprom.band_1_channels;
  3772. *eeprom_ch_index = iwl3945_eeprom_band_1;
  3773. break;
  3774. case 2: /* 4.9GHz band */
  3775. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  3776. *eeprom_ch_info = priv->eeprom.band_2_channels;
  3777. *eeprom_ch_index = iwl3945_eeprom_band_2;
  3778. break;
  3779. case 3: /* 5.2GHz band */
  3780. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  3781. *eeprom_ch_info = priv->eeprom.band_3_channels;
  3782. *eeprom_ch_index = iwl3945_eeprom_band_3;
  3783. break;
  3784. case 4: /* 5.5GHz band */
  3785. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  3786. *eeprom_ch_info = priv->eeprom.band_4_channels;
  3787. *eeprom_ch_index = iwl3945_eeprom_band_4;
  3788. break;
  3789. case 5: /* 5.7GHz band */
  3790. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  3791. *eeprom_ch_info = priv->eeprom.band_5_channels;
  3792. *eeprom_ch_index = iwl3945_eeprom_band_5;
  3793. break;
  3794. default:
  3795. BUG();
  3796. return;
  3797. }
  3798. }
  3799. /**
  3800. * iwl3945_get_channel_info - Find driver's private channel info
  3801. *
  3802. * Based on band and channel number.
  3803. */
  3804. const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
  3805. enum ieee80211_band band, u16 channel)
  3806. {
  3807. int i;
  3808. switch (band) {
  3809. case IEEE80211_BAND_5GHZ:
  3810. for (i = 14; i < priv->channel_count; i++) {
  3811. if (priv->channel_info[i].channel == channel)
  3812. return &priv->channel_info[i];
  3813. }
  3814. break;
  3815. case IEEE80211_BAND_2GHZ:
  3816. if (channel >= 1 && channel <= 14)
  3817. return &priv->channel_info[channel - 1];
  3818. break;
  3819. case IEEE80211_NUM_BANDS:
  3820. WARN_ON(1);
  3821. }
  3822. return NULL;
  3823. }
  3824. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  3825. ? # x " " : "")
  3826. /**
  3827. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  3828. */
  3829. static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
  3830. {
  3831. int eeprom_ch_count = 0;
  3832. const u8 *eeprom_ch_index = NULL;
  3833. const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
  3834. int band, ch;
  3835. struct iwl3945_channel_info *ch_info;
  3836. if (priv->channel_count) {
  3837. IWL_DEBUG_INFO("Channel map already initialized.\n");
  3838. return 0;
  3839. }
  3840. if (priv->eeprom.version < 0x2f) {
  3841. IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
  3842. priv->eeprom.version);
  3843. return -EINVAL;
  3844. }
  3845. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  3846. priv->channel_count =
  3847. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  3848. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  3849. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  3850. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  3851. ARRAY_SIZE(iwl3945_eeprom_band_5);
  3852. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  3853. priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
  3854. priv->channel_count, GFP_KERNEL);
  3855. if (!priv->channel_info) {
  3856. IWL_ERROR("Could not allocate channel_info\n");
  3857. priv->channel_count = 0;
  3858. return -ENOMEM;
  3859. }
  3860. ch_info = priv->channel_info;
  3861. /* Loop through the 5 EEPROM bands adding them in order to the
  3862. * channel map we maintain (that contains additional information than
  3863. * what just in the EEPROM) */
  3864. for (band = 1; band <= 5; band++) {
  3865. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  3866. &eeprom_ch_info, &eeprom_ch_index);
  3867. /* Loop through each band adding each of the channels */
  3868. for (ch = 0; ch < eeprom_ch_count; ch++) {
  3869. ch_info->channel = eeprom_ch_index[ch];
  3870. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  3871. IEEE80211_BAND_5GHZ;
  3872. /* permanently store EEPROM's channel regulatory flags
  3873. * and max power in channel info database. */
  3874. ch_info->eeprom = eeprom_ch_info[ch];
  3875. /* Copy the run-time flags so they are there even on
  3876. * invalid channels */
  3877. ch_info->flags = eeprom_ch_info[ch].flags;
  3878. if (!(is_channel_valid(ch_info))) {
  3879. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  3880. "No traffic\n",
  3881. ch_info->channel,
  3882. ch_info->flags,
  3883. is_channel_a_band(ch_info) ?
  3884. "5.2" : "2.4");
  3885. ch_info++;
  3886. continue;
  3887. }
  3888. /* Initialize regulatory-based run-time data */
  3889. ch_info->max_power_avg = ch_info->curr_txpow =
  3890. eeprom_ch_info[ch].max_power_avg;
  3891. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  3892. ch_info->min_power = 0;
  3893. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  3894. " %ddBm): Ad-Hoc %ssupported\n",
  3895. ch_info->channel,
  3896. is_channel_a_band(ch_info) ?
  3897. "5.2" : "2.4",
  3898. CHECK_AND_PRINT(VALID),
  3899. CHECK_AND_PRINT(IBSS),
  3900. CHECK_AND_PRINT(ACTIVE),
  3901. CHECK_AND_PRINT(RADAR),
  3902. CHECK_AND_PRINT(WIDE),
  3903. CHECK_AND_PRINT(DFS),
  3904. eeprom_ch_info[ch].flags,
  3905. eeprom_ch_info[ch].max_power_avg,
  3906. ((eeprom_ch_info[ch].
  3907. flags & EEPROM_CHANNEL_IBSS)
  3908. && !(eeprom_ch_info[ch].
  3909. flags & EEPROM_CHANNEL_RADAR))
  3910. ? "" : "not ");
  3911. /* Set the user_txpower_limit to the highest power
  3912. * supported by any channel */
  3913. if (eeprom_ch_info[ch].max_power_avg >
  3914. priv->user_txpower_limit)
  3915. priv->user_txpower_limit =
  3916. eeprom_ch_info[ch].max_power_avg;
  3917. ch_info++;
  3918. }
  3919. }
  3920. /* Set up txpower settings in driver for all channels */
  3921. if (iwl3945_txpower_set_from_eeprom(priv))
  3922. return -EIO;
  3923. return 0;
  3924. }
  3925. /*
  3926. * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
  3927. */
  3928. static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
  3929. {
  3930. kfree(priv->channel_info);
  3931. priv->channel_count = 0;
  3932. }
  3933. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  3934. * sending probe req. This should be set long enough to hear probe responses
  3935. * from more than one AP. */
  3936. #define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
  3937. #define IWL_ACTIVE_DWELL_TIME_52 (20)
  3938. #define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
  3939. #define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
  3940. /* For faster active scanning, scan will move to the next channel if fewer than
  3941. * PLCP_QUIET_THRESH packets are heard on this channel within
  3942. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  3943. * time if it's a quiet channel (nothing responded to our probe, and there's
  3944. * no other traffic).
  3945. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  3946. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  3947. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */
  3948. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  3949. * Must be set longer than active dwell time.
  3950. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  3951. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  3952. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  3953. #define IWL_PASSIVE_DWELL_BASE (100)
  3954. #define IWL_CHANNEL_TUNE_TIME 5
  3955. #define IWL_SCAN_PROBE_MASK(n) (BIT(n) | (BIT(n) - BIT(1)))
  3956. static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
  3957. enum ieee80211_band band,
  3958. u8 n_probes)
  3959. {
  3960. if (band == IEEE80211_BAND_5GHZ)
  3961. return IWL_ACTIVE_DWELL_TIME_52 +
  3962. IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
  3963. else
  3964. return IWL_ACTIVE_DWELL_TIME_24 +
  3965. IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
  3966. }
  3967. static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
  3968. enum ieee80211_band band)
  3969. {
  3970. u16 passive = (band == IEEE80211_BAND_2GHZ) ?
  3971. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  3972. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  3973. if (iwl3945_is_associated(priv)) {
  3974. /* If we're associated, we clamp the maximum passive
  3975. * dwell time to be 98% of the beacon interval (minus
  3976. * 2 * channel tune time) */
  3977. passive = priv->beacon_int;
  3978. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  3979. passive = IWL_PASSIVE_DWELL_BASE;
  3980. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  3981. }
  3982. return passive;
  3983. }
  3984. static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
  3985. enum ieee80211_band band,
  3986. u8 is_active, u8 n_probes,
  3987. struct iwl3945_scan_channel *scan_ch)
  3988. {
  3989. const struct ieee80211_channel *channels = NULL;
  3990. const struct ieee80211_supported_band *sband;
  3991. const struct iwl3945_channel_info *ch_info;
  3992. u16 passive_dwell = 0;
  3993. u16 active_dwell = 0;
  3994. int added, i;
  3995. sband = iwl3945_get_band(priv, band);
  3996. if (!sband)
  3997. return 0;
  3998. channels = sband->channels;
  3999. active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes);
  4000. passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
  4001. if (passive_dwell <= active_dwell)
  4002. passive_dwell = active_dwell + 1;
  4003. for (i = 0, added = 0; i < sband->n_channels; i++) {
  4004. if (channels[i].flags & IEEE80211_CHAN_DISABLED)
  4005. continue;
  4006. scan_ch->channel = channels[i].hw_value;
  4007. ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
  4008. if (!is_channel_valid(ch_info)) {
  4009. IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
  4010. scan_ch->channel);
  4011. continue;
  4012. }
  4013. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  4014. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  4015. /* If passive , set up for auto-switch
  4016. * and use long active_dwell time.
  4017. */
  4018. if (!is_active || is_channel_passive(ch_info) ||
  4019. (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
  4020. scan_ch->type = 0; /* passive */
  4021. if (IWL_UCODE_API(priv->ucode_ver) == 1)
  4022. scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
  4023. } else {
  4024. scan_ch->type = 1; /* active */
  4025. }
  4026. /* Set direct probe bits. These may be used both for active
  4027. * scan channels (probes gets sent right away),
  4028. * or for passive channels (probes get se sent only after
  4029. * hearing clear Rx packet).*/
  4030. if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
  4031. if (n_probes)
  4032. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  4033. } else {
  4034. /* uCode v1 does not allow setting direct probe bits on
  4035. * passive channel. */
  4036. if ((scan_ch->type & 1) && n_probes)
  4037. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  4038. }
  4039. /* Set txpower levels to defaults */
  4040. scan_ch->tpc.dsp_atten = 110;
  4041. /* scan_pwr_info->tpc.dsp_atten; */
  4042. /*scan_pwr_info->tpc.tx_gain; */
  4043. if (band == IEEE80211_BAND_5GHZ)
  4044. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  4045. else {
  4046. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  4047. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  4048. * power level:
  4049. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  4050. */
  4051. }
  4052. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  4053. scan_ch->channel,
  4054. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  4055. (scan_ch->type & 1) ?
  4056. active_dwell : passive_dwell);
  4057. scan_ch++;
  4058. added++;
  4059. }
  4060. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  4061. return added;
  4062. }
  4063. static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
  4064. struct ieee80211_rate *rates)
  4065. {
  4066. int i;
  4067. for (i = 0; i < IWL_RATE_COUNT; i++) {
  4068. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  4069. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  4070. rates[i].hw_value_short = i;
  4071. rates[i].flags = 0;
  4072. if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  4073. /*
  4074. * If CCK != 1M then set short preamble rate flag.
  4075. */
  4076. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  4077. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  4078. }
  4079. }
  4080. }
  4081. /**
  4082. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  4083. */
  4084. static int iwl3945_init_geos(struct iwl3945_priv *priv)
  4085. {
  4086. struct iwl3945_channel_info *ch;
  4087. struct ieee80211_supported_band *sband;
  4088. struct ieee80211_channel *channels;
  4089. struct ieee80211_channel *geo_ch;
  4090. struct ieee80211_rate *rates;
  4091. int i = 0;
  4092. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  4093. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  4094. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  4095. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4096. return 0;
  4097. }
  4098. channels = kzalloc(sizeof(struct ieee80211_channel) *
  4099. priv->channel_count, GFP_KERNEL);
  4100. if (!channels)
  4101. return -ENOMEM;
  4102. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  4103. GFP_KERNEL);
  4104. if (!rates) {
  4105. kfree(channels);
  4106. return -ENOMEM;
  4107. }
  4108. /* 5.2GHz channels start after the 2.4GHz channels */
  4109. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4110. sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  4111. /* just OFDM */
  4112. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  4113. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  4114. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4115. sband->channels = channels;
  4116. /* OFDM & CCK */
  4117. sband->bitrates = rates;
  4118. sband->n_bitrates = IWL_RATE_COUNT;
  4119. priv->ieee_channels = channels;
  4120. priv->ieee_rates = rates;
  4121. iwl3945_init_hw_rates(priv, rates);
  4122. for (i = 0; i < priv->channel_count; i++) {
  4123. ch = &priv->channel_info[i];
  4124. /* FIXME: might be removed if scan is OK*/
  4125. if (!is_channel_valid(ch))
  4126. continue;
  4127. if (is_channel_a_band(ch))
  4128. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4129. else
  4130. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4131. geo_ch = &sband->channels[sband->n_channels++];
  4132. geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
  4133. geo_ch->max_power = ch->max_power_avg;
  4134. geo_ch->max_antenna_gain = 0xff;
  4135. geo_ch->hw_value = ch->channel;
  4136. if (is_channel_valid(ch)) {
  4137. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  4138. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  4139. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  4140. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  4141. if (ch->flags & EEPROM_CHANNEL_RADAR)
  4142. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  4143. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  4144. priv->max_channel_txpower_limit =
  4145. ch->max_power_avg;
  4146. } else {
  4147. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  4148. }
  4149. /* Save flags for reg domain usage */
  4150. geo_ch->orig_flags = geo_ch->flags;
  4151. IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
  4152. ch->channel, geo_ch->center_freq,
  4153. is_channel_a_band(ch) ? "5.2" : "2.4",
  4154. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  4155. "restricted" : "valid",
  4156. geo_ch->flags);
  4157. }
  4158. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  4159. priv->cfg->sku & IWL_SKU_A) {
  4160. printk(KERN_INFO DRV_NAME
  4161. ": Incorrectly detected BG card as ABG. Please send "
  4162. "your PCI ID 0x%04X:0x%04X to maintainer.\n",
  4163. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  4164. priv->cfg->sku &= ~IWL_SKU_A;
  4165. }
  4166. printk(KERN_INFO DRV_NAME
  4167. ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  4168. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  4169. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  4170. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  4171. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  4172. &priv->bands[IEEE80211_BAND_2GHZ];
  4173. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  4174. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  4175. &priv->bands[IEEE80211_BAND_5GHZ];
  4176. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4177. return 0;
  4178. }
  4179. /*
  4180. * iwl3945_free_geos - undo allocations in iwl3945_init_geos
  4181. */
  4182. static void iwl3945_free_geos(struct iwl3945_priv *priv)
  4183. {
  4184. kfree(priv->ieee_channels);
  4185. kfree(priv->ieee_rates);
  4186. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4187. }
  4188. /******************************************************************************
  4189. *
  4190. * uCode download functions
  4191. *
  4192. ******************************************************************************/
  4193. static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
  4194. {
  4195. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  4196. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  4197. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4198. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  4199. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4200. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4201. }
  4202. /**
  4203. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  4204. * looking at all data.
  4205. */
  4206. static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4207. {
  4208. u32 val;
  4209. u32 save_len = len;
  4210. int rc = 0;
  4211. u32 errcnt;
  4212. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4213. rc = iwl3945_grab_nic_access(priv);
  4214. if (rc)
  4215. return rc;
  4216. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
  4217. errcnt = 0;
  4218. for (; len > 0; len -= sizeof(u32), image++) {
  4219. /* read data comes through single port, auto-incr addr */
  4220. /* NOTE: Use the debugless read so we don't flood kernel log
  4221. * if IWL_DL_IO is set */
  4222. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4223. if (val != le32_to_cpu(*image)) {
  4224. IWL_ERROR("uCode INST section is invalid at "
  4225. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4226. save_len - len, val, le32_to_cpu(*image));
  4227. rc = -EIO;
  4228. errcnt++;
  4229. if (errcnt >= 20)
  4230. break;
  4231. }
  4232. }
  4233. iwl3945_release_nic_access(priv);
  4234. if (!errcnt)
  4235. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  4236. return rc;
  4237. }
  4238. /**
  4239. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  4240. * using sample data 100 bytes apart. If these sample points are good,
  4241. * it's a pretty good bet that everything between them is good, too.
  4242. */
  4243. static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4244. {
  4245. u32 val;
  4246. int rc = 0;
  4247. u32 errcnt = 0;
  4248. u32 i;
  4249. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4250. rc = iwl3945_grab_nic_access(priv);
  4251. if (rc)
  4252. return rc;
  4253. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  4254. /* read data comes through single port, auto-incr addr */
  4255. /* NOTE: Use the debugless read so we don't flood kernel log
  4256. * if IWL_DL_IO is set */
  4257. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4258. i + RTC_INST_LOWER_BOUND);
  4259. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4260. if (val != le32_to_cpu(*image)) {
  4261. #if 0 /* Enable this if you want to see details */
  4262. IWL_ERROR("uCode INST section is invalid at "
  4263. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4264. i, val, *image);
  4265. #endif
  4266. rc = -EIO;
  4267. errcnt++;
  4268. if (errcnt >= 3)
  4269. break;
  4270. }
  4271. }
  4272. iwl3945_release_nic_access(priv);
  4273. return rc;
  4274. }
  4275. /**
  4276. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  4277. * and verify its contents
  4278. */
  4279. static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
  4280. {
  4281. __le32 *image;
  4282. u32 len;
  4283. int rc = 0;
  4284. /* Try bootstrap */
  4285. image = (__le32 *)priv->ucode_boot.v_addr;
  4286. len = priv->ucode_boot.len;
  4287. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4288. if (rc == 0) {
  4289. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  4290. return 0;
  4291. }
  4292. /* Try initialize */
  4293. image = (__le32 *)priv->ucode_init.v_addr;
  4294. len = priv->ucode_init.len;
  4295. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4296. if (rc == 0) {
  4297. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  4298. return 0;
  4299. }
  4300. /* Try runtime/protocol */
  4301. image = (__le32 *)priv->ucode_code.v_addr;
  4302. len = priv->ucode_code.len;
  4303. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4304. if (rc == 0) {
  4305. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  4306. return 0;
  4307. }
  4308. IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  4309. /* Since nothing seems to match, show first several data entries in
  4310. * instruction SRAM, so maybe visual inspection will give a clue.
  4311. * Selection of bootstrap image (vs. other images) is arbitrary. */
  4312. image = (__le32 *)priv->ucode_boot.v_addr;
  4313. len = priv->ucode_boot.len;
  4314. rc = iwl3945_verify_inst_full(priv, image, len);
  4315. return rc;
  4316. }
  4317. /* check contents of special bootstrap uCode SRAM */
  4318. static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
  4319. {
  4320. __le32 *image = priv->ucode_boot.v_addr;
  4321. u32 len = priv->ucode_boot.len;
  4322. u32 reg;
  4323. u32 val;
  4324. IWL_DEBUG_INFO("Begin verify bsm\n");
  4325. /* verify BSM SRAM contents */
  4326. val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
  4327. for (reg = BSM_SRAM_LOWER_BOUND;
  4328. reg < BSM_SRAM_LOWER_BOUND + len;
  4329. reg += sizeof(u32), image++) {
  4330. val = iwl3945_read_prph(priv, reg);
  4331. if (val != le32_to_cpu(*image)) {
  4332. IWL_ERROR("BSM uCode verification failed at "
  4333. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  4334. BSM_SRAM_LOWER_BOUND,
  4335. reg - BSM_SRAM_LOWER_BOUND, len,
  4336. val, le32_to_cpu(*image));
  4337. return -EIO;
  4338. }
  4339. }
  4340. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  4341. return 0;
  4342. }
  4343. /**
  4344. * iwl3945_load_bsm - Load bootstrap instructions
  4345. *
  4346. * BSM operation:
  4347. *
  4348. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  4349. * in special SRAM that does not power down during RFKILL. When powering back
  4350. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  4351. * the bootstrap program into the on-board processor, and starts it.
  4352. *
  4353. * The bootstrap program loads (via DMA) instructions and data for a new
  4354. * program from host DRAM locations indicated by the host driver in the
  4355. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  4356. * automatically.
  4357. *
  4358. * When initializing the NIC, the host driver points the BSM to the
  4359. * "initialize" uCode image. This uCode sets up some internal data, then
  4360. * notifies host via "initialize alive" that it is complete.
  4361. *
  4362. * The host then replaces the BSM_DRAM_* pointer values to point to the
  4363. * normal runtime uCode instructions and a backup uCode data cache buffer
  4364. * (filled initially with starting data values for the on-board processor),
  4365. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  4366. * which begins normal operation.
  4367. *
  4368. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  4369. * the backup data cache in DRAM before SRAM is powered down.
  4370. *
  4371. * When powering back up, the BSM loads the bootstrap program. This reloads
  4372. * the runtime uCode instructions and the backup data cache into SRAM,
  4373. * and re-launches the runtime uCode from where it left off.
  4374. */
  4375. static int iwl3945_load_bsm(struct iwl3945_priv *priv)
  4376. {
  4377. __le32 *image = priv->ucode_boot.v_addr;
  4378. u32 len = priv->ucode_boot.len;
  4379. dma_addr_t pinst;
  4380. dma_addr_t pdata;
  4381. u32 inst_len;
  4382. u32 data_len;
  4383. int rc;
  4384. int i;
  4385. u32 done;
  4386. u32 reg_offset;
  4387. IWL_DEBUG_INFO("Begin load bsm\n");
  4388. /* make sure bootstrap program is no larger than BSM's SRAM size */
  4389. if (len > IWL_MAX_BSM_SIZE)
  4390. return -EINVAL;
  4391. /* Tell bootstrap uCode where to find the "Initialize" uCode
  4392. * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
  4393. * NOTE: iwl3945_initialize_alive_start() will replace these values,
  4394. * after the "initialize" uCode has run, to point to
  4395. * runtime/protocol instructions and backup data cache. */
  4396. pinst = priv->ucode_init.p_addr;
  4397. pdata = priv->ucode_init_data.p_addr;
  4398. inst_len = priv->ucode_init.len;
  4399. data_len = priv->ucode_init_data.len;
  4400. rc = iwl3945_grab_nic_access(priv);
  4401. if (rc)
  4402. return rc;
  4403. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4404. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4405. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  4406. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  4407. /* Fill BSM memory with bootstrap instructions */
  4408. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  4409. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  4410. reg_offset += sizeof(u32), image++)
  4411. _iwl3945_write_prph(priv, reg_offset,
  4412. le32_to_cpu(*image));
  4413. rc = iwl3945_verify_bsm(priv);
  4414. if (rc) {
  4415. iwl3945_release_nic_access(priv);
  4416. return rc;
  4417. }
  4418. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  4419. iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  4420. iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
  4421. RTC_INST_LOWER_BOUND);
  4422. iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  4423. /* Load bootstrap code into instruction SRAM now,
  4424. * to prepare to load "initialize" uCode */
  4425. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4426. BSM_WR_CTRL_REG_BIT_START);
  4427. /* Wait for load of bootstrap uCode to finish */
  4428. for (i = 0; i < 100; i++) {
  4429. done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
  4430. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  4431. break;
  4432. udelay(10);
  4433. }
  4434. if (i < 100)
  4435. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  4436. else {
  4437. IWL_ERROR("BSM write did not complete!\n");
  4438. return -EIO;
  4439. }
  4440. /* Enable future boot loads whenever power management unit triggers it
  4441. * (e.g. when powering back up after power-save shutdown) */
  4442. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4443. BSM_WR_CTRL_REG_BIT_START_EN);
  4444. iwl3945_release_nic_access(priv);
  4445. return 0;
  4446. }
  4447. static void iwl3945_nic_start(struct iwl3945_priv *priv)
  4448. {
  4449. /* Remove all resets to allow NIC to operate */
  4450. iwl3945_write32(priv, CSR_RESET, 0);
  4451. }
  4452. /**
  4453. * iwl3945_read_ucode - Read uCode images from disk file.
  4454. *
  4455. * Copy into buffers for card to fetch via bus-mastering
  4456. */
  4457. static int iwl3945_read_ucode(struct iwl3945_priv *priv)
  4458. {
  4459. struct iwl3945_ucode *ucode;
  4460. int ret = -EINVAL, index;
  4461. const struct firmware *ucode_raw;
  4462. /* firmware file name contains uCode/driver compatibility version */
  4463. const char *name_pre = priv->cfg->fw_name_pre;
  4464. const unsigned int api_max = priv->cfg->ucode_api_max;
  4465. const unsigned int api_min = priv->cfg->ucode_api_min;
  4466. char buf[25];
  4467. u8 *src;
  4468. size_t len;
  4469. u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4470. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4471. * request_firmware() is synchronous, file is in memory on return. */
  4472. for (index = api_max; index >= api_min; index--) {
  4473. sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
  4474. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  4475. if (ret < 0) {
  4476. IWL_ERROR("%s firmware file req failed: Reason %d\n",
  4477. buf, ret);
  4478. if (ret == -ENOENT)
  4479. continue;
  4480. else
  4481. goto error;
  4482. } else {
  4483. if (index < api_max)
  4484. IWL_ERROR("Loaded firmware %s, which is deprecated. Please use API v%u instead.\n",
  4485. buf, api_max);
  4486. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4487. buf, ucode_raw->size);
  4488. break;
  4489. }
  4490. }
  4491. if (ret < 0)
  4492. goto error;
  4493. /* Make sure that we got at least our header! */
  4494. if (ucode_raw->size < sizeof(*ucode)) {
  4495. IWL_ERROR("File size way too small!\n");
  4496. ret = -EINVAL;
  4497. goto err_release;
  4498. }
  4499. /* Data from ucode file: header followed by uCode images */
  4500. ucode = (void *)ucode_raw->data;
  4501. priv->ucode_ver = le32_to_cpu(ucode->ver);
  4502. api_ver = IWL_UCODE_API(priv->ucode_ver);
  4503. inst_size = le32_to_cpu(ucode->inst_size);
  4504. data_size = le32_to_cpu(ucode->data_size);
  4505. init_size = le32_to_cpu(ucode->init_size);
  4506. init_data_size = le32_to_cpu(ucode->init_data_size);
  4507. boot_size = le32_to_cpu(ucode->boot_size);
  4508. /* api_ver should match the api version forming part of the
  4509. * firmware filename ... but we don't check for that and only rely
  4510. * on the API version read from firware header from here on forward */
  4511. if (api_ver < api_min || api_ver > api_max) {
  4512. IWL_ERROR("Driver unable to support your firmware API. "
  4513. "Driver supports v%u, firmware is v%u.\n",
  4514. api_max, api_ver);
  4515. priv->ucode_ver = 0;
  4516. ret = -EINVAL;
  4517. goto err_release;
  4518. }
  4519. if (api_ver != api_max)
  4520. IWL_ERROR("Firmware has old API version. Expected %u, "
  4521. "got %u. New firmware can be obtained "
  4522. "from http://www.intellinuxwireless.org.\n",
  4523. api_max, api_ver);
  4524. printk(KERN_INFO DRV_NAME " loaded firmware version %u.%u.%u.%u\n",
  4525. IWL_UCODE_MAJOR(priv->ucode_ver),
  4526. IWL_UCODE_MINOR(priv->ucode_ver),
  4527. IWL_UCODE_API(priv->ucode_ver),
  4528. IWL_UCODE_SERIAL(priv->ucode_ver));
  4529. IWL_DEBUG_INFO("f/w package hdr ucode version raw = 0x%x\n",
  4530. priv->ucode_ver);
  4531. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4532. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4533. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4534. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4535. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4536. /* Verify size of file vs. image size info in file's header */
  4537. if (ucode_raw->size < sizeof(*ucode) +
  4538. inst_size + data_size + init_size +
  4539. init_data_size + boot_size) {
  4540. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4541. (int)ucode_raw->size);
  4542. ret = -EINVAL;
  4543. goto err_release;
  4544. }
  4545. /* Verify that uCode images will fit in card's SRAM */
  4546. if (inst_size > IWL_MAX_INST_SIZE) {
  4547. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4548. inst_size);
  4549. ret = -EINVAL;
  4550. goto err_release;
  4551. }
  4552. if (data_size > IWL_MAX_DATA_SIZE) {
  4553. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4554. data_size);
  4555. ret = -EINVAL;
  4556. goto err_release;
  4557. }
  4558. if (init_size > IWL_MAX_INST_SIZE) {
  4559. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4560. init_size);
  4561. ret = -EINVAL;
  4562. goto err_release;
  4563. }
  4564. if (init_data_size > IWL_MAX_DATA_SIZE) {
  4565. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4566. init_data_size);
  4567. ret = -EINVAL;
  4568. goto err_release;
  4569. }
  4570. if (boot_size > IWL_MAX_BSM_SIZE) {
  4571. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4572. boot_size);
  4573. ret = -EINVAL;
  4574. goto err_release;
  4575. }
  4576. /* Allocate ucode buffers for card's bus-master loading ... */
  4577. /* Runtime instructions and 2 copies of data:
  4578. * 1) unmodified from disk
  4579. * 2) backup cache for save/restore during power-downs */
  4580. priv->ucode_code.len = inst_size;
  4581. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4582. priv->ucode_data.len = data_size;
  4583. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4584. priv->ucode_data_backup.len = data_size;
  4585. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4586. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4587. !priv->ucode_data_backup.v_addr)
  4588. goto err_pci_alloc;
  4589. /* Initialization instructions and data */
  4590. if (init_size && init_data_size) {
  4591. priv->ucode_init.len = init_size;
  4592. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4593. priv->ucode_init_data.len = init_data_size;
  4594. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4595. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4596. goto err_pci_alloc;
  4597. }
  4598. /* Bootstrap (instructions only, no data) */
  4599. if (boot_size) {
  4600. priv->ucode_boot.len = boot_size;
  4601. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4602. if (!priv->ucode_boot.v_addr)
  4603. goto err_pci_alloc;
  4604. }
  4605. /* Copy images into buffers for card's bus-master reads ... */
  4606. /* Runtime instructions (first block of data in file) */
  4607. src = &ucode->data[0];
  4608. len = priv->ucode_code.len;
  4609. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4610. memcpy(priv->ucode_code.v_addr, src, len);
  4611. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4612. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4613. /* Runtime data (2nd block)
  4614. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4615. src = &ucode->data[inst_size];
  4616. len = priv->ucode_data.len;
  4617. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4618. memcpy(priv->ucode_data.v_addr, src, len);
  4619. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4620. /* Initialization instructions (3rd block) */
  4621. if (init_size) {
  4622. src = &ucode->data[inst_size + data_size];
  4623. len = priv->ucode_init.len;
  4624. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4625. len);
  4626. memcpy(priv->ucode_init.v_addr, src, len);
  4627. }
  4628. /* Initialization data (4th block) */
  4629. if (init_data_size) {
  4630. src = &ucode->data[inst_size + data_size + init_size];
  4631. len = priv->ucode_init_data.len;
  4632. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  4633. (int)len);
  4634. memcpy(priv->ucode_init_data.v_addr, src, len);
  4635. }
  4636. /* Bootstrap instructions (5th block) */
  4637. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  4638. len = priv->ucode_boot.len;
  4639. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  4640. (int)len);
  4641. memcpy(priv->ucode_boot.v_addr, src, len);
  4642. /* We have our copies now, allow OS release its copies */
  4643. release_firmware(ucode_raw);
  4644. return 0;
  4645. err_pci_alloc:
  4646. IWL_ERROR("failed to allocate pci memory\n");
  4647. ret = -ENOMEM;
  4648. iwl3945_dealloc_ucode_pci(priv);
  4649. err_release:
  4650. release_firmware(ucode_raw);
  4651. error:
  4652. return ret;
  4653. }
  4654. /**
  4655. * iwl3945_set_ucode_ptrs - Set uCode address location
  4656. *
  4657. * Tell initialization uCode where to find runtime uCode.
  4658. *
  4659. * BSM registers initially contain pointers to initialization uCode.
  4660. * We need to replace them to load runtime uCode inst and data,
  4661. * and to save runtime data when powering down.
  4662. */
  4663. static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
  4664. {
  4665. dma_addr_t pinst;
  4666. dma_addr_t pdata;
  4667. int rc = 0;
  4668. unsigned long flags;
  4669. /* bits 31:0 for 3945 */
  4670. pinst = priv->ucode_code.p_addr;
  4671. pdata = priv->ucode_data_backup.p_addr;
  4672. spin_lock_irqsave(&priv->lock, flags);
  4673. rc = iwl3945_grab_nic_access(priv);
  4674. if (rc) {
  4675. spin_unlock_irqrestore(&priv->lock, flags);
  4676. return rc;
  4677. }
  4678. /* Tell bootstrap uCode where to find image to load */
  4679. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4680. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4681. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  4682. priv->ucode_data.len);
  4683. /* Inst byte count must be last to set up, bit 31 signals uCode
  4684. * that all new ptr/size info is in place */
  4685. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  4686. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  4687. iwl3945_release_nic_access(priv);
  4688. spin_unlock_irqrestore(&priv->lock, flags);
  4689. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  4690. return rc;
  4691. }
  4692. /**
  4693. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  4694. *
  4695. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  4696. *
  4697. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  4698. */
  4699. static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
  4700. {
  4701. /* Check alive response for "valid" sign from uCode */
  4702. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  4703. /* We had an error bringing up the hardware, so take it
  4704. * all the way back down so we can try again */
  4705. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  4706. goto restart;
  4707. }
  4708. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  4709. * This is a paranoid check, because we would not have gotten the
  4710. * "initialize" alive if code weren't properly loaded. */
  4711. if (iwl3945_verify_ucode(priv)) {
  4712. /* Runtime instruction load was bad;
  4713. * take it all the way back down so we can try again */
  4714. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  4715. goto restart;
  4716. }
  4717. /* Send pointers to protocol/runtime uCode image ... init code will
  4718. * load and launch runtime uCode, which will send us another "Alive"
  4719. * notification. */
  4720. IWL_DEBUG_INFO("Initialization Alive received.\n");
  4721. if (iwl3945_set_ucode_ptrs(priv)) {
  4722. /* Runtime instruction load won't happen;
  4723. * take it all the way back down so we can try again */
  4724. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  4725. goto restart;
  4726. }
  4727. return;
  4728. restart:
  4729. queue_work(priv->workqueue, &priv->restart);
  4730. }
  4731. /* temporary */
  4732. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw,
  4733. struct sk_buff *skb);
  4734. /**
  4735. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  4736. * from protocol/runtime uCode (initialization uCode's
  4737. * Alive gets handled by iwl3945_init_alive_start()).
  4738. */
  4739. static void iwl3945_alive_start(struct iwl3945_priv *priv)
  4740. {
  4741. int rc = 0;
  4742. int thermal_spin = 0;
  4743. u32 rfkill;
  4744. IWL_DEBUG_INFO("Runtime Alive received.\n");
  4745. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  4746. /* We had an error bringing up the hardware, so take it
  4747. * all the way back down so we can try again */
  4748. IWL_DEBUG_INFO("Alive failed.\n");
  4749. goto restart;
  4750. }
  4751. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  4752. * This is a paranoid check, because we would not have gotten the
  4753. * "runtime" alive if code weren't properly loaded. */
  4754. if (iwl3945_verify_ucode(priv)) {
  4755. /* Runtime instruction load was bad;
  4756. * take it all the way back down so we can try again */
  4757. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  4758. goto restart;
  4759. }
  4760. iwl3945_clear_stations_table(priv);
  4761. rc = iwl3945_grab_nic_access(priv);
  4762. if (rc) {
  4763. IWL_WARNING("Can not read RFKILL status from adapter\n");
  4764. return;
  4765. }
  4766. rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
  4767. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  4768. iwl3945_release_nic_access(priv);
  4769. if (rfkill & 0x1) {
  4770. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4771. /* if RFKILL is not on, then wait for thermal
  4772. * sensor in adapter to kick in */
  4773. while (iwl3945_hw_get_temperature(priv) == 0) {
  4774. thermal_spin++;
  4775. udelay(10);
  4776. }
  4777. if (thermal_spin)
  4778. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  4779. thermal_spin * 10);
  4780. } else
  4781. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4782. /* After the ALIVE response, we can send commands to 3945 uCode */
  4783. set_bit(STATUS_ALIVE, &priv->status);
  4784. /* Clear out the uCode error bit if it is set */
  4785. clear_bit(STATUS_FW_ERROR, &priv->status);
  4786. if (iwl3945_is_rfkill(priv))
  4787. return;
  4788. ieee80211_wake_queues(priv->hw);
  4789. priv->active_rate = priv->rates_mask;
  4790. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  4791. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  4792. if (iwl3945_is_associated(priv)) {
  4793. struct iwl3945_rxon_cmd *active_rxon =
  4794. (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
  4795. memcpy(&priv->staging_rxon, &priv->active_rxon,
  4796. sizeof(priv->staging_rxon));
  4797. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4798. } else {
  4799. /* Initialize our rx_config data */
  4800. iwl3945_connection_init_rx_config(priv, priv->iw_mode);
  4801. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  4802. }
  4803. /* Configure Bluetooth device coexistence support */
  4804. iwl3945_send_bt_config(priv);
  4805. /* Configure the adapter for unassociated operation */
  4806. iwl3945_commit_rxon(priv);
  4807. iwl3945_reg_txpower_periodic(priv);
  4808. iwl3945_led_register(priv);
  4809. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  4810. set_bit(STATUS_READY, &priv->status);
  4811. wake_up_interruptible(&priv->wait_command_queue);
  4812. if (priv->error_recovering)
  4813. iwl3945_error_recovery(priv);
  4814. /* reassociate for ADHOC mode */
  4815. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  4816. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  4817. priv->vif);
  4818. if (beacon)
  4819. iwl3945_mac_beacon_update(priv->hw, beacon);
  4820. }
  4821. return;
  4822. restart:
  4823. queue_work(priv->workqueue, &priv->restart);
  4824. }
  4825. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
  4826. static void __iwl3945_down(struct iwl3945_priv *priv)
  4827. {
  4828. unsigned long flags;
  4829. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  4830. struct ieee80211_conf *conf = NULL;
  4831. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  4832. conf = ieee80211_get_hw_conf(priv->hw);
  4833. if (!exit_pending)
  4834. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4835. iwl3945_led_unregister(priv);
  4836. iwl3945_clear_stations_table(priv);
  4837. /* Unblock any waiting calls */
  4838. wake_up_interruptible_all(&priv->wait_command_queue);
  4839. /* Wipe out the EXIT_PENDING status bit if we are not actually
  4840. * exiting the module */
  4841. if (!exit_pending)
  4842. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4843. /* stop and reset the on-board processor */
  4844. iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  4845. /* tell the device to stop sending interrupts */
  4846. spin_lock_irqsave(&priv->lock, flags);
  4847. iwl3945_disable_interrupts(priv);
  4848. spin_unlock_irqrestore(&priv->lock, flags);
  4849. iwl_synchronize_irq(priv);
  4850. if (priv->mac80211_registered)
  4851. ieee80211_stop_queues(priv->hw);
  4852. /* If we have not previously called iwl3945_init() then
  4853. * clear all bits but the RF Kill and SUSPEND bits and return */
  4854. if (!iwl3945_is_init(priv)) {
  4855. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4856. STATUS_RF_KILL_HW |
  4857. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4858. STATUS_RF_KILL_SW |
  4859. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4860. STATUS_GEO_CONFIGURED |
  4861. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4862. STATUS_IN_SUSPEND |
  4863. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4864. STATUS_EXIT_PENDING;
  4865. goto exit;
  4866. }
  4867. /* ...otherwise clear out all the status bits but the RF Kill and
  4868. * SUSPEND bits and continue taking the NIC down. */
  4869. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4870. STATUS_RF_KILL_HW |
  4871. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4872. STATUS_RF_KILL_SW |
  4873. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4874. STATUS_GEO_CONFIGURED |
  4875. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4876. STATUS_IN_SUSPEND |
  4877. test_bit(STATUS_FW_ERROR, &priv->status) <<
  4878. STATUS_FW_ERROR |
  4879. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4880. STATUS_EXIT_PENDING;
  4881. spin_lock_irqsave(&priv->lock, flags);
  4882. iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  4883. spin_unlock_irqrestore(&priv->lock, flags);
  4884. iwl3945_hw_txq_ctx_stop(priv);
  4885. iwl3945_hw_rxq_stop(priv);
  4886. spin_lock_irqsave(&priv->lock, flags);
  4887. if (!iwl3945_grab_nic_access(priv)) {
  4888. iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
  4889. APMG_CLK_VAL_DMA_CLK_RQT);
  4890. iwl3945_release_nic_access(priv);
  4891. }
  4892. spin_unlock_irqrestore(&priv->lock, flags);
  4893. udelay(5);
  4894. iwl3945_hw_nic_stop_master(priv);
  4895. iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  4896. iwl3945_hw_nic_reset(priv);
  4897. exit:
  4898. memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
  4899. if (priv->ibss_beacon)
  4900. dev_kfree_skb(priv->ibss_beacon);
  4901. priv->ibss_beacon = NULL;
  4902. /* clear out any free frames */
  4903. iwl3945_clear_free_frames(priv);
  4904. }
  4905. static void iwl3945_down(struct iwl3945_priv *priv)
  4906. {
  4907. mutex_lock(&priv->mutex);
  4908. __iwl3945_down(priv);
  4909. mutex_unlock(&priv->mutex);
  4910. iwl3945_cancel_deferred_work(priv);
  4911. }
  4912. #define MAX_HW_RESTARTS 5
  4913. static int __iwl3945_up(struct iwl3945_priv *priv)
  4914. {
  4915. int rc, i;
  4916. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  4917. IWL_WARNING("Exit pending; will not bring the NIC up\n");
  4918. return -EIO;
  4919. }
  4920. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  4921. IWL_WARNING("Radio disabled by SW RF kill (module "
  4922. "parameter)\n");
  4923. return -ENODEV;
  4924. }
  4925. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  4926. IWL_ERROR("ucode not available for device bring up\n");
  4927. return -EIO;
  4928. }
  4929. /* If platform's RF_KILL switch is NOT set to KILL */
  4930. if (iwl3945_read32(priv, CSR_GP_CNTRL) &
  4931. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  4932. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4933. else {
  4934. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4935. if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
  4936. IWL_WARNING("Radio disabled by HW RF Kill switch\n");
  4937. return -ENODEV;
  4938. }
  4939. }
  4940. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  4941. rc = iwl3945_hw_nic_init(priv);
  4942. if (rc) {
  4943. IWL_ERROR("Unable to int nic\n");
  4944. return rc;
  4945. }
  4946. /* make sure rfkill handshake bits are cleared */
  4947. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4948. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  4949. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  4950. /* clear (again), then enable host interrupts */
  4951. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  4952. iwl3945_enable_interrupts(priv);
  4953. /* really make sure rfkill handshake bits are cleared */
  4954. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4955. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4956. /* Copy original ucode data image from disk into backup cache.
  4957. * This will be used to initialize the on-board processor's
  4958. * data SRAM for a clean start when the runtime program first loads. */
  4959. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  4960. priv->ucode_data.len);
  4961. /* We return success when we resume from suspend and rf_kill is on. */
  4962. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  4963. return 0;
  4964. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  4965. iwl3945_clear_stations_table(priv);
  4966. /* load bootstrap state machine,
  4967. * load bootstrap program into processor's memory,
  4968. * prepare to load the "initialize" uCode */
  4969. rc = iwl3945_load_bsm(priv);
  4970. if (rc) {
  4971. IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
  4972. continue;
  4973. }
  4974. /* start card; "initialize" will load runtime ucode */
  4975. iwl3945_nic_start(priv);
  4976. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  4977. return 0;
  4978. }
  4979. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4980. __iwl3945_down(priv);
  4981. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4982. /* tried to restart and config the device for as long as our
  4983. * patience could withstand */
  4984. IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
  4985. return -EIO;
  4986. }
  4987. /*****************************************************************************
  4988. *
  4989. * Workqueue callbacks
  4990. *
  4991. *****************************************************************************/
  4992. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  4993. {
  4994. struct iwl3945_priv *priv =
  4995. container_of(data, struct iwl3945_priv, init_alive_start.work);
  4996. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4997. return;
  4998. mutex_lock(&priv->mutex);
  4999. iwl3945_init_alive_start(priv);
  5000. mutex_unlock(&priv->mutex);
  5001. }
  5002. static void iwl3945_bg_alive_start(struct work_struct *data)
  5003. {
  5004. struct iwl3945_priv *priv =
  5005. container_of(data, struct iwl3945_priv, alive_start.work);
  5006. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5007. return;
  5008. mutex_lock(&priv->mutex);
  5009. iwl3945_alive_start(priv);
  5010. mutex_unlock(&priv->mutex);
  5011. }
  5012. static void iwl3945_bg_rf_kill(struct work_struct *work)
  5013. {
  5014. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
  5015. wake_up_interruptible(&priv->wait_command_queue);
  5016. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5017. return;
  5018. mutex_lock(&priv->mutex);
  5019. if (!iwl3945_is_rfkill(priv)) {
  5020. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  5021. "HW and/or SW RF Kill no longer active, restarting "
  5022. "device\n");
  5023. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5024. queue_work(priv->workqueue, &priv->restart);
  5025. } else {
  5026. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  5027. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  5028. "disabled by SW switch\n");
  5029. else
  5030. IWL_WARNING("Radio Frequency Kill Switch is On:\n"
  5031. "Kill switch must be turned off for "
  5032. "wireless networking to work.\n");
  5033. }
  5034. mutex_unlock(&priv->mutex);
  5035. iwl3945_rfkill_set_hw_state(priv);
  5036. }
  5037. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  5038. static void iwl3945_bg_scan_check(struct work_struct *data)
  5039. {
  5040. struct iwl3945_priv *priv =
  5041. container_of(data, struct iwl3945_priv, scan_check.work);
  5042. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5043. return;
  5044. mutex_lock(&priv->mutex);
  5045. if (test_bit(STATUS_SCANNING, &priv->status) ||
  5046. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5047. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  5048. "Scan completion watchdog resetting adapter (%dms)\n",
  5049. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  5050. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5051. iwl3945_send_scan_abort(priv);
  5052. }
  5053. mutex_unlock(&priv->mutex);
  5054. }
  5055. static void iwl3945_bg_request_scan(struct work_struct *data)
  5056. {
  5057. struct iwl3945_priv *priv =
  5058. container_of(data, struct iwl3945_priv, request_scan);
  5059. struct iwl3945_host_cmd cmd = {
  5060. .id = REPLY_SCAN_CMD,
  5061. .len = sizeof(struct iwl3945_scan_cmd),
  5062. .meta.flags = CMD_SIZE_HUGE,
  5063. };
  5064. int rc = 0;
  5065. struct iwl3945_scan_cmd *scan;
  5066. struct ieee80211_conf *conf = NULL;
  5067. u8 n_probes = 2;
  5068. enum ieee80211_band band;
  5069. DECLARE_SSID_BUF(ssid);
  5070. conf = ieee80211_get_hw_conf(priv->hw);
  5071. mutex_lock(&priv->mutex);
  5072. if (!iwl3945_is_ready(priv)) {
  5073. IWL_WARNING("request scan called when driver not ready.\n");
  5074. goto done;
  5075. }
  5076. /* Make sure the scan wasn't canceled before this queued work
  5077. * was given the chance to run... */
  5078. if (!test_bit(STATUS_SCANNING, &priv->status))
  5079. goto done;
  5080. /* This should never be called or scheduled if there is currently
  5081. * a scan active in the hardware. */
  5082. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  5083. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  5084. "Ignoring second request.\n");
  5085. rc = -EIO;
  5086. goto done;
  5087. }
  5088. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5089. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  5090. goto done;
  5091. }
  5092. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5093. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  5094. goto done;
  5095. }
  5096. if (iwl3945_is_rfkill(priv)) {
  5097. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  5098. goto done;
  5099. }
  5100. if (!test_bit(STATUS_READY, &priv->status)) {
  5101. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  5102. goto done;
  5103. }
  5104. if (!priv->scan_bands) {
  5105. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  5106. goto done;
  5107. }
  5108. if (!priv->scan) {
  5109. priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  5110. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  5111. if (!priv->scan) {
  5112. rc = -ENOMEM;
  5113. goto done;
  5114. }
  5115. }
  5116. scan = priv->scan;
  5117. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  5118. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  5119. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  5120. if (iwl3945_is_associated(priv)) {
  5121. u16 interval = 0;
  5122. u32 extra;
  5123. u32 suspend_time = 100;
  5124. u32 scan_suspend_time = 100;
  5125. unsigned long flags;
  5126. IWL_DEBUG_INFO("Scanning while associated...\n");
  5127. spin_lock_irqsave(&priv->lock, flags);
  5128. interval = priv->beacon_int;
  5129. spin_unlock_irqrestore(&priv->lock, flags);
  5130. scan->suspend_time = 0;
  5131. scan->max_out_time = cpu_to_le32(200 * 1024);
  5132. if (!interval)
  5133. interval = suspend_time;
  5134. /*
  5135. * suspend time format:
  5136. * 0-19: beacon interval in usec (time before exec.)
  5137. * 20-23: 0
  5138. * 24-31: number of beacons (suspend between channels)
  5139. */
  5140. extra = (suspend_time / interval) << 24;
  5141. scan_suspend_time = 0xFF0FFFFF &
  5142. (extra | ((suspend_time % interval) * 1024));
  5143. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  5144. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  5145. scan_suspend_time, interval);
  5146. }
  5147. /* We should add the ability for user to lock to PASSIVE ONLY */
  5148. if (priv->one_direct_scan) {
  5149. IWL_DEBUG_SCAN
  5150. ("Kicking off one direct scan for '%s'\n",
  5151. print_ssid(ssid, priv->direct_ssid,
  5152. priv->direct_ssid_len));
  5153. scan->direct_scan[0].id = WLAN_EID_SSID;
  5154. scan->direct_scan[0].len = priv->direct_ssid_len;
  5155. memcpy(scan->direct_scan[0].ssid,
  5156. priv->direct_ssid, priv->direct_ssid_len);
  5157. n_probes++;
  5158. } else
  5159. IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
  5160. /* We don't build a direct scan probe request; the uCode will do
  5161. * that based on the direct_mask added to each channel entry */
  5162. scan->tx_cmd.len = cpu_to_le16(
  5163. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  5164. IWL_MAX_SCAN_SIZE - sizeof(*scan)));
  5165. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  5166. scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
  5167. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  5168. /* flags + rate selection */
  5169. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
  5170. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  5171. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  5172. scan->good_CRC_th = 0;
  5173. band = IEEE80211_BAND_2GHZ;
  5174. } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
  5175. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  5176. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  5177. band = IEEE80211_BAND_5GHZ;
  5178. } else {
  5179. IWL_WARNING("Invalid scan band count\n");
  5180. goto done;
  5181. }
  5182. /* select Rx antennas */
  5183. scan->flags |= iwl3945_get_antenna_flags(priv);
  5184. if (priv->iw_mode == NL80211_IFTYPE_MONITOR)
  5185. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  5186. scan->channel_count =
  5187. iwl3945_get_channels_for_scan(priv, band, 1, /* active */
  5188. n_probes,
  5189. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5190. if (scan->channel_count == 0) {
  5191. IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count);
  5192. goto done;
  5193. }
  5194. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  5195. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  5196. cmd.data = scan;
  5197. scan->len = cpu_to_le16(cmd.len);
  5198. set_bit(STATUS_SCAN_HW, &priv->status);
  5199. rc = iwl3945_send_cmd_sync(priv, &cmd);
  5200. if (rc)
  5201. goto done;
  5202. queue_delayed_work(priv->workqueue, &priv->scan_check,
  5203. IWL_SCAN_CHECK_WATCHDOG);
  5204. mutex_unlock(&priv->mutex);
  5205. return;
  5206. done:
  5207. /* can not perform scan make sure we clear scanning
  5208. * bits from status so next scan request can be performed.
  5209. * if we dont clear scanning status bit here all next scan
  5210. * will fail
  5211. */
  5212. clear_bit(STATUS_SCAN_HW, &priv->status);
  5213. clear_bit(STATUS_SCANNING, &priv->status);
  5214. /* inform mac80211 scan aborted */
  5215. queue_work(priv->workqueue, &priv->scan_completed);
  5216. mutex_unlock(&priv->mutex);
  5217. }
  5218. static void iwl3945_bg_up(struct work_struct *data)
  5219. {
  5220. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
  5221. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5222. return;
  5223. mutex_lock(&priv->mutex);
  5224. __iwl3945_up(priv);
  5225. mutex_unlock(&priv->mutex);
  5226. iwl3945_rfkill_set_hw_state(priv);
  5227. }
  5228. static void iwl3945_bg_restart(struct work_struct *data)
  5229. {
  5230. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
  5231. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5232. return;
  5233. iwl3945_down(priv);
  5234. queue_work(priv->workqueue, &priv->up);
  5235. }
  5236. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  5237. {
  5238. struct iwl3945_priv *priv =
  5239. container_of(data, struct iwl3945_priv, rx_replenish);
  5240. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5241. return;
  5242. mutex_lock(&priv->mutex);
  5243. iwl3945_rx_replenish(priv);
  5244. mutex_unlock(&priv->mutex);
  5245. }
  5246. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  5247. static void iwl3945_post_associate(struct iwl3945_priv *priv)
  5248. {
  5249. int rc = 0;
  5250. struct ieee80211_conf *conf = NULL;
  5251. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  5252. IWL_ERROR("%s Should not be called in AP mode\n", __func__);
  5253. return;
  5254. }
  5255. IWL_DEBUG_ASSOC("Associated as %d to: %pM\n",
  5256. priv->assoc_id, priv->active_rxon.bssid_addr);
  5257. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5258. return;
  5259. if (!priv->vif || !priv->is_open)
  5260. return;
  5261. iwl3945_scan_cancel_timeout(priv, 200);
  5262. conf = ieee80211_get_hw_conf(priv->hw);
  5263. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5264. iwl3945_commit_rxon(priv);
  5265. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5266. iwl3945_setup_rxon_timing(priv);
  5267. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5268. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5269. if (rc)
  5270. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5271. "Attempting to continue.\n");
  5272. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5273. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5274. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  5275. priv->assoc_id, priv->beacon_int);
  5276. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5277. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5278. else
  5279. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5280. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5281. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5282. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  5283. else
  5284. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5285. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  5286. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5287. }
  5288. iwl3945_commit_rxon(priv);
  5289. switch (priv->iw_mode) {
  5290. case NL80211_IFTYPE_STATION:
  5291. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  5292. break;
  5293. case NL80211_IFTYPE_ADHOC:
  5294. priv->assoc_id = 1;
  5295. iwl3945_add_station(priv, priv->bssid, 0, 0);
  5296. iwl3945_sync_sta(priv, IWL_STA_ID,
  5297. (priv->band == IEEE80211_BAND_5GHZ) ?
  5298. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  5299. CMD_ASYNC);
  5300. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  5301. iwl3945_send_beacon_cmd(priv);
  5302. break;
  5303. default:
  5304. IWL_ERROR("%s Should not be called in %d mode\n",
  5305. __func__, priv->iw_mode);
  5306. break;
  5307. }
  5308. iwl3945_activate_qos(priv, 0);
  5309. /* we have just associated, don't start scan too early */
  5310. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  5311. }
  5312. static void iwl3945_bg_abort_scan(struct work_struct *work)
  5313. {
  5314. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
  5315. if (!iwl3945_is_ready(priv))
  5316. return;
  5317. mutex_lock(&priv->mutex);
  5318. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  5319. iwl3945_send_scan_abort(priv);
  5320. mutex_unlock(&priv->mutex);
  5321. }
  5322. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed);
  5323. static void iwl3945_bg_scan_completed(struct work_struct *work)
  5324. {
  5325. struct iwl3945_priv *priv =
  5326. container_of(work, struct iwl3945_priv, scan_completed);
  5327. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  5328. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5329. return;
  5330. if (test_bit(STATUS_CONF_PENDING, &priv->status))
  5331. iwl3945_mac_config(priv->hw, 0);
  5332. ieee80211_scan_completed(priv->hw);
  5333. /* Since setting the TXPOWER may have been deferred while
  5334. * performing the scan, fire one off */
  5335. mutex_lock(&priv->mutex);
  5336. iwl3945_hw_reg_send_txpower(priv);
  5337. mutex_unlock(&priv->mutex);
  5338. }
  5339. /*****************************************************************************
  5340. *
  5341. * mac80211 entry point functions
  5342. *
  5343. *****************************************************************************/
  5344. #define UCODE_READY_TIMEOUT (2 * HZ)
  5345. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  5346. {
  5347. struct iwl3945_priv *priv = hw->priv;
  5348. int ret;
  5349. IWL_DEBUG_MAC80211("enter\n");
  5350. if (pci_enable_device(priv->pci_dev)) {
  5351. IWL_ERROR("Fail to pci_enable_device\n");
  5352. return -ENODEV;
  5353. }
  5354. pci_restore_state(priv->pci_dev);
  5355. pci_enable_msi(priv->pci_dev);
  5356. ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
  5357. DRV_NAME, priv);
  5358. if (ret) {
  5359. IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
  5360. goto out_disable_msi;
  5361. }
  5362. /* we should be verifying the device is ready to be opened */
  5363. mutex_lock(&priv->mutex);
  5364. memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
  5365. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  5366. * ucode filename and max sizes are card-specific. */
  5367. if (!priv->ucode_code.len) {
  5368. ret = iwl3945_read_ucode(priv);
  5369. if (ret) {
  5370. IWL_ERROR("Could not read microcode: %d\n", ret);
  5371. mutex_unlock(&priv->mutex);
  5372. goto out_release_irq;
  5373. }
  5374. }
  5375. ret = __iwl3945_up(priv);
  5376. mutex_unlock(&priv->mutex);
  5377. iwl3945_rfkill_set_hw_state(priv);
  5378. if (ret)
  5379. goto out_release_irq;
  5380. IWL_DEBUG_INFO("Start UP work.\n");
  5381. if (test_bit(STATUS_IN_SUSPEND, &priv->status))
  5382. return 0;
  5383. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  5384. * mac80211 will not be run successfully. */
  5385. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  5386. test_bit(STATUS_READY, &priv->status),
  5387. UCODE_READY_TIMEOUT);
  5388. if (!ret) {
  5389. if (!test_bit(STATUS_READY, &priv->status)) {
  5390. IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
  5391. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  5392. ret = -ETIMEDOUT;
  5393. goto out_release_irq;
  5394. }
  5395. }
  5396. priv->is_open = 1;
  5397. IWL_DEBUG_MAC80211("leave\n");
  5398. return 0;
  5399. out_release_irq:
  5400. free_irq(priv->pci_dev->irq, priv);
  5401. out_disable_msi:
  5402. pci_disable_msi(priv->pci_dev);
  5403. pci_disable_device(priv->pci_dev);
  5404. priv->is_open = 0;
  5405. IWL_DEBUG_MAC80211("leave - failed\n");
  5406. return ret;
  5407. }
  5408. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  5409. {
  5410. struct iwl3945_priv *priv = hw->priv;
  5411. IWL_DEBUG_MAC80211("enter\n");
  5412. if (!priv->is_open) {
  5413. IWL_DEBUG_MAC80211("leave - skip\n");
  5414. return;
  5415. }
  5416. priv->is_open = 0;
  5417. if (iwl3945_is_ready_rf(priv)) {
  5418. /* stop mac, cancel any scan request and clear
  5419. * RXON_FILTER_ASSOC_MSK BIT
  5420. */
  5421. mutex_lock(&priv->mutex);
  5422. iwl3945_scan_cancel_timeout(priv, 100);
  5423. mutex_unlock(&priv->mutex);
  5424. }
  5425. iwl3945_down(priv);
  5426. flush_workqueue(priv->workqueue);
  5427. free_irq(priv->pci_dev->irq, priv);
  5428. pci_disable_msi(priv->pci_dev);
  5429. pci_save_state(priv->pci_dev);
  5430. pci_disable_device(priv->pci_dev);
  5431. IWL_DEBUG_MAC80211("leave\n");
  5432. }
  5433. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  5434. {
  5435. struct iwl3945_priv *priv = hw->priv;
  5436. IWL_DEBUG_MAC80211("enter\n");
  5437. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  5438. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  5439. if (iwl3945_tx_skb(priv, skb))
  5440. dev_kfree_skb_any(skb);
  5441. IWL_DEBUG_MAC80211("leave\n");
  5442. return NETDEV_TX_OK;
  5443. }
  5444. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  5445. struct ieee80211_if_init_conf *conf)
  5446. {
  5447. struct iwl3945_priv *priv = hw->priv;
  5448. unsigned long flags;
  5449. IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
  5450. if (priv->vif) {
  5451. IWL_DEBUG_MAC80211("leave - vif != NULL\n");
  5452. return -EOPNOTSUPP;
  5453. }
  5454. spin_lock_irqsave(&priv->lock, flags);
  5455. priv->vif = conf->vif;
  5456. priv->iw_mode = conf->type;
  5457. spin_unlock_irqrestore(&priv->lock, flags);
  5458. mutex_lock(&priv->mutex);
  5459. if (conf->mac_addr) {
  5460. IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr);
  5461. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5462. }
  5463. if (iwl3945_is_ready(priv))
  5464. iwl3945_set_mode(priv, conf->type);
  5465. mutex_unlock(&priv->mutex);
  5466. IWL_DEBUG_MAC80211("leave\n");
  5467. return 0;
  5468. }
  5469. /**
  5470. * iwl3945_mac_config - mac80211 config callback
  5471. *
  5472. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5473. * be set inappropriately and the driver currently sets the hardware up to
  5474. * use it whenever needed.
  5475. */
  5476. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed)
  5477. {
  5478. struct iwl3945_priv *priv = hw->priv;
  5479. const struct iwl3945_channel_info *ch_info;
  5480. struct ieee80211_conf *conf = &hw->conf;
  5481. unsigned long flags;
  5482. int ret = 0;
  5483. mutex_lock(&priv->mutex);
  5484. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
  5485. if (!iwl3945_is_ready(priv)) {
  5486. IWL_DEBUG_MAC80211("leave - not ready\n");
  5487. ret = -EIO;
  5488. goto out;
  5489. }
  5490. if (unlikely(!iwl3945_param_disable_hw_scan &&
  5491. test_bit(STATUS_SCANNING, &priv->status))) {
  5492. IWL_DEBUG_MAC80211("leave - scanning\n");
  5493. set_bit(STATUS_CONF_PENDING, &priv->status);
  5494. mutex_unlock(&priv->mutex);
  5495. return 0;
  5496. }
  5497. spin_lock_irqsave(&priv->lock, flags);
  5498. ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
  5499. conf->channel->hw_value);
  5500. if (!is_channel_valid(ch_info)) {
  5501. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
  5502. conf->channel->hw_value, conf->channel->band);
  5503. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5504. spin_unlock_irqrestore(&priv->lock, flags);
  5505. ret = -EINVAL;
  5506. goto out;
  5507. }
  5508. iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
  5509. iwl3945_set_flags_for_phymode(priv, conf->channel->band);
  5510. /* The list of supported rates and rate mask can be different
  5511. * for each phymode; since the phymode may have changed, reset
  5512. * the rate mask to what mac80211 lists */
  5513. iwl3945_set_rate(priv);
  5514. spin_unlock_irqrestore(&priv->lock, flags);
  5515. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5516. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5517. iwl3945_hw_channel_switch(priv, conf->channel);
  5518. goto out;
  5519. }
  5520. #endif
  5521. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5522. if (!conf->radio_enabled) {
  5523. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5524. goto out;
  5525. }
  5526. if (iwl3945_is_rfkill(priv)) {
  5527. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5528. ret = -EIO;
  5529. goto out;
  5530. }
  5531. iwl3945_set_rate(priv);
  5532. if (memcmp(&priv->active_rxon,
  5533. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  5534. iwl3945_commit_rxon(priv);
  5535. else
  5536. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5537. IWL_DEBUG_MAC80211("leave\n");
  5538. out:
  5539. clear_bit(STATUS_CONF_PENDING, &priv->status);
  5540. mutex_unlock(&priv->mutex);
  5541. return ret;
  5542. }
  5543. static void iwl3945_config_ap(struct iwl3945_priv *priv)
  5544. {
  5545. int rc = 0;
  5546. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5547. return;
  5548. /* The following should be done only at AP bring up */
  5549. if (!(iwl3945_is_associated(priv))) {
  5550. /* RXON - unassoc (to set timing command) */
  5551. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5552. iwl3945_commit_rxon(priv);
  5553. /* RXON Timing */
  5554. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5555. iwl3945_setup_rxon_timing(priv);
  5556. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5557. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5558. if (rc)
  5559. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5560. "Attempting to continue.\n");
  5561. /* FIXME: what should be the assoc_id for AP? */
  5562. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5563. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5564. priv->staging_rxon.flags |=
  5565. RXON_FLG_SHORT_PREAMBLE_MSK;
  5566. else
  5567. priv->staging_rxon.flags &=
  5568. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5569. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5570. if (priv->assoc_capability &
  5571. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5572. priv->staging_rxon.flags |=
  5573. RXON_FLG_SHORT_SLOT_MSK;
  5574. else
  5575. priv->staging_rxon.flags &=
  5576. ~RXON_FLG_SHORT_SLOT_MSK;
  5577. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  5578. priv->staging_rxon.flags &=
  5579. ~RXON_FLG_SHORT_SLOT_MSK;
  5580. }
  5581. /* restore RXON assoc */
  5582. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5583. iwl3945_commit_rxon(priv);
  5584. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5585. }
  5586. iwl3945_send_beacon_cmd(priv);
  5587. /* FIXME - we need to add code here to detect a totally new
  5588. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5589. * clear sta table, add BCAST sta... */
  5590. }
  5591. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
  5592. struct ieee80211_vif *vif,
  5593. struct ieee80211_if_conf *conf)
  5594. {
  5595. struct iwl3945_priv *priv = hw->priv;
  5596. int rc;
  5597. if (conf == NULL)
  5598. return -EIO;
  5599. if (priv->vif != vif) {
  5600. IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
  5601. return 0;
  5602. }
  5603. /* handle this temporarily here */
  5604. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  5605. conf->changed & IEEE80211_IFCC_BEACON) {
  5606. struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
  5607. if (!beacon)
  5608. return -ENOMEM;
  5609. mutex_lock(&priv->mutex);
  5610. rc = iwl3945_mac_beacon_update(hw, beacon);
  5611. mutex_unlock(&priv->mutex);
  5612. if (rc)
  5613. return rc;
  5614. }
  5615. if (!iwl3945_is_alive(priv))
  5616. return -EAGAIN;
  5617. mutex_lock(&priv->mutex);
  5618. if (conf->bssid)
  5619. IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid);
  5620. /*
  5621. * very dubious code was here; the probe filtering flag is never set:
  5622. *
  5623. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5624. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5625. */
  5626. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  5627. if (!conf->bssid) {
  5628. conf->bssid = priv->mac_addr;
  5629. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5630. IWL_DEBUG_MAC80211("bssid was set to: %pM\n",
  5631. conf->bssid);
  5632. }
  5633. if (priv->ibss_beacon)
  5634. dev_kfree_skb(priv->ibss_beacon);
  5635. priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
  5636. }
  5637. if (iwl3945_is_rfkill(priv))
  5638. goto done;
  5639. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  5640. !is_multicast_ether_addr(conf->bssid)) {
  5641. /* If there is currently a HW scan going on in the background
  5642. * then we need to cancel it else the RXON below will fail. */
  5643. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  5644. IWL_WARNING("Aborted scan still in progress "
  5645. "after 100ms\n");
  5646. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  5647. mutex_unlock(&priv->mutex);
  5648. return -EAGAIN;
  5649. }
  5650. memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  5651. /* TODO: Audit driver for usage of these members and see
  5652. * if mac80211 deprecates them (priv->bssid looks like it
  5653. * shouldn't be there, but I haven't scanned the IBSS code
  5654. * to verify) - jpk */
  5655. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  5656. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5657. iwl3945_config_ap(priv);
  5658. else {
  5659. rc = iwl3945_commit_rxon(priv);
  5660. if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
  5661. iwl3945_add_station(priv,
  5662. priv->active_rxon.bssid_addr, 1, 0);
  5663. }
  5664. } else {
  5665. iwl3945_scan_cancel_timeout(priv, 100);
  5666. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5667. iwl3945_commit_rxon(priv);
  5668. }
  5669. done:
  5670. IWL_DEBUG_MAC80211("leave\n");
  5671. mutex_unlock(&priv->mutex);
  5672. return 0;
  5673. }
  5674. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  5675. unsigned int changed_flags,
  5676. unsigned int *total_flags,
  5677. int mc_count, struct dev_addr_list *mc_list)
  5678. {
  5679. struct iwl3945_priv *priv = hw->priv;
  5680. __le32 *filter_flags = &priv->staging_rxon.filter_flags;
  5681. IWL_DEBUG_MAC80211("Enter: changed: 0x%x, total: 0x%x\n",
  5682. changed_flags, *total_flags);
  5683. if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
  5684. if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
  5685. *filter_flags |= RXON_FILTER_PROMISC_MSK;
  5686. else
  5687. *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
  5688. }
  5689. if (changed_flags & FIF_ALLMULTI) {
  5690. if (*total_flags & FIF_ALLMULTI)
  5691. *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
  5692. else
  5693. *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
  5694. }
  5695. if (changed_flags & FIF_CONTROL) {
  5696. if (*total_flags & FIF_CONTROL)
  5697. *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
  5698. else
  5699. *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
  5700. }
  5701. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  5702. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  5703. *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
  5704. else
  5705. *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
  5706. }
  5707. /* We avoid iwl_commit_rxon here to commit the new filter flags
  5708. * since mac80211 will call ieee80211_hw_config immediately.
  5709. * (mc_list is not supported at this time). Otherwise, we need to
  5710. * queue a background iwl_commit_rxon work.
  5711. */
  5712. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  5713. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  5714. }
  5715. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  5716. struct ieee80211_if_init_conf *conf)
  5717. {
  5718. struct iwl3945_priv *priv = hw->priv;
  5719. IWL_DEBUG_MAC80211("enter\n");
  5720. mutex_lock(&priv->mutex);
  5721. if (iwl3945_is_ready_rf(priv)) {
  5722. iwl3945_scan_cancel_timeout(priv, 100);
  5723. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5724. iwl3945_commit_rxon(priv);
  5725. }
  5726. if (priv->vif == conf->vif) {
  5727. priv->vif = NULL;
  5728. memset(priv->bssid, 0, ETH_ALEN);
  5729. }
  5730. mutex_unlock(&priv->mutex);
  5731. IWL_DEBUG_MAC80211("leave\n");
  5732. }
  5733. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  5734. static void iwl3945_bss_info_changed(struct ieee80211_hw *hw,
  5735. struct ieee80211_vif *vif,
  5736. struct ieee80211_bss_conf *bss_conf,
  5737. u32 changes)
  5738. {
  5739. struct iwl3945_priv *priv = hw->priv;
  5740. IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
  5741. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  5742. IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
  5743. bss_conf->use_short_preamble);
  5744. if (bss_conf->use_short_preamble)
  5745. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5746. else
  5747. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5748. }
  5749. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  5750. IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
  5751. if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
  5752. priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
  5753. else
  5754. priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  5755. }
  5756. if (changes & BSS_CHANGED_ASSOC) {
  5757. IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
  5758. /* This should never happen as this function should
  5759. * never be called from interrupt context. */
  5760. if (WARN_ON_ONCE(in_interrupt()))
  5761. return;
  5762. if (bss_conf->assoc) {
  5763. priv->assoc_id = bss_conf->aid;
  5764. priv->beacon_int = bss_conf->beacon_int;
  5765. priv->timestamp0 = bss_conf->timestamp & 0xFFFFFFFF;
  5766. priv->timestamp1 = (bss_conf->timestamp >> 32) &
  5767. 0xFFFFFFFF;
  5768. priv->assoc_capability = bss_conf->assoc_capability;
  5769. priv->next_scan_jiffies = jiffies +
  5770. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  5771. mutex_lock(&priv->mutex);
  5772. iwl3945_post_associate(priv);
  5773. mutex_unlock(&priv->mutex);
  5774. } else {
  5775. priv->assoc_id = 0;
  5776. IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
  5777. }
  5778. } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) {
  5779. IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
  5780. iwl3945_send_rxon_assoc(priv);
  5781. }
  5782. }
  5783. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  5784. {
  5785. int rc = 0;
  5786. unsigned long flags;
  5787. struct iwl3945_priv *priv = hw->priv;
  5788. DECLARE_SSID_BUF(ssid_buf);
  5789. IWL_DEBUG_MAC80211("enter\n");
  5790. mutex_lock(&priv->mutex);
  5791. spin_lock_irqsave(&priv->lock, flags);
  5792. if (!iwl3945_is_ready_rf(priv)) {
  5793. rc = -EIO;
  5794. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  5795. goto out_unlock;
  5796. }
  5797. /* we don't schedule scan within next_scan_jiffies period */
  5798. if (priv->next_scan_jiffies &&
  5799. time_after(priv->next_scan_jiffies, jiffies)) {
  5800. rc = -EAGAIN;
  5801. goto out_unlock;
  5802. }
  5803. /* if we just finished scan ask for delay for a broadcast scan */
  5804. if ((len == 0) && priv->last_scan_jiffies &&
  5805. time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
  5806. jiffies)) {
  5807. rc = -EAGAIN;
  5808. goto out_unlock;
  5809. }
  5810. if (len) {
  5811. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  5812. print_ssid(ssid_buf, ssid, len), (int)len);
  5813. priv->one_direct_scan = 1;
  5814. priv->direct_ssid_len = (u8)
  5815. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  5816. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  5817. } else
  5818. priv->one_direct_scan = 0;
  5819. rc = iwl3945_scan_initiate(priv);
  5820. IWL_DEBUG_MAC80211("leave\n");
  5821. out_unlock:
  5822. spin_unlock_irqrestore(&priv->lock, flags);
  5823. mutex_unlock(&priv->mutex);
  5824. return rc;
  5825. }
  5826. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  5827. const u8 *local_addr, const u8 *addr,
  5828. struct ieee80211_key_conf *key)
  5829. {
  5830. struct iwl3945_priv *priv = hw->priv;
  5831. int rc = 0;
  5832. u8 sta_id;
  5833. IWL_DEBUG_MAC80211("enter\n");
  5834. if (!iwl3945_param_hwcrypto) {
  5835. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  5836. return -EOPNOTSUPP;
  5837. }
  5838. if (is_zero_ether_addr(addr))
  5839. /* only support pairwise keys */
  5840. return -EOPNOTSUPP;
  5841. sta_id = iwl3945_hw_find_station(priv, addr);
  5842. if (sta_id == IWL_INVALID_STATION) {
  5843. IWL_DEBUG_MAC80211("leave - %pM not in station map.\n",
  5844. addr);
  5845. return -EINVAL;
  5846. }
  5847. mutex_lock(&priv->mutex);
  5848. iwl3945_scan_cancel_timeout(priv, 100);
  5849. switch (cmd) {
  5850. case SET_KEY:
  5851. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  5852. if (!rc) {
  5853. iwl3945_set_rxon_hwcrypto(priv, 1);
  5854. iwl3945_commit_rxon(priv);
  5855. key->hw_key_idx = sta_id;
  5856. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  5857. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  5858. }
  5859. break;
  5860. case DISABLE_KEY:
  5861. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  5862. if (!rc) {
  5863. iwl3945_set_rxon_hwcrypto(priv, 0);
  5864. iwl3945_commit_rxon(priv);
  5865. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  5866. }
  5867. break;
  5868. default:
  5869. rc = -EINVAL;
  5870. }
  5871. IWL_DEBUG_MAC80211("leave\n");
  5872. mutex_unlock(&priv->mutex);
  5873. return rc;
  5874. }
  5875. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  5876. const struct ieee80211_tx_queue_params *params)
  5877. {
  5878. struct iwl3945_priv *priv = hw->priv;
  5879. unsigned long flags;
  5880. int q;
  5881. IWL_DEBUG_MAC80211("enter\n");
  5882. if (!iwl3945_is_ready_rf(priv)) {
  5883. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5884. return -EIO;
  5885. }
  5886. if (queue >= AC_NUM) {
  5887. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  5888. return 0;
  5889. }
  5890. q = AC_NUM - 1 - queue;
  5891. spin_lock_irqsave(&priv->lock, flags);
  5892. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  5893. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  5894. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  5895. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  5896. cpu_to_le16((params->txop * 32));
  5897. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  5898. priv->qos_data.qos_active = 1;
  5899. spin_unlock_irqrestore(&priv->lock, flags);
  5900. mutex_lock(&priv->mutex);
  5901. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5902. iwl3945_activate_qos(priv, 1);
  5903. else if (priv->assoc_id && iwl3945_is_associated(priv))
  5904. iwl3945_activate_qos(priv, 0);
  5905. mutex_unlock(&priv->mutex);
  5906. IWL_DEBUG_MAC80211("leave\n");
  5907. return 0;
  5908. }
  5909. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  5910. struct ieee80211_tx_queue_stats *stats)
  5911. {
  5912. struct iwl3945_priv *priv = hw->priv;
  5913. int i, avail;
  5914. struct iwl3945_tx_queue *txq;
  5915. struct iwl3945_queue *q;
  5916. unsigned long flags;
  5917. IWL_DEBUG_MAC80211("enter\n");
  5918. if (!iwl3945_is_ready_rf(priv)) {
  5919. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5920. return -EIO;
  5921. }
  5922. spin_lock_irqsave(&priv->lock, flags);
  5923. for (i = 0; i < AC_NUM; i++) {
  5924. txq = &priv->txq[i];
  5925. q = &txq->q;
  5926. avail = iwl3945_queue_space(q);
  5927. stats[i].len = q->n_window - avail;
  5928. stats[i].limit = q->n_window - q->high_mark;
  5929. stats[i].count = q->n_window;
  5930. }
  5931. spin_unlock_irqrestore(&priv->lock, flags);
  5932. IWL_DEBUG_MAC80211("leave\n");
  5933. return 0;
  5934. }
  5935. static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
  5936. struct ieee80211_low_level_stats *stats)
  5937. {
  5938. IWL_DEBUG_MAC80211("enter\n");
  5939. IWL_DEBUG_MAC80211("leave\n");
  5940. return 0;
  5941. }
  5942. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  5943. {
  5944. struct iwl3945_priv *priv = hw->priv;
  5945. unsigned long flags;
  5946. mutex_lock(&priv->mutex);
  5947. IWL_DEBUG_MAC80211("enter\n");
  5948. iwl3945_reset_qos(priv);
  5949. spin_lock_irqsave(&priv->lock, flags);
  5950. priv->assoc_id = 0;
  5951. priv->assoc_capability = 0;
  5952. priv->call_post_assoc_from_beacon = 0;
  5953. /* new association get rid of ibss beacon skb */
  5954. if (priv->ibss_beacon)
  5955. dev_kfree_skb(priv->ibss_beacon);
  5956. priv->ibss_beacon = NULL;
  5957. priv->beacon_int = priv->hw->conf.beacon_int;
  5958. priv->timestamp1 = 0;
  5959. priv->timestamp0 = 0;
  5960. if ((priv->iw_mode == NL80211_IFTYPE_STATION))
  5961. priv->beacon_int = 0;
  5962. spin_unlock_irqrestore(&priv->lock, flags);
  5963. if (!iwl3945_is_ready_rf(priv)) {
  5964. IWL_DEBUG_MAC80211("leave - not ready\n");
  5965. mutex_unlock(&priv->mutex);
  5966. return;
  5967. }
  5968. /* we are restarting association process
  5969. * clear RXON_FILTER_ASSOC_MSK bit
  5970. */
  5971. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  5972. iwl3945_scan_cancel_timeout(priv, 100);
  5973. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5974. iwl3945_commit_rxon(priv);
  5975. }
  5976. /* Per mac80211.h: This is only used in IBSS mode... */
  5977. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5978. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  5979. mutex_unlock(&priv->mutex);
  5980. return;
  5981. }
  5982. iwl3945_set_rate(priv);
  5983. mutex_unlock(&priv->mutex);
  5984. IWL_DEBUG_MAC80211("leave\n");
  5985. }
  5986. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  5987. {
  5988. struct iwl3945_priv *priv = hw->priv;
  5989. unsigned long flags;
  5990. IWL_DEBUG_MAC80211("enter\n");
  5991. if (!iwl3945_is_ready_rf(priv)) {
  5992. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5993. return -EIO;
  5994. }
  5995. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5996. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  5997. return -EIO;
  5998. }
  5999. spin_lock_irqsave(&priv->lock, flags);
  6000. if (priv->ibss_beacon)
  6001. dev_kfree_skb(priv->ibss_beacon);
  6002. priv->ibss_beacon = skb;
  6003. priv->assoc_id = 0;
  6004. IWL_DEBUG_MAC80211("leave\n");
  6005. spin_unlock_irqrestore(&priv->lock, flags);
  6006. iwl3945_reset_qos(priv);
  6007. iwl3945_post_associate(priv);
  6008. return 0;
  6009. }
  6010. /*****************************************************************************
  6011. *
  6012. * sysfs attributes
  6013. *
  6014. *****************************************************************************/
  6015. #ifdef CONFIG_IWL3945_DEBUG
  6016. /*
  6017. * The following adds a new attribute to the sysfs representation
  6018. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  6019. * used for controlling the debug level.
  6020. *
  6021. * See the level definitions in iwl for details.
  6022. */
  6023. static ssize_t show_debug_level(struct device_driver *d, char *buf)
  6024. {
  6025. return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
  6026. }
  6027. static ssize_t store_debug_level(struct device_driver *d,
  6028. const char *buf, size_t count)
  6029. {
  6030. char *p = (char *)buf;
  6031. u32 val;
  6032. val = simple_strtoul(p, &p, 0);
  6033. if (p == buf)
  6034. printk(KERN_INFO DRV_NAME
  6035. ": %s is not in hex or decimal form.\n", buf);
  6036. else
  6037. iwl3945_debug_level = val;
  6038. return strnlen(buf, count);
  6039. }
  6040. static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
  6041. show_debug_level, store_debug_level);
  6042. #endif /* CONFIG_IWL3945_DEBUG */
  6043. static ssize_t show_temperature(struct device *d,
  6044. struct device_attribute *attr, char *buf)
  6045. {
  6046. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6047. if (!iwl3945_is_alive(priv))
  6048. return -EAGAIN;
  6049. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  6050. }
  6051. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  6052. static ssize_t show_tx_power(struct device *d,
  6053. struct device_attribute *attr, char *buf)
  6054. {
  6055. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6056. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  6057. }
  6058. static ssize_t store_tx_power(struct device *d,
  6059. struct device_attribute *attr,
  6060. const char *buf, size_t count)
  6061. {
  6062. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6063. char *p = (char *)buf;
  6064. u32 val;
  6065. val = simple_strtoul(p, &p, 10);
  6066. if (p == buf)
  6067. printk(KERN_INFO DRV_NAME
  6068. ": %s is not in decimal form.\n", buf);
  6069. else
  6070. iwl3945_hw_reg_set_txpower(priv, val);
  6071. return count;
  6072. }
  6073. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  6074. static ssize_t show_flags(struct device *d,
  6075. struct device_attribute *attr, char *buf)
  6076. {
  6077. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6078. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  6079. }
  6080. static ssize_t store_flags(struct device *d,
  6081. struct device_attribute *attr,
  6082. const char *buf, size_t count)
  6083. {
  6084. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6085. u32 flags = simple_strtoul(buf, NULL, 0);
  6086. mutex_lock(&priv->mutex);
  6087. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  6088. /* Cancel any currently running scans... */
  6089. if (iwl3945_scan_cancel_timeout(priv, 100))
  6090. IWL_WARNING("Could not cancel scan.\n");
  6091. else {
  6092. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  6093. flags);
  6094. priv->staging_rxon.flags = cpu_to_le32(flags);
  6095. iwl3945_commit_rxon(priv);
  6096. }
  6097. }
  6098. mutex_unlock(&priv->mutex);
  6099. return count;
  6100. }
  6101. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  6102. static ssize_t show_filter_flags(struct device *d,
  6103. struct device_attribute *attr, char *buf)
  6104. {
  6105. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6106. return sprintf(buf, "0x%04X\n",
  6107. le32_to_cpu(priv->active_rxon.filter_flags));
  6108. }
  6109. static ssize_t store_filter_flags(struct device *d,
  6110. struct device_attribute *attr,
  6111. const char *buf, size_t count)
  6112. {
  6113. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6114. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  6115. mutex_lock(&priv->mutex);
  6116. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  6117. /* Cancel any currently running scans... */
  6118. if (iwl3945_scan_cancel_timeout(priv, 100))
  6119. IWL_WARNING("Could not cancel scan.\n");
  6120. else {
  6121. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  6122. "0x%04X\n", filter_flags);
  6123. priv->staging_rxon.filter_flags =
  6124. cpu_to_le32(filter_flags);
  6125. iwl3945_commit_rxon(priv);
  6126. }
  6127. }
  6128. mutex_unlock(&priv->mutex);
  6129. return count;
  6130. }
  6131. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  6132. store_filter_flags);
  6133. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6134. static ssize_t show_measurement(struct device *d,
  6135. struct device_attribute *attr, char *buf)
  6136. {
  6137. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6138. struct iwl_spectrum_notification measure_report;
  6139. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  6140. u8 *data = (u8 *)&measure_report;
  6141. unsigned long flags;
  6142. spin_lock_irqsave(&priv->lock, flags);
  6143. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  6144. spin_unlock_irqrestore(&priv->lock, flags);
  6145. return 0;
  6146. }
  6147. memcpy(&measure_report, &priv->measure_report, size);
  6148. priv->measurement_status = 0;
  6149. spin_unlock_irqrestore(&priv->lock, flags);
  6150. while (size && (PAGE_SIZE - len)) {
  6151. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6152. PAGE_SIZE - len, 1);
  6153. len = strlen(buf);
  6154. if (PAGE_SIZE - len)
  6155. buf[len++] = '\n';
  6156. ofs += 16;
  6157. size -= min(size, 16U);
  6158. }
  6159. return len;
  6160. }
  6161. static ssize_t store_measurement(struct device *d,
  6162. struct device_attribute *attr,
  6163. const char *buf, size_t count)
  6164. {
  6165. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6166. struct ieee80211_measurement_params params = {
  6167. .channel = le16_to_cpu(priv->active_rxon.channel),
  6168. .start_time = cpu_to_le64(priv->last_tsf),
  6169. .duration = cpu_to_le16(1),
  6170. };
  6171. u8 type = IWL_MEASURE_BASIC;
  6172. u8 buffer[32];
  6173. u8 channel;
  6174. if (count) {
  6175. char *p = buffer;
  6176. strncpy(buffer, buf, min(sizeof(buffer), count));
  6177. channel = simple_strtoul(p, NULL, 0);
  6178. if (channel)
  6179. params.channel = channel;
  6180. p = buffer;
  6181. while (*p && *p != ' ')
  6182. p++;
  6183. if (*p)
  6184. type = simple_strtoul(p + 1, NULL, 0);
  6185. }
  6186. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  6187. "channel %d (for '%s')\n", type, params.channel, buf);
  6188. iwl3945_get_measurement(priv, &params, type);
  6189. return count;
  6190. }
  6191. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  6192. show_measurement, store_measurement);
  6193. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  6194. static ssize_t store_retry_rate(struct device *d,
  6195. struct device_attribute *attr,
  6196. const char *buf, size_t count)
  6197. {
  6198. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6199. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  6200. if (priv->retry_rate <= 0)
  6201. priv->retry_rate = 1;
  6202. return count;
  6203. }
  6204. static ssize_t show_retry_rate(struct device *d,
  6205. struct device_attribute *attr, char *buf)
  6206. {
  6207. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6208. return sprintf(buf, "%d", priv->retry_rate);
  6209. }
  6210. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  6211. store_retry_rate);
  6212. static ssize_t store_power_level(struct device *d,
  6213. struct device_attribute *attr,
  6214. const char *buf, size_t count)
  6215. {
  6216. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6217. int rc;
  6218. int mode;
  6219. mode = simple_strtoul(buf, NULL, 0);
  6220. mutex_lock(&priv->mutex);
  6221. if (!iwl3945_is_ready(priv)) {
  6222. rc = -EAGAIN;
  6223. goto out;
  6224. }
  6225. if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
  6226. mode = IWL_POWER_AC;
  6227. else
  6228. mode |= IWL_POWER_ENABLED;
  6229. if (mode != priv->power_mode) {
  6230. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  6231. if (rc) {
  6232. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  6233. goto out;
  6234. }
  6235. priv->power_mode = mode;
  6236. }
  6237. rc = count;
  6238. out:
  6239. mutex_unlock(&priv->mutex);
  6240. return rc;
  6241. }
  6242. #define MAX_WX_STRING 80
  6243. /* Values are in microsecond */
  6244. static const s32 timeout_duration[] = {
  6245. 350000,
  6246. 250000,
  6247. 75000,
  6248. 37000,
  6249. 25000,
  6250. };
  6251. static const s32 period_duration[] = {
  6252. 400000,
  6253. 700000,
  6254. 1000000,
  6255. 1000000,
  6256. 1000000
  6257. };
  6258. static ssize_t show_power_level(struct device *d,
  6259. struct device_attribute *attr, char *buf)
  6260. {
  6261. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6262. int level = IWL_POWER_LEVEL(priv->power_mode);
  6263. char *p = buf;
  6264. p += sprintf(p, "%d ", level);
  6265. switch (level) {
  6266. case IWL_POWER_MODE_CAM:
  6267. case IWL_POWER_AC:
  6268. p += sprintf(p, "(AC)");
  6269. break;
  6270. case IWL_POWER_BATTERY:
  6271. p += sprintf(p, "(BATTERY)");
  6272. break;
  6273. default:
  6274. p += sprintf(p,
  6275. "(Timeout %dms, Period %dms)",
  6276. timeout_duration[level - 1] / 1000,
  6277. period_duration[level - 1] / 1000);
  6278. }
  6279. if (!(priv->power_mode & IWL_POWER_ENABLED))
  6280. p += sprintf(p, " OFF\n");
  6281. else
  6282. p += sprintf(p, " \n");
  6283. return p - buf + 1;
  6284. }
  6285. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  6286. store_power_level);
  6287. static ssize_t show_channels(struct device *d,
  6288. struct device_attribute *attr, char *buf)
  6289. {
  6290. /* all this shit doesn't belong into sysfs anyway */
  6291. return 0;
  6292. }
  6293. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  6294. static ssize_t show_statistics(struct device *d,
  6295. struct device_attribute *attr, char *buf)
  6296. {
  6297. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6298. u32 size = sizeof(struct iwl3945_notif_statistics);
  6299. u32 len = 0, ofs = 0;
  6300. u8 *data = (u8 *)&priv->statistics;
  6301. int rc = 0;
  6302. if (!iwl3945_is_alive(priv))
  6303. return -EAGAIN;
  6304. mutex_lock(&priv->mutex);
  6305. rc = iwl3945_send_statistics_request(priv);
  6306. mutex_unlock(&priv->mutex);
  6307. if (rc) {
  6308. len = sprintf(buf,
  6309. "Error sending statistics request: 0x%08X\n", rc);
  6310. return len;
  6311. }
  6312. while (size && (PAGE_SIZE - len)) {
  6313. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6314. PAGE_SIZE - len, 1);
  6315. len = strlen(buf);
  6316. if (PAGE_SIZE - len)
  6317. buf[len++] = '\n';
  6318. ofs += 16;
  6319. size -= min(size, 16U);
  6320. }
  6321. return len;
  6322. }
  6323. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  6324. static ssize_t show_antenna(struct device *d,
  6325. struct device_attribute *attr, char *buf)
  6326. {
  6327. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6328. if (!iwl3945_is_alive(priv))
  6329. return -EAGAIN;
  6330. return sprintf(buf, "%d\n", priv->antenna);
  6331. }
  6332. static ssize_t store_antenna(struct device *d,
  6333. struct device_attribute *attr,
  6334. const char *buf, size_t count)
  6335. {
  6336. int ant;
  6337. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6338. if (count == 0)
  6339. return 0;
  6340. if (sscanf(buf, "%1i", &ant) != 1) {
  6341. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  6342. return count;
  6343. }
  6344. if ((ant >= 0) && (ant <= 2)) {
  6345. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  6346. priv->antenna = (enum iwl3945_antenna)ant;
  6347. } else
  6348. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  6349. return count;
  6350. }
  6351. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  6352. static ssize_t show_status(struct device *d,
  6353. struct device_attribute *attr, char *buf)
  6354. {
  6355. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6356. if (!iwl3945_is_alive(priv))
  6357. return -EAGAIN;
  6358. return sprintf(buf, "0x%08x\n", (int)priv->status);
  6359. }
  6360. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  6361. static ssize_t dump_error_log(struct device *d,
  6362. struct device_attribute *attr,
  6363. const char *buf, size_t count)
  6364. {
  6365. char *p = (char *)buf;
  6366. if (p[0] == '1')
  6367. iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
  6368. return strnlen(buf, count);
  6369. }
  6370. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  6371. static ssize_t dump_event_log(struct device *d,
  6372. struct device_attribute *attr,
  6373. const char *buf, size_t count)
  6374. {
  6375. char *p = (char *)buf;
  6376. if (p[0] == '1')
  6377. iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
  6378. return strnlen(buf, count);
  6379. }
  6380. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  6381. /*****************************************************************************
  6382. *
  6383. * driver setup and tear down
  6384. *
  6385. *****************************************************************************/
  6386. static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
  6387. {
  6388. priv->workqueue = create_workqueue(DRV_NAME);
  6389. init_waitqueue_head(&priv->wait_command_queue);
  6390. INIT_WORK(&priv->up, iwl3945_bg_up);
  6391. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  6392. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  6393. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  6394. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  6395. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  6396. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  6397. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  6398. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  6399. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  6400. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  6401. iwl3945_hw_setup_deferred_work(priv);
  6402. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  6403. iwl3945_irq_tasklet, (unsigned long)priv);
  6404. }
  6405. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
  6406. {
  6407. iwl3945_hw_cancel_deferred_work(priv);
  6408. cancel_delayed_work_sync(&priv->init_alive_start);
  6409. cancel_delayed_work(&priv->scan_check);
  6410. cancel_delayed_work(&priv->alive_start);
  6411. cancel_work_sync(&priv->beacon_update);
  6412. }
  6413. static struct attribute *iwl3945_sysfs_entries[] = {
  6414. &dev_attr_antenna.attr,
  6415. &dev_attr_channels.attr,
  6416. &dev_attr_dump_errors.attr,
  6417. &dev_attr_dump_events.attr,
  6418. &dev_attr_flags.attr,
  6419. &dev_attr_filter_flags.attr,
  6420. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6421. &dev_attr_measurement.attr,
  6422. #endif
  6423. &dev_attr_power_level.attr,
  6424. &dev_attr_retry_rate.attr,
  6425. &dev_attr_statistics.attr,
  6426. &dev_attr_status.attr,
  6427. &dev_attr_temperature.attr,
  6428. &dev_attr_tx_power.attr,
  6429. NULL
  6430. };
  6431. static struct attribute_group iwl3945_attribute_group = {
  6432. .name = NULL, /* put in device directory */
  6433. .attrs = iwl3945_sysfs_entries,
  6434. };
  6435. static struct ieee80211_ops iwl3945_hw_ops = {
  6436. .tx = iwl3945_mac_tx,
  6437. .start = iwl3945_mac_start,
  6438. .stop = iwl3945_mac_stop,
  6439. .add_interface = iwl3945_mac_add_interface,
  6440. .remove_interface = iwl3945_mac_remove_interface,
  6441. .config = iwl3945_mac_config,
  6442. .config_interface = iwl3945_mac_config_interface,
  6443. .configure_filter = iwl3945_configure_filter,
  6444. .set_key = iwl3945_mac_set_key,
  6445. .get_stats = iwl3945_mac_get_stats,
  6446. .get_tx_stats = iwl3945_mac_get_tx_stats,
  6447. .conf_tx = iwl3945_mac_conf_tx,
  6448. .reset_tsf = iwl3945_mac_reset_tsf,
  6449. .bss_info_changed = iwl3945_bss_info_changed,
  6450. .hw_scan = iwl3945_mac_hw_scan
  6451. };
  6452. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6453. {
  6454. int err = 0;
  6455. struct iwl3945_priv *priv;
  6456. struct ieee80211_hw *hw;
  6457. struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data);
  6458. unsigned long flags;
  6459. /***********************
  6460. * 1. Allocating HW data
  6461. * ********************/
  6462. /* Disabling hardware scan means that mac80211 will perform scans
  6463. * "the hard way", rather than using device's scan. */
  6464. if (iwl3945_param_disable_hw_scan) {
  6465. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6466. iwl3945_hw_ops.hw_scan = NULL;
  6467. }
  6468. if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) ||
  6469. (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
  6470. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  6471. IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
  6472. err = -EINVAL;
  6473. goto out;
  6474. }
  6475. /* mac80211 allocates memory for this device instance, including
  6476. * space for this driver's private structure */
  6477. hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
  6478. if (hw == NULL) {
  6479. IWL_ERROR("Can not allocate network device\n");
  6480. err = -ENOMEM;
  6481. goto out;
  6482. }
  6483. SET_IEEE80211_DEV(hw, &pdev->dev);
  6484. priv = hw->priv;
  6485. priv->hw = hw;
  6486. priv->pci_dev = pdev;
  6487. priv->cfg = cfg;
  6488. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6489. hw->rate_control_algorithm = "iwl-3945-rs";
  6490. hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
  6491. /* Select antenna (may be helpful if only one antenna is connected) */
  6492. priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
  6493. #ifdef CONFIG_IWL3945_DEBUG
  6494. iwl3945_debug_level = iwl3945_param_debug;
  6495. atomic_set(&priv->restrict_refcnt, 0);
  6496. #endif
  6497. /* Tell mac80211 our characteristics */
  6498. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  6499. IEEE80211_HW_NOISE_DBM;
  6500. hw->wiphy->interface_modes =
  6501. BIT(NL80211_IFTYPE_STATION) |
  6502. BIT(NL80211_IFTYPE_ADHOC);
  6503. hw->wiphy->fw_handles_regulatory = true;
  6504. /* 4 EDCA QOS priorities */
  6505. hw->queues = 4;
  6506. /***************************
  6507. * 2. Initializing PCI bus
  6508. * *************************/
  6509. if (pci_enable_device(pdev)) {
  6510. err = -ENODEV;
  6511. goto out_ieee80211_free_hw;
  6512. }
  6513. pci_set_master(pdev);
  6514. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6515. if (!err)
  6516. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6517. if (err) {
  6518. printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
  6519. goto out_pci_disable_device;
  6520. }
  6521. pci_set_drvdata(pdev, priv);
  6522. err = pci_request_regions(pdev, DRV_NAME);
  6523. if (err)
  6524. goto out_pci_disable_device;
  6525. /***********************
  6526. * 3. Read REV Register
  6527. * ********************/
  6528. priv->hw_base = pci_iomap(pdev, 0, 0);
  6529. if (!priv->hw_base) {
  6530. err = -ENODEV;
  6531. goto out_pci_release_regions;
  6532. }
  6533. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6534. (unsigned long long) pci_resource_len(pdev, 0));
  6535. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6536. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6537. * PCI Tx retries from interfering with C3 CPU state */
  6538. pci_write_config_byte(pdev, 0x41, 0x00);
  6539. /* nic init */
  6540. iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  6541. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  6542. iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  6543. err = iwl3945_poll_direct_bit(priv, CSR_GP_CNTRL,
  6544. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  6545. if (err < 0) {
  6546. IWL_DEBUG_INFO("Failed to init the card\n");
  6547. goto out_remove_sysfs;
  6548. }
  6549. /***********************
  6550. * 4. Read EEPROM
  6551. * ********************/
  6552. /* Read the EEPROM */
  6553. err = iwl3945_eeprom_init(priv);
  6554. if (err) {
  6555. IWL_ERROR("Unable to init EEPROM\n");
  6556. goto out_remove_sysfs;
  6557. }
  6558. /* MAC Address location in EEPROM same for 3945/4965 */
  6559. get_eeprom_mac(priv, priv->mac_addr);
  6560. IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr);
  6561. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  6562. /***********************
  6563. * 5. Setup HW Constants
  6564. * ********************/
  6565. /* Device-specific setup */
  6566. if (iwl3945_hw_set_hw_setting(priv)) {
  6567. IWL_ERROR("failed to set hw settings\n");
  6568. goto out_iounmap;
  6569. }
  6570. /***********************
  6571. * 6. Setup priv
  6572. * ********************/
  6573. priv->retry_rate = 1;
  6574. priv->ibss_beacon = NULL;
  6575. spin_lock_init(&priv->lock);
  6576. spin_lock_init(&priv->power_data.lock);
  6577. spin_lock_init(&priv->sta_lock);
  6578. spin_lock_init(&priv->hcmd_lock);
  6579. INIT_LIST_HEAD(&priv->free_frames);
  6580. mutex_init(&priv->mutex);
  6581. /* Clear the driver's (not device's) station table */
  6582. iwl3945_clear_stations_table(priv);
  6583. priv->data_retry_limit = -1;
  6584. priv->ieee_channels = NULL;
  6585. priv->ieee_rates = NULL;
  6586. priv->band = IEEE80211_BAND_2GHZ;
  6587. priv->iw_mode = NL80211_IFTYPE_STATION;
  6588. iwl3945_reset_qos(priv);
  6589. priv->qos_data.qos_active = 0;
  6590. priv->qos_data.qos_cap.val = 0;
  6591. priv->rates_mask = IWL_RATES_MASK;
  6592. /* If power management is turned on, default to AC mode */
  6593. priv->power_mode = IWL_POWER_AC;
  6594. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  6595. err = iwl3945_init_channel_map(priv);
  6596. if (err) {
  6597. IWL_ERROR("initializing regulatory failed: %d\n", err);
  6598. goto out_release_irq;
  6599. }
  6600. err = iwl3945_init_geos(priv);
  6601. if (err) {
  6602. IWL_ERROR("initializing geos failed: %d\n", err);
  6603. goto out_free_channel_map;
  6604. }
  6605. printk(KERN_INFO DRV_NAME
  6606. ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
  6607. /***********************************
  6608. * 7. Initialize Module Parameters
  6609. * **********************************/
  6610. /* Initialize module parameter values here */
  6611. /* Disable radio (SW RF KILL) via parameter when loading driver */
  6612. if (iwl3945_param_disable) {
  6613. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6614. IWL_DEBUG_INFO("Radio disabled.\n");
  6615. }
  6616. /***********************
  6617. * 8. Setup Services
  6618. * ********************/
  6619. spin_lock_irqsave(&priv->lock, flags);
  6620. iwl3945_disable_interrupts(priv);
  6621. spin_unlock_irqrestore(&priv->lock, flags);
  6622. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6623. if (err) {
  6624. IWL_ERROR("failed to create sysfs device attributes\n");
  6625. goto out_free_geos;
  6626. }
  6627. iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  6628. iwl3945_setup_deferred_work(priv);
  6629. iwl3945_setup_rx_handlers(priv);
  6630. /***********************
  6631. * 9. Conclude
  6632. * ********************/
  6633. pci_save_state(pdev);
  6634. pci_disable_device(pdev);
  6635. /*********************************
  6636. * 10. Setup and Register mac80211
  6637. * *******************************/
  6638. err = ieee80211_register_hw(priv->hw);
  6639. if (err) {
  6640. IWL_ERROR("Failed to register network device (error %d)\n", err);
  6641. goto out_remove_sysfs;
  6642. }
  6643. priv->hw->conf.beacon_int = 100;
  6644. priv->mac80211_registered = 1;
  6645. err = iwl3945_rfkill_init(priv);
  6646. if (err)
  6647. IWL_ERROR("Unable to initialize RFKILL system. "
  6648. "Ignoring error: %d\n", err);
  6649. return 0;
  6650. out_remove_sysfs:
  6651. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6652. out_free_geos:
  6653. iwl3945_free_geos(priv);
  6654. out_free_channel_map:
  6655. iwl3945_free_channel_map(priv);
  6656. out_release_irq:
  6657. destroy_workqueue(priv->workqueue);
  6658. priv->workqueue = NULL;
  6659. iwl3945_unset_hw_setting(priv);
  6660. out_iounmap:
  6661. pci_iounmap(pdev, priv->hw_base);
  6662. out_pci_release_regions:
  6663. pci_release_regions(pdev);
  6664. out_pci_disable_device:
  6665. pci_disable_device(pdev);
  6666. pci_set_drvdata(pdev, NULL);
  6667. out_ieee80211_free_hw:
  6668. ieee80211_free_hw(priv->hw);
  6669. out:
  6670. return err;
  6671. }
  6672. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  6673. {
  6674. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6675. unsigned long flags;
  6676. if (!priv)
  6677. return;
  6678. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  6679. set_bit(STATUS_EXIT_PENDING, &priv->status);
  6680. iwl3945_down(priv);
  6681. /* make sure we flush any pending irq or
  6682. * tasklet for the driver
  6683. */
  6684. spin_lock_irqsave(&priv->lock, flags);
  6685. iwl3945_disable_interrupts(priv);
  6686. spin_unlock_irqrestore(&priv->lock, flags);
  6687. iwl_synchronize_irq(priv);
  6688. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6689. iwl3945_rfkill_unregister(priv);
  6690. iwl3945_dealloc_ucode_pci(priv);
  6691. if (priv->rxq.bd)
  6692. iwl3945_rx_queue_free(priv, &priv->rxq);
  6693. iwl3945_hw_txq_ctx_free(priv);
  6694. iwl3945_unset_hw_setting(priv);
  6695. iwl3945_clear_stations_table(priv);
  6696. if (priv->mac80211_registered)
  6697. ieee80211_unregister_hw(priv->hw);
  6698. /*netif_stop_queue(dev); */
  6699. flush_workqueue(priv->workqueue);
  6700. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  6701. * priv->workqueue... so we can't take down the workqueue
  6702. * until now... */
  6703. destroy_workqueue(priv->workqueue);
  6704. priv->workqueue = NULL;
  6705. pci_iounmap(pdev, priv->hw_base);
  6706. pci_release_regions(pdev);
  6707. pci_disable_device(pdev);
  6708. pci_set_drvdata(pdev, NULL);
  6709. iwl3945_free_channel_map(priv);
  6710. iwl3945_free_geos(priv);
  6711. kfree(priv->scan);
  6712. if (priv->ibss_beacon)
  6713. dev_kfree_skb(priv->ibss_beacon);
  6714. ieee80211_free_hw(priv->hw);
  6715. }
  6716. #ifdef CONFIG_PM
  6717. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  6718. {
  6719. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6720. if (priv->is_open) {
  6721. set_bit(STATUS_IN_SUSPEND, &priv->status);
  6722. iwl3945_mac_stop(priv->hw);
  6723. priv->is_open = 1;
  6724. }
  6725. pci_set_power_state(pdev, PCI_D3hot);
  6726. return 0;
  6727. }
  6728. static int iwl3945_pci_resume(struct pci_dev *pdev)
  6729. {
  6730. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6731. pci_set_power_state(pdev, PCI_D0);
  6732. if (priv->is_open)
  6733. iwl3945_mac_start(priv->hw);
  6734. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  6735. return 0;
  6736. }
  6737. #endif /* CONFIG_PM */
  6738. /*************** RFKILL FUNCTIONS **********/
  6739. #ifdef CONFIG_IWL3945_RFKILL
  6740. /* software rf-kill from user */
  6741. static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
  6742. {
  6743. struct iwl3945_priv *priv = data;
  6744. int err = 0;
  6745. if (!priv->rfkill)
  6746. return 0;
  6747. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  6748. return 0;
  6749. IWL_DEBUG_RF_KILL("we received soft RFKILL set to state %d\n", state);
  6750. mutex_lock(&priv->mutex);
  6751. switch (state) {
  6752. case RFKILL_STATE_UNBLOCKED:
  6753. if (iwl3945_is_rfkill_hw(priv)) {
  6754. err = -EBUSY;
  6755. goto out_unlock;
  6756. }
  6757. iwl3945_radio_kill_sw(priv, 0);
  6758. break;
  6759. case RFKILL_STATE_SOFT_BLOCKED:
  6760. iwl3945_radio_kill_sw(priv, 1);
  6761. break;
  6762. default:
  6763. IWL_WARNING("we received unexpected RFKILL state %d\n", state);
  6764. break;
  6765. }
  6766. out_unlock:
  6767. mutex_unlock(&priv->mutex);
  6768. return err;
  6769. }
  6770. int iwl3945_rfkill_init(struct iwl3945_priv *priv)
  6771. {
  6772. struct device *device = wiphy_dev(priv->hw->wiphy);
  6773. int ret = 0;
  6774. BUG_ON(device == NULL);
  6775. IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
  6776. priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
  6777. if (!priv->rfkill) {
  6778. IWL_ERROR("Unable to allocate rfkill device.\n");
  6779. ret = -ENOMEM;
  6780. goto error;
  6781. }
  6782. priv->rfkill->name = priv->cfg->name;
  6783. priv->rfkill->data = priv;
  6784. priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
  6785. priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
  6786. priv->rfkill->user_claim_unsupported = 1;
  6787. priv->rfkill->dev.class->suspend = NULL;
  6788. priv->rfkill->dev.class->resume = NULL;
  6789. ret = rfkill_register(priv->rfkill);
  6790. if (ret) {
  6791. IWL_ERROR("Unable to register rfkill: %d\n", ret);
  6792. goto freed_rfkill;
  6793. }
  6794. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6795. return ret;
  6796. freed_rfkill:
  6797. if (priv->rfkill != NULL)
  6798. rfkill_free(priv->rfkill);
  6799. priv->rfkill = NULL;
  6800. error:
  6801. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6802. return ret;
  6803. }
  6804. void iwl3945_rfkill_unregister(struct iwl3945_priv *priv)
  6805. {
  6806. if (priv->rfkill)
  6807. rfkill_unregister(priv->rfkill);
  6808. priv->rfkill = NULL;
  6809. }
  6810. /* set rf-kill to the right state. */
  6811. void iwl3945_rfkill_set_hw_state(struct iwl3945_priv *priv)
  6812. {
  6813. if (!priv->rfkill)
  6814. return;
  6815. if (iwl3945_is_rfkill_hw(priv)) {
  6816. rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
  6817. return;
  6818. }
  6819. if (!iwl3945_is_rfkill_sw(priv))
  6820. rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
  6821. else
  6822. rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
  6823. }
  6824. #endif
  6825. /*****************************************************************************
  6826. *
  6827. * driver and module entry point
  6828. *
  6829. *****************************************************************************/
  6830. static struct pci_driver iwl3945_driver = {
  6831. .name = DRV_NAME,
  6832. .id_table = iwl3945_hw_card_ids,
  6833. .probe = iwl3945_pci_probe,
  6834. .remove = __devexit_p(iwl3945_pci_remove),
  6835. #ifdef CONFIG_PM
  6836. .suspend = iwl3945_pci_suspend,
  6837. .resume = iwl3945_pci_resume,
  6838. #endif
  6839. };
  6840. static int __init iwl3945_init(void)
  6841. {
  6842. int ret;
  6843. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  6844. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  6845. ret = iwl3945_rate_control_register();
  6846. if (ret) {
  6847. IWL_ERROR("Unable to register rate control algorithm: %d\n", ret);
  6848. return ret;
  6849. }
  6850. ret = pci_register_driver(&iwl3945_driver);
  6851. if (ret) {
  6852. IWL_ERROR("Unable to initialize PCI module\n");
  6853. goto error_register;
  6854. }
  6855. #ifdef CONFIG_IWL3945_DEBUG
  6856. ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  6857. if (ret) {
  6858. IWL_ERROR("Unable to create driver sysfs file\n");
  6859. goto error_debug;
  6860. }
  6861. #endif
  6862. return ret;
  6863. #ifdef CONFIG_IWL3945_DEBUG
  6864. error_debug:
  6865. pci_unregister_driver(&iwl3945_driver);
  6866. #endif
  6867. error_register:
  6868. iwl3945_rate_control_unregister();
  6869. return ret;
  6870. }
  6871. static void __exit iwl3945_exit(void)
  6872. {
  6873. #ifdef CONFIG_IWL3945_DEBUG
  6874. driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  6875. #endif
  6876. pci_unregister_driver(&iwl3945_driver);
  6877. iwl3945_rate_control_unregister();
  6878. }
  6879. MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
  6880. module_param_named(antenna, iwl3945_param_antenna, int, 0444);
  6881. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  6882. module_param_named(disable, iwl3945_param_disable, int, 0444);
  6883. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  6884. module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
  6885. MODULE_PARM_DESC(hwcrypto,
  6886. "using hardware crypto engine (default 0 [software])\n");
  6887. module_param_named(debug, iwl3945_param_debug, uint, 0444);
  6888. MODULE_PARM_DESC(debug, "debug output mask");
  6889. module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
  6890. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  6891. module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
  6892. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  6893. module_exit(iwl3945_exit);
  6894. module_init(iwl3945_init);