nouveau_sgdma.c 7.7 KB

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  1. #include "drmP.h"
  2. #include "nouveau_drv.h"
  3. #include <linux/pagemap.h>
  4. #include <linux/slab.h>
  5. #define NV_CTXDMA_PAGE_SHIFT 12
  6. #define NV_CTXDMA_PAGE_SIZE (1 << NV_CTXDMA_PAGE_SHIFT)
  7. #define NV_CTXDMA_PAGE_MASK (NV_CTXDMA_PAGE_SIZE - 1)
  8. struct nouveau_sgdma_be {
  9. struct ttm_backend backend;
  10. struct drm_device *dev;
  11. dma_addr_t *pages;
  12. unsigned nr_pages;
  13. unsigned pte_start;
  14. bool bound;
  15. };
  16. static int
  17. nouveau_sgdma_populate(struct ttm_backend *be, unsigned long num_pages,
  18. struct page **pages, struct page *dummy_read_page)
  19. {
  20. struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
  21. struct drm_device *dev = nvbe->dev;
  22. NV_DEBUG(nvbe->dev, "num_pages = %ld\n", num_pages);
  23. if (nvbe->pages)
  24. return -EINVAL;
  25. nvbe->pages = kmalloc(sizeof(dma_addr_t) * num_pages, GFP_KERNEL);
  26. if (!nvbe->pages)
  27. return -ENOMEM;
  28. nvbe->nr_pages = 0;
  29. while (num_pages--) {
  30. nvbe->pages[nvbe->nr_pages] =
  31. pci_map_page(dev->pdev, pages[nvbe->nr_pages], 0,
  32. PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  33. if (pci_dma_mapping_error(dev->pdev,
  34. nvbe->pages[nvbe->nr_pages])) {
  35. be->func->clear(be);
  36. return -EFAULT;
  37. }
  38. nvbe->nr_pages++;
  39. }
  40. return 0;
  41. }
  42. static void
  43. nouveau_sgdma_clear(struct ttm_backend *be)
  44. {
  45. struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
  46. struct drm_device *dev;
  47. if (nvbe && nvbe->pages) {
  48. dev = nvbe->dev;
  49. NV_DEBUG(dev, "\n");
  50. if (nvbe->bound)
  51. be->func->unbind(be);
  52. while (nvbe->nr_pages--) {
  53. pci_unmap_page(dev->pdev, nvbe->pages[nvbe->nr_pages],
  54. PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  55. }
  56. kfree(nvbe->pages);
  57. nvbe->pages = NULL;
  58. nvbe->nr_pages = 0;
  59. }
  60. }
  61. static inline unsigned
  62. nouveau_sgdma_pte(struct drm_device *dev, uint64_t offset)
  63. {
  64. struct drm_nouveau_private *dev_priv = dev->dev_private;
  65. unsigned pte = (offset >> NV_CTXDMA_PAGE_SHIFT);
  66. if (dev_priv->card_type < NV_50)
  67. return pte + 2;
  68. return pte << 1;
  69. }
  70. static int
  71. nouveau_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem)
  72. {
  73. struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
  74. struct drm_device *dev = nvbe->dev;
  75. struct drm_nouveau_private *dev_priv = dev->dev_private;
  76. struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;
  77. unsigned i, j, pte;
  78. NV_DEBUG(dev, "pg=0x%lx\n", mem->mm_node->start);
  79. pte = nouveau_sgdma_pte(nvbe->dev, mem->mm_node->start << PAGE_SHIFT);
  80. nvbe->pte_start = pte;
  81. for (i = 0; i < nvbe->nr_pages; i++) {
  82. dma_addr_t dma_offset = nvbe->pages[i];
  83. uint32_t offset_l = lower_32_bits(dma_offset);
  84. uint32_t offset_h = upper_32_bits(dma_offset);
  85. for (j = 0; j < PAGE_SIZE / NV_CTXDMA_PAGE_SIZE; j++) {
  86. if (dev_priv->card_type < NV_50)
  87. nv_wo32(dev, gpuobj, pte++, offset_l | 3);
  88. else {
  89. nv_wo32(dev, gpuobj, pte++, offset_l | 0x21);
  90. nv_wo32(dev, gpuobj, pte++, offset_h & 0xff);
  91. }
  92. dma_offset += NV_CTXDMA_PAGE_SIZE;
  93. }
  94. }
  95. dev_priv->engine.instmem.flush(nvbe->dev);
  96. if (dev_priv->card_type == NV_50) {
  97. nv50_vm_flush(dev, 5); /* PGRAPH */
  98. nv50_vm_flush(dev, 0); /* PFIFO */
  99. }
  100. nvbe->bound = true;
  101. return 0;
  102. }
  103. static int
  104. nouveau_sgdma_unbind(struct ttm_backend *be)
  105. {
  106. struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
  107. struct drm_device *dev = nvbe->dev;
  108. struct drm_nouveau_private *dev_priv = dev->dev_private;
  109. struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;
  110. unsigned i, j, pte;
  111. NV_DEBUG(dev, "\n");
  112. if (!nvbe->bound)
  113. return 0;
  114. pte = nvbe->pte_start;
  115. for (i = 0; i < nvbe->nr_pages; i++) {
  116. dma_addr_t dma_offset = dev_priv->gart_info.sg_dummy_bus;
  117. for (j = 0; j < PAGE_SIZE / NV_CTXDMA_PAGE_SIZE; j++) {
  118. if (dev_priv->card_type < NV_50)
  119. nv_wo32(dev, gpuobj, pte++, dma_offset | 3);
  120. else {
  121. nv_wo32(dev, gpuobj, pte++, dma_offset | 0x21);
  122. nv_wo32(dev, gpuobj, pte++, 0x00000000);
  123. }
  124. dma_offset += NV_CTXDMA_PAGE_SIZE;
  125. }
  126. }
  127. dev_priv->engine.instmem.flush(nvbe->dev);
  128. if (dev_priv->card_type == NV_50) {
  129. nv50_vm_flush(dev, 5);
  130. nv50_vm_flush(dev, 0);
  131. }
  132. nvbe->bound = false;
  133. return 0;
  134. }
  135. static void
  136. nouveau_sgdma_destroy(struct ttm_backend *be)
  137. {
  138. struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
  139. if (be) {
  140. NV_DEBUG(nvbe->dev, "\n");
  141. if (nvbe) {
  142. if (nvbe->pages)
  143. be->func->clear(be);
  144. kfree(nvbe);
  145. }
  146. }
  147. }
  148. static struct ttm_backend_func nouveau_sgdma_backend = {
  149. .populate = nouveau_sgdma_populate,
  150. .clear = nouveau_sgdma_clear,
  151. .bind = nouveau_sgdma_bind,
  152. .unbind = nouveau_sgdma_unbind,
  153. .destroy = nouveau_sgdma_destroy
  154. };
  155. struct ttm_backend *
  156. nouveau_sgdma_init_ttm(struct drm_device *dev)
  157. {
  158. struct drm_nouveau_private *dev_priv = dev->dev_private;
  159. struct nouveau_sgdma_be *nvbe;
  160. if (!dev_priv->gart_info.sg_ctxdma)
  161. return NULL;
  162. nvbe = kzalloc(sizeof(*nvbe), GFP_KERNEL);
  163. if (!nvbe)
  164. return NULL;
  165. nvbe->dev = dev;
  166. nvbe->backend.func = &nouveau_sgdma_backend;
  167. return &nvbe->backend;
  168. }
  169. int
  170. nouveau_sgdma_init(struct drm_device *dev)
  171. {
  172. struct drm_nouveau_private *dev_priv = dev->dev_private;
  173. struct nouveau_gpuobj *gpuobj = NULL;
  174. uint32_t aper_size, obj_size;
  175. int i, ret;
  176. if (dev_priv->card_type < NV_50) {
  177. aper_size = (64 * 1024 * 1024);
  178. obj_size = (aper_size >> NV_CTXDMA_PAGE_SHIFT) * 4;
  179. obj_size += 8; /* ctxdma header */
  180. } else {
  181. /* 1 entire VM page table */
  182. aper_size = (512 * 1024 * 1024);
  183. obj_size = (aper_size >> NV_CTXDMA_PAGE_SHIFT) * 8;
  184. }
  185. ret = nouveau_gpuobj_new(dev, NULL, obj_size, 16,
  186. NVOBJ_FLAG_ALLOW_NO_REFS |
  187. NVOBJ_FLAG_ZERO_ALLOC |
  188. NVOBJ_FLAG_ZERO_FREE, &gpuobj);
  189. if (ret) {
  190. NV_ERROR(dev, "Error creating sgdma object: %d\n", ret);
  191. return ret;
  192. }
  193. dev_priv->gart_info.sg_dummy_page =
  194. alloc_page(GFP_KERNEL|__GFP_DMA32);
  195. set_bit(PG_locked, &dev_priv->gart_info.sg_dummy_page->flags);
  196. dev_priv->gart_info.sg_dummy_bus =
  197. pci_map_page(dev->pdev, dev_priv->gart_info.sg_dummy_page, 0,
  198. PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  199. if (dev_priv->card_type < NV_50) {
  200. /* Maybe use NV_DMA_TARGET_AGP for PCIE? NVIDIA do this, and
  201. * confirmed to work on c51. Perhaps means NV_DMA_TARGET_PCIE
  202. * on those cards? */
  203. nv_wo32(dev, gpuobj, 0, NV_CLASS_DMA_IN_MEMORY |
  204. (1 << 12) /* PT present */ |
  205. (0 << 13) /* PT *not* linear */ |
  206. (NV_DMA_ACCESS_RW << 14) |
  207. (NV_DMA_TARGET_PCI << 16));
  208. nv_wo32(dev, gpuobj, 1, aper_size - 1);
  209. for (i = 2; i < 2 + (aper_size >> 12); i++) {
  210. nv_wo32(dev, gpuobj, i,
  211. dev_priv->gart_info.sg_dummy_bus | 3);
  212. }
  213. } else {
  214. for (i = 0; i < obj_size; i += 8) {
  215. nv_wo32(dev, gpuobj, (i+0)/4,
  216. dev_priv->gart_info.sg_dummy_bus | 0x21);
  217. nv_wo32(dev, gpuobj, (i+4)/4, 0);
  218. }
  219. }
  220. dev_priv->engine.instmem.flush(dev);
  221. dev_priv->gart_info.type = NOUVEAU_GART_SGDMA;
  222. dev_priv->gart_info.aper_base = 0;
  223. dev_priv->gart_info.aper_size = aper_size;
  224. dev_priv->gart_info.sg_ctxdma = gpuobj;
  225. return 0;
  226. }
  227. void
  228. nouveau_sgdma_takedown(struct drm_device *dev)
  229. {
  230. struct drm_nouveau_private *dev_priv = dev->dev_private;
  231. if (dev_priv->gart_info.sg_dummy_page) {
  232. pci_unmap_page(dev->pdev, dev_priv->gart_info.sg_dummy_bus,
  233. NV_CTXDMA_PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  234. unlock_page(dev_priv->gart_info.sg_dummy_page);
  235. __free_page(dev_priv->gart_info.sg_dummy_page);
  236. dev_priv->gart_info.sg_dummy_page = NULL;
  237. dev_priv->gart_info.sg_dummy_bus = 0;
  238. }
  239. nouveau_gpuobj_del(dev, &dev_priv->gart_info.sg_ctxdma);
  240. }
  241. int
  242. nouveau_sgdma_get_page(struct drm_device *dev, uint32_t offset, uint32_t *page)
  243. {
  244. struct drm_nouveau_private *dev_priv = dev->dev_private;
  245. struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;
  246. int pte;
  247. pte = (offset >> NV_CTXDMA_PAGE_SHIFT);
  248. if (dev_priv->card_type < NV_50) {
  249. *page = nv_ro32(dev, gpuobj, (pte + 2)) & ~NV_CTXDMA_PAGE_MASK;
  250. return 0;
  251. }
  252. NV_ERROR(dev, "Unimplemented on NV50\n");
  253. return -EINVAL;
  254. }