intel_sdvo.c 87 KB

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  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2007 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. */
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <linux/delay.h>
  31. #include "drmP.h"
  32. #include "drm.h"
  33. #include "drm_crtc.h"
  34. #include "intel_drv.h"
  35. #include "drm_edid.h"
  36. #include "i915_drm.h"
  37. #include "i915_drv.h"
  38. #include "intel_sdvo_regs.h"
  39. #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
  40. #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
  41. #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
  42. #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
  43. #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
  44. SDVO_TV_MASK)
  45. #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
  46. #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
  47. static char *tv_format_names[] = {
  48. "NTSC_M" , "NTSC_J" , "NTSC_443",
  49. "PAL_B" , "PAL_D" , "PAL_G" ,
  50. "PAL_H" , "PAL_I" , "PAL_M" ,
  51. "PAL_N" , "PAL_NC" , "PAL_60" ,
  52. "SECAM_B" , "SECAM_D" , "SECAM_G" ,
  53. "SECAM_K" , "SECAM_K1", "SECAM_L" ,
  54. "SECAM_60"
  55. };
  56. #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
  57. struct intel_sdvo_priv {
  58. u8 slave_addr;
  59. /* Register for the SDVO device: SDVOB or SDVOC */
  60. int sdvo_reg;
  61. /* Active outputs controlled by this SDVO output */
  62. uint16_t controlled_output;
  63. /*
  64. * Capabilities of the SDVO device returned by
  65. * i830_sdvo_get_capabilities()
  66. */
  67. struct intel_sdvo_caps caps;
  68. /* Pixel clock limitations reported by the SDVO device, in kHz */
  69. int pixel_clock_min, pixel_clock_max;
  70. /*
  71. * For multiple function SDVO device,
  72. * this is for current attached outputs.
  73. */
  74. uint16_t attached_output;
  75. /**
  76. * This is set if we're going to treat the device as TV-out.
  77. *
  78. * While we have these nice friendly flags for output types that ought
  79. * to decide this for us, the S-Video output on our HDMI+S-Video card
  80. * shows up as RGB1 (VGA).
  81. */
  82. bool is_tv;
  83. /* This is for current tv format name */
  84. char *tv_format_name;
  85. /**
  86. * This is set if we treat the device as HDMI, instead of DVI.
  87. */
  88. bool is_hdmi;
  89. /**
  90. * This is set if we detect output of sdvo device as LVDS.
  91. */
  92. bool is_lvds;
  93. /**
  94. * This is sdvo flags for input timing.
  95. */
  96. uint8_t sdvo_flags;
  97. /**
  98. * This is sdvo fixed pannel mode pointer
  99. */
  100. struct drm_display_mode *sdvo_lvds_fixed_mode;
  101. /*
  102. * supported encoding mode, used to determine whether HDMI is
  103. * supported
  104. */
  105. struct intel_sdvo_encode encode;
  106. /* DDC bus used by this SDVO encoder */
  107. uint8_t ddc_bus;
  108. /* Mac mini hack -- use the same DDC as the analog connector */
  109. struct i2c_adapter *analog_ddc_bus;
  110. };
  111. struct intel_sdvo_connector {
  112. /* Mark the type of connector */
  113. uint16_t output_flag;
  114. /* This contains all current supported TV format */
  115. char *tv_format_supported[TV_FORMAT_NUM];
  116. int format_supported_num;
  117. struct drm_property *tv_format_property;
  118. struct drm_property *tv_format_name_property[TV_FORMAT_NUM];
  119. /**
  120. * Returned SDTV resolutions allowed for the current format, if the
  121. * device reported it.
  122. */
  123. struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
  124. /* add the property for the SDVO-TV */
  125. struct drm_property *left_property;
  126. struct drm_property *right_property;
  127. struct drm_property *top_property;
  128. struct drm_property *bottom_property;
  129. struct drm_property *hpos_property;
  130. struct drm_property *vpos_property;
  131. /* add the property for the SDVO-TV/LVDS */
  132. struct drm_property *brightness_property;
  133. struct drm_property *contrast_property;
  134. struct drm_property *saturation_property;
  135. struct drm_property *hue_property;
  136. /* Add variable to record current setting for the above property */
  137. u32 left_margin, right_margin, top_margin, bottom_margin;
  138. /* this is to get the range of margin.*/
  139. u32 max_hscan, max_vscan;
  140. u32 max_hpos, cur_hpos;
  141. u32 max_vpos, cur_vpos;
  142. u32 cur_brightness, max_brightness;
  143. u32 cur_contrast, max_contrast;
  144. u32 cur_saturation, max_saturation;
  145. u32 cur_hue, max_hue;
  146. };
  147. static bool
  148. intel_sdvo_output_setup(struct intel_encoder *intel_encoder,
  149. uint16_t flags);
  150. static void
  151. intel_sdvo_tv_create_property(struct drm_connector *connector, int type);
  152. static void
  153. intel_sdvo_create_enhance_property(struct drm_connector *connector);
  154. /**
  155. * Writes the SDVOB or SDVOC with the given value, but always writes both
  156. * SDVOB and SDVOC to work around apparent hardware issues (according to
  157. * comments in the BIOS).
  158. */
  159. static void intel_sdvo_write_sdvox(struct intel_encoder *intel_encoder, u32 val)
  160. {
  161. struct drm_device *dev = intel_encoder->enc.dev;
  162. struct drm_i915_private *dev_priv = dev->dev_private;
  163. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  164. u32 bval = val, cval = val;
  165. int i;
  166. if (sdvo_priv->sdvo_reg == PCH_SDVOB) {
  167. I915_WRITE(sdvo_priv->sdvo_reg, val);
  168. I915_READ(sdvo_priv->sdvo_reg);
  169. return;
  170. }
  171. if (sdvo_priv->sdvo_reg == SDVOB) {
  172. cval = I915_READ(SDVOC);
  173. } else {
  174. bval = I915_READ(SDVOB);
  175. }
  176. /*
  177. * Write the registers twice for luck. Sometimes,
  178. * writing them only once doesn't appear to 'stick'.
  179. * The BIOS does this too. Yay, magic
  180. */
  181. for (i = 0; i < 2; i++)
  182. {
  183. I915_WRITE(SDVOB, bval);
  184. I915_READ(SDVOB);
  185. I915_WRITE(SDVOC, cval);
  186. I915_READ(SDVOC);
  187. }
  188. }
  189. static bool intel_sdvo_read_byte(struct intel_encoder *intel_encoder, u8 addr,
  190. u8 *ch)
  191. {
  192. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  193. u8 out_buf[2];
  194. u8 buf[2];
  195. int ret;
  196. struct i2c_msg msgs[] = {
  197. {
  198. .addr = sdvo_priv->slave_addr >> 1,
  199. .flags = 0,
  200. .len = 1,
  201. .buf = out_buf,
  202. },
  203. {
  204. .addr = sdvo_priv->slave_addr >> 1,
  205. .flags = I2C_M_RD,
  206. .len = 1,
  207. .buf = buf,
  208. }
  209. };
  210. out_buf[0] = addr;
  211. out_buf[1] = 0;
  212. if ((ret = i2c_transfer(intel_encoder->i2c_bus, msgs, 2)) == 2)
  213. {
  214. *ch = buf[0];
  215. return true;
  216. }
  217. DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
  218. return false;
  219. }
  220. static bool intel_sdvo_write_byte(struct intel_encoder *intel_encoder, int addr,
  221. u8 ch)
  222. {
  223. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  224. u8 out_buf[2];
  225. struct i2c_msg msgs[] = {
  226. {
  227. .addr = sdvo_priv->slave_addr >> 1,
  228. .flags = 0,
  229. .len = 2,
  230. .buf = out_buf,
  231. }
  232. };
  233. out_buf[0] = addr;
  234. out_buf[1] = ch;
  235. if (i2c_transfer(intel_encoder->i2c_bus, msgs, 1) == 1)
  236. {
  237. return true;
  238. }
  239. return false;
  240. }
  241. #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
  242. /** Mapping of command numbers to names, for debug output */
  243. static const struct _sdvo_cmd_name {
  244. u8 cmd;
  245. char *name;
  246. } sdvo_cmd_names[] = {
  247. SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
  248. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
  249. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
  250. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
  251. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
  252. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
  253. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
  254. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
  255. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
  256. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
  257. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
  258. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
  259. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
  260. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
  261. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
  262. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
  263. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
  264. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  265. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
  266. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  267. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
  268. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
  269. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
  270. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
  271. SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
  272. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
  273. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
  274. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
  275. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
  276. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
  277. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
  278. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
  279. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
  280. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
  281. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
  282. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
  283. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
  284. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
  285. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
  286. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
  287. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
  288. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
  289. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
  290. /* Add the op code for SDVO enhancements */
  291. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_H),
  292. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_H),
  293. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_H),
  294. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_V),
  295. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_V),
  296. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_V),
  297. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
  298. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
  299. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
  300. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
  301. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
  302. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
  303. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
  304. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
  305. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
  306. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
  307. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
  308. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
  309. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
  310. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
  311. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
  312. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
  313. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
  314. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
  315. /* HDMI op code */
  316. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
  317. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
  318. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
  319. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
  320. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
  321. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
  322. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
  323. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
  324. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
  325. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
  326. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
  327. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
  328. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
  329. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
  330. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
  331. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
  332. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
  333. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
  334. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
  335. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
  336. };
  337. #define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
  338. #define SDVO_NAME(dev_priv) (IS_SDVOB((dev_priv)->sdvo_reg) ? "SDVOB" : "SDVOC")
  339. #define SDVO_PRIV(encoder) ((struct intel_sdvo_priv *) (encoder)->dev_priv)
  340. static void intel_sdvo_debug_write(struct intel_encoder *intel_encoder, u8 cmd,
  341. void *args, int args_len)
  342. {
  343. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  344. int i;
  345. DRM_DEBUG_KMS("%s: W: %02X ",
  346. SDVO_NAME(sdvo_priv), cmd);
  347. for (i = 0; i < args_len; i++)
  348. DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
  349. for (; i < 8; i++)
  350. DRM_LOG_KMS(" ");
  351. for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
  352. if (cmd == sdvo_cmd_names[i].cmd) {
  353. DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
  354. break;
  355. }
  356. }
  357. if (i == ARRAY_SIZE(sdvo_cmd_names))
  358. DRM_LOG_KMS("(%02X)", cmd);
  359. DRM_LOG_KMS("\n");
  360. }
  361. static void intel_sdvo_write_cmd(struct intel_encoder *intel_encoder, u8 cmd,
  362. void *args, int args_len)
  363. {
  364. int i;
  365. intel_sdvo_debug_write(intel_encoder, cmd, args, args_len);
  366. for (i = 0; i < args_len; i++) {
  367. intel_sdvo_write_byte(intel_encoder, SDVO_I2C_ARG_0 - i,
  368. ((u8*)args)[i]);
  369. }
  370. intel_sdvo_write_byte(intel_encoder, SDVO_I2C_OPCODE, cmd);
  371. }
  372. static const char *cmd_status_names[] = {
  373. "Power on",
  374. "Success",
  375. "Not supported",
  376. "Invalid arg",
  377. "Pending",
  378. "Target not specified",
  379. "Scaling not supported"
  380. };
  381. static void intel_sdvo_debug_response(struct intel_encoder *intel_encoder,
  382. void *response, int response_len,
  383. u8 status)
  384. {
  385. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  386. int i;
  387. DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv));
  388. for (i = 0; i < response_len; i++)
  389. DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
  390. for (; i < 8; i++)
  391. DRM_LOG_KMS(" ");
  392. if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
  393. DRM_LOG_KMS("(%s)", cmd_status_names[status]);
  394. else
  395. DRM_LOG_KMS("(??? %d)", status);
  396. DRM_LOG_KMS("\n");
  397. }
  398. static u8 intel_sdvo_read_response(struct intel_encoder *intel_encoder,
  399. void *response, int response_len)
  400. {
  401. int i;
  402. u8 status;
  403. u8 retry = 50;
  404. while (retry--) {
  405. /* Read the command response */
  406. for (i = 0; i < response_len; i++) {
  407. intel_sdvo_read_byte(intel_encoder,
  408. SDVO_I2C_RETURN_0 + i,
  409. &((u8 *)response)[i]);
  410. }
  411. /* read the return status */
  412. intel_sdvo_read_byte(intel_encoder, SDVO_I2C_CMD_STATUS,
  413. &status);
  414. intel_sdvo_debug_response(intel_encoder, response, response_len,
  415. status);
  416. if (status != SDVO_CMD_STATUS_PENDING)
  417. return status;
  418. mdelay(50);
  419. }
  420. return status;
  421. }
  422. static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
  423. {
  424. if (mode->clock >= 100000)
  425. return 1;
  426. else if (mode->clock >= 50000)
  427. return 2;
  428. else
  429. return 4;
  430. }
  431. /**
  432. * Try to read the response after issuie the DDC switch command. But it
  433. * is noted that we must do the action of reading response and issuing DDC
  434. * switch command in one I2C transaction. Otherwise when we try to start
  435. * another I2C transaction after issuing the DDC bus switch, it will be
  436. * switched to the internal SDVO register.
  437. */
  438. static void intel_sdvo_set_control_bus_switch(struct intel_encoder *intel_encoder,
  439. u8 target)
  440. {
  441. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  442. u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
  443. struct i2c_msg msgs[] = {
  444. {
  445. .addr = sdvo_priv->slave_addr >> 1,
  446. .flags = 0,
  447. .len = 2,
  448. .buf = out_buf,
  449. },
  450. /* the following two are to read the response */
  451. {
  452. .addr = sdvo_priv->slave_addr >> 1,
  453. .flags = 0,
  454. .len = 1,
  455. .buf = cmd_buf,
  456. },
  457. {
  458. .addr = sdvo_priv->slave_addr >> 1,
  459. .flags = I2C_M_RD,
  460. .len = 1,
  461. .buf = ret_value,
  462. },
  463. };
  464. intel_sdvo_debug_write(intel_encoder, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
  465. &target, 1);
  466. /* write the DDC switch command argument */
  467. intel_sdvo_write_byte(intel_encoder, SDVO_I2C_ARG_0, target);
  468. out_buf[0] = SDVO_I2C_OPCODE;
  469. out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
  470. cmd_buf[0] = SDVO_I2C_CMD_STATUS;
  471. cmd_buf[1] = 0;
  472. ret_value[0] = 0;
  473. ret_value[1] = 0;
  474. ret = i2c_transfer(intel_encoder->i2c_bus, msgs, 3);
  475. if (ret != 3) {
  476. /* failure in I2C transfer */
  477. DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
  478. return;
  479. }
  480. if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) {
  481. DRM_DEBUG_KMS("DDC switch command returns response %d\n",
  482. ret_value[0]);
  483. return;
  484. }
  485. return;
  486. }
  487. static bool intel_sdvo_set_target_input(struct intel_encoder *intel_encoder, bool target_0, bool target_1)
  488. {
  489. struct intel_sdvo_set_target_input_args targets = {0};
  490. u8 status;
  491. if (target_0 && target_1)
  492. return SDVO_CMD_STATUS_NOTSUPP;
  493. if (target_1)
  494. targets.target_1 = 1;
  495. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TARGET_INPUT, &targets,
  496. sizeof(targets));
  497. status = intel_sdvo_read_response(intel_encoder, NULL, 0);
  498. return (status == SDVO_CMD_STATUS_SUCCESS);
  499. }
  500. /**
  501. * Return whether each input is trained.
  502. *
  503. * This function is making an assumption about the layout of the response,
  504. * which should be checked against the docs.
  505. */
  506. static bool intel_sdvo_get_trained_inputs(struct intel_encoder *intel_encoder, bool *input_1, bool *input_2)
  507. {
  508. struct intel_sdvo_get_trained_inputs_response response;
  509. u8 status;
  510. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
  511. status = intel_sdvo_read_response(intel_encoder, &response, sizeof(response));
  512. if (status != SDVO_CMD_STATUS_SUCCESS)
  513. return false;
  514. *input_1 = response.input0_trained;
  515. *input_2 = response.input1_trained;
  516. return true;
  517. }
  518. static bool intel_sdvo_set_active_outputs(struct intel_encoder *intel_encoder,
  519. u16 outputs)
  520. {
  521. u8 status;
  522. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
  523. sizeof(outputs));
  524. status = intel_sdvo_read_response(intel_encoder, NULL, 0);
  525. return (status == SDVO_CMD_STATUS_SUCCESS);
  526. }
  527. static bool intel_sdvo_set_encoder_power_state(struct intel_encoder *intel_encoder,
  528. int mode)
  529. {
  530. u8 status, state = SDVO_ENCODER_STATE_ON;
  531. switch (mode) {
  532. case DRM_MODE_DPMS_ON:
  533. state = SDVO_ENCODER_STATE_ON;
  534. break;
  535. case DRM_MODE_DPMS_STANDBY:
  536. state = SDVO_ENCODER_STATE_STANDBY;
  537. break;
  538. case DRM_MODE_DPMS_SUSPEND:
  539. state = SDVO_ENCODER_STATE_SUSPEND;
  540. break;
  541. case DRM_MODE_DPMS_OFF:
  542. state = SDVO_ENCODER_STATE_OFF;
  543. break;
  544. }
  545. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
  546. sizeof(state));
  547. status = intel_sdvo_read_response(intel_encoder, NULL, 0);
  548. return (status == SDVO_CMD_STATUS_SUCCESS);
  549. }
  550. static bool intel_sdvo_get_input_pixel_clock_range(struct intel_encoder *intel_encoder,
  551. int *clock_min,
  552. int *clock_max)
  553. {
  554. struct intel_sdvo_pixel_clock_range clocks;
  555. u8 status;
  556. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
  557. NULL, 0);
  558. status = intel_sdvo_read_response(intel_encoder, &clocks, sizeof(clocks));
  559. if (status != SDVO_CMD_STATUS_SUCCESS)
  560. return false;
  561. /* Convert the values from units of 10 kHz to kHz. */
  562. *clock_min = clocks.min * 10;
  563. *clock_max = clocks.max * 10;
  564. return true;
  565. }
  566. static bool intel_sdvo_set_target_output(struct intel_encoder *intel_encoder,
  567. u16 outputs)
  568. {
  569. u8 status;
  570. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
  571. sizeof(outputs));
  572. status = intel_sdvo_read_response(intel_encoder, NULL, 0);
  573. return (status == SDVO_CMD_STATUS_SUCCESS);
  574. }
  575. static bool intel_sdvo_set_timing(struct intel_encoder *intel_encoder, u8 cmd,
  576. struct intel_sdvo_dtd *dtd)
  577. {
  578. u8 status;
  579. intel_sdvo_write_cmd(intel_encoder, cmd, &dtd->part1, sizeof(dtd->part1));
  580. status = intel_sdvo_read_response(intel_encoder, NULL, 0);
  581. if (status != SDVO_CMD_STATUS_SUCCESS)
  582. return false;
  583. intel_sdvo_write_cmd(intel_encoder, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  584. status = intel_sdvo_read_response(intel_encoder, NULL, 0);
  585. if (status != SDVO_CMD_STATUS_SUCCESS)
  586. return false;
  587. return true;
  588. }
  589. static bool intel_sdvo_set_input_timing(struct intel_encoder *intel_encoder,
  590. struct intel_sdvo_dtd *dtd)
  591. {
  592. return intel_sdvo_set_timing(intel_encoder,
  593. SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
  594. }
  595. static bool intel_sdvo_set_output_timing(struct intel_encoder *intel_encoder,
  596. struct intel_sdvo_dtd *dtd)
  597. {
  598. return intel_sdvo_set_timing(intel_encoder,
  599. SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
  600. }
  601. static bool
  602. intel_sdvo_create_preferred_input_timing(struct intel_encoder *intel_encoder,
  603. uint16_t clock,
  604. uint16_t width,
  605. uint16_t height)
  606. {
  607. struct intel_sdvo_preferred_input_timing_args args;
  608. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  609. uint8_t status;
  610. memset(&args, 0, sizeof(args));
  611. args.clock = clock;
  612. args.width = width;
  613. args.height = height;
  614. args.interlace = 0;
  615. if (sdvo_priv->is_lvds &&
  616. (sdvo_priv->sdvo_lvds_fixed_mode->hdisplay != width ||
  617. sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height))
  618. args.scaled = 1;
  619. intel_sdvo_write_cmd(intel_encoder,
  620. SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
  621. &args, sizeof(args));
  622. status = intel_sdvo_read_response(intel_encoder, NULL, 0);
  623. if (status != SDVO_CMD_STATUS_SUCCESS)
  624. return false;
  625. return true;
  626. }
  627. static bool intel_sdvo_get_preferred_input_timing(struct intel_encoder *intel_encoder,
  628. struct intel_sdvo_dtd *dtd)
  629. {
  630. bool status;
  631. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
  632. NULL, 0);
  633. status = intel_sdvo_read_response(intel_encoder, &dtd->part1,
  634. sizeof(dtd->part1));
  635. if (status != SDVO_CMD_STATUS_SUCCESS)
  636. return false;
  637. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
  638. NULL, 0);
  639. status = intel_sdvo_read_response(intel_encoder, &dtd->part2,
  640. sizeof(dtd->part2));
  641. if (status != SDVO_CMD_STATUS_SUCCESS)
  642. return false;
  643. return false;
  644. }
  645. static bool intel_sdvo_set_clock_rate_mult(struct intel_encoder *intel_encoder, u8 val)
  646. {
  647. u8 status;
  648. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
  649. status = intel_sdvo_read_response(intel_encoder, NULL, 0);
  650. if (status != SDVO_CMD_STATUS_SUCCESS)
  651. return false;
  652. return true;
  653. }
  654. static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
  655. struct drm_display_mode *mode)
  656. {
  657. uint16_t width, height;
  658. uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
  659. uint16_t h_sync_offset, v_sync_offset;
  660. width = mode->crtc_hdisplay;
  661. height = mode->crtc_vdisplay;
  662. /* do some mode translations */
  663. h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
  664. h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
  665. v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
  666. v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
  667. h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
  668. v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
  669. dtd->part1.clock = mode->clock / 10;
  670. dtd->part1.h_active = width & 0xff;
  671. dtd->part1.h_blank = h_blank_len & 0xff;
  672. dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
  673. ((h_blank_len >> 8) & 0xf);
  674. dtd->part1.v_active = height & 0xff;
  675. dtd->part1.v_blank = v_blank_len & 0xff;
  676. dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
  677. ((v_blank_len >> 8) & 0xf);
  678. dtd->part2.h_sync_off = h_sync_offset & 0xff;
  679. dtd->part2.h_sync_width = h_sync_len & 0xff;
  680. dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
  681. (v_sync_len & 0xf);
  682. dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
  683. ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
  684. ((v_sync_len & 0x30) >> 4);
  685. dtd->part2.dtd_flags = 0x18;
  686. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  687. dtd->part2.dtd_flags |= 0x2;
  688. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  689. dtd->part2.dtd_flags |= 0x4;
  690. dtd->part2.sdvo_flags = 0;
  691. dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
  692. dtd->part2.reserved = 0;
  693. }
  694. static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
  695. struct intel_sdvo_dtd *dtd)
  696. {
  697. mode->hdisplay = dtd->part1.h_active;
  698. mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
  699. mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
  700. mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
  701. mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
  702. mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
  703. mode->htotal = mode->hdisplay + dtd->part1.h_blank;
  704. mode->htotal += (dtd->part1.h_high & 0xf) << 8;
  705. mode->vdisplay = dtd->part1.v_active;
  706. mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
  707. mode->vsync_start = mode->vdisplay;
  708. mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
  709. mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
  710. mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
  711. mode->vsync_end = mode->vsync_start +
  712. (dtd->part2.v_sync_off_width & 0xf);
  713. mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
  714. mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
  715. mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
  716. mode->clock = dtd->part1.clock * 10;
  717. mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  718. if (dtd->part2.dtd_flags & 0x2)
  719. mode->flags |= DRM_MODE_FLAG_PHSYNC;
  720. if (dtd->part2.dtd_flags & 0x4)
  721. mode->flags |= DRM_MODE_FLAG_PVSYNC;
  722. }
  723. static bool intel_sdvo_get_supp_encode(struct intel_encoder *intel_encoder,
  724. struct intel_sdvo_encode *encode)
  725. {
  726. uint8_t status;
  727. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
  728. status = intel_sdvo_read_response(intel_encoder, encode, sizeof(*encode));
  729. if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
  730. memset(encode, 0, sizeof(*encode));
  731. return false;
  732. }
  733. return true;
  734. }
  735. static bool intel_sdvo_set_encode(struct intel_encoder *intel_encoder,
  736. uint8_t mode)
  737. {
  738. uint8_t status;
  739. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODE, &mode, 1);
  740. status = intel_sdvo_read_response(intel_encoder, NULL, 0);
  741. return (status == SDVO_CMD_STATUS_SUCCESS);
  742. }
  743. static bool intel_sdvo_set_colorimetry(struct intel_encoder *intel_encoder,
  744. uint8_t mode)
  745. {
  746. uint8_t status;
  747. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
  748. status = intel_sdvo_read_response(intel_encoder, NULL, 0);
  749. return (status == SDVO_CMD_STATUS_SUCCESS);
  750. }
  751. #if 0
  752. static void intel_sdvo_dump_hdmi_buf(struct intel_encoder *intel_encoder)
  753. {
  754. int i, j;
  755. uint8_t set_buf_index[2];
  756. uint8_t av_split;
  757. uint8_t buf_size;
  758. uint8_t buf[48];
  759. uint8_t *pos;
  760. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
  761. intel_sdvo_read_response(encoder, &av_split, 1);
  762. for (i = 0; i <= av_split; i++) {
  763. set_buf_index[0] = i; set_buf_index[1] = 0;
  764. intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
  765. set_buf_index, 2);
  766. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
  767. intel_sdvo_read_response(encoder, &buf_size, 1);
  768. pos = buf;
  769. for (j = 0; j <= buf_size; j += 8) {
  770. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
  771. NULL, 0);
  772. intel_sdvo_read_response(encoder, pos, 8);
  773. pos += 8;
  774. }
  775. }
  776. }
  777. #endif
  778. static void intel_sdvo_set_hdmi_buf(struct intel_encoder *intel_encoder,
  779. int index,
  780. uint8_t *data, int8_t size, uint8_t tx_rate)
  781. {
  782. uint8_t set_buf_index[2];
  783. set_buf_index[0] = index;
  784. set_buf_index[1] = 0;
  785. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_INDEX,
  786. set_buf_index, 2);
  787. for (; size > 0; size -= 8) {
  788. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_DATA, data, 8);
  789. data += 8;
  790. }
  791. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
  792. }
  793. static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
  794. {
  795. uint8_t csum = 0;
  796. int i;
  797. for (i = 0; i < size; i++)
  798. csum += data[i];
  799. return 0x100 - csum;
  800. }
  801. #define DIP_TYPE_AVI 0x82
  802. #define DIP_VERSION_AVI 0x2
  803. #define DIP_LEN_AVI 13
  804. struct dip_infoframe {
  805. uint8_t type;
  806. uint8_t version;
  807. uint8_t len;
  808. uint8_t checksum;
  809. union {
  810. struct {
  811. /* Packet Byte #1 */
  812. uint8_t S:2;
  813. uint8_t B:2;
  814. uint8_t A:1;
  815. uint8_t Y:2;
  816. uint8_t rsvd1:1;
  817. /* Packet Byte #2 */
  818. uint8_t R:4;
  819. uint8_t M:2;
  820. uint8_t C:2;
  821. /* Packet Byte #3 */
  822. uint8_t SC:2;
  823. uint8_t Q:2;
  824. uint8_t EC:3;
  825. uint8_t ITC:1;
  826. /* Packet Byte #4 */
  827. uint8_t VIC:7;
  828. uint8_t rsvd2:1;
  829. /* Packet Byte #5 */
  830. uint8_t PR:4;
  831. uint8_t rsvd3:4;
  832. /* Packet Byte #6~13 */
  833. uint16_t top_bar_end;
  834. uint16_t bottom_bar_start;
  835. uint16_t left_bar_end;
  836. uint16_t right_bar_start;
  837. } avi;
  838. struct {
  839. /* Packet Byte #1 */
  840. uint8_t channel_count:3;
  841. uint8_t rsvd1:1;
  842. uint8_t coding_type:4;
  843. /* Packet Byte #2 */
  844. uint8_t sample_size:2; /* SS0, SS1 */
  845. uint8_t sample_frequency:3;
  846. uint8_t rsvd2:3;
  847. /* Packet Byte #3 */
  848. uint8_t coding_type_private:5;
  849. uint8_t rsvd3:3;
  850. /* Packet Byte #4 */
  851. uint8_t channel_allocation;
  852. /* Packet Byte #5 */
  853. uint8_t rsvd4:3;
  854. uint8_t level_shift:4;
  855. uint8_t downmix_inhibit:1;
  856. } audio;
  857. uint8_t payload[28];
  858. } __attribute__ ((packed)) u;
  859. } __attribute__((packed));
  860. static void intel_sdvo_set_avi_infoframe(struct intel_encoder *intel_encoder,
  861. struct drm_display_mode * mode)
  862. {
  863. struct dip_infoframe avi_if = {
  864. .type = DIP_TYPE_AVI,
  865. .version = DIP_VERSION_AVI,
  866. .len = DIP_LEN_AVI,
  867. };
  868. avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
  869. 4 + avi_if.len);
  870. intel_sdvo_set_hdmi_buf(intel_encoder, 1, (uint8_t *)&avi_if,
  871. 4 + avi_if.len,
  872. SDVO_HBUF_TX_VSYNC);
  873. }
  874. static void intel_sdvo_set_tv_format(struct intel_encoder *intel_encoder)
  875. {
  876. struct intel_sdvo_tv_format format;
  877. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  878. uint32_t format_map, i;
  879. uint8_t status;
  880. for (i = 0; i < TV_FORMAT_NUM; i++)
  881. if (tv_format_names[i] == sdvo_priv->tv_format_name)
  882. break;
  883. format_map = 1 << i;
  884. memset(&format, 0, sizeof(format));
  885. memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ?
  886. sizeof(format) : sizeof(format_map));
  887. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TV_FORMAT, &format,
  888. sizeof(format));
  889. status = intel_sdvo_read_response(intel_encoder, NULL, 0);
  890. if (status != SDVO_CMD_STATUS_SUCCESS)
  891. DRM_DEBUG_KMS("%s: Failed to set TV format\n",
  892. SDVO_NAME(sdvo_priv));
  893. }
  894. static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
  895. struct drm_display_mode *mode,
  896. struct drm_display_mode *adjusted_mode)
  897. {
  898. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  899. struct intel_sdvo_priv *dev_priv = intel_encoder->dev_priv;
  900. if (dev_priv->is_tv) {
  901. struct intel_sdvo_dtd output_dtd;
  902. bool success;
  903. /* We need to construct preferred input timings based on our
  904. * output timings. To do that, we have to set the output
  905. * timings, even though this isn't really the right place in
  906. * the sequence to do it. Oh well.
  907. */
  908. /* Set output timings */
  909. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  910. intel_sdvo_set_target_output(intel_encoder,
  911. dev_priv->attached_output);
  912. intel_sdvo_set_output_timing(intel_encoder, &output_dtd);
  913. /* Set the input timing to the screen. Assume always input 0. */
  914. intel_sdvo_set_target_input(intel_encoder, true, false);
  915. success = intel_sdvo_create_preferred_input_timing(intel_encoder,
  916. mode->clock / 10,
  917. mode->hdisplay,
  918. mode->vdisplay);
  919. if (success) {
  920. struct intel_sdvo_dtd input_dtd;
  921. intel_sdvo_get_preferred_input_timing(intel_encoder,
  922. &input_dtd);
  923. intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
  924. dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
  925. drm_mode_set_crtcinfo(adjusted_mode, 0);
  926. mode->clock = adjusted_mode->clock;
  927. adjusted_mode->clock *=
  928. intel_sdvo_get_pixel_multiplier(mode);
  929. } else {
  930. return false;
  931. }
  932. } else if (dev_priv->is_lvds) {
  933. struct intel_sdvo_dtd output_dtd;
  934. bool success;
  935. drm_mode_set_crtcinfo(dev_priv->sdvo_lvds_fixed_mode, 0);
  936. /* Set output timings */
  937. intel_sdvo_get_dtd_from_mode(&output_dtd,
  938. dev_priv->sdvo_lvds_fixed_mode);
  939. intel_sdvo_set_target_output(intel_encoder,
  940. dev_priv->attached_output);
  941. intel_sdvo_set_output_timing(intel_encoder, &output_dtd);
  942. /* Set the input timing to the screen. Assume always input 0. */
  943. intel_sdvo_set_target_input(intel_encoder, true, false);
  944. success = intel_sdvo_create_preferred_input_timing(
  945. intel_encoder,
  946. mode->clock / 10,
  947. mode->hdisplay,
  948. mode->vdisplay);
  949. if (success) {
  950. struct intel_sdvo_dtd input_dtd;
  951. intel_sdvo_get_preferred_input_timing(intel_encoder,
  952. &input_dtd);
  953. intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
  954. dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
  955. drm_mode_set_crtcinfo(adjusted_mode, 0);
  956. mode->clock = adjusted_mode->clock;
  957. adjusted_mode->clock *=
  958. intel_sdvo_get_pixel_multiplier(mode);
  959. } else {
  960. return false;
  961. }
  962. } else {
  963. /* Make the CRTC code factor in the SDVO pixel multiplier. The
  964. * SDVO device will be told of the multiplier during mode_set.
  965. */
  966. adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
  967. }
  968. return true;
  969. }
  970. static void intel_sdvo_mode_set(struct drm_encoder *encoder,
  971. struct drm_display_mode *mode,
  972. struct drm_display_mode *adjusted_mode)
  973. {
  974. struct drm_device *dev = encoder->dev;
  975. struct drm_i915_private *dev_priv = dev->dev_private;
  976. struct drm_crtc *crtc = encoder->crtc;
  977. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  978. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  979. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  980. u32 sdvox = 0;
  981. int sdvo_pixel_multiply;
  982. struct intel_sdvo_in_out_map in_out;
  983. struct intel_sdvo_dtd input_dtd;
  984. u8 status;
  985. if (!mode)
  986. return;
  987. /* First, set the input mapping for the first input to our controlled
  988. * output. This is only correct if we're a single-input device, in
  989. * which case the first input is the output from the appropriate SDVO
  990. * channel on the motherboard. In a two-input device, the first input
  991. * will be SDVOB and the second SDVOC.
  992. */
  993. in_out.in0 = sdvo_priv->attached_output;
  994. in_out.in1 = 0;
  995. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_IN_OUT_MAP,
  996. &in_out, sizeof(in_out));
  997. status = intel_sdvo_read_response(intel_encoder, NULL, 0);
  998. if (sdvo_priv->is_hdmi) {
  999. intel_sdvo_set_avi_infoframe(intel_encoder, mode);
  1000. sdvox |= SDVO_AUDIO_ENABLE;
  1001. }
  1002. /* We have tried to get input timing in mode_fixup, and filled into
  1003. adjusted_mode */
  1004. if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
  1005. intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
  1006. input_dtd.part2.sdvo_flags = sdvo_priv->sdvo_flags;
  1007. } else
  1008. intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
  1009. /* If it's a TV, we already set the output timing in mode_fixup.
  1010. * Otherwise, the output timing is equal to the input timing.
  1011. */
  1012. if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) {
  1013. /* Set the output timing to the screen */
  1014. intel_sdvo_set_target_output(intel_encoder,
  1015. sdvo_priv->attached_output);
  1016. intel_sdvo_set_output_timing(intel_encoder, &input_dtd);
  1017. }
  1018. /* Set the input timing to the screen. Assume always input 0. */
  1019. intel_sdvo_set_target_input(intel_encoder, true, false);
  1020. if (sdvo_priv->is_tv)
  1021. intel_sdvo_set_tv_format(intel_encoder);
  1022. /* We would like to use intel_sdvo_create_preferred_input_timing() to
  1023. * provide the device with a timing it can support, if it supports that
  1024. * feature. However, presumably we would need to adjust the CRTC to
  1025. * output the preferred timing, and we don't support that currently.
  1026. */
  1027. #if 0
  1028. success = intel_sdvo_create_preferred_input_timing(encoder, clock,
  1029. width, height);
  1030. if (success) {
  1031. struct intel_sdvo_dtd *input_dtd;
  1032. intel_sdvo_get_preferred_input_timing(encoder, &input_dtd);
  1033. intel_sdvo_set_input_timing(encoder, &input_dtd);
  1034. }
  1035. #else
  1036. intel_sdvo_set_input_timing(intel_encoder, &input_dtd);
  1037. #endif
  1038. switch (intel_sdvo_get_pixel_multiplier(mode)) {
  1039. case 1:
  1040. intel_sdvo_set_clock_rate_mult(intel_encoder,
  1041. SDVO_CLOCK_RATE_MULT_1X);
  1042. break;
  1043. case 2:
  1044. intel_sdvo_set_clock_rate_mult(intel_encoder,
  1045. SDVO_CLOCK_RATE_MULT_2X);
  1046. break;
  1047. case 4:
  1048. intel_sdvo_set_clock_rate_mult(intel_encoder,
  1049. SDVO_CLOCK_RATE_MULT_4X);
  1050. break;
  1051. }
  1052. /* Set the SDVO control regs. */
  1053. if (IS_I965G(dev)) {
  1054. sdvox |= SDVO_BORDER_ENABLE;
  1055. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  1056. sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
  1057. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  1058. sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
  1059. } else {
  1060. sdvox |= I915_READ(sdvo_priv->sdvo_reg);
  1061. switch (sdvo_priv->sdvo_reg) {
  1062. case SDVOB:
  1063. sdvox &= SDVOB_PRESERVE_MASK;
  1064. break;
  1065. case SDVOC:
  1066. sdvox &= SDVOC_PRESERVE_MASK;
  1067. break;
  1068. }
  1069. sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
  1070. }
  1071. if (intel_crtc->pipe == 1)
  1072. sdvox |= SDVO_PIPE_B_SELECT;
  1073. sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
  1074. if (IS_I965G(dev)) {
  1075. /* done in crtc_mode_set as the dpll_md reg must be written early */
  1076. } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  1077. /* done in crtc_mode_set as it lives inside the dpll register */
  1078. } else {
  1079. sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
  1080. }
  1081. if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL)
  1082. sdvox |= SDVO_STALL_SELECT;
  1083. intel_sdvo_write_sdvox(intel_encoder, sdvox);
  1084. }
  1085. static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
  1086. {
  1087. struct drm_device *dev = encoder->dev;
  1088. struct drm_i915_private *dev_priv = dev->dev_private;
  1089. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  1090. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  1091. u32 temp;
  1092. if (mode != DRM_MODE_DPMS_ON) {
  1093. intel_sdvo_set_active_outputs(intel_encoder, 0);
  1094. if (0)
  1095. intel_sdvo_set_encoder_power_state(intel_encoder, mode);
  1096. if (mode == DRM_MODE_DPMS_OFF) {
  1097. temp = I915_READ(sdvo_priv->sdvo_reg);
  1098. if ((temp & SDVO_ENABLE) != 0) {
  1099. intel_sdvo_write_sdvox(intel_encoder, temp & ~SDVO_ENABLE);
  1100. }
  1101. }
  1102. } else {
  1103. bool input1, input2;
  1104. int i;
  1105. u8 status;
  1106. temp = I915_READ(sdvo_priv->sdvo_reg);
  1107. if ((temp & SDVO_ENABLE) == 0)
  1108. intel_sdvo_write_sdvox(intel_encoder, temp | SDVO_ENABLE);
  1109. for (i = 0; i < 2; i++)
  1110. intel_wait_for_vblank(dev);
  1111. status = intel_sdvo_get_trained_inputs(intel_encoder, &input1,
  1112. &input2);
  1113. /* Warn if the device reported failure to sync.
  1114. * A lot of SDVO devices fail to notify of sync, but it's
  1115. * a given it the status is a success, we succeeded.
  1116. */
  1117. if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
  1118. DRM_DEBUG_KMS("First %s output reported failure to "
  1119. "sync\n", SDVO_NAME(sdvo_priv));
  1120. }
  1121. if (0)
  1122. intel_sdvo_set_encoder_power_state(intel_encoder, mode);
  1123. intel_sdvo_set_active_outputs(intel_encoder, sdvo_priv->attached_output);
  1124. }
  1125. return;
  1126. }
  1127. static int intel_sdvo_mode_valid(struct drm_connector *connector,
  1128. struct drm_display_mode *mode)
  1129. {
  1130. struct drm_encoder *encoder = intel_attached_encoder(connector);
  1131. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  1132. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  1133. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  1134. return MODE_NO_DBLESCAN;
  1135. if (sdvo_priv->pixel_clock_min > mode->clock)
  1136. return MODE_CLOCK_LOW;
  1137. if (sdvo_priv->pixel_clock_max < mode->clock)
  1138. return MODE_CLOCK_HIGH;
  1139. if (sdvo_priv->is_lvds == true) {
  1140. if (sdvo_priv->sdvo_lvds_fixed_mode == NULL)
  1141. return MODE_PANEL;
  1142. if (mode->hdisplay > sdvo_priv->sdvo_lvds_fixed_mode->hdisplay)
  1143. return MODE_PANEL;
  1144. if (mode->vdisplay > sdvo_priv->sdvo_lvds_fixed_mode->vdisplay)
  1145. return MODE_PANEL;
  1146. }
  1147. return MODE_OK;
  1148. }
  1149. static bool intel_sdvo_get_capabilities(struct intel_encoder *intel_encoder, struct intel_sdvo_caps *caps)
  1150. {
  1151. u8 status;
  1152. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
  1153. status = intel_sdvo_read_response(intel_encoder, caps, sizeof(*caps));
  1154. if (status != SDVO_CMD_STATUS_SUCCESS)
  1155. return false;
  1156. return true;
  1157. }
  1158. /* No use! */
  1159. #if 0
  1160. struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
  1161. {
  1162. struct drm_connector *connector = NULL;
  1163. struct intel_encoder *iout = NULL;
  1164. struct intel_sdvo_priv *sdvo;
  1165. /* find the sdvo connector */
  1166. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  1167. iout = to_intel_encoder(connector);
  1168. if (iout->type != INTEL_OUTPUT_SDVO)
  1169. continue;
  1170. sdvo = iout->dev_priv;
  1171. if (sdvo->sdvo_reg == SDVOB && sdvoB)
  1172. return connector;
  1173. if (sdvo->sdvo_reg == SDVOC && !sdvoB)
  1174. return connector;
  1175. }
  1176. return NULL;
  1177. }
  1178. int intel_sdvo_supports_hotplug(struct drm_connector *connector)
  1179. {
  1180. u8 response[2];
  1181. u8 status;
  1182. struct intel_encoder *intel_encoder;
  1183. DRM_DEBUG_KMS("\n");
  1184. if (!connector)
  1185. return 0;
  1186. intel_encoder = to_intel_encoder(connector);
  1187. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
  1188. status = intel_sdvo_read_response(intel_encoder, &response, 2);
  1189. if (response[0] !=0)
  1190. return 1;
  1191. return 0;
  1192. }
  1193. void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
  1194. {
  1195. u8 response[2];
  1196. u8 status;
  1197. struct intel_encoder *intel_encoder = to_intel_encoder(connector);
  1198. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
  1199. intel_sdvo_read_response(intel_encoder, &response, 2);
  1200. if (on) {
  1201. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
  1202. status = intel_sdvo_read_response(intel_encoder, &response, 2);
  1203. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
  1204. } else {
  1205. response[0] = 0;
  1206. response[1] = 0;
  1207. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
  1208. }
  1209. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
  1210. intel_sdvo_read_response(intel_encoder, &response, 2);
  1211. }
  1212. #endif
  1213. static bool
  1214. intel_sdvo_multifunc_encoder(struct intel_encoder *intel_encoder)
  1215. {
  1216. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  1217. int caps = 0;
  1218. if (sdvo_priv->caps.output_flags &
  1219. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
  1220. caps++;
  1221. if (sdvo_priv->caps.output_flags &
  1222. (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
  1223. caps++;
  1224. if (sdvo_priv->caps.output_flags &
  1225. (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
  1226. caps++;
  1227. if (sdvo_priv->caps.output_flags &
  1228. (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
  1229. caps++;
  1230. if (sdvo_priv->caps.output_flags &
  1231. (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
  1232. caps++;
  1233. if (sdvo_priv->caps.output_flags &
  1234. (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
  1235. caps++;
  1236. if (sdvo_priv->caps.output_flags &
  1237. (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
  1238. caps++;
  1239. return (caps > 1);
  1240. }
  1241. static struct drm_connector *
  1242. intel_find_analog_connector(struct drm_device *dev)
  1243. {
  1244. struct drm_connector *connector;
  1245. struct drm_encoder *encoder;
  1246. struct intel_encoder *intel_encoder;
  1247. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1248. intel_encoder = enc_to_intel_encoder(encoder);
  1249. if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
  1250. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  1251. if (encoder == intel_attached_encoder(connector))
  1252. return connector;
  1253. }
  1254. }
  1255. }
  1256. return NULL;
  1257. }
  1258. static int
  1259. intel_analog_is_connected(struct drm_device *dev)
  1260. {
  1261. struct drm_connector *analog_connector;
  1262. analog_connector = intel_find_analog_connector(dev);
  1263. if (!analog_connector)
  1264. return false;
  1265. if (analog_connector->funcs->detect(analog_connector) ==
  1266. connector_status_disconnected)
  1267. return false;
  1268. return true;
  1269. }
  1270. enum drm_connector_status
  1271. intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
  1272. {
  1273. struct drm_encoder *encoder = intel_attached_encoder(connector);
  1274. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  1275. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  1276. struct intel_connector *intel_connector = to_intel_connector(connector);
  1277. struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
  1278. enum drm_connector_status status = connector_status_connected;
  1279. struct edid *edid = NULL;
  1280. edid = drm_get_edid(connector, intel_encoder->ddc_bus);
  1281. /* This is only applied to SDVO cards with multiple outputs */
  1282. if (edid == NULL && intel_sdvo_multifunc_encoder(intel_encoder)) {
  1283. uint8_t saved_ddc, temp_ddc;
  1284. saved_ddc = sdvo_priv->ddc_bus;
  1285. temp_ddc = sdvo_priv->ddc_bus >> 1;
  1286. /*
  1287. * Don't use the 1 as the argument of DDC bus switch to get
  1288. * the EDID. It is used for SDVO SPD ROM.
  1289. */
  1290. while(temp_ddc > 1) {
  1291. sdvo_priv->ddc_bus = temp_ddc;
  1292. edid = drm_get_edid(connector, intel_encoder->ddc_bus);
  1293. if (edid) {
  1294. /*
  1295. * When we can get the EDID, maybe it is the
  1296. * correct DDC bus. Update it.
  1297. */
  1298. sdvo_priv->ddc_bus = temp_ddc;
  1299. break;
  1300. }
  1301. temp_ddc >>= 1;
  1302. }
  1303. if (edid == NULL)
  1304. sdvo_priv->ddc_bus = saved_ddc;
  1305. }
  1306. /* when there is no edid and no monitor is connected with VGA
  1307. * port, try to use the CRT ddc to read the EDID for DVI-connector
  1308. */
  1309. if (edid == NULL && sdvo_priv->analog_ddc_bus &&
  1310. !intel_analog_is_connected(connector->dev))
  1311. edid = drm_get_edid(connector, sdvo_priv->analog_ddc_bus);
  1312. if (edid != NULL) {
  1313. bool is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
  1314. bool need_digital = !!(sdvo_connector->output_flag & SDVO_TMDS_MASK);
  1315. /* DDC bus is shared, match EDID to connector type */
  1316. if (is_digital && need_digital)
  1317. sdvo_priv->is_hdmi = drm_detect_hdmi_monitor(edid);
  1318. else if (is_digital != need_digital)
  1319. status = connector_status_disconnected;
  1320. connector->display_info.raw_edid = NULL;
  1321. } else
  1322. status = connector_status_disconnected;
  1323. kfree(edid);
  1324. return status;
  1325. }
  1326. static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
  1327. {
  1328. uint16_t response;
  1329. u8 status;
  1330. struct drm_encoder *encoder = intel_attached_encoder(connector);
  1331. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  1332. struct intel_connector *intel_connector = to_intel_connector(connector);
  1333. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  1334. struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
  1335. enum drm_connector_status ret;
  1336. intel_sdvo_write_cmd(intel_encoder,
  1337. SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
  1338. if (sdvo_priv->is_tv) {
  1339. /* add 30ms delay when the output type is SDVO-TV */
  1340. mdelay(30);
  1341. }
  1342. status = intel_sdvo_read_response(intel_encoder, &response, 2);
  1343. DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
  1344. if (status != SDVO_CMD_STATUS_SUCCESS)
  1345. return connector_status_unknown;
  1346. if (response == 0)
  1347. return connector_status_disconnected;
  1348. sdvo_priv->attached_output = response;
  1349. if ((sdvo_connector->output_flag & response) == 0)
  1350. ret = connector_status_disconnected;
  1351. else if (response & SDVO_TMDS_MASK)
  1352. ret = intel_sdvo_hdmi_sink_detect(connector);
  1353. else
  1354. ret = connector_status_connected;
  1355. /* May update encoder flag for like clock for SDVO TV, etc.*/
  1356. if (ret == connector_status_connected) {
  1357. sdvo_priv->is_tv = false;
  1358. sdvo_priv->is_lvds = false;
  1359. intel_encoder->needs_tv_clock = false;
  1360. if (response & SDVO_TV_MASK) {
  1361. sdvo_priv->is_tv = true;
  1362. intel_encoder->needs_tv_clock = true;
  1363. }
  1364. if (response & SDVO_LVDS_MASK)
  1365. sdvo_priv->is_lvds = true;
  1366. }
  1367. return ret;
  1368. }
  1369. static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
  1370. {
  1371. struct drm_encoder *encoder = intel_attached_encoder(connector);
  1372. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  1373. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  1374. int num_modes;
  1375. /* set the bus switch and get the modes */
  1376. num_modes = intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
  1377. /*
  1378. * Mac mini hack. On this device, the DVI-I connector shares one DDC
  1379. * link between analog and digital outputs. So, if the regular SDVO
  1380. * DDC fails, check to see if the analog output is disconnected, in
  1381. * which case we'll look there for the digital DDC data.
  1382. */
  1383. if (num_modes == 0 &&
  1384. sdvo_priv->analog_ddc_bus &&
  1385. !intel_analog_is_connected(connector->dev)) {
  1386. /* Switch to the analog ddc bus and try that
  1387. */
  1388. (void) intel_ddc_get_modes(connector, sdvo_priv->analog_ddc_bus);
  1389. }
  1390. }
  1391. /*
  1392. * Set of SDVO TV modes.
  1393. * Note! This is in reply order (see loop in get_tv_modes).
  1394. * XXX: all 60Hz refresh?
  1395. */
  1396. struct drm_display_mode sdvo_tv_modes[] = {
  1397. { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
  1398. 416, 0, 200, 201, 232, 233, 0,
  1399. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1400. { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
  1401. 416, 0, 240, 241, 272, 273, 0,
  1402. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1403. { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
  1404. 496, 0, 300, 301, 332, 333, 0,
  1405. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1406. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
  1407. 736, 0, 350, 351, 382, 383, 0,
  1408. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1409. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
  1410. 736, 0, 400, 401, 432, 433, 0,
  1411. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1412. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
  1413. 736, 0, 480, 481, 512, 513, 0,
  1414. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1415. { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
  1416. 800, 0, 480, 481, 512, 513, 0,
  1417. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1418. { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
  1419. 800, 0, 576, 577, 608, 609, 0,
  1420. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1421. { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
  1422. 816, 0, 350, 351, 382, 383, 0,
  1423. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1424. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
  1425. 816, 0, 400, 401, 432, 433, 0,
  1426. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1427. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
  1428. 816, 0, 480, 481, 512, 513, 0,
  1429. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1430. { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
  1431. 816, 0, 540, 541, 572, 573, 0,
  1432. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1433. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
  1434. 816, 0, 576, 577, 608, 609, 0,
  1435. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1436. { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
  1437. 864, 0, 576, 577, 608, 609, 0,
  1438. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1439. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
  1440. 896, 0, 600, 601, 632, 633, 0,
  1441. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1442. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
  1443. 928, 0, 624, 625, 656, 657, 0,
  1444. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1445. { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
  1446. 1016, 0, 766, 767, 798, 799, 0,
  1447. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1448. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
  1449. 1120, 0, 768, 769, 800, 801, 0,
  1450. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1451. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
  1452. 1376, 0, 1024, 1025, 1056, 1057, 0,
  1453. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1454. };
  1455. static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
  1456. {
  1457. struct drm_encoder *encoder = intel_attached_encoder(connector);
  1458. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  1459. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  1460. struct intel_sdvo_sdtv_resolution_request tv_res;
  1461. uint32_t reply = 0, format_map = 0;
  1462. int i;
  1463. uint8_t status;
  1464. /* Read the list of supported input resolutions for the selected TV
  1465. * format.
  1466. */
  1467. for (i = 0; i < TV_FORMAT_NUM; i++)
  1468. if (tv_format_names[i] == sdvo_priv->tv_format_name)
  1469. break;
  1470. format_map = (1 << i);
  1471. memcpy(&tv_res, &format_map,
  1472. sizeof(struct intel_sdvo_sdtv_resolution_request) >
  1473. sizeof(format_map) ? sizeof(format_map) :
  1474. sizeof(struct intel_sdvo_sdtv_resolution_request));
  1475. intel_sdvo_set_target_output(intel_encoder, sdvo_priv->attached_output);
  1476. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
  1477. &tv_res, sizeof(tv_res));
  1478. status = intel_sdvo_read_response(intel_encoder, &reply, 3);
  1479. if (status != SDVO_CMD_STATUS_SUCCESS)
  1480. return;
  1481. for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
  1482. if (reply & (1 << i)) {
  1483. struct drm_display_mode *nmode;
  1484. nmode = drm_mode_duplicate(connector->dev,
  1485. &sdvo_tv_modes[i]);
  1486. if (nmode)
  1487. drm_mode_probed_add(connector, nmode);
  1488. }
  1489. }
  1490. static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
  1491. {
  1492. struct drm_encoder *encoder = intel_attached_encoder(connector);
  1493. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  1494. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1495. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  1496. struct drm_display_mode *newmode;
  1497. /*
  1498. * Attempt to get the mode list from DDC.
  1499. * Assume that the preferred modes are
  1500. * arranged in priority order.
  1501. */
  1502. intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
  1503. if (list_empty(&connector->probed_modes) == false)
  1504. goto end;
  1505. /* Fetch modes from VBT */
  1506. if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
  1507. newmode = drm_mode_duplicate(connector->dev,
  1508. dev_priv->sdvo_lvds_vbt_mode);
  1509. if (newmode != NULL) {
  1510. /* Guarantee the mode is preferred */
  1511. newmode->type = (DRM_MODE_TYPE_PREFERRED |
  1512. DRM_MODE_TYPE_DRIVER);
  1513. drm_mode_probed_add(connector, newmode);
  1514. }
  1515. }
  1516. end:
  1517. list_for_each_entry(newmode, &connector->probed_modes, head) {
  1518. if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
  1519. sdvo_priv->sdvo_lvds_fixed_mode =
  1520. drm_mode_duplicate(connector->dev, newmode);
  1521. break;
  1522. }
  1523. }
  1524. }
  1525. static int intel_sdvo_get_modes(struct drm_connector *connector)
  1526. {
  1527. struct intel_connector *intel_connector = to_intel_connector(connector);
  1528. struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
  1529. if (IS_TV(sdvo_connector))
  1530. intel_sdvo_get_tv_modes(connector);
  1531. else if (IS_LVDS(sdvo_connector))
  1532. intel_sdvo_get_lvds_modes(connector);
  1533. else
  1534. intel_sdvo_get_ddc_modes(connector);
  1535. if (list_empty(&connector->probed_modes))
  1536. return 0;
  1537. return 1;
  1538. }
  1539. static
  1540. void intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
  1541. {
  1542. struct intel_connector *intel_connector = to_intel_connector(connector);
  1543. struct intel_sdvo_connector *sdvo_priv = intel_connector->dev_priv;
  1544. struct drm_device *dev = connector->dev;
  1545. if (IS_TV(sdvo_priv)) {
  1546. if (sdvo_priv->left_property)
  1547. drm_property_destroy(dev, sdvo_priv->left_property);
  1548. if (sdvo_priv->right_property)
  1549. drm_property_destroy(dev, sdvo_priv->right_property);
  1550. if (sdvo_priv->top_property)
  1551. drm_property_destroy(dev, sdvo_priv->top_property);
  1552. if (sdvo_priv->bottom_property)
  1553. drm_property_destroy(dev, sdvo_priv->bottom_property);
  1554. if (sdvo_priv->hpos_property)
  1555. drm_property_destroy(dev, sdvo_priv->hpos_property);
  1556. if (sdvo_priv->vpos_property)
  1557. drm_property_destroy(dev, sdvo_priv->vpos_property);
  1558. if (sdvo_priv->saturation_property)
  1559. drm_property_destroy(dev,
  1560. sdvo_priv->saturation_property);
  1561. if (sdvo_priv->contrast_property)
  1562. drm_property_destroy(dev,
  1563. sdvo_priv->contrast_property);
  1564. if (sdvo_priv->hue_property)
  1565. drm_property_destroy(dev, sdvo_priv->hue_property);
  1566. }
  1567. if (IS_TV(sdvo_priv) || IS_LVDS(sdvo_priv)) {
  1568. if (sdvo_priv->brightness_property)
  1569. drm_property_destroy(dev,
  1570. sdvo_priv->brightness_property);
  1571. }
  1572. return;
  1573. }
  1574. static void intel_sdvo_destroy(struct drm_connector *connector)
  1575. {
  1576. struct intel_connector *intel_connector = to_intel_connector(connector);
  1577. struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
  1578. if (sdvo_connector->tv_format_property)
  1579. drm_property_destroy(connector->dev,
  1580. sdvo_connector->tv_format_property);
  1581. intel_sdvo_destroy_enhance_property(connector);
  1582. drm_sysfs_connector_remove(connector);
  1583. drm_connector_cleanup(connector);
  1584. kfree(connector);
  1585. }
  1586. static int
  1587. intel_sdvo_set_property(struct drm_connector *connector,
  1588. struct drm_property *property,
  1589. uint64_t val)
  1590. {
  1591. struct drm_encoder *encoder = intel_attached_encoder(connector);
  1592. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  1593. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  1594. struct intel_connector *intel_connector = to_intel_connector(connector);
  1595. struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
  1596. struct drm_crtc *crtc = encoder->crtc;
  1597. int ret = 0;
  1598. bool changed = false;
  1599. uint8_t cmd, status;
  1600. uint16_t temp_value;
  1601. ret = drm_connector_property_set_value(connector, property, val);
  1602. if (ret < 0)
  1603. goto out;
  1604. if (property == sdvo_connector->tv_format_property) {
  1605. if (val >= TV_FORMAT_NUM) {
  1606. ret = -EINVAL;
  1607. goto out;
  1608. }
  1609. if (sdvo_priv->tv_format_name ==
  1610. sdvo_connector->tv_format_supported[val])
  1611. goto out;
  1612. sdvo_priv->tv_format_name = sdvo_connector->tv_format_supported[val];
  1613. changed = true;
  1614. }
  1615. if (IS_TV(sdvo_connector) || IS_LVDS(sdvo_connector)) {
  1616. cmd = 0;
  1617. temp_value = val;
  1618. if (sdvo_connector->left_property == property) {
  1619. drm_connector_property_set_value(connector,
  1620. sdvo_connector->right_property, val);
  1621. if (sdvo_connector->left_margin == temp_value)
  1622. goto out;
  1623. sdvo_connector->left_margin = temp_value;
  1624. sdvo_connector->right_margin = temp_value;
  1625. temp_value = sdvo_connector->max_hscan -
  1626. sdvo_connector->left_margin;
  1627. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1628. } else if (sdvo_connector->right_property == property) {
  1629. drm_connector_property_set_value(connector,
  1630. sdvo_connector->left_property, val);
  1631. if (sdvo_connector->right_margin == temp_value)
  1632. goto out;
  1633. sdvo_connector->left_margin = temp_value;
  1634. sdvo_connector->right_margin = temp_value;
  1635. temp_value = sdvo_connector->max_hscan -
  1636. sdvo_connector->left_margin;
  1637. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1638. } else if (sdvo_connector->top_property == property) {
  1639. drm_connector_property_set_value(connector,
  1640. sdvo_connector->bottom_property, val);
  1641. if (sdvo_connector->top_margin == temp_value)
  1642. goto out;
  1643. sdvo_connector->top_margin = temp_value;
  1644. sdvo_connector->bottom_margin = temp_value;
  1645. temp_value = sdvo_connector->max_vscan -
  1646. sdvo_connector->top_margin;
  1647. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1648. } else if (sdvo_connector->bottom_property == property) {
  1649. drm_connector_property_set_value(connector,
  1650. sdvo_connector->top_property, val);
  1651. if (sdvo_connector->bottom_margin == temp_value)
  1652. goto out;
  1653. sdvo_connector->top_margin = temp_value;
  1654. sdvo_connector->bottom_margin = temp_value;
  1655. temp_value = sdvo_connector->max_vscan -
  1656. sdvo_connector->top_margin;
  1657. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1658. } else if (sdvo_connector->hpos_property == property) {
  1659. if (sdvo_connector->cur_hpos == temp_value)
  1660. goto out;
  1661. cmd = SDVO_CMD_SET_POSITION_H;
  1662. sdvo_connector->cur_hpos = temp_value;
  1663. } else if (sdvo_connector->vpos_property == property) {
  1664. if (sdvo_connector->cur_vpos == temp_value)
  1665. goto out;
  1666. cmd = SDVO_CMD_SET_POSITION_V;
  1667. sdvo_connector->cur_vpos = temp_value;
  1668. } else if (sdvo_connector->saturation_property == property) {
  1669. if (sdvo_connector->cur_saturation == temp_value)
  1670. goto out;
  1671. cmd = SDVO_CMD_SET_SATURATION;
  1672. sdvo_connector->cur_saturation = temp_value;
  1673. } else if (sdvo_connector->contrast_property == property) {
  1674. if (sdvo_connector->cur_contrast == temp_value)
  1675. goto out;
  1676. cmd = SDVO_CMD_SET_CONTRAST;
  1677. sdvo_connector->cur_contrast = temp_value;
  1678. } else if (sdvo_connector->hue_property == property) {
  1679. if (sdvo_connector->cur_hue == temp_value)
  1680. goto out;
  1681. cmd = SDVO_CMD_SET_HUE;
  1682. sdvo_connector->cur_hue = temp_value;
  1683. } else if (sdvo_connector->brightness_property == property) {
  1684. if (sdvo_connector->cur_brightness == temp_value)
  1685. goto out;
  1686. cmd = SDVO_CMD_SET_BRIGHTNESS;
  1687. sdvo_connector->cur_brightness = temp_value;
  1688. }
  1689. if (cmd) {
  1690. intel_sdvo_write_cmd(intel_encoder, cmd, &temp_value, 2);
  1691. status = intel_sdvo_read_response(intel_encoder,
  1692. NULL, 0);
  1693. if (status != SDVO_CMD_STATUS_SUCCESS) {
  1694. DRM_DEBUG_KMS("Incorrect SDVO command \n");
  1695. return -EINVAL;
  1696. }
  1697. changed = true;
  1698. }
  1699. }
  1700. if (changed && crtc)
  1701. drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
  1702. crtc->y, crtc->fb);
  1703. out:
  1704. return ret;
  1705. }
  1706. static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
  1707. .dpms = intel_sdvo_dpms,
  1708. .mode_fixup = intel_sdvo_mode_fixup,
  1709. .prepare = intel_encoder_prepare,
  1710. .mode_set = intel_sdvo_mode_set,
  1711. .commit = intel_encoder_commit,
  1712. };
  1713. static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
  1714. .dpms = drm_helper_connector_dpms,
  1715. .detect = intel_sdvo_detect,
  1716. .fill_modes = drm_helper_probe_single_connector_modes,
  1717. .set_property = intel_sdvo_set_property,
  1718. .destroy = intel_sdvo_destroy,
  1719. };
  1720. static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
  1721. .get_modes = intel_sdvo_get_modes,
  1722. .mode_valid = intel_sdvo_mode_valid,
  1723. .best_encoder = intel_attached_encoder,
  1724. };
  1725. static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
  1726. {
  1727. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  1728. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  1729. if (intel_encoder->i2c_bus)
  1730. intel_i2c_destroy(intel_encoder->i2c_bus);
  1731. if (intel_encoder->ddc_bus)
  1732. intel_i2c_destroy(intel_encoder->ddc_bus);
  1733. if (sdvo_priv->analog_ddc_bus)
  1734. intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
  1735. if (sdvo_priv->sdvo_lvds_fixed_mode != NULL)
  1736. drm_mode_destroy(encoder->dev,
  1737. sdvo_priv->sdvo_lvds_fixed_mode);
  1738. drm_encoder_cleanup(encoder);
  1739. kfree(intel_encoder);
  1740. }
  1741. static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
  1742. .destroy = intel_sdvo_enc_destroy,
  1743. };
  1744. /**
  1745. * Choose the appropriate DDC bus for control bus switch command for this
  1746. * SDVO output based on the controlled output.
  1747. *
  1748. * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
  1749. * outputs, then LVDS outputs.
  1750. */
  1751. static void
  1752. intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
  1753. struct intel_sdvo_priv *sdvo, u32 reg)
  1754. {
  1755. struct sdvo_device_mapping *mapping;
  1756. if (IS_SDVOB(reg))
  1757. mapping = &(dev_priv->sdvo_mappings[0]);
  1758. else
  1759. mapping = &(dev_priv->sdvo_mappings[1]);
  1760. sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
  1761. }
  1762. static bool
  1763. intel_sdvo_get_digital_encoding_mode(struct intel_encoder *output, int device)
  1764. {
  1765. struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
  1766. uint8_t status;
  1767. if (device == 0)
  1768. intel_sdvo_set_target_output(output, SDVO_OUTPUT_TMDS0);
  1769. else
  1770. intel_sdvo_set_target_output(output, SDVO_OUTPUT_TMDS1);
  1771. intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
  1772. status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
  1773. if (status != SDVO_CMD_STATUS_SUCCESS)
  1774. return false;
  1775. return true;
  1776. }
  1777. static struct intel_encoder *
  1778. intel_sdvo_chan_to_intel_encoder(struct intel_i2c_chan *chan)
  1779. {
  1780. struct drm_device *dev = chan->drm_dev;
  1781. struct drm_encoder *encoder;
  1782. struct intel_encoder *intel_encoder = NULL;
  1783. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1784. intel_encoder = enc_to_intel_encoder(encoder);
  1785. if (intel_encoder->ddc_bus == &chan->adapter)
  1786. break;
  1787. }
  1788. return intel_encoder;
  1789. }
  1790. static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
  1791. struct i2c_msg msgs[], int num)
  1792. {
  1793. struct intel_encoder *intel_encoder;
  1794. struct intel_sdvo_priv *sdvo_priv;
  1795. struct i2c_algo_bit_data *algo_data;
  1796. const struct i2c_algorithm *algo;
  1797. algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
  1798. intel_encoder =
  1799. intel_sdvo_chan_to_intel_encoder(
  1800. (struct intel_i2c_chan *)(algo_data->data));
  1801. if (intel_encoder == NULL)
  1802. return -EINVAL;
  1803. sdvo_priv = intel_encoder->dev_priv;
  1804. algo = intel_encoder->i2c_bus->algo;
  1805. intel_sdvo_set_control_bus_switch(intel_encoder, sdvo_priv->ddc_bus);
  1806. return algo->master_xfer(i2c_adap, msgs, num);
  1807. }
  1808. static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
  1809. .master_xfer = intel_sdvo_master_xfer,
  1810. };
  1811. static u8
  1812. intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
  1813. {
  1814. struct drm_i915_private *dev_priv = dev->dev_private;
  1815. struct sdvo_device_mapping *my_mapping, *other_mapping;
  1816. if (IS_SDVOB(sdvo_reg)) {
  1817. my_mapping = &dev_priv->sdvo_mappings[0];
  1818. other_mapping = &dev_priv->sdvo_mappings[1];
  1819. } else {
  1820. my_mapping = &dev_priv->sdvo_mappings[1];
  1821. other_mapping = &dev_priv->sdvo_mappings[0];
  1822. }
  1823. /* If the BIOS described our SDVO device, take advantage of it. */
  1824. if (my_mapping->slave_addr)
  1825. return my_mapping->slave_addr;
  1826. /* If the BIOS only described a different SDVO device, use the
  1827. * address that it isn't using.
  1828. */
  1829. if (other_mapping->slave_addr) {
  1830. if (other_mapping->slave_addr == 0x70)
  1831. return 0x72;
  1832. else
  1833. return 0x70;
  1834. }
  1835. /* No SDVO device info is found for another DVO port,
  1836. * so use mapping assumption we had before BIOS parsing.
  1837. */
  1838. if (IS_SDVOB(sdvo_reg))
  1839. return 0x70;
  1840. else
  1841. return 0x72;
  1842. }
  1843. static bool
  1844. intel_sdvo_connector_alloc (struct intel_connector **ret)
  1845. {
  1846. struct intel_connector *intel_connector;
  1847. struct intel_sdvo_connector *sdvo_connector;
  1848. *ret = kzalloc(sizeof(*intel_connector) +
  1849. sizeof(*sdvo_connector), GFP_KERNEL);
  1850. if (!*ret)
  1851. return false;
  1852. intel_connector = *ret;
  1853. sdvo_connector = (struct intel_sdvo_connector *)(intel_connector + 1);
  1854. intel_connector->dev_priv = sdvo_connector;
  1855. return true;
  1856. }
  1857. static void
  1858. intel_sdvo_connector_create (struct drm_encoder *encoder,
  1859. struct drm_connector *connector)
  1860. {
  1861. drm_connector_init(encoder->dev, connector, &intel_sdvo_connector_funcs,
  1862. connector->connector_type);
  1863. drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
  1864. connector->interlace_allowed = 0;
  1865. connector->doublescan_allowed = 0;
  1866. connector->display_info.subpixel_order = SubPixelHorizontalRGB;
  1867. drm_mode_connector_attach_encoder(connector, encoder);
  1868. drm_sysfs_connector_add(connector);
  1869. }
  1870. static bool
  1871. intel_sdvo_dvi_init(struct intel_encoder *intel_encoder, int device)
  1872. {
  1873. struct drm_encoder *encoder = &intel_encoder->enc;
  1874. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  1875. struct drm_connector *connector;
  1876. struct intel_connector *intel_connector;
  1877. struct intel_sdvo_connector *sdvo_connector;
  1878. if (!intel_sdvo_connector_alloc(&intel_connector))
  1879. return false;
  1880. sdvo_connector = intel_connector->dev_priv;
  1881. if (device == 0) {
  1882. sdvo_priv->controlled_output |= SDVO_OUTPUT_TMDS0;
  1883. sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
  1884. } else if (device == 1) {
  1885. sdvo_priv->controlled_output |= SDVO_OUTPUT_TMDS1;
  1886. sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
  1887. }
  1888. connector = &intel_connector->base;
  1889. connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
  1890. encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
  1891. connector->connector_type = DRM_MODE_CONNECTOR_DVID;
  1892. if (intel_sdvo_get_supp_encode(intel_encoder, &sdvo_priv->encode)
  1893. && intel_sdvo_get_digital_encoding_mode(intel_encoder, device)
  1894. && sdvo_priv->is_hdmi) {
  1895. /* enable hdmi encoding mode if supported */
  1896. intel_sdvo_set_encode(intel_encoder, SDVO_ENCODE_HDMI);
  1897. intel_sdvo_set_colorimetry(intel_encoder,
  1898. SDVO_COLORIMETRY_RGB256);
  1899. connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
  1900. }
  1901. intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1902. (1 << INTEL_ANALOG_CLONE_BIT);
  1903. intel_sdvo_connector_create(encoder, connector);
  1904. return true;
  1905. }
  1906. static bool
  1907. intel_sdvo_tv_init(struct intel_encoder *intel_encoder, int type)
  1908. {
  1909. struct drm_encoder *encoder = &intel_encoder->enc;
  1910. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  1911. struct drm_connector *connector;
  1912. struct intel_connector *intel_connector;
  1913. struct intel_sdvo_connector *sdvo_connector;
  1914. if (!intel_sdvo_connector_alloc(&intel_connector))
  1915. return false;
  1916. connector = &intel_connector->base;
  1917. encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
  1918. connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
  1919. sdvo_connector = intel_connector->dev_priv;
  1920. sdvo_priv->controlled_output |= type;
  1921. sdvo_connector->output_flag = type;
  1922. sdvo_priv->is_tv = true;
  1923. intel_encoder->needs_tv_clock = true;
  1924. intel_encoder->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
  1925. intel_sdvo_connector_create(encoder, connector);
  1926. intel_sdvo_tv_create_property(connector, type);
  1927. intel_sdvo_create_enhance_property(connector);
  1928. return true;
  1929. }
  1930. static bool
  1931. intel_sdvo_analog_init(struct intel_encoder *intel_encoder, int device)
  1932. {
  1933. struct drm_encoder *encoder = &intel_encoder->enc;
  1934. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  1935. struct drm_connector *connector;
  1936. struct intel_connector *intel_connector;
  1937. struct intel_sdvo_connector *sdvo_connector;
  1938. if (!intel_sdvo_connector_alloc(&intel_connector))
  1939. return false;
  1940. connector = &intel_connector->base;
  1941. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  1942. encoder->encoder_type = DRM_MODE_ENCODER_DAC;
  1943. connector->connector_type = DRM_MODE_CONNECTOR_VGA;
  1944. sdvo_connector = intel_connector->dev_priv;
  1945. if (device == 0) {
  1946. sdvo_priv->controlled_output |= SDVO_OUTPUT_RGB0;
  1947. sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
  1948. } else if (device == 1) {
  1949. sdvo_priv->controlled_output |= SDVO_OUTPUT_RGB1;
  1950. sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
  1951. }
  1952. intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1953. (1 << INTEL_ANALOG_CLONE_BIT);
  1954. intel_sdvo_connector_create(encoder, connector);
  1955. return true;
  1956. }
  1957. static bool
  1958. intel_sdvo_lvds_init(struct intel_encoder *intel_encoder, int device)
  1959. {
  1960. struct drm_encoder *encoder = &intel_encoder->enc;
  1961. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  1962. struct drm_connector *connector;
  1963. struct intel_connector *intel_connector;
  1964. struct intel_sdvo_connector *sdvo_connector;
  1965. if (!intel_sdvo_connector_alloc(&intel_connector))
  1966. return false;
  1967. connector = &intel_connector->base;
  1968. encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
  1969. connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
  1970. sdvo_connector = intel_connector->dev_priv;
  1971. sdvo_priv->is_lvds = true;
  1972. if (device == 0) {
  1973. sdvo_priv->controlled_output |= SDVO_OUTPUT_LVDS0;
  1974. sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
  1975. } else if (device == 1) {
  1976. sdvo_priv->controlled_output |= SDVO_OUTPUT_LVDS1;
  1977. sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
  1978. }
  1979. intel_encoder->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
  1980. (1 << INTEL_SDVO_LVDS_CLONE_BIT);
  1981. intel_sdvo_connector_create(encoder, connector);
  1982. intel_sdvo_create_enhance_property(connector);
  1983. return true;
  1984. }
  1985. static bool
  1986. intel_sdvo_output_setup(struct intel_encoder *intel_encoder, uint16_t flags)
  1987. {
  1988. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  1989. sdvo_priv->is_tv = false;
  1990. intel_encoder->needs_tv_clock = false;
  1991. sdvo_priv->is_lvds = false;
  1992. /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
  1993. if (flags & SDVO_OUTPUT_TMDS0)
  1994. if (!intel_sdvo_dvi_init(intel_encoder, 0))
  1995. return false;
  1996. if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
  1997. if (!intel_sdvo_dvi_init(intel_encoder, 1))
  1998. return false;
  1999. /* TV has no XXX1 function block */
  2000. if (flags & SDVO_OUTPUT_SVID0)
  2001. if (!intel_sdvo_tv_init(intel_encoder, SDVO_OUTPUT_SVID0))
  2002. return false;
  2003. if (flags & SDVO_OUTPUT_CVBS0)
  2004. if (!intel_sdvo_tv_init(intel_encoder, SDVO_OUTPUT_CVBS0))
  2005. return false;
  2006. if (flags & SDVO_OUTPUT_RGB0)
  2007. if (!intel_sdvo_analog_init(intel_encoder, 0))
  2008. return false;
  2009. if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
  2010. if (!intel_sdvo_analog_init(intel_encoder, 1))
  2011. return false;
  2012. if (flags & SDVO_OUTPUT_LVDS0)
  2013. if (!intel_sdvo_lvds_init(intel_encoder, 0))
  2014. return false;
  2015. if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
  2016. if (!intel_sdvo_lvds_init(intel_encoder, 1))
  2017. return false;
  2018. if ((flags & SDVO_OUTPUT_MASK) == 0) {
  2019. unsigned char bytes[2];
  2020. sdvo_priv->controlled_output = 0;
  2021. memcpy(bytes, &sdvo_priv->caps.output_flags, 2);
  2022. DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
  2023. SDVO_NAME(sdvo_priv),
  2024. bytes[0], bytes[1]);
  2025. return false;
  2026. }
  2027. intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
  2028. return true;
  2029. }
  2030. static void intel_sdvo_tv_create_property(struct drm_connector *connector, int type)
  2031. {
  2032. struct drm_encoder *encoder = intel_attached_encoder(connector);
  2033. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  2034. struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
  2035. struct intel_connector *intel_connector = to_intel_connector(connector);
  2036. struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
  2037. struct intel_sdvo_tv_format format;
  2038. uint32_t format_map, i;
  2039. uint8_t status;
  2040. intel_sdvo_set_target_output(intel_encoder, type);
  2041. intel_sdvo_write_cmd(intel_encoder,
  2042. SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0);
  2043. status = intel_sdvo_read_response(intel_encoder,
  2044. &format, sizeof(format));
  2045. if (status != SDVO_CMD_STATUS_SUCCESS)
  2046. return;
  2047. memcpy(&format_map, &format, sizeof(format) > sizeof(format_map) ?
  2048. sizeof(format_map) : sizeof(format));
  2049. if (format_map == 0)
  2050. return;
  2051. sdvo_connector->format_supported_num = 0;
  2052. for (i = 0 ; i < TV_FORMAT_NUM; i++)
  2053. if (format_map & (1 << i)) {
  2054. sdvo_connector->tv_format_supported
  2055. [sdvo_connector->format_supported_num++] =
  2056. tv_format_names[i];
  2057. }
  2058. sdvo_connector->tv_format_property =
  2059. drm_property_create(
  2060. connector->dev, DRM_MODE_PROP_ENUM,
  2061. "mode", sdvo_connector->format_supported_num);
  2062. for (i = 0; i < sdvo_connector->format_supported_num; i++)
  2063. drm_property_add_enum(
  2064. sdvo_connector->tv_format_property, i,
  2065. i, sdvo_connector->tv_format_supported[i]);
  2066. sdvo_priv->tv_format_name = sdvo_connector->tv_format_supported[0];
  2067. drm_connector_attach_property(
  2068. connector, sdvo_connector->tv_format_property, 0);
  2069. }
  2070. static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
  2071. {
  2072. struct drm_encoder *encoder = intel_attached_encoder(connector);
  2073. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  2074. struct intel_connector *intel_connector = to_intel_connector(connector);
  2075. struct intel_sdvo_connector *sdvo_priv = intel_connector->dev_priv;
  2076. struct intel_sdvo_enhancements_reply sdvo_data;
  2077. struct drm_device *dev = connector->dev;
  2078. uint8_t status;
  2079. uint16_t response, data_value[2];
  2080. intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
  2081. NULL, 0);
  2082. status = intel_sdvo_read_response(intel_encoder, &sdvo_data,
  2083. sizeof(sdvo_data));
  2084. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2085. DRM_DEBUG_KMS(" incorrect response is returned\n");
  2086. return;
  2087. }
  2088. response = *((uint16_t *)&sdvo_data);
  2089. if (!response) {
  2090. DRM_DEBUG_KMS("No enhancement is supported\n");
  2091. return;
  2092. }
  2093. if (IS_TV(sdvo_priv)) {
  2094. /* when horizontal overscan is supported, Add the left/right
  2095. * property
  2096. */
  2097. if (sdvo_data.overscan_h) {
  2098. intel_sdvo_write_cmd(intel_encoder,
  2099. SDVO_CMD_GET_MAX_OVERSCAN_H, NULL, 0);
  2100. status = intel_sdvo_read_response(intel_encoder,
  2101. &data_value, 4);
  2102. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2103. DRM_DEBUG_KMS("Incorrect SDVO max "
  2104. "h_overscan\n");
  2105. return;
  2106. }
  2107. intel_sdvo_write_cmd(intel_encoder,
  2108. SDVO_CMD_GET_OVERSCAN_H, NULL, 0);
  2109. status = intel_sdvo_read_response(intel_encoder,
  2110. &response, 2);
  2111. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2112. DRM_DEBUG_KMS("Incorrect SDVO h_overscan\n");
  2113. return;
  2114. }
  2115. sdvo_priv->max_hscan = data_value[0];
  2116. sdvo_priv->left_margin = data_value[0] - response;
  2117. sdvo_priv->right_margin = sdvo_priv->left_margin;
  2118. sdvo_priv->left_property =
  2119. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2120. "left_margin", 2);
  2121. sdvo_priv->left_property->values[0] = 0;
  2122. sdvo_priv->left_property->values[1] = data_value[0];
  2123. drm_connector_attach_property(connector,
  2124. sdvo_priv->left_property,
  2125. sdvo_priv->left_margin);
  2126. sdvo_priv->right_property =
  2127. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2128. "right_margin", 2);
  2129. sdvo_priv->right_property->values[0] = 0;
  2130. sdvo_priv->right_property->values[1] = data_value[0];
  2131. drm_connector_attach_property(connector,
  2132. sdvo_priv->right_property,
  2133. sdvo_priv->right_margin);
  2134. DRM_DEBUG_KMS("h_overscan: max %d, "
  2135. "default %d, current %d\n",
  2136. data_value[0], data_value[1], response);
  2137. }
  2138. if (sdvo_data.overscan_v) {
  2139. intel_sdvo_write_cmd(intel_encoder,
  2140. SDVO_CMD_GET_MAX_OVERSCAN_V, NULL, 0);
  2141. status = intel_sdvo_read_response(intel_encoder,
  2142. &data_value, 4);
  2143. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2144. DRM_DEBUG_KMS("Incorrect SDVO max "
  2145. "v_overscan\n");
  2146. return;
  2147. }
  2148. intel_sdvo_write_cmd(intel_encoder,
  2149. SDVO_CMD_GET_OVERSCAN_V, NULL, 0);
  2150. status = intel_sdvo_read_response(intel_encoder,
  2151. &response, 2);
  2152. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2153. DRM_DEBUG_KMS("Incorrect SDVO v_overscan\n");
  2154. return;
  2155. }
  2156. sdvo_priv->max_vscan = data_value[0];
  2157. sdvo_priv->top_margin = data_value[0] - response;
  2158. sdvo_priv->bottom_margin = sdvo_priv->top_margin;
  2159. sdvo_priv->top_property =
  2160. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2161. "top_margin", 2);
  2162. sdvo_priv->top_property->values[0] = 0;
  2163. sdvo_priv->top_property->values[1] = data_value[0];
  2164. drm_connector_attach_property(connector,
  2165. sdvo_priv->top_property,
  2166. sdvo_priv->top_margin);
  2167. sdvo_priv->bottom_property =
  2168. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2169. "bottom_margin", 2);
  2170. sdvo_priv->bottom_property->values[0] = 0;
  2171. sdvo_priv->bottom_property->values[1] = data_value[0];
  2172. drm_connector_attach_property(connector,
  2173. sdvo_priv->bottom_property,
  2174. sdvo_priv->bottom_margin);
  2175. DRM_DEBUG_KMS("v_overscan: max %d, "
  2176. "default %d, current %d\n",
  2177. data_value[0], data_value[1], response);
  2178. }
  2179. if (sdvo_data.position_h) {
  2180. intel_sdvo_write_cmd(intel_encoder,
  2181. SDVO_CMD_GET_MAX_POSITION_H, NULL, 0);
  2182. status = intel_sdvo_read_response(intel_encoder,
  2183. &data_value, 4);
  2184. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2185. DRM_DEBUG_KMS("Incorrect SDVO Max h_pos\n");
  2186. return;
  2187. }
  2188. intel_sdvo_write_cmd(intel_encoder,
  2189. SDVO_CMD_GET_POSITION_H, NULL, 0);
  2190. status = intel_sdvo_read_response(intel_encoder,
  2191. &response, 2);
  2192. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2193. DRM_DEBUG_KMS("Incorrect SDVO get h_postion\n");
  2194. return;
  2195. }
  2196. sdvo_priv->max_hpos = data_value[0];
  2197. sdvo_priv->cur_hpos = response;
  2198. sdvo_priv->hpos_property =
  2199. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2200. "hpos", 2);
  2201. sdvo_priv->hpos_property->values[0] = 0;
  2202. sdvo_priv->hpos_property->values[1] = data_value[0];
  2203. drm_connector_attach_property(connector,
  2204. sdvo_priv->hpos_property,
  2205. sdvo_priv->cur_hpos);
  2206. DRM_DEBUG_KMS("h_position: max %d, "
  2207. "default %d, current %d\n",
  2208. data_value[0], data_value[1], response);
  2209. }
  2210. if (sdvo_data.position_v) {
  2211. intel_sdvo_write_cmd(intel_encoder,
  2212. SDVO_CMD_GET_MAX_POSITION_V, NULL, 0);
  2213. status = intel_sdvo_read_response(intel_encoder,
  2214. &data_value, 4);
  2215. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2216. DRM_DEBUG_KMS("Incorrect SDVO Max v_pos\n");
  2217. return;
  2218. }
  2219. intel_sdvo_write_cmd(intel_encoder,
  2220. SDVO_CMD_GET_POSITION_V, NULL, 0);
  2221. status = intel_sdvo_read_response(intel_encoder,
  2222. &response, 2);
  2223. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2224. DRM_DEBUG_KMS("Incorrect SDVO get v_postion\n");
  2225. return;
  2226. }
  2227. sdvo_priv->max_vpos = data_value[0];
  2228. sdvo_priv->cur_vpos = response;
  2229. sdvo_priv->vpos_property =
  2230. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2231. "vpos", 2);
  2232. sdvo_priv->vpos_property->values[0] = 0;
  2233. sdvo_priv->vpos_property->values[1] = data_value[0];
  2234. drm_connector_attach_property(connector,
  2235. sdvo_priv->vpos_property,
  2236. sdvo_priv->cur_vpos);
  2237. DRM_DEBUG_KMS("v_position: max %d, "
  2238. "default %d, current %d\n",
  2239. data_value[0], data_value[1], response);
  2240. }
  2241. if (sdvo_data.saturation) {
  2242. intel_sdvo_write_cmd(intel_encoder,
  2243. SDVO_CMD_GET_MAX_SATURATION, NULL, 0);
  2244. status = intel_sdvo_read_response(intel_encoder,
  2245. &data_value, 4);
  2246. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2247. DRM_DEBUG_KMS("Incorrect SDVO Max sat\n");
  2248. return;
  2249. }
  2250. intel_sdvo_write_cmd(intel_encoder,
  2251. SDVO_CMD_GET_SATURATION, NULL, 0);
  2252. status = intel_sdvo_read_response(intel_encoder,
  2253. &response, 2);
  2254. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2255. DRM_DEBUG_KMS("Incorrect SDVO get sat\n");
  2256. return;
  2257. }
  2258. sdvo_priv->max_saturation = data_value[0];
  2259. sdvo_priv->cur_saturation = response;
  2260. sdvo_priv->saturation_property =
  2261. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2262. "saturation", 2);
  2263. sdvo_priv->saturation_property->values[0] = 0;
  2264. sdvo_priv->saturation_property->values[1] =
  2265. data_value[0];
  2266. drm_connector_attach_property(connector,
  2267. sdvo_priv->saturation_property,
  2268. sdvo_priv->cur_saturation);
  2269. DRM_DEBUG_KMS("saturation: max %d, "
  2270. "default %d, current %d\n",
  2271. data_value[0], data_value[1], response);
  2272. }
  2273. if (sdvo_data.contrast) {
  2274. intel_sdvo_write_cmd(intel_encoder,
  2275. SDVO_CMD_GET_MAX_CONTRAST, NULL, 0);
  2276. status = intel_sdvo_read_response(intel_encoder,
  2277. &data_value, 4);
  2278. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2279. DRM_DEBUG_KMS("Incorrect SDVO Max contrast\n");
  2280. return;
  2281. }
  2282. intel_sdvo_write_cmd(intel_encoder,
  2283. SDVO_CMD_GET_CONTRAST, NULL, 0);
  2284. status = intel_sdvo_read_response(intel_encoder,
  2285. &response, 2);
  2286. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2287. DRM_DEBUG_KMS("Incorrect SDVO get contrast\n");
  2288. return;
  2289. }
  2290. sdvo_priv->max_contrast = data_value[0];
  2291. sdvo_priv->cur_contrast = response;
  2292. sdvo_priv->contrast_property =
  2293. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2294. "contrast", 2);
  2295. sdvo_priv->contrast_property->values[0] = 0;
  2296. sdvo_priv->contrast_property->values[1] = data_value[0];
  2297. drm_connector_attach_property(connector,
  2298. sdvo_priv->contrast_property,
  2299. sdvo_priv->cur_contrast);
  2300. DRM_DEBUG_KMS("contrast: max %d, "
  2301. "default %d, current %d\n",
  2302. data_value[0], data_value[1], response);
  2303. }
  2304. if (sdvo_data.hue) {
  2305. intel_sdvo_write_cmd(intel_encoder,
  2306. SDVO_CMD_GET_MAX_HUE, NULL, 0);
  2307. status = intel_sdvo_read_response(intel_encoder,
  2308. &data_value, 4);
  2309. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2310. DRM_DEBUG_KMS("Incorrect SDVO Max hue\n");
  2311. return;
  2312. }
  2313. intel_sdvo_write_cmd(intel_encoder,
  2314. SDVO_CMD_GET_HUE, NULL, 0);
  2315. status = intel_sdvo_read_response(intel_encoder,
  2316. &response, 2);
  2317. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2318. DRM_DEBUG_KMS("Incorrect SDVO get hue\n");
  2319. return;
  2320. }
  2321. sdvo_priv->max_hue = data_value[0];
  2322. sdvo_priv->cur_hue = response;
  2323. sdvo_priv->hue_property =
  2324. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2325. "hue", 2);
  2326. sdvo_priv->hue_property->values[0] = 0;
  2327. sdvo_priv->hue_property->values[1] =
  2328. data_value[0];
  2329. drm_connector_attach_property(connector,
  2330. sdvo_priv->hue_property,
  2331. sdvo_priv->cur_hue);
  2332. DRM_DEBUG_KMS("hue: max %d, default %d, current %d\n",
  2333. data_value[0], data_value[1], response);
  2334. }
  2335. }
  2336. if (IS_TV(sdvo_priv) || IS_LVDS(sdvo_priv)) {
  2337. if (sdvo_data.brightness) {
  2338. intel_sdvo_write_cmd(intel_encoder,
  2339. SDVO_CMD_GET_MAX_BRIGHTNESS, NULL, 0);
  2340. status = intel_sdvo_read_response(intel_encoder,
  2341. &data_value, 4);
  2342. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2343. DRM_DEBUG_KMS("Incorrect SDVO Max bright\n");
  2344. return;
  2345. }
  2346. intel_sdvo_write_cmd(intel_encoder,
  2347. SDVO_CMD_GET_BRIGHTNESS, NULL, 0);
  2348. status = intel_sdvo_read_response(intel_encoder,
  2349. &response, 2);
  2350. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2351. DRM_DEBUG_KMS("Incorrect SDVO get brigh\n");
  2352. return;
  2353. }
  2354. sdvo_priv->max_brightness = data_value[0];
  2355. sdvo_priv->cur_brightness = response;
  2356. sdvo_priv->brightness_property =
  2357. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2358. "brightness", 2);
  2359. sdvo_priv->brightness_property->values[0] = 0;
  2360. sdvo_priv->brightness_property->values[1] =
  2361. data_value[0];
  2362. drm_connector_attach_property(connector,
  2363. sdvo_priv->brightness_property,
  2364. sdvo_priv->cur_brightness);
  2365. DRM_DEBUG_KMS("brightness: max %d, "
  2366. "default %d, current %d\n",
  2367. data_value[0], data_value[1], response);
  2368. }
  2369. }
  2370. return;
  2371. }
  2372. bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
  2373. {
  2374. struct drm_i915_private *dev_priv = dev->dev_private;
  2375. struct intel_encoder *intel_encoder;
  2376. struct intel_sdvo_priv *sdvo_priv;
  2377. u8 ch[0x40];
  2378. int i;
  2379. u32 i2c_reg, ddc_reg, analog_ddc_reg;
  2380. intel_encoder = kcalloc(sizeof(struct intel_encoder)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
  2381. if (!intel_encoder) {
  2382. return false;
  2383. }
  2384. sdvo_priv = (struct intel_sdvo_priv *)(intel_encoder + 1);
  2385. sdvo_priv->sdvo_reg = sdvo_reg;
  2386. intel_encoder->dev_priv = sdvo_priv;
  2387. intel_encoder->type = INTEL_OUTPUT_SDVO;
  2388. if (HAS_PCH_SPLIT(dev)) {
  2389. i2c_reg = PCH_GPIOE;
  2390. ddc_reg = PCH_GPIOE;
  2391. analog_ddc_reg = PCH_GPIOA;
  2392. } else {
  2393. i2c_reg = GPIOE;
  2394. ddc_reg = GPIOE;
  2395. analog_ddc_reg = GPIOA;
  2396. }
  2397. /* setup the DDC bus. */
  2398. if (IS_SDVOB(sdvo_reg))
  2399. intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOB");
  2400. else
  2401. intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOC");
  2402. if (!intel_encoder->i2c_bus)
  2403. goto err_inteloutput;
  2404. sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg);
  2405. /* Save the bit-banging i2c functionality for use by the DDC wrapper */
  2406. intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality;
  2407. /* Read the regs to test if we can talk to the device */
  2408. for (i = 0; i < 0x40; i++) {
  2409. if (!intel_sdvo_read_byte(intel_encoder, i, &ch[i])) {
  2410. DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
  2411. IS_SDVOB(sdvo_reg) ? 'B' : 'C');
  2412. goto err_i2c;
  2413. }
  2414. }
  2415. /* setup the DDC bus. */
  2416. if (IS_SDVOB(sdvo_reg)) {
  2417. intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOB DDC BUS");
  2418. sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
  2419. "SDVOB/VGA DDC BUS");
  2420. dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
  2421. } else {
  2422. intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOC DDC BUS");
  2423. sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
  2424. "SDVOC/VGA DDC BUS");
  2425. dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
  2426. }
  2427. if (intel_encoder->ddc_bus == NULL)
  2428. goto err_i2c;
  2429. /* Wrap with our custom algo which switches to DDC mode */
  2430. intel_encoder->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
  2431. /* encoder type will be decided later */
  2432. drm_encoder_init(dev, &intel_encoder->enc, &intel_sdvo_enc_funcs, 0);
  2433. drm_encoder_helper_add(&intel_encoder->enc, &intel_sdvo_helper_funcs);
  2434. /* In default case sdvo lvds is false */
  2435. intel_sdvo_get_capabilities(intel_encoder, &sdvo_priv->caps);
  2436. if (intel_sdvo_output_setup(intel_encoder,
  2437. sdvo_priv->caps.output_flags) != true) {
  2438. DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
  2439. IS_SDVOB(sdvo_reg) ? 'B' : 'C');
  2440. goto err_i2c;
  2441. }
  2442. intel_sdvo_select_ddc_bus(dev_priv, sdvo_priv, sdvo_reg);
  2443. /* Set the input timing to the screen. Assume always input 0. */
  2444. intel_sdvo_set_target_input(intel_encoder, true, false);
  2445. intel_sdvo_get_input_pixel_clock_range(intel_encoder,
  2446. &sdvo_priv->pixel_clock_min,
  2447. &sdvo_priv->pixel_clock_max);
  2448. DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
  2449. "clock range %dMHz - %dMHz, "
  2450. "input 1: %c, input 2: %c, "
  2451. "output 1: %c, output 2: %c\n",
  2452. SDVO_NAME(sdvo_priv),
  2453. sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
  2454. sdvo_priv->caps.device_rev_id,
  2455. sdvo_priv->pixel_clock_min / 1000,
  2456. sdvo_priv->pixel_clock_max / 1000,
  2457. (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
  2458. (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
  2459. /* check currently supported outputs */
  2460. sdvo_priv->caps.output_flags &
  2461. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
  2462. sdvo_priv->caps.output_flags &
  2463. (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
  2464. return true;
  2465. err_i2c:
  2466. if (sdvo_priv->analog_ddc_bus != NULL)
  2467. intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
  2468. if (intel_encoder->ddc_bus != NULL)
  2469. intel_i2c_destroy(intel_encoder->ddc_bus);
  2470. if (intel_encoder->i2c_bus != NULL)
  2471. intel_i2c_destroy(intel_encoder->i2c_bus);
  2472. err_inteloutput:
  2473. kfree(intel_encoder);
  2474. return false;
  2475. }