intel_overlay.c 37 KB

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  1. /*
  2. * Copyright © 2009
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21. * SOFTWARE.
  22. *
  23. * Authors:
  24. * Daniel Vetter <daniel@ffwll.ch>
  25. *
  26. * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
  27. */
  28. #include "drmP.h"
  29. #include "drm.h"
  30. #include "i915_drm.h"
  31. #include "i915_drv.h"
  32. #include "i915_reg.h"
  33. #include "intel_drv.h"
  34. /* Limits for overlay size. According to intel doc, the real limits are:
  35. * Y width: 4095, UV width (planar): 2047, Y height: 2047,
  36. * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
  37. * the mininum of both. */
  38. #define IMAGE_MAX_WIDTH 2048
  39. #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
  40. /* on 830 and 845 these large limits result in the card hanging */
  41. #define IMAGE_MAX_WIDTH_LEGACY 1024
  42. #define IMAGE_MAX_HEIGHT_LEGACY 1088
  43. /* overlay register definitions */
  44. /* OCMD register */
  45. #define OCMD_TILED_SURFACE (0x1<<19)
  46. #define OCMD_MIRROR_MASK (0x3<<17)
  47. #define OCMD_MIRROR_MODE (0x3<<17)
  48. #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
  49. #define OCMD_MIRROR_VERTICAL (0x2<<17)
  50. #define OCMD_MIRROR_BOTH (0x3<<17)
  51. #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
  52. #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
  53. #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
  54. #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
  55. #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
  56. #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
  57. #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
  58. #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
  59. #define OCMD_YUV_422_PACKED (0x8<<10)
  60. #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
  61. #define OCMD_YUV_420_PLANAR (0xc<<10)
  62. #define OCMD_YUV_422_PLANAR (0xd<<10)
  63. #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
  64. #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
  65. #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
  66. #define OCMD_BUF_TYPE_MASK (0x1<<5)
  67. #define OCMD_BUF_TYPE_FRAME (0x0<<5)
  68. #define OCMD_BUF_TYPE_FIELD (0x1<<5)
  69. #define OCMD_TEST_MODE (0x1<<4)
  70. #define OCMD_BUFFER_SELECT (0x3<<2)
  71. #define OCMD_BUFFER0 (0x0<<2)
  72. #define OCMD_BUFFER1 (0x1<<2)
  73. #define OCMD_FIELD_SELECT (0x1<<2)
  74. #define OCMD_FIELD0 (0x0<<1)
  75. #define OCMD_FIELD1 (0x1<<1)
  76. #define OCMD_ENABLE (0x1<<0)
  77. /* OCONFIG register */
  78. #define OCONF_PIPE_MASK (0x1<<18)
  79. #define OCONF_PIPE_A (0x0<<18)
  80. #define OCONF_PIPE_B (0x1<<18)
  81. #define OCONF_GAMMA2_ENABLE (0x1<<16)
  82. #define OCONF_CSC_MODE_BT601 (0x0<<5)
  83. #define OCONF_CSC_MODE_BT709 (0x1<<5)
  84. #define OCONF_CSC_BYPASS (0x1<<4)
  85. #define OCONF_CC_OUT_8BIT (0x1<<3)
  86. #define OCONF_TEST_MODE (0x1<<2)
  87. #define OCONF_THREE_LINE_BUFFER (0x1<<0)
  88. #define OCONF_TWO_LINE_BUFFER (0x0<<0)
  89. /* DCLRKM (dst-key) register */
  90. #define DST_KEY_ENABLE (0x1<<31)
  91. #define CLK_RGB24_MASK 0x0
  92. #define CLK_RGB16_MASK 0x070307
  93. #define CLK_RGB15_MASK 0x070707
  94. #define CLK_RGB8I_MASK 0xffffff
  95. #define RGB16_TO_COLORKEY(c) \
  96. (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
  97. #define RGB15_TO_COLORKEY(c) \
  98. (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
  99. /* overlay flip addr flag */
  100. #define OFC_UPDATE 0x1
  101. /* polyphase filter coefficients */
  102. #define N_HORIZ_Y_TAPS 5
  103. #define N_VERT_Y_TAPS 3
  104. #define N_HORIZ_UV_TAPS 3
  105. #define N_VERT_UV_TAPS 3
  106. #define N_PHASES 17
  107. #define MAX_TAPS 5
  108. /* memory bufferd overlay registers */
  109. struct overlay_registers {
  110. u32 OBUF_0Y;
  111. u32 OBUF_1Y;
  112. u32 OBUF_0U;
  113. u32 OBUF_0V;
  114. u32 OBUF_1U;
  115. u32 OBUF_1V;
  116. u32 OSTRIDE;
  117. u32 YRGB_VPH;
  118. u32 UV_VPH;
  119. u32 HORZ_PH;
  120. u32 INIT_PHS;
  121. u32 DWINPOS;
  122. u32 DWINSZ;
  123. u32 SWIDTH;
  124. u32 SWIDTHSW;
  125. u32 SHEIGHT;
  126. u32 YRGBSCALE;
  127. u32 UVSCALE;
  128. u32 OCLRC0;
  129. u32 OCLRC1;
  130. u32 DCLRKV;
  131. u32 DCLRKM;
  132. u32 SCLRKVH;
  133. u32 SCLRKVL;
  134. u32 SCLRKEN;
  135. u32 OCONFIG;
  136. u32 OCMD;
  137. u32 RESERVED1; /* 0x6C */
  138. u32 OSTART_0Y;
  139. u32 OSTART_1Y;
  140. u32 OSTART_0U;
  141. u32 OSTART_0V;
  142. u32 OSTART_1U;
  143. u32 OSTART_1V;
  144. u32 OTILEOFF_0Y;
  145. u32 OTILEOFF_1Y;
  146. u32 OTILEOFF_0U;
  147. u32 OTILEOFF_0V;
  148. u32 OTILEOFF_1U;
  149. u32 OTILEOFF_1V;
  150. u32 FASTHSCALE; /* 0xA0 */
  151. u32 UVSCALEV; /* 0xA4 */
  152. u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
  153. u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
  154. u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
  155. u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
  156. u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
  157. u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
  158. u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
  159. u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
  160. u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
  161. };
  162. /* overlay flip addr flag */
  163. #define OFC_UPDATE 0x1
  164. #define OVERLAY_NONPHYSICAL(dev) (IS_G33(dev) || IS_I965G(dev))
  165. #define OVERLAY_EXISTS(dev) (!IS_G4X(dev) && !IS_IRONLAKE(dev) && !IS_GEN6(dev))
  166. static struct overlay_registers *intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
  167. {
  168. drm_i915_private_t *dev_priv = overlay->dev->dev_private;
  169. struct overlay_registers *regs;
  170. /* no recursive mappings */
  171. BUG_ON(overlay->virt_addr);
  172. if (OVERLAY_NONPHYSICAL(overlay->dev)) {
  173. regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
  174. overlay->reg_bo->gtt_offset,
  175. KM_USER0);
  176. if (!regs) {
  177. DRM_ERROR("failed to map overlay regs in GTT\n");
  178. return NULL;
  179. }
  180. } else
  181. regs = overlay->reg_bo->phys_obj->handle->vaddr;
  182. return overlay->virt_addr = regs;
  183. }
  184. static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay)
  185. {
  186. if (OVERLAY_NONPHYSICAL(overlay->dev))
  187. io_mapping_unmap_atomic(overlay->virt_addr, KM_USER0);
  188. overlay->virt_addr = NULL;
  189. return;
  190. }
  191. /* overlay needs to be disable in OCMD reg */
  192. static int intel_overlay_on(struct intel_overlay *overlay)
  193. {
  194. struct drm_device *dev = overlay->dev;
  195. int ret;
  196. drm_i915_private_t *dev_priv = dev->dev_private;
  197. BUG_ON(overlay->active);
  198. overlay->active = 1;
  199. overlay->hw_wedged = NEEDS_WAIT_FOR_FLIP;
  200. BEGIN_LP_RING(4);
  201. OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
  202. OUT_RING(overlay->flip_addr | OFC_UPDATE);
  203. OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
  204. OUT_RING(MI_NOOP);
  205. ADVANCE_LP_RING();
  206. overlay->last_flip_req =
  207. i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
  208. if (overlay->last_flip_req == 0)
  209. return -ENOMEM;
  210. ret = i915_do_wait_request(dev,
  211. overlay->last_flip_req, 1, &dev_priv->render_ring);
  212. if (ret != 0)
  213. return ret;
  214. overlay->hw_wedged = 0;
  215. overlay->last_flip_req = 0;
  216. return 0;
  217. }
  218. /* overlay needs to be enabled in OCMD reg */
  219. static void intel_overlay_continue(struct intel_overlay *overlay,
  220. bool load_polyphase_filter)
  221. {
  222. struct drm_device *dev = overlay->dev;
  223. drm_i915_private_t *dev_priv = dev->dev_private;
  224. u32 flip_addr = overlay->flip_addr;
  225. u32 tmp;
  226. BUG_ON(!overlay->active);
  227. if (load_polyphase_filter)
  228. flip_addr |= OFC_UPDATE;
  229. /* check for underruns */
  230. tmp = I915_READ(DOVSTA);
  231. if (tmp & (1 << 17))
  232. DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
  233. BEGIN_LP_RING(2);
  234. OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
  235. OUT_RING(flip_addr);
  236. ADVANCE_LP_RING();
  237. overlay->last_flip_req =
  238. i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
  239. }
  240. static int intel_overlay_wait_flip(struct intel_overlay *overlay)
  241. {
  242. struct drm_device *dev = overlay->dev;
  243. drm_i915_private_t *dev_priv = dev->dev_private;
  244. int ret;
  245. u32 tmp;
  246. if (overlay->last_flip_req != 0) {
  247. ret = i915_do_wait_request(dev, overlay->last_flip_req,
  248. 1, &dev_priv->render_ring);
  249. if (ret == 0) {
  250. overlay->last_flip_req = 0;
  251. tmp = I915_READ(ISR);
  252. if (!(tmp & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT))
  253. return 0;
  254. }
  255. }
  256. /* synchronous slowpath */
  257. overlay->hw_wedged = RELEASE_OLD_VID;
  258. BEGIN_LP_RING(2);
  259. OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
  260. OUT_RING(MI_NOOP);
  261. ADVANCE_LP_RING();
  262. overlay->last_flip_req =
  263. i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
  264. if (overlay->last_flip_req == 0)
  265. return -ENOMEM;
  266. ret = i915_do_wait_request(dev, overlay->last_flip_req,
  267. 1, &dev_priv->render_ring);
  268. if (ret != 0)
  269. return ret;
  270. overlay->hw_wedged = 0;
  271. overlay->last_flip_req = 0;
  272. return 0;
  273. }
  274. /* overlay needs to be disabled in OCMD reg */
  275. static int intel_overlay_off(struct intel_overlay *overlay)
  276. {
  277. u32 flip_addr = overlay->flip_addr;
  278. struct drm_device *dev = overlay->dev;
  279. drm_i915_private_t *dev_priv = dev->dev_private;
  280. int ret;
  281. BUG_ON(!overlay->active);
  282. /* According to intel docs the overlay hw may hang (when switching
  283. * off) without loading the filter coeffs. It is however unclear whether
  284. * this applies to the disabling of the overlay or to the switching off
  285. * of the hw. Do it in both cases */
  286. flip_addr |= OFC_UPDATE;
  287. /* wait for overlay to go idle */
  288. overlay->hw_wedged = SWITCH_OFF_STAGE_1;
  289. BEGIN_LP_RING(4);
  290. OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
  291. OUT_RING(flip_addr);
  292. OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
  293. OUT_RING(MI_NOOP);
  294. ADVANCE_LP_RING();
  295. overlay->last_flip_req =
  296. i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
  297. if (overlay->last_flip_req == 0)
  298. return -ENOMEM;
  299. ret = i915_do_wait_request(dev, overlay->last_flip_req,
  300. 1, &dev_priv->render_ring);
  301. if (ret != 0)
  302. return ret;
  303. /* turn overlay off */
  304. overlay->hw_wedged = SWITCH_OFF_STAGE_2;
  305. BEGIN_LP_RING(4);
  306. OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
  307. OUT_RING(flip_addr);
  308. OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
  309. OUT_RING(MI_NOOP);
  310. ADVANCE_LP_RING();
  311. overlay->last_flip_req =
  312. i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
  313. if (overlay->last_flip_req == 0)
  314. return -ENOMEM;
  315. ret = i915_do_wait_request(dev, overlay->last_flip_req,
  316. 1, &dev_priv->render_ring);
  317. if (ret != 0)
  318. return ret;
  319. overlay->hw_wedged = 0;
  320. overlay->last_flip_req = 0;
  321. return ret;
  322. }
  323. static void intel_overlay_off_tail(struct intel_overlay *overlay)
  324. {
  325. struct drm_gem_object *obj;
  326. /* never have the overlay hw on without showing a frame */
  327. BUG_ON(!overlay->vid_bo);
  328. obj = &overlay->vid_bo->base;
  329. i915_gem_object_unpin(obj);
  330. drm_gem_object_unreference(obj);
  331. overlay->vid_bo = NULL;
  332. overlay->crtc->overlay = NULL;
  333. overlay->crtc = NULL;
  334. overlay->active = 0;
  335. }
  336. /* recover from an interruption due to a signal
  337. * We have to be careful not to repeat work forever an make forward progess. */
  338. int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay,
  339. int interruptible)
  340. {
  341. struct drm_device *dev = overlay->dev;
  342. struct drm_gem_object *obj;
  343. drm_i915_private_t *dev_priv = dev->dev_private;
  344. u32 flip_addr;
  345. int ret;
  346. if (overlay->hw_wedged == HW_WEDGED)
  347. return -EIO;
  348. if (overlay->last_flip_req == 0) {
  349. overlay->last_flip_req =
  350. i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
  351. if (overlay->last_flip_req == 0)
  352. return -ENOMEM;
  353. }
  354. ret = i915_do_wait_request(dev, overlay->last_flip_req,
  355. interruptible, &dev_priv->render_ring);
  356. if (ret != 0)
  357. return ret;
  358. switch (overlay->hw_wedged) {
  359. case RELEASE_OLD_VID:
  360. obj = &overlay->old_vid_bo->base;
  361. i915_gem_object_unpin(obj);
  362. drm_gem_object_unreference(obj);
  363. overlay->old_vid_bo = NULL;
  364. break;
  365. case SWITCH_OFF_STAGE_1:
  366. flip_addr = overlay->flip_addr;
  367. flip_addr |= OFC_UPDATE;
  368. overlay->hw_wedged = SWITCH_OFF_STAGE_2;
  369. BEGIN_LP_RING(4);
  370. OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
  371. OUT_RING(flip_addr);
  372. OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
  373. OUT_RING(MI_NOOP);
  374. ADVANCE_LP_RING();
  375. overlay->last_flip_req = i915_add_request(dev, NULL,
  376. 0, &dev_priv->render_ring);
  377. if (overlay->last_flip_req == 0)
  378. return -ENOMEM;
  379. ret = i915_do_wait_request(dev, overlay->last_flip_req,
  380. interruptible, &dev_priv->render_ring);
  381. if (ret != 0)
  382. return ret;
  383. case SWITCH_OFF_STAGE_2:
  384. intel_overlay_off_tail(overlay);
  385. break;
  386. default:
  387. BUG_ON(overlay->hw_wedged != NEEDS_WAIT_FOR_FLIP);
  388. }
  389. overlay->hw_wedged = 0;
  390. overlay->last_flip_req = 0;
  391. return 0;
  392. }
  393. /* Wait for pending overlay flip and release old frame.
  394. * Needs to be called before the overlay register are changed
  395. * via intel_overlay_(un)map_regs_atomic */
  396. static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
  397. {
  398. int ret;
  399. struct drm_gem_object *obj;
  400. /* only wait if there is actually an old frame to release to
  401. * guarantee forward progress */
  402. if (!overlay->old_vid_bo)
  403. return 0;
  404. ret = intel_overlay_wait_flip(overlay);
  405. if (ret != 0)
  406. return ret;
  407. obj = &overlay->old_vid_bo->base;
  408. i915_gem_object_unpin(obj);
  409. drm_gem_object_unreference(obj);
  410. overlay->old_vid_bo = NULL;
  411. return 0;
  412. }
  413. struct put_image_params {
  414. int format;
  415. short dst_x;
  416. short dst_y;
  417. short dst_w;
  418. short dst_h;
  419. short src_w;
  420. short src_scan_h;
  421. short src_scan_w;
  422. short src_h;
  423. short stride_Y;
  424. short stride_UV;
  425. int offset_Y;
  426. int offset_U;
  427. int offset_V;
  428. };
  429. static int packed_depth_bytes(u32 format)
  430. {
  431. switch (format & I915_OVERLAY_DEPTH_MASK) {
  432. case I915_OVERLAY_YUV422:
  433. return 4;
  434. case I915_OVERLAY_YUV411:
  435. /* return 6; not implemented */
  436. default:
  437. return -EINVAL;
  438. }
  439. }
  440. static int packed_width_bytes(u32 format, short width)
  441. {
  442. switch (format & I915_OVERLAY_DEPTH_MASK) {
  443. case I915_OVERLAY_YUV422:
  444. return width << 1;
  445. default:
  446. return -EINVAL;
  447. }
  448. }
  449. static int uv_hsubsampling(u32 format)
  450. {
  451. switch (format & I915_OVERLAY_DEPTH_MASK) {
  452. case I915_OVERLAY_YUV422:
  453. case I915_OVERLAY_YUV420:
  454. return 2;
  455. case I915_OVERLAY_YUV411:
  456. case I915_OVERLAY_YUV410:
  457. return 4;
  458. default:
  459. return -EINVAL;
  460. }
  461. }
  462. static int uv_vsubsampling(u32 format)
  463. {
  464. switch (format & I915_OVERLAY_DEPTH_MASK) {
  465. case I915_OVERLAY_YUV420:
  466. case I915_OVERLAY_YUV410:
  467. return 2;
  468. case I915_OVERLAY_YUV422:
  469. case I915_OVERLAY_YUV411:
  470. return 1;
  471. default:
  472. return -EINVAL;
  473. }
  474. }
  475. static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
  476. {
  477. u32 mask, shift, ret;
  478. if (IS_I9XX(dev)) {
  479. mask = 0x3f;
  480. shift = 6;
  481. } else {
  482. mask = 0x1f;
  483. shift = 5;
  484. }
  485. ret = ((offset + width + mask) >> shift) - (offset >> shift);
  486. if (IS_I9XX(dev))
  487. ret <<= 1;
  488. ret -=1;
  489. return ret << 2;
  490. }
  491. static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
  492. 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
  493. 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
  494. 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
  495. 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
  496. 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
  497. 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
  498. 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
  499. 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
  500. 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
  501. 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
  502. 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
  503. 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
  504. 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
  505. 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
  506. 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
  507. 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
  508. 0xb000, 0x3000, 0x0800, 0x3000, 0xb000};
  509. static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
  510. 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
  511. 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
  512. 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
  513. 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
  514. 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
  515. 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
  516. 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
  517. 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
  518. 0x3000, 0x0800, 0x3000};
  519. static void update_polyphase_filter(struct overlay_registers *regs)
  520. {
  521. memcpy(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
  522. memcpy(regs->UV_HCOEFS, uv_static_hcoeffs, sizeof(uv_static_hcoeffs));
  523. }
  524. static bool update_scaling_factors(struct intel_overlay *overlay,
  525. struct overlay_registers *regs,
  526. struct put_image_params *params)
  527. {
  528. /* fixed point with a 12 bit shift */
  529. u32 xscale, yscale, xscale_UV, yscale_UV;
  530. #define FP_SHIFT 12
  531. #define FRACT_MASK 0xfff
  532. bool scale_changed = false;
  533. int uv_hscale = uv_hsubsampling(params->format);
  534. int uv_vscale = uv_vsubsampling(params->format);
  535. if (params->dst_w > 1)
  536. xscale = ((params->src_scan_w - 1) << FP_SHIFT)
  537. /(params->dst_w);
  538. else
  539. xscale = 1 << FP_SHIFT;
  540. if (params->dst_h > 1)
  541. yscale = ((params->src_scan_h - 1) << FP_SHIFT)
  542. /(params->dst_h);
  543. else
  544. yscale = 1 << FP_SHIFT;
  545. /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
  546. xscale_UV = xscale/uv_hscale;
  547. yscale_UV = yscale/uv_vscale;
  548. /* make the Y scale to UV scale ratio an exact multiply */
  549. xscale = xscale_UV * uv_hscale;
  550. yscale = yscale_UV * uv_vscale;
  551. /*} else {
  552. xscale_UV = 0;
  553. yscale_UV = 0;
  554. }*/
  555. if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
  556. scale_changed = true;
  557. overlay->old_xscale = xscale;
  558. overlay->old_yscale = yscale;
  559. regs->YRGBSCALE = ((yscale & FRACT_MASK) << 20)
  560. | ((xscale >> FP_SHIFT) << 16)
  561. | ((xscale & FRACT_MASK) << 3);
  562. regs->UVSCALE = ((yscale_UV & FRACT_MASK) << 20)
  563. | ((xscale_UV >> FP_SHIFT) << 16)
  564. | ((xscale_UV & FRACT_MASK) << 3);
  565. regs->UVSCALEV = ((yscale >> FP_SHIFT) << 16)
  566. | ((yscale_UV >> FP_SHIFT) << 0);
  567. if (scale_changed)
  568. update_polyphase_filter(regs);
  569. return scale_changed;
  570. }
  571. static void update_colorkey(struct intel_overlay *overlay,
  572. struct overlay_registers *regs)
  573. {
  574. u32 key = overlay->color_key;
  575. switch (overlay->crtc->base.fb->bits_per_pixel) {
  576. case 8:
  577. regs->DCLRKV = 0;
  578. regs->DCLRKM = CLK_RGB8I_MASK | DST_KEY_ENABLE;
  579. case 16:
  580. if (overlay->crtc->base.fb->depth == 15) {
  581. regs->DCLRKV = RGB15_TO_COLORKEY(key);
  582. regs->DCLRKM = CLK_RGB15_MASK | DST_KEY_ENABLE;
  583. } else {
  584. regs->DCLRKV = RGB16_TO_COLORKEY(key);
  585. regs->DCLRKM = CLK_RGB16_MASK | DST_KEY_ENABLE;
  586. }
  587. case 24:
  588. case 32:
  589. regs->DCLRKV = key;
  590. regs->DCLRKM = CLK_RGB24_MASK | DST_KEY_ENABLE;
  591. }
  592. }
  593. static u32 overlay_cmd_reg(struct put_image_params *params)
  594. {
  595. u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
  596. if (params->format & I915_OVERLAY_YUV_PLANAR) {
  597. switch (params->format & I915_OVERLAY_DEPTH_MASK) {
  598. case I915_OVERLAY_YUV422:
  599. cmd |= OCMD_YUV_422_PLANAR;
  600. break;
  601. case I915_OVERLAY_YUV420:
  602. cmd |= OCMD_YUV_420_PLANAR;
  603. break;
  604. case I915_OVERLAY_YUV411:
  605. case I915_OVERLAY_YUV410:
  606. cmd |= OCMD_YUV_410_PLANAR;
  607. break;
  608. }
  609. } else { /* YUV packed */
  610. switch (params->format & I915_OVERLAY_DEPTH_MASK) {
  611. case I915_OVERLAY_YUV422:
  612. cmd |= OCMD_YUV_422_PACKED;
  613. break;
  614. case I915_OVERLAY_YUV411:
  615. cmd |= OCMD_YUV_411_PACKED;
  616. break;
  617. }
  618. switch (params->format & I915_OVERLAY_SWAP_MASK) {
  619. case I915_OVERLAY_NO_SWAP:
  620. break;
  621. case I915_OVERLAY_UV_SWAP:
  622. cmd |= OCMD_UV_SWAP;
  623. break;
  624. case I915_OVERLAY_Y_SWAP:
  625. cmd |= OCMD_Y_SWAP;
  626. break;
  627. case I915_OVERLAY_Y_AND_UV_SWAP:
  628. cmd |= OCMD_Y_AND_UV_SWAP;
  629. break;
  630. }
  631. }
  632. return cmd;
  633. }
  634. int intel_overlay_do_put_image(struct intel_overlay *overlay,
  635. struct drm_gem_object *new_bo,
  636. struct put_image_params *params)
  637. {
  638. int ret, tmp_width;
  639. struct overlay_registers *regs;
  640. bool scale_changed = false;
  641. struct drm_i915_gem_object *bo_priv = to_intel_bo(new_bo);
  642. struct drm_device *dev = overlay->dev;
  643. BUG_ON(!mutex_is_locked(&dev->struct_mutex));
  644. BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
  645. BUG_ON(!overlay);
  646. ret = intel_overlay_release_old_vid(overlay);
  647. if (ret != 0)
  648. return ret;
  649. ret = i915_gem_object_pin(new_bo, PAGE_SIZE);
  650. if (ret != 0)
  651. return ret;
  652. ret = i915_gem_object_set_to_gtt_domain(new_bo, 0);
  653. if (ret != 0)
  654. goto out_unpin;
  655. if (!overlay->active) {
  656. regs = intel_overlay_map_regs_atomic(overlay);
  657. if (!regs) {
  658. ret = -ENOMEM;
  659. goto out_unpin;
  660. }
  661. regs->OCONFIG = OCONF_CC_OUT_8BIT;
  662. if (IS_I965GM(overlay->dev))
  663. regs->OCONFIG |= OCONF_CSC_MODE_BT709;
  664. regs->OCONFIG |= overlay->crtc->pipe == 0 ?
  665. OCONF_PIPE_A : OCONF_PIPE_B;
  666. intel_overlay_unmap_regs_atomic(overlay);
  667. ret = intel_overlay_on(overlay);
  668. if (ret != 0)
  669. goto out_unpin;
  670. }
  671. regs = intel_overlay_map_regs_atomic(overlay);
  672. if (!regs) {
  673. ret = -ENOMEM;
  674. goto out_unpin;
  675. }
  676. regs->DWINPOS = (params->dst_y << 16) | params->dst_x;
  677. regs->DWINSZ = (params->dst_h << 16) | params->dst_w;
  678. if (params->format & I915_OVERLAY_YUV_PACKED)
  679. tmp_width = packed_width_bytes(params->format, params->src_w);
  680. else
  681. tmp_width = params->src_w;
  682. regs->SWIDTH = params->src_w;
  683. regs->SWIDTHSW = calc_swidthsw(overlay->dev,
  684. params->offset_Y, tmp_width);
  685. regs->SHEIGHT = params->src_h;
  686. regs->OBUF_0Y = bo_priv->gtt_offset + params-> offset_Y;
  687. regs->OSTRIDE = params->stride_Y;
  688. if (params->format & I915_OVERLAY_YUV_PLANAR) {
  689. int uv_hscale = uv_hsubsampling(params->format);
  690. int uv_vscale = uv_vsubsampling(params->format);
  691. u32 tmp_U, tmp_V;
  692. regs->SWIDTH |= (params->src_w/uv_hscale) << 16;
  693. tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
  694. params->src_w/uv_hscale);
  695. tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
  696. params->src_w/uv_hscale);
  697. regs->SWIDTHSW |= max_t(u32, tmp_U, tmp_V) << 16;
  698. regs->SHEIGHT |= (params->src_h/uv_vscale) << 16;
  699. regs->OBUF_0U = bo_priv->gtt_offset + params->offset_U;
  700. regs->OBUF_0V = bo_priv->gtt_offset + params->offset_V;
  701. regs->OSTRIDE |= params->stride_UV << 16;
  702. }
  703. scale_changed = update_scaling_factors(overlay, regs, params);
  704. update_colorkey(overlay, regs);
  705. regs->OCMD = overlay_cmd_reg(params);
  706. intel_overlay_unmap_regs_atomic(overlay);
  707. intel_overlay_continue(overlay, scale_changed);
  708. overlay->old_vid_bo = overlay->vid_bo;
  709. overlay->vid_bo = to_intel_bo(new_bo);
  710. return 0;
  711. out_unpin:
  712. i915_gem_object_unpin(new_bo);
  713. return ret;
  714. }
  715. int intel_overlay_switch_off(struct intel_overlay *overlay)
  716. {
  717. int ret;
  718. struct overlay_registers *regs;
  719. struct drm_device *dev = overlay->dev;
  720. BUG_ON(!mutex_is_locked(&dev->struct_mutex));
  721. BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
  722. if (overlay->hw_wedged) {
  723. ret = intel_overlay_recover_from_interrupt(overlay, 1);
  724. if (ret != 0)
  725. return ret;
  726. }
  727. if (!overlay->active)
  728. return 0;
  729. ret = intel_overlay_release_old_vid(overlay);
  730. if (ret != 0)
  731. return ret;
  732. regs = intel_overlay_map_regs_atomic(overlay);
  733. regs->OCMD = 0;
  734. intel_overlay_unmap_regs_atomic(overlay);
  735. ret = intel_overlay_off(overlay);
  736. if (ret != 0)
  737. return ret;
  738. intel_overlay_off_tail(overlay);
  739. return 0;
  740. }
  741. static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
  742. struct intel_crtc *crtc)
  743. {
  744. drm_i915_private_t *dev_priv = overlay->dev->dev_private;
  745. u32 pipeconf;
  746. int pipeconf_reg = (crtc->pipe == 0) ? PIPEACONF : PIPEBCONF;
  747. if (!crtc->base.enabled || crtc->dpms_mode != DRM_MODE_DPMS_ON)
  748. return -EINVAL;
  749. pipeconf = I915_READ(pipeconf_reg);
  750. /* can't use the overlay with double wide pipe */
  751. if (!IS_I965G(overlay->dev) && pipeconf & PIPEACONF_DOUBLE_WIDE)
  752. return -EINVAL;
  753. return 0;
  754. }
  755. static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
  756. {
  757. struct drm_device *dev = overlay->dev;
  758. drm_i915_private_t *dev_priv = dev->dev_private;
  759. u32 ratio;
  760. u32 pfit_control = I915_READ(PFIT_CONTROL);
  761. /* XXX: This is not the same logic as in the xorg driver, but more in
  762. * line with the intel documentation for the i965 */
  763. if (!IS_I965G(dev) && (pfit_control & VERT_AUTO_SCALE)) {
  764. ratio = I915_READ(PFIT_AUTO_RATIOS) >> PFIT_VERT_SCALE_SHIFT;
  765. } else { /* on i965 use the PGM reg to read out the autoscaler values */
  766. ratio = I915_READ(PFIT_PGM_RATIOS);
  767. if (IS_I965G(dev))
  768. ratio >>= PFIT_VERT_SCALE_SHIFT_965;
  769. else
  770. ratio >>= PFIT_VERT_SCALE_SHIFT;
  771. }
  772. overlay->pfit_vscale_ratio = ratio;
  773. }
  774. static int check_overlay_dst(struct intel_overlay *overlay,
  775. struct drm_intel_overlay_put_image *rec)
  776. {
  777. struct drm_display_mode *mode = &overlay->crtc->base.mode;
  778. if ((rec->dst_x < mode->crtc_hdisplay)
  779. && (rec->dst_x + rec->dst_width
  780. <= mode->crtc_hdisplay)
  781. && (rec->dst_y < mode->crtc_vdisplay)
  782. && (rec->dst_y + rec->dst_height
  783. <= mode->crtc_vdisplay))
  784. return 0;
  785. else
  786. return -EINVAL;
  787. }
  788. static int check_overlay_scaling(struct put_image_params *rec)
  789. {
  790. u32 tmp;
  791. /* downscaling limit is 8.0 */
  792. tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
  793. if (tmp > 7)
  794. return -EINVAL;
  795. tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
  796. if (tmp > 7)
  797. return -EINVAL;
  798. return 0;
  799. }
  800. static int check_overlay_src(struct drm_device *dev,
  801. struct drm_intel_overlay_put_image *rec,
  802. struct drm_gem_object *new_bo)
  803. {
  804. u32 stride_mask;
  805. int depth;
  806. int uv_hscale = uv_hsubsampling(rec->flags);
  807. int uv_vscale = uv_vsubsampling(rec->flags);
  808. size_t tmp;
  809. /* check src dimensions */
  810. if (IS_845G(dev) || IS_I830(dev)) {
  811. if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY
  812. || rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
  813. return -EINVAL;
  814. } else {
  815. if (rec->src_height > IMAGE_MAX_HEIGHT
  816. || rec->src_width > IMAGE_MAX_WIDTH)
  817. return -EINVAL;
  818. }
  819. /* better safe than sorry, use 4 as the maximal subsampling ratio */
  820. if (rec->src_height < N_VERT_Y_TAPS*4
  821. || rec->src_width < N_HORIZ_Y_TAPS*4)
  822. return -EINVAL;
  823. /* check alignment constraints */
  824. switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
  825. case I915_OVERLAY_RGB:
  826. /* not implemented */
  827. return -EINVAL;
  828. case I915_OVERLAY_YUV_PACKED:
  829. depth = packed_depth_bytes(rec->flags);
  830. if (uv_vscale != 1)
  831. return -EINVAL;
  832. if (depth < 0)
  833. return depth;
  834. /* ignore UV planes */
  835. rec->stride_UV = 0;
  836. rec->offset_U = 0;
  837. rec->offset_V = 0;
  838. /* check pixel alignment */
  839. if (rec->offset_Y % depth)
  840. return -EINVAL;
  841. break;
  842. case I915_OVERLAY_YUV_PLANAR:
  843. if (uv_vscale < 0 || uv_hscale < 0)
  844. return -EINVAL;
  845. /* no offset restrictions for planar formats */
  846. break;
  847. default:
  848. return -EINVAL;
  849. }
  850. if (rec->src_width % uv_hscale)
  851. return -EINVAL;
  852. /* stride checking */
  853. if (IS_I830(dev) || IS_845G(dev))
  854. stride_mask = 255;
  855. else
  856. stride_mask = 63;
  857. if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
  858. return -EINVAL;
  859. if (IS_I965G(dev) && rec->stride_Y < 512)
  860. return -EINVAL;
  861. tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
  862. 4 : 8;
  863. if (rec->stride_Y > tmp*1024 || rec->stride_UV > 2*1024)
  864. return -EINVAL;
  865. /* check buffer dimensions */
  866. switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
  867. case I915_OVERLAY_RGB:
  868. case I915_OVERLAY_YUV_PACKED:
  869. /* always 4 Y values per depth pixels */
  870. if (packed_width_bytes(rec->flags, rec->src_width)
  871. > rec->stride_Y)
  872. return -EINVAL;
  873. tmp = rec->stride_Y*rec->src_height;
  874. if (rec->offset_Y + tmp > new_bo->size)
  875. return -EINVAL;
  876. break;
  877. case I915_OVERLAY_YUV_PLANAR:
  878. if (rec->src_width > rec->stride_Y)
  879. return -EINVAL;
  880. if (rec->src_width/uv_hscale > rec->stride_UV)
  881. return -EINVAL;
  882. tmp = rec->stride_Y*rec->src_height;
  883. if (rec->offset_Y + tmp > new_bo->size)
  884. return -EINVAL;
  885. tmp = rec->stride_UV*rec->src_height;
  886. tmp /= uv_vscale;
  887. if (rec->offset_U + tmp > new_bo->size
  888. || rec->offset_V + tmp > new_bo->size)
  889. return -EINVAL;
  890. break;
  891. }
  892. return 0;
  893. }
  894. int intel_overlay_put_image(struct drm_device *dev, void *data,
  895. struct drm_file *file_priv)
  896. {
  897. struct drm_intel_overlay_put_image *put_image_rec = data;
  898. drm_i915_private_t *dev_priv = dev->dev_private;
  899. struct intel_overlay *overlay;
  900. struct drm_mode_object *drmmode_obj;
  901. struct intel_crtc *crtc;
  902. struct drm_gem_object *new_bo;
  903. struct put_image_params *params;
  904. int ret;
  905. if (!dev_priv) {
  906. DRM_ERROR("called with no initialization\n");
  907. return -EINVAL;
  908. }
  909. overlay = dev_priv->overlay;
  910. if (!overlay) {
  911. DRM_DEBUG("userspace bug: no overlay\n");
  912. return -ENODEV;
  913. }
  914. if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
  915. mutex_lock(&dev->mode_config.mutex);
  916. mutex_lock(&dev->struct_mutex);
  917. ret = intel_overlay_switch_off(overlay);
  918. mutex_unlock(&dev->struct_mutex);
  919. mutex_unlock(&dev->mode_config.mutex);
  920. return ret;
  921. }
  922. params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
  923. if (!params)
  924. return -ENOMEM;
  925. drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
  926. DRM_MODE_OBJECT_CRTC);
  927. if (!drmmode_obj) {
  928. ret = -ENOENT;
  929. goto out_free;
  930. }
  931. crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
  932. new_bo = drm_gem_object_lookup(dev, file_priv,
  933. put_image_rec->bo_handle);
  934. if (!new_bo) {
  935. ret = -ENOENT;
  936. goto out_free;
  937. }
  938. mutex_lock(&dev->mode_config.mutex);
  939. mutex_lock(&dev->struct_mutex);
  940. if (overlay->hw_wedged) {
  941. ret = intel_overlay_recover_from_interrupt(overlay, 1);
  942. if (ret != 0)
  943. goto out_unlock;
  944. }
  945. if (overlay->crtc != crtc) {
  946. struct drm_display_mode *mode = &crtc->base.mode;
  947. ret = intel_overlay_switch_off(overlay);
  948. if (ret != 0)
  949. goto out_unlock;
  950. ret = check_overlay_possible_on_crtc(overlay, crtc);
  951. if (ret != 0)
  952. goto out_unlock;
  953. overlay->crtc = crtc;
  954. crtc->overlay = overlay;
  955. if (intel_panel_fitter_pipe(dev) == crtc->pipe
  956. /* and line to wide, i.e. one-line-mode */
  957. && mode->hdisplay > 1024) {
  958. overlay->pfit_active = 1;
  959. update_pfit_vscale_ratio(overlay);
  960. } else
  961. overlay->pfit_active = 0;
  962. }
  963. ret = check_overlay_dst(overlay, put_image_rec);
  964. if (ret != 0)
  965. goto out_unlock;
  966. if (overlay->pfit_active) {
  967. params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
  968. overlay->pfit_vscale_ratio);
  969. /* shifting right rounds downwards, so add 1 */
  970. params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
  971. overlay->pfit_vscale_ratio) + 1;
  972. } else {
  973. params->dst_y = put_image_rec->dst_y;
  974. params->dst_h = put_image_rec->dst_height;
  975. }
  976. params->dst_x = put_image_rec->dst_x;
  977. params->dst_w = put_image_rec->dst_width;
  978. params->src_w = put_image_rec->src_width;
  979. params->src_h = put_image_rec->src_height;
  980. params->src_scan_w = put_image_rec->src_scan_width;
  981. params->src_scan_h = put_image_rec->src_scan_height;
  982. if (params->src_scan_h > params->src_h
  983. || params->src_scan_w > params->src_w) {
  984. ret = -EINVAL;
  985. goto out_unlock;
  986. }
  987. ret = check_overlay_src(dev, put_image_rec, new_bo);
  988. if (ret != 0)
  989. goto out_unlock;
  990. params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
  991. params->stride_Y = put_image_rec->stride_Y;
  992. params->stride_UV = put_image_rec->stride_UV;
  993. params->offset_Y = put_image_rec->offset_Y;
  994. params->offset_U = put_image_rec->offset_U;
  995. params->offset_V = put_image_rec->offset_V;
  996. /* Check scaling after src size to prevent a divide-by-zero. */
  997. ret = check_overlay_scaling(params);
  998. if (ret != 0)
  999. goto out_unlock;
  1000. ret = intel_overlay_do_put_image(overlay, new_bo, params);
  1001. if (ret != 0)
  1002. goto out_unlock;
  1003. mutex_unlock(&dev->struct_mutex);
  1004. mutex_unlock(&dev->mode_config.mutex);
  1005. kfree(params);
  1006. return 0;
  1007. out_unlock:
  1008. mutex_unlock(&dev->struct_mutex);
  1009. mutex_unlock(&dev->mode_config.mutex);
  1010. drm_gem_object_unreference_unlocked(new_bo);
  1011. out_free:
  1012. kfree(params);
  1013. return ret;
  1014. }
  1015. static void update_reg_attrs(struct intel_overlay *overlay,
  1016. struct overlay_registers *regs)
  1017. {
  1018. regs->OCLRC0 = (overlay->contrast << 18) | (overlay->brightness & 0xff);
  1019. regs->OCLRC1 = overlay->saturation;
  1020. }
  1021. static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
  1022. {
  1023. int i;
  1024. if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
  1025. return false;
  1026. for (i = 0; i < 3; i++) {
  1027. if (((gamma1 >> i * 8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
  1028. return false;
  1029. }
  1030. return true;
  1031. }
  1032. static bool check_gamma5_errata(u32 gamma5)
  1033. {
  1034. int i;
  1035. for (i = 0; i < 3; i++) {
  1036. if (((gamma5 >> i*8) & 0xff) == 0x80)
  1037. return false;
  1038. }
  1039. return true;
  1040. }
  1041. static int check_gamma(struct drm_intel_overlay_attrs *attrs)
  1042. {
  1043. if (!check_gamma_bounds(0, attrs->gamma0)
  1044. || !check_gamma_bounds(attrs->gamma0, attrs->gamma1)
  1045. || !check_gamma_bounds(attrs->gamma1, attrs->gamma2)
  1046. || !check_gamma_bounds(attrs->gamma2, attrs->gamma3)
  1047. || !check_gamma_bounds(attrs->gamma3, attrs->gamma4)
  1048. || !check_gamma_bounds(attrs->gamma4, attrs->gamma5)
  1049. || !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
  1050. return -EINVAL;
  1051. if (!check_gamma5_errata(attrs->gamma5))
  1052. return -EINVAL;
  1053. return 0;
  1054. }
  1055. int intel_overlay_attrs(struct drm_device *dev, void *data,
  1056. struct drm_file *file_priv)
  1057. {
  1058. struct drm_intel_overlay_attrs *attrs = data;
  1059. drm_i915_private_t *dev_priv = dev->dev_private;
  1060. struct intel_overlay *overlay;
  1061. struct overlay_registers *regs;
  1062. int ret;
  1063. if (!dev_priv) {
  1064. DRM_ERROR("called with no initialization\n");
  1065. return -EINVAL;
  1066. }
  1067. overlay = dev_priv->overlay;
  1068. if (!overlay) {
  1069. DRM_DEBUG("userspace bug: no overlay\n");
  1070. return -ENODEV;
  1071. }
  1072. mutex_lock(&dev->mode_config.mutex);
  1073. mutex_lock(&dev->struct_mutex);
  1074. if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
  1075. attrs->color_key = overlay->color_key;
  1076. attrs->brightness = overlay->brightness;
  1077. attrs->contrast = overlay->contrast;
  1078. attrs->saturation = overlay->saturation;
  1079. if (IS_I9XX(dev)) {
  1080. attrs->gamma0 = I915_READ(OGAMC0);
  1081. attrs->gamma1 = I915_READ(OGAMC1);
  1082. attrs->gamma2 = I915_READ(OGAMC2);
  1083. attrs->gamma3 = I915_READ(OGAMC3);
  1084. attrs->gamma4 = I915_READ(OGAMC4);
  1085. attrs->gamma5 = I915_READ(OGAMC5);
  1086. }
  1087. ret = 0;
  1088. } else {
  1089. overlay->color_key = attrs->color_key;
  1090. if (attrs->brightness >= -128 && attrs->brightness <= 127) {
  1091. overlay->brightness = attrs->brightness;
  1092. } else {
  1093. ret = -EINVAL;
  1094. goto out_unlock;
  1095. }
  1096. if (attrs->contrast <= 255) {
  1097. overlay->contrast = attrs->contrast;
  1098. } else {
  1099. ret = -EINVAL;
  1100. goto out_unlock;
  1101. }
  1102. if (attrs->saturation <= 1023) {
  1103. overlay->saturation = attrs->saturation;
  1104. } else {
  1105. ret = -EINVAL;
  1106. goto out_unlock;
  1107. }
  1108. regs = intel_overlay_map_regs_atomic(overlay);
  1109. if (!regs) {
  1110. ret = -ENOMEM;
  1111. goto out_unlock;
  1112. }
  1113. update_reg_attrs(overlay, regs);
  1114. intel_overlay_unmap_regs_atomic(overlay);
  1115. if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
  1116. if (!IS_I9XX(dev)) {
  1117. ret = -EINVAL;
  1118. goto out_unlock;
  1119. }
  1120. if (overlay->active) {
  1121. ret = -EBUSY;
  1122. goto out_unlock;
  1123. }
  1124. ret = check_gamma(attrs);
  1125. if (ret != 0)
  1126. goto out_unlock;
  1127. I915_WRITE(OGAMC0, attrs->gamma0);
  1128. I915_WRITE(OGAMC1, attrs->gamma1);
  1129. I915_WRITE(OGAMC2, attrs->gamma2);
  1130. I915_WRITE(OGAMC3, attrs->gamma3);
  1131. I915_WRITE(OGAMC4, attrs->gamma4);
  1132. I915_WRITE(OGAMC5, attrs->gamma5);
  1133. }
  1134. ret = 0;
  1135. }
  1136. out_unlock:
  1137. mutex_unlock(&dev->struct_mutex);
  1138. mutex_unlock(&dev->mode_config.mutex);
  1139. return ret;
  1140. }
  1141. void intel_setup_overlay(struct drm_device *dev)
  1142. {
  1143. drm_i915_private_t *dev_priv = dev->dev_private;
  1144. struct intel_overlay *overlay;
  1145. struct drm_gem_object *reg_bo;
  1146. struct overlay_registers *regs;
  1147. int ret;
  1148. if (!OVERLAY_EXISTS(dev))
  1149. return;
  1150. overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
  1151. if (!overlay)
  1152. return;
  1153. overlay->dev = dev;
  1154. reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
  1155. if (!reg_bo)
  1156. goto out_free;
  1157. overlay->reg_bo = to_intel_bo(reg_bo);
  1158. if (OVERLAY_NONPHYSICAL(dev)) {
  1159. ret = i915_gem_object_pin(reg_bo, PAGE_SIZE);
  1160. if (ret) {
  1161. DRM_ERROR("failed to pin overlay register bo\n");
  1162. goto out_free_bo;
  1163. }
  1164. overlay->flip_addr = overlay->reg_bo->gtt_offset;
  1165. } else {
  1166. ret = i915_gem_attach_phys_object(dev, reg_bo,
  1167. I915_GEM_PHYS_OVERLAY_REGS);
  1168. if (ret) {
  1169. DRM_ERROR("failed to attach phys overlay regs\n");
  1170. goto out_free_bo;
  1171. }
  1172. overlay->flip_addr = overlay->reg_bo->phys_obj->handle->busaddr;
  1173. }
  1174. /* init all values */
  1175. overlay->color_key = 0x0101fe;
  1176. overlay->brightness = -19;
  1177. overlay->contrast = 75;
  1178. overlay->saturation = 146;
  1179. regs = intel_overlay_map_regs_atomic(overlay);
  1180. if (!regs)
  1181. goto out_free_bo;
  1182. memset(regs, 0, sizeof(struct overlay_registers));
  1183. update_polyphase_filter(regs);
  1184. update_reg_attrs(overlay, regs);
  1185. intel_overlay_unmap_regs_atomic(overlay);
  1186. dev_priv->overlay = overlay;
  1187. DRM_INFO("initialized overlay support\n");
  1188. return;
  1189. out_free_bo:
  1190. drm_gem_object_unreference(reg_bo);
  1191. out_free:
  1192. kfree(overlay);
  1193. return;
  1194. }
  1195. void intel_cleanup_overlay(struct drm_device *dev)
  1196. {
  1197. drm_i915_private_t *dev_priv = dev->dev_private;
  1198. if (dev_priv->overlay) {
  1199. /* The bo's should be free'd by the generic code already.
  1200. * Furthermore modesetting teardown happens beforehand so the
  1201. * hardware should be off already */
  1202. BUG_ON(dev_priv->overlay->active);
  1203. kfree(dev_priv->overlay);
  1204. }
  1205. }