intel_lvds.c 29 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22. * DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors:
  25. * Eric Anholt <eric@anholt.net>
  26. * Dave Airlie <airlied@linux.ie>
  27. * Jesse Barnes <jesse.barnes@intel.com>
  28. */
  29. #include <acpi/button.h>
  30. #include <linux/dmi.h>
  31. #include <linux/i2c.h>
  32. #include <linux/slab.h>
  33. #include "drmP.h"
  34. #include "drm.h"
  35. #include "drm_crtc.h"
  36. #include "drm_edid.h"
  37. #include "intel_drv.h"
  38. #include "i915_drm.h"
  39. #include "i915_drv.h"
  40. #include <linux/acpi.h>
  41. /* Private structure for the integrated LVDS support */
  42. struct intel_lvds_priv {
  43. int fitting_mode;
  44. u32 pfit_control;
  45. u32 pfit_pgm_ratios;
  46. };
  47. /**
  48. * Sets the backlight level.
  49. *
  50. * \param level backlight level, from 0 to intel_lvds_get_max_backlight().
  51. */
  52. static void intel_lvds_set_backlight(struct drm_device *dev, int level)
  53. {
  54. struct drm_i915_private *dev_priv = dev->dev_private;
  55. u32 blc_pwm_ctl, reg;
  56. if (HAS_PCH_SPLIT(dev))
  57. reg = BLC_PWM_CPU_CTL;
  58. else
  59. reg = BLC_PWM_CTL;
  60. blc_pwm_ctl = I915_READ(reg) & ~BACKLIGHT_DUTY_CYCLE_MASK;
  61. I915_WRITE(reg, (blc_pwm_ctl |
  62. (level << BACKLIGHT_DUTY_CYCLE_SHIFT)));
  63. }
  64. /**
  65. * Returns the maximum level of the backlight duty cycle field.
  66. */
  67. static u32 intel_lvds_get_max_backlight(struct drm_device *dev)
  68. {
  69. struct drm_i915_private *dev_priv = dev->dev_private;
  70. u32 reg;
  71. if (HAS_PCH_SPLIT(dev))
  72. reg = BLC_PWM_PCH_CTL2;
  73. else
  74. reg = BLC_PWM_CTL;
  75. return ((I915_READ(reg) & BACKLIGHT_MODULATION_FREQ_MASK) >>
  76. BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
  77. }
  78. /**
  79. * Sets the power state for the panel.
  80. */
  81. static void intel_lvds_set_power(struct drm_device *dev, bool on)
  82. {
  83. struct drm_i915_private *dev_priv = dev->dev_private;
  84. u32 pp_status, ctl_reg, status_reg, lvds_reg;
  85. if (HAS_PCH_SPLIT(dev)) {
  86. ctl_reg = PCH_PP_CONTROL;
  87. status_reg = PCH_PP_STATUS;
  88. lvds_reg = PCH_LVDS;
  89. } else {
  90. ctl_reg = PP_CONTROL;
  91. status_reg = PP_STATUS;
  92. lvds_reg = LVDS;
  93. }
  94. if (on) {
  95. I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN);
  96. POSTING_READ(lvds_reg);
  97. I915_WRITE(ctl_reg, I915_READ(ctl_reg) |
  98. POWER_TARGET_ON);
  99. do {
  100. pp_status = I915_READ(status_reg);
  101. } while ((pp_status & PP_ON) == 0);
  102. intel_lvds_set_backlight(dev, dev_priv->backlight_duty_cycle);
  103. } else {
  104. intel_lvds_set_backlight(dev, 0);
  105. I915_WRITE(ctl_reg, I915_READ(ctl_reg) &
  106. ~POWER_TARGET_ON);
  107. do {
  108. pp_status = I915_READ(status_reg);
  109. } while (pp_status & PP_ON);
  110. I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN);
  111. POSTING_READ(lvds_reg);
  112. }
  113. }
  114. static void intel_lvds_dpms(struct drm_encoder *encoder, int mode)
  115. {
  116. struct drm_device *dev = encoder->dev;
  117. if (mode == DRM_MODE_DPMS_ON)
  118. intel_lvds_set_power(dev, true);
  119. else
  120. intel_lvds_set_power(dev, false);
  121. /* XXX: We never power down the LVDS pairs. */
  122. }
  123. static int intel_lvds_mode_valid(struct drm_connector *connector,
  124. struct drm_display_mode *mode)
  125. {
  126. struct drm_device *dev = connector->dev;
  127. struct drm_i915_private *dev_priv = dev->dev_private;
  128. struct drm_display_mode *fixed_mode = dev_priv->panel_fixed_mode;
  129. if (fixed_mode) {
  130. if (mode->hdisplay > fixed_mode->hdisplay)
  131. return MODE_PANEL;
  132. if (mode->vdisplay > fixed_mode->vdisplay)
  133. return MODE_PANEL;
  134. }
  135. return MODE_OK;
  136. }
  137. static void
  138. centre_horizontally(struct drm_display_mode *mode,
  139. int width)
  140. {
  141. u32 border, sync_pos, blank_width, sync_width;
  142. /* keep the hsync and hblank widths constant */
  143. sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
  144. blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
  145. sync_pos = (blank_width - sync_width + 1) / 2;
  146. border = (mode->hdisplay - width + 1) / 2;
  147. border += border & 1; /* make the border even */
  148. mode->crtc_hdisplay = width;
  149. mode->crtc_hblank_start = width + border;
  150. mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
  151. mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
  152. mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
  153. }
  154. static void
  155. centre_vertically(struct drm_display_mode *mode,
  156. int height)
  157. {
  158. u32 border, sync_pos, blank_width, sync_width;
  159. /* keep the vsync and vblank widths constant */
  160. sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
  161. blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
  162. sync_pos = (blank_width - sync_width + 1) / 2;
  163. border = (mode->vdisplay - height + 1) / 2;
  164. mode->crtc_vdisplay = height;
  165. mode->crtc_vblank_start = height + border;
  166. mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
  167. mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
  168. mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
  169. }
  170. static inline u32 panel_fitter_scaling(u32 source, u32 target)
  171. {
  172. /*
  173. * Floating point operation is not supported. So the FACTOR
  174. * is defined, which can avoid the floating point computation
  175. * when calculating the panel ratio.
  176. */
  177. #define ACCURACY 12
  178. #define FACTOR (1 << ACCURACY)
  179. u32 ratio = source * FACTOR / target;
  180. return (FACTOR * ratio + FACTOR/2) / FACTOR;
  181. }
  182. static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
  183. struct drm_display_mode *mode,
  184. struct drm_display_mode *adjusted_mode)
  185. {
  186. struct drm_device *dev = encoder->dev;
  187. struct drm_i915_private *dev_priv = dev->dev_private;
  188. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  189. struct drm_encoder *tmp_encoder;
  190. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  191. struct intel_lvds_priv *lvds_priv = intel_encoder->dev_priv;
  192. u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
  193. /* Should never happen!! */
  194. if (!IS_I965G(dev) && intel_crtc->pipe == 0) {
  195. DRM_ERROR("Can't support LVDS on pipe A\n");
  196. return false;
  197. }
  198. /* Should never happen!! */
  199. list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list, head) {
  200. if (tmp_encoder != encoder && tmp_encoder->crtc == encoder->crtc) {
  201. DRM_ERROR("Can't enable LVDS and another "
  202. "encoder on the same pipe\n");
  203. return false;
  204. }
  205. }
  206. /* If we don't have a panel mode, there is nothing we can do */
  207. if (dev_priv->panel_fixed_mode == NULL)
  208. return true;
  209. /*
  210. * We have timings from the BIOS for the panel, put them in
  211. * to the adjusted mode. The CRTC will be set up for this mode,
  212. * with the panel scaling set up to source from the H/VDisplay
  213. * of the original mode.
  214. */
  215. adjusted_mode->hdisplay = dev_priv->panel_fixed_mode->hdisplay;
  216. adjusted_mode->hsync_start =
  217. dev_priv->panel_fixed_mode->hsync_start;
  218. adjusted_mode->hsync_end =
  219. dev_priv->panel_fixed_mode->hsync_end;
  220. adjusted_mode->htotal = dev_priv->panel_fixed_mode->htotal;
  221. adjusted_mode->vdisplay = dev_priv->panel_fixed_mode->vdisplay;
  222. adjusted_mode->vsync_start =
  223. dev_priv->panel_fixed_mode->vsync_start;
  224. adjusted_mode->vsync_end =
  225. dev_priv->panel_fixed_mode->vsync_end;
  226. adjusted_mode->vtotal = dev_priv->panel_fixed_mode->vtotal;
  227. adjusted_mode->clock = dev_priv->panel_fixed_mode->clock;
  228. drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
  229. /* Make sure pre-965s set dither correctly */
  230. if (!IS_I965G(dev)) {
  231. if (dev_priv->panel_wants_dither || dev_priv->lvds_dither)
  232. pfit_control |= PANEL_8TO6_DITHER_ENABLE;
  233. }
  234. /* Native modes don't need fitting */
  235. if (adjusted_mode->hdisplay == mode->hdisplay &&
  236. adjusted_mode->vdisplay == mode->vdisplay)
  237. goto out;
  238. /* full screen scale for now */
  239. if (HAS_PCH_SPLIT(dev))
  240. goto out;
  241. /* 965+ wants fuzzy fitting */
  242. if (IS_I965G(dev))
  243. pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
  244. PFIT_FILTER_FUZZY);
  245. /*
  246. * Enable automatic panel scaling for non-native modes so that they fill
  247. * the screen. Should be enabled before the pipe is enabled, according
  248. * to register description and PRM.
  249. * Change the value here to see the borders for debugging
  250. */
  251. if (!HAS_PCH_SPLIT(dev)) {
  252. I915_WRITE(BCLRPAT_A, 0);
  253. I915_WRITE(BCLRPAT_B, 0);
  254. }
  255. switch (lvds_priv->fitting_mode) {
  256. case DRM_MODE_SCALE_CENTER:
  257. /*
  258. * For centered modes, we have to calculate border widths &
  259. * heights and modify the values programmed into the CRTC.
  260. */
  261. centre_horizontally(adjusted_mode, mode->hdisplay);
  262. centre_vertically(adjusted_mode, mode->vdisplay);
  263. border = LVDS_BORDER_ENABLE;
  264. break;
  265. case DRM_MODE_SCALE_ASPECT:
  266. /* Scale but preserve the aspect ratio */
  267. if (IS_I965G(dev)) {
  268. u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
  269. u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
  270. pfit_control |= PFIT_ENABLE;
  271. /* 965+ is easy, it does everything in hw */
  272. if (scaled_width > scaled_height)
  273. pfit_control |= PFIT_SCALING_PILLAR;
  274. else if (scaled_width < scaled_height)
  275. pfit_control |= PFIT_SCALING_LETTER;
  276. else
  277. pfit_control |= PFIT_SCALING_AUTO;
  278. } else {
  279. u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
  280. u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
  281. /*
  282. * For earlier chips we have to calculate the scaling
  283. * ratio by hand and program it into the
  284. * PFIT_PGM_RATIO register
  285. */
  286. if (scaled_width > scaled_height) { /* pillar */
  287. centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay);
  288. border = LVDS_BORDER_ENABLE;
  289. if (mode->vdisplay != adjusted_mode->vdisplay) {
  290. u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay);
  291. pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
  292. bits << PFIT_VERT_SCALE_SHIFT);
  293. pfit_control |= (PFIT_ENABLE |
  294. VERT_INTERP_BILINEAR |
  295. HORIZ_INTERP_BILINEAR);
  296. }
  297. } else if (scaled_width < scaled_height) { /* letter */
  298. centre_vertically(adjusted_mode, scaled_width / mode->hdisplay);
  299. border = LVDS_BORDER_ENABLE;
  300. if (mode->hdisplay != adjusted_mode->hdisplay) {
  301. u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay);
  302. pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
  303. bits << PFIT_VERT_SCALE_SHIFT);
  304. pfit_control |= (PFIT_ENABLE |
  305. VERT_INTERP_BILINEAR |
  306. HORIZ_INTERP_BILINEAR);
  307. }
  308. } else
  309. /* Aspects match, Let hw scale both directions */
  310. pfit_control |= (PFIT_ENABLE |
  311. VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
  312. VERT_INTERP_BILINEAR |
  313. HORIZ_INTERP_BILINEAR);
  314. }
  315. break;
  316. case DRM_MODE_SCALE_FULLSCREEN:
  317. /*
  318. * Full scaling, even if it changes the aspect ratio.
  319. * Fortunately this is all done for us in hw.
  320. */
  321. pfit_control |= PFIT_ENABLE;
  322. if (IS_I965G(dev))
  323. pfit_control |= PFIT_SCALING_AUTO;
  324. else
  325. pfit_control |= (VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
  326. VERT_INTERP_BILINEAR |
  327. HORIZ_INTERP_BILINEAR);
  328. break;
  329. default:
  330. break;
  331. }
  332. out:
  333. lvds_priv->pfit_control = pfit_control;
  334. lvds_priv->pfit_pgm_ratios = pfit_pgm_ratios;
  335. dev_priv->lvds_border_bits = border;
  336. /*
  337. * XXX: It would be nice to support lower refresh rates on the
  338. * panels to reduce power consumption, and perhaps match the
  339. * user's requested refresh rate.
  340. */
  341. return true;
  342. }
  343. static void intel_lvds_prepare(struct drm_encoder *encoder)
  344. {
  345. struct drm_device *dev = encoder->dev;
  346. struct drm_i915_private *dev_priv = dev->dev_private;
  347. u32 reg;
  348. if (HAS_PCH_SPLIT(dev))
  349. reg = BLC_PWM_CPU_CTL;
  350. else
  351. reg = BLC_PWM_CTL;
  352. dev_priv->saveBLC_PWM_CTL = I915_READ(reg);
  353. dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL &
  354. BACKLIGHT_DUTY_CYCLE_MASK);
  355. intel_lvds_set_power(dev, false);
  356. }
  357. static void intel_lvds_commit( struct drm_encoder *encoder)
  358. {
  359. struct drm_device *dev = encoder->dev;
  360. struct drm_i915_private *dev_priv = dev->dev_private;
  361. if (dev_priv->backlight_duty_cycle == 0)
  362. dev_priv->backlight_duty_cycle =
  363. intel_lvds_get_max_backlight(dev);
  364. intel_lvds_set_power(dev, true);
  365. }
  366. static void intel_lvds_mode_set(struct drm_encoder *encoder,
  367. struct drm_display_mode *mode,
  368. struct drm_display_mode *adjusted_mode)
  369. {
  370. struct drm_device *dev = encoder->dev;
  371. struct drm_i915_private *dev_priv = dev->dev_private;
  372. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  373. struct intel_lvds_priv *lvds_priv = intel_encoder->dev_priv;
  374. /*
  375. * The LVDS pin pair will already have been turned on in the
  376. * intel_crtc_mode_set since it has a large impact on the DPLL
  377. * settings.
  378. */
  379. if (HAS_PCH_SPLIT(dev))
  380. return;
  381. /*
  382. * Enable automatic panel scaling so that non-native modes fill the
  383. * screen. Should be enabled before the pipe is enabled, according to
  384. * register description and PRM.
  385. */
  386. I915_WRITE(PFIT_PGM_RATIOS, lvds_priv->pfit_pgm_ratios);
  387. I915_WRITE(PFIT_CONTROL, lvds_priv->pfit_control);
  388. }
  389. /**
  390. * Detect the LVDS connection.
  391. *
  392. * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
  393. * connected and closed means disconnected. We also send hotplug events as
  394. * needed, using lid status notification from the input layer.
  395. */
  396. static enum drm_connector_status intel_lvds_detect(struct drm_connector *connector)
  397. {
  398. struct drm_device *dev = connector->dev;
  399. enum drm_connector_status status = connector_status_connected;
  400. /* ACPI lid methods were generally unreliable in this generation, so
  401. * don't even bother.
  402. */
  403. if (IS_GEN2(dev) || IS_GEN3(dev))
  404. return connector_status_connected;
  405. return status;
  406. }
  407. /**
  408. * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
  409. */
  410. static int intel_lvds_get_modes(struct drm_connector *connector)
  411. {
  412. struct drm_device *dev = connector->dev;
  413. struct drm_encoder *encoder = intel_attached_encoder(connector);
  414. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  415. struct drm_i915_private *dev_priv = dev->dev_private;
  416. int ret = 0;
  417. if (dev_priv->lvds_edid_good) {
  418. ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
  419. if (ret)
  420. return ret;
  421. }
  422. /* Didn't get an EDID, so
  423. * Set wide sync ranges so we get all modes
  424. * handed to valid_mode for checking
  425. */
  426. connector->display_info.min_vfreq = 0;
  427. connector->display_info.max_vfreq = 200;
  428. connector->display_info.min_hfreq = 0;
  429. connector->display_info.max_hfreq = 200;
  430. if (dev_priv->panel_fixed_mode != NULL) {
  431. struct drm_display_mode *mode;
  432. mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
  433. drm_mode_probed_add(connector, mode);
  434. return 1;
  435. }
  436. return 0;
  437. }
  438. static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
  439. {
  440. DRM_DEBUG_KMS("Skipping forced modeset for %s\n", id->ident);
  441. return 1;
  442. }
  443. /* The GPU hangs up on these systems if modeset is performed on LID open */
  444. static const struct dmi_system_id intel_no_modeset_on_lid[] = {
  445. {
  446. .callback = intel_no_modeset_on_lid_dmi_callback,
  447. .ident = "Toshiba Tecra A11",
  448. .matches = {
  449. DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
  450. DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
  451. },
  452. },
  453. { } /* terminating entry */
  454. };
  455. /*
  456. * Lid events. Note the use of 'modeset_on_lid':
  457. * - we set it on lid close, and reset it on open
  458. * - we use it as a "only once" bit (ie we ignore
  459. * duplicate events where it was already properly
  460. * set/reset)
  461. * - the suspend/resume paths will also set it to
  462. * zero, since they restore the mode ("lid open").
  463. */
  464. static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
  465. void *unused)
  466. {
  467. struct drm_i915_private *dev_priv =
  468. container_of(nb, struct drm_i915_private, lid_notifier);
  469. struct drm_device *dev = dev_priv->dev;
  470. struct drm_connector *connector = dev_priv->int_lvds_connector;
  471. /*
  472. * check and update the status of LVDS connector after receiving
  473. * the LID nofication event.
  474. */
  475. if (connector)
  476. connector->status = connector->funcs->detect(connector);
  477. /* Don't force modeset on machines where it causes a GPU lockup */
  478. if (dmi_check_system(intel_no_modeset_on_lid))
  479. return NOTIFY_OK;
  480. if (!acpi_lid_open()) {
  481. dev_priv->modeset_on_lid = 1;
  482. return NOTIFY_OK;
  483. }
  484. if (!dev_priv->modeset_on_lid)
  485. return NOTIFY_OK;
  486. dev_priv->modeset_on_lid = 0;
  487. mutex_lock(&dev->mode_config.mutex);
  488. drm_helper_resume_force_mode(dev);
  489. mutex_unlock(&dev->mode_config.mutex);
  490. return NOTIFY_OK;
  491. }
  492. /**
  493. * intel_lvds_destroy - unregister and free LVDS structures
  494. * @connector: connector to free
  495. *
  496. * Unregister the DDC bus for this connector then free the driver private
  497. * structure.
  498. */
  499. static void intel_lvds_destroy(struct drm_connector *connector)
  500. {
  501. struct drm_device *dev = connector->dev;
  502. struct drm_i915_private *dev_priv = dev->dev_private;
  503. if (dev_priv->lid_notifier.notifier_call)
  504. acpi_lid_notifier_unregister(&dev_priv->lid_notifier);
  505. drm_sysfs_connector_remove(connector);
  506. drm_connector_cleanup(connector);
  507. kfree(connector);
  508. }
  509. static int intel_lvds_set_property(struct drm_connector *connector,
  510. struct drm_property *property,
  511. uint64_t value)
  512. {
  513. struct drm_device *dev = connector->dev;
  514. if (property == dev->mode_config.scaling_mode_property &&
  515. connector->encoder) {
  516. struct drm_crtc *crtc = connector->encoder->crtc;
  517. struct drm_encoder *encoder = connector->encoder;
  518. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  519. struct intel_lvds_priv *lvds_priv = intel_encoder->dev_priv;
  520. if (value == DRM_MODE_SCALE_NONE) {
  521. DRM_DEBUG_KMS("no scaling not supported\n");
  522. return 0;
  523. }
  524. if (lvds_priv->fitting_mode == value) {
  525. /* the LVDS scaling property is not changed */
  526. return 0;
  527. }
  528. lvds_priv->fitting_mode = value;
  529. if (crtc && crtc->enabled) {
  530. /*
  531. * If the CRTC is enabled, the display will be changed
  532. * according to the new panel fitting mode.
  533. */
  534. drm_crtc_helper_set_mode(crtc, &crtc->mode,
  535. crtc->x, crtc->y, crtc->fb);
  536. }
  537. }
  538. return 0;
  539. }
  540. static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
  541. .dpms = intel_lvds_dpms,
  542. .mode_fixup = intel_lvds_mode_fixup,
  543. .prepare = intel_lvds_prepare,
  544. .mode_set = intel_lvds_mode_set,
  545. .commit = intel_lvds_commit,
  546. };
  547. static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
  548. .get_modes = intel_lvds_get_modes,
  549. .mode_valid = intel_lvds_mode_valid,
  550. .best_encoder = intel_attached_encoder,
  551. };
  552. static const struct drm_connector_funcs intel_lvds_connector_funcs = {
  553. .dpms = drm_helper_connector_dpms,
  554. .detect = intel_lvds_detect,
  555. .fill_modes = drm_helper_probe_single_connector_modes,
  556. .set_property = intel_lvds_set_property,
  557. .destroy = intel_lvds_destroy,
  558. };
  559. static void intel_lvds_enc_destroy(struct drm_encoder *encoder)
  560. {
  561. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  562. if (intel_encoder->ddc_bus)
  563. intel_i2c_destroy(intel_encoder->ddc_bus);
  564. drm_encoder_cleanup(encoder);
  565. kfree(intel_encoder);
  566. }
  567. static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
  568. .destroy = intel_lvds_enc_destroy,
  569. };
  570. static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
  571. {
  572. DRM_DEBUG_KMS("Skipping LVDS initialization for %s\n", id->ident);
  573. return 1;
  574. }
  575. /* These systems claim to have LVDS, but really don't */
  576. static const struct dmi_system_id intel_no_lvds[] = {
  577. {
  578. .callback = intel_no_lvds_dmi_callback,
  579. .ident = "Apple Mac Mini (Core series)",
  580. .matches = {
  581. DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
  582. DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
  583. },
  584. },
  585. {
  586. .callback = intel_no_lvds_dmi_callback,
  587. .ident = "Apple Mac Mini (Core 2 series)",
  588. .matches = {
  589. DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
  590. DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
  591. },
  592. },
  593. {
  594. .callback = intel_no_lvds_dmi_callback,
  595. .ident = "MSI IM-945GSE-A",
  596. .matches = {
  597. DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
  598. DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
  599. },
  600. },
  601. {
  602. .callback = intel_no_lvds_dmi_callback,
  603. .ident = "Dell Studio Hybrid",
  604. .matches = {
  605. DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
  606. DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
  607. },
  608. },
  609. {
  610. .callback = intel_no_lvds_dmi_callback,
  611. .ident = "AOpen Mini PC",
  612. .matches = {
  613. DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
  614. DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
  615. },
  616. },
  617. {
  618. .callback = intel_no_lvds_dmi_callback,
  619. .ident = "AOpen Mini PC MP915",
  620. .matches = {
  621. DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
  622. DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
  623. },
  624. },
  625. {
  626. .callback = intel_no_lvds_dmi_callback,
  627. .ident = "Aopen i945GTt-VFA",
  628. .matches = {
  629. DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
  630. },
  631. },
  632. {
  633. .callback = intel_no_lvds_dmi_callback,
  634. .ident = "Clientron U800",
  635. .matches = {
  636. DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
  637. DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
  638. },
  639. },
  640. { } /* terminating entry */
  641. };
  642. /**
  643. * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
  644. * @dev: drm device
  645. * @connector: LVDS connector
  646. *
  647. * Find the reduced downclock for LVDS in EDID.
  648. */
  649. static void intel_find_lvds_downclock(struct drm_device *dev,
  650. struct drm_connector *connector)
  651. {
  652. struct drm_i915_private *dev_priv = dev->dev_private;
  653. struct drm_display_mode *scan, *panel_fixed_mode;
  654. int temp_downclock;
  655. panel_fixed_mode = dev_priv->panel_fixed_mode;
  656. temp_downclock = panel_fixed_mode->clock;
  657. mutex_lock(&dev->mode_config.mutex);
  658. list_for_each_entry(scan, &connector->probed_modes, head) {
  659. /*
  660. * If one mode has the same resolution with the fixed_panel
  661. * mode while they have the different refresh rate, it means
  662. * that the reduced downclock is found for the LVDS. In such
  663. * case we can set the different FPx0/1 to dynamically select
  664. * between low and high frequency.
  665. */
  666. if (scan->hdisplay == panel_fixed_mode->hdisplay &&
  667. scan->hsync_start == panel_fixed_mode->hsync_start &&
  668. scan->hsync_end == panel_fixed_mode->hsync_end &&
  669. scan->htotal == panel_fixed_mode->htotal &&
  670. scan->vdisplay == panel_fixed_mode->vdisplay &&
  671. scan->vsync_start == panel_fixed_mode->vsync_start &&
  672. scan->vsync_end == panel_fixed_mode->vsync_end &&
  673. scan->vtotal == panel_fixed_mode->vtotal) {
  674. if (scan->clock < temp_downclock) {
  675. /*
  676. * The downclock is already found. But we
  677. * expect to find the lower downclock.
  678. */
  679. temp_downclock = scan->clock;
  680. }
  681. }
  682. }
  683. mutex_unlock(&dev->mode_config.mutex);
  684. if (temp_downclock < panel_fixed_mode->clock &&
  685. i915_lvds_downclock) {
  686. /* We found the downclock for LVDS. */
  687. dev_priv->lvds_downclock_avail = 1;
  688. dev_priv->lvds_downclock = temp_downclock;
  689. DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
  690. "Normal clock %dKhz, downclock %dKhz\n",
  691. panel_fixed_mode->clock, temp_downclock);
  692. }
  693. return;
  694. }
  695. /*
  696. * Enumerate the child dev array parsed from VBT to check whether
  697. * the LVDS is present.
  698. * If it is present, return 1.
  699. * If it is not present, return false.
  700. * If no child dev is parsed from VBT, it assumes that the LVDS is present.
  701. * Note: The addin_offset should also be checked for LVDS panel.
  702. * Only when it is non-zero, it is assumed that it is present.
  703. */
  704. static int lvds_is_present_in_vbt(struct drm_device *dev)
  705. {
  706. struct drm_i915_private *dev_priv = dev->dev_private;
  707. struct child_device_config *p_child;
  708. int i, ret;
  709. if (!dev_priv->child_dev_num)
  710. return 1;
  711. ret = 0;
  712. for (i = 0; i < dev_priv->child_dev_num; i++) {
  713. p_child = dev_priv->child_dev + i;
  714. /*
  715. * If the device type is not LFP, continue.
  716. * If the device type is 0x22, it is also regarded as LFP.
  717. */
  718. if (p_child->device_type != DEVICE_TYPE_INT_LFP &&
  719. p_child->device_type != DEVICE_TYPE_LFP)
  720. continue;
  721. /* The addin_offset should be checked. Only when it is
  722. * non-zero, it is regarded as present.
  723. */
  724. if (p_child->addin_offset) {
  725. ret = 1;
  726. break;
  727. }
  728. }
  729. return ret;
  730. }
  731. /**
  732. * intel_lvds_init - setup LVDS connectors on this device
  733. * @dev: drm device
  734. *
  735. * Create the connector, register the LVDS DDC bus, and try to figure out what
  736. * modes we can display on the LVDS panel (if present).
  737. */
  738. void intel_lvds_init(struct drm_device *dev)
  739. {
  740. struct drm_i915_private *dev_priv = dev->dev_private;
  741. struct intel_encoder *intel_encoder;
  742. struct intel_connector *intel_connector;
  743. struct drm_connector *connector;
  744. struct drm_encoder *encoder;
  745. struct drm_display_mode *scan; /* *modes, *bios_mode; */
  746. struct drm_crtc *crtc;
  747. struct intel_lvds_priv *lvds_priv;
  748. u32 lvds;
  749. int pipe, gpio = GPIOC;
  750. /* Skip init on machines we know falsely report LVDS */
  751. if (dmi_check_system(intel_no_lvds))
  752. return;
  753. if (!lvds_is_present_in_vbt(dev)) {
  754. DRM_DEBUG_KMS("LVDS is not present in VBT\n");
  755. return;
  756. }
  757. if (HAS_PCH_SPLIT(dev)) {
  758. if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
  759. return;
  760. if (dev_priv->edp_support) {
  761. DRM_DEBUG_KMS("disable LVDS for eDP support\n");
  762. return;
  763. }
  764. gpio = PCH_GPIOC;
  765. }
  766. intel_encoder = kzalloc(sizeof(struct intel_encoder) +
  767. sizeof(struct intel_lvds_priv), GFP_KERNEL);
  768. if (!intel_encoder) {
  769. return;
  770. }
  771. intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  772. if (!intel_connector) {
  773. kfree(intel_encoder);
  774. return;
  775. }
  776. connector = &intel_connector->base;
  777. encoder = &intel_encoder->enc;
  778. drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
  779. DRM_MODE_CONNECTOR_LVDS);
  780. drm_encoder_init(dev, &intel_encoder->enc, &intel_lvds_enc_funcs,
  781. DRM_MODE_ENCODER_LVDS);
  782. drm_mode_connector_attach_encoder(&intel_connector->base, &intel_encoder->enc);
  783. intel_encoder->type = INTEL_OUTPUT_LVDS;
  784. intel_encoder->clone_mask = (1 << INTEL_LVDS_CLONE_BIT);
  785. intel_encoder->crtc_mask = (1 << 1);
  786. if (IS_I965G(dev))
  787. intel_encoder->crtc_mask |= (1 << 0);
  788. drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
  789. drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
  790. connector->display_info.subpixel_order = SubPixelHorizontalRGB;
  791. connector->interlace_allowed = false;
  792. connector->doublescan_allowed = false;
  793. lvds_priv = (struct intel_lvds_priv *)(intel_encoder + 1);
  794. intel_encoder->dev_priv = lvds_priv;
  795. /* create the scaling mode property */
  796. drm_mode_create_scaling_mode_property(dev);
  797. /*
  798. * the initial panel fitting mode will be FULL_SCREEN.
  799. */
  800. drm_connector_attach_property(&intel_connector->base,
  801. dev->mode_config.scaling_mode_property,
  802. DRM_MODE_SCALE_ASPECT);
  803. lvds_priv->fitting_mode = DRM_MODE_SCALE_ASPECT;
  804. /*
  805. * LVDS discovery:
  806. * 1) check for EDID on DDC
  807. * 2) check for VBT data
  808. * 3) check to see if LVDS is already on
  809. * if none of the above, no panel
  810. * 4) make sure lid is open
  811. * if closed, act like it's not there for now
  812. */
  813. /* Set up the DDC bus. */
  814. intel_encoder->ddc_bus = intel_i2c_create(dev, gpio, "LVDSDDC_C");
  815. if (!intel_encoder->ddc_bus) {
  816. dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration "
  817. "failed.\n");
  818. goto failed;
  819. }
  820. /*
  821. * Attempt to get the fixed panel mode from DDC. Assume that the
  822. * preferred mode is the right one.
  823. */
  824. dev_priv->lvds_edid_good = true;
  825. if (!intel_ddc_get_modes(connector, intel_encoder->ddc_bus))
  826. dev_priv->lvds_edid_good = false;
  827. list_for_each_entry(scan, &connector->probed_modes, head) {
  828. mutex_lock(&dev->mode_config.mutex);
  829. if (scan->type & DRM_MODE_TYPE_PREFERRED) {
  830. dev_priv->panel_fixed_mode =
  831. drm_mode_duplicate(dev, scan);
  832. mutex_unlock(&dev->mode_config.mutex);
  833. intel_find_lvds_downclock(dev, connector);
  834. goto out;
  835. }
  836. mutex_unlock(&dev->mode_config.mutex);
  837. }
  838. /* Failed to get EDID, what about VBT? */
  839. if (dev_priv->lfp_lvds_vbt_mode) {
  840. mutex_lock(&dev->mode_config.mutex);
  841. dev_priv->panel_fixed_mode =
  842. drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
  843. mutex_unlock(&dev->mode_config.mutex);
  844. if (dev_priv->panel_fixed_mode) {
  845. dev_priv->panel_fixed_mode->type |=
  846. DRM_MODE_TYPE_PREFERRED;
  847. goto out;
  848. }
  849. }
  850. /*
  851. * If we didn't get EDID, try checking if the panel is already turned
  852. * on. If so, assume that whatever is currently programmed is the
  853. * correct mode.
  854. */
  855. /* Ironlake: FIXME if still fail, not try pipe mode now */
  856. if (HAS_PCH_SPLIT(dev))
  857. goto failed;
  858. lvds = I915_READ(LVDS);
  859. pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
  860. crtc = intel_get_crtc_from_pipe(dev, pipe);
  861. if (crtc && (lvds & LVDS_PORT_EN)) {
  862. dev_priv->panel_fixed_mode = intel_crtc_mode_get(dev, crtc);
  863. if (dev_priv->panel_fixed_mode) {
  864. dev_priv->panel_fixed_mode->type |=
  865. DRM_MODE_TYPE_PREFERRED;
  866. goto out;
  867. }
  868. }
  869. /* If we still don't have a mode after all that, give up. */
  870. if (!dev_priv->panel_fixed_mode)
  871. goto failed;
  872. out:
  873. if (HAS_PCH_SPLIT(dev)) {
  874. u32 pwm;
  875. /* make sure PWM is enabled */
  876. pwm = I915_READ(BLC_PWM_CPU_CTL2);
  877. pwm |= (PWM_ENABLE | PWM_PIPE_B);
  878. I915_WRITE(BLC_PWM_CPU_CTL2, pwm);
  879. pwm = I915_READ(BLC_PWM_PCH_CTL1);
  880. pwm |= PWM_PCH_ENABLE;
  881. I915_WRITE(BLC_PWM_PCH_CTL1, pwm);
  882. }
  883. dev_priv->lid_notifier.notifier_call = intel_lid_notify;
  884. if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) {
  885. DRM_DEBUG_KMS("lid notifier registration failed\n");
  886. dev_priv->lid_notifier.notifier_call = NULL;
  887. }
  888. /* keep the LVDS connector */
  889. dev_priv->int_lvds_connector = connector;
  890. drm_sysfs_connector_add(connector);
  891. return;
  892. failed:
  893. DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
  894. if (intel_encoder->ddc_bus)
  895. intel_i2c_destroy(intel_encoder->ddc_bus);
  896. drm_connector_cleanup(connector);
  897. drm_encoder_cleanup(encoder);
  898. kfree(intel_encoder);
  899. kfree(intel_connector);
  900. }